7,11c7,11
< host_inst_rate 145313 # Simulator instruction rate (inst/s)
< host_op_rate 145313 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5108711594 # Simulator tick rate (ticks/s)
< host_mem_usage 309496 # Number of bytes of host memory used
< host_seconds 364.28 # Real time elapsed on the host
---
> host_inst_rate 152837 # Simulator instruction rate (inst/s)
> host_op_rate 152837 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5373256396 # Simulator tick rate (ticks/s)
> host_mem_usage 376300 # Number of bytes of host memory used
> host_seconds 346.35 # Real time elapsed on the host
54c54
< system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write
264,265c264,265
< system.physmem.totQLat 3741903500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3741904500 # Total ticks spent queuing
> system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM
402c402
< system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking
404,405c404,405
< system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking
---
> system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking
410c410
< system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full
419c419
< system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer
423c423
< system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores.
---
> system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores.
435,436c435,436
< system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle
438c438
< system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle
440,441c440,441
< system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle
479c479
< system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available
518c518
< system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested
520c520
< system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads
526c526
< system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses
537c537
< system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked
541c541
< system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking
548c548
< system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall
579c579
< system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle
581c581
< system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle
583c583
< system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle
585c585
< system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle
635,636c635,636
< system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 177593269 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 177593268 # The number of ROB reads
695,696c695,696
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles
701,704c701,704
< system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles
731,732c731,732
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency
737,741c737,741
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked
745c745
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked
772a773,778
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
775,776c781,782
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles
781,784c787,790
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles
805,806c811,812
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency
811,820c817,826
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency
944,945c950,951
< system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits
947,948c953,954
< system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits
950,951c956,957
< system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits
959,960c965,966
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses
962,963c968,969
< system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses
965,966c971,972
< system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404332 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404334 # number of overall misses
974,975c980,981
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles
977,978c983,984
< system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles
980,981c986,987
< system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles
1006,1007c1012,1013
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses
1009,1010c1015,1016
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses
1012,1013c1018,1019
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses
1021,1022c1027,1028
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency
1024,1025c1030,1031
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency
1027,1028c1033,1034
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency
1052,1053c1058,1059
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses
1055,1056c1061,1062
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses
1058,1059c1064,1071
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
1067,1068c1079,1080
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles
1070,1071c1082,1083
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles
1073,1074c1085,1086
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles
1088,1089c1100,1101
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses
1091,1092c1103,1104
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses
1094,1095c1106,1107
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses
1103,1104c1115,1116
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency
1106,1107c1118,1119
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
1109,1116c1121,1128
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency
1137,1139c1149,1151
< system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram
1142,1143c1154,1155
< system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram
1147c1159
< system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram
1154c1166
< system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks)
1339c1351
< system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 187 # Transaction distribution
1341c1353
< system.membus.trans_dist::UpgradeResp 190 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 192 # Transaction distribution
1346c1358
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes)
1348c1360
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes)
1351c1363
< system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes)
1359c1371
< system.membus.snoop_fanout::samples 563651 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 580180 # Request fanout histogram
1364c1376
< system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram
1369c1381
< system.membus.snoop_fanout::total 563651 # Request fanout histogram
---
> system.membus.snoop_fanout::total 580180 # Request fanout histogram
1372c1384
< system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks)
1376c1388
< system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks)
< host_inst_rate 145313 # Simulator instruction rate (inst/s)
< host_op_rate 145313 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5108711594 # Simulator tick rate (ticks/s)
< host_mem_usage 309496 # Number of bytes of host memory used
< host_seconds 364.28 # Real time elapsed on the host
---
> host_inst_rate 152837 # Simulator instruction rate (inst/s)
> host_op_rate 152837 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5373256396 # Simulator tick rate (ticks/s)
> host_mem_usage 376300 # Number of bytes of host memory used
> host_seconds 346.35 # Real time elapsed on the host
54c54
< system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write
264,265c264,265
< system.physmem.totQLat 3741903500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3741904500 # Total ticks spent queuing
> system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM
402c402
< system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking
404,405c404,405
< system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking
---
> system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking
410c410
< system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full
419c419
< system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer
423c423
< system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores.
---
> system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores.
435,436c435,436
< system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle
438c438
< system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle
440,441c440,441
< system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle
479c479
< system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available
518c518
< system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
---
> system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested
520c520
< system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads
526c526
< system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses
537c537
< system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked
541c541
< system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking
---
> system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking
548c548
< system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall
579c579
< system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle
581c581
< system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle
583c583
< system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle
585c585
< system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle
635,636c635,636
< system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 177593269 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 177593268 # The number of ROB reads
695,696c695,696
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles
701,704c701,704
< system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles
731,732c731,732
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency
737,741c737,741
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked
745c745
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked
772a773,778
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
775,776c781,782
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles
781,784c787,790
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles
805,806c811,812
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency
811,820c817,826
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency
944,945c950,951
< system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits
947,948c953,954
< system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits
950,951c956,957
< system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits
959,960c965,966
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses
962,963c968,969
< system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses
965,966c971,972
< system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404332 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404334 # number of overall misses
974,975c980,981
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles
977,978c983,984
< system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles
980,981c986,987
< system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles
1006,1007c1012,1013
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses
1009,1010c1015,1016
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses
1012,1013c1018,1019
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses
1021,1022c1027,1028
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency
1024,1025c1030,1031
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency
1027,1028c1033,1034
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency
1052,1053c1058,1059
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses
1055,1056c1061,1062
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses
1058,1059c1064,1071
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
1067,1068c1079,1080
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles
1070,1071c1082,1083
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles
1073,1074c1085,1086
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles
1088,1089c1100,1101
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses
1091,1092c1103,1104
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses
1094,1095c1106,1107
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses
1103,1104c1115,1116
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency
1106,1107c1118,1119
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
1109,1116c1121,1128
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency
1137,1139c1149,1151
< system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram
1142,1143c1154,1155
< system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram
1147c1159
< system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram
1154c1166
< system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks)
1339c1351
< system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 187 # Transaction distribution
1341c1353
< system.membus.trans_dist::UpgradeResp 190 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 192 # Transaction distribution
1346c1358
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes)
1348c1360
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes)
1351c1363
< system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes)
1359c1371
< system.membus.snoop_fanout::samples 563651 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 580180 # Request fanout histogram
1364c1376
< system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram
1369c1381
< system.membus.snoop_fanout::total 563651 # Request fanout histogram
---
> system.membus.snoop_fanout::total 580180 # Request fanout histogram
1372c1384
< system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks)
1376c1388
< system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks)