3,5c3,5
< sim_seconds 1.859045 # Number of seconds simulated
< sim_ticks 1859045389000 # Number of ticks simulated
< final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.861006 # Number of seconds simulated
> sim_ticks 1861005569500 # Number of ticks simulated
> final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 155751 # Simulator instruction rate (inst/s)
< host_op_rate 155751 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5470499619 # Simulator tick rate (ticks/s)
< host_mem_usage 374716 # Number of bytes of host memory used
< host_seconds 339.83 # Real time elapsed on the host
< sim_insts 52929026 # Number of instructions simulated
< sim_ops 52929026 # Number of ops (including micro ops) simulated
---
> host_inst_rate 153218 # Simulator instruction rate (inst/s)
> host_op_rate 153218 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5386630373 # Simulator tick rate (ticks/s)
> host_mem_usage 376136 # Number of bytes of host memory used
> host_seconds 345.49 # Real time elapsed on the host
> sim_insts 52934565 # Number of instructions simulated
> sim_ops 52934565 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory
19,25c19,25
< system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory
27,31c27,31
< system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s)
33,40c33,40
< system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s)
42,60c42,60
< system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 403836 # Number of read requests accepted
< system.physmem.writeReqs 159002 # Number of write requests accepted
< system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue
< system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25744 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25557 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25510 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25348 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25387 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24799 # Per bank write bursts
---
> system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 403841 # Number of read requests accepted
> system.physmem.writeReqs 159009 # Number of write requests accepted
> system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25748 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25559 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25508 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25346 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25393 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24806 # Per bank write bursts
62,64c62,64
< system.physmem.perBankRdBursts::7 25129 # Per bank write bursts
< system.physmem.perBankRdBursts::8 24928 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25032 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 25127 # Per bank write bursts
> system.physmem.perBankRdBursts::8 24925 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25034 # Per bank write bursts
66c66
< system.physmem.perBankRdBursts::11 24784 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 24774 # Per bank write bursts
68,86c68,86
< system.physmem.perBankRdBursts::13 25235 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25659 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25606 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10485 # Per bank write bursts
< system.physmem.perBankWrBursts::1 10108 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10574 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9632 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9668 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9137 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9064 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8900 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9821 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8750 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9677 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9460 # Per bank write bursts
< system.physmem.perBankWrBursts::12 10019 # Per bank write bursts
< system.physmem.perBankWrBursts::13 10709 # Per bank write bursts
< system.physmem.perBankWrBursts::14 10502 # Per bank write bursts
< system.physmem.perBankWrBursts::15 10405 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 25233 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25663 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25612 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9148 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8514 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8998 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8298 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8214 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7705 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7696 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7707 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8055 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7602 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8149 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7799 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8377 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9062 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8903 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8889 # Per bank write bursts
88,89c88,89
< system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
< system.physmem.totGap 1859040142000 # Total gap between requests
---
> system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
> system.physmem.totGap 1861000236500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 403836 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 403841 # Read request sizes (log2)
103,110c103,110
< system.physmem.writePktSize::6 159002 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 159009 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
151,217c151,217
< system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes
221,261c221,267
< system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads
< system.physmem.totQLat 3621320000 # Total ticks spent queuing
< system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads
> system.physmem.totQLat 3741903500 # Total ticks spent queuing
> system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst
263,266c269,272
< system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s
269c275
< system.physmem.busUtil 0.15 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.14 # Data bus utilization in percentage
272,290c278,296
< system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing
< system.physmem.readRowHits 364717 # Number of row buffer hits during reads
< system.physmem.writeRowHits 132230 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes
< system.physmem.avgGap 3302975.53 # Average gap between requests
< system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.311493 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states
---
> system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing
> system.physmem.readRowHits 364326 # Number of row buffer hits during reads
> system.physmem.writeRowHits 109846 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes
> system.physmem.avgGap 3306387.56 # Average gap between requests
> system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.297807 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states
> system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states
292c298
< system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states
294,304c300,310
< system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.308507 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states
---
> system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.286901 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states
> system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states
306c312
< system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states
308,312c314,318
< system.cpu.branchPred.lookups 17755011 # Number of BP lookups
< system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits
---
> system.cpu.branchPred.lookups 17721924 # Number of BP lookups
> system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits
314,316c320,322
< system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions.
322,331c328,337
< system.cpu.dtb.read_hits 10297861 # DTB read hits
< system.cpu.dtb.read_misses 41459 # DTB read misses
< system.cpu.dtb.read_acv 502 # DTB read access violations
< system.cpu.dtb.read_accesses 968382 # DTB read accesses
< system.cpu.dtb.write_hits 6648165 # DTB write hits
< system.cpu.dtb.write_misses 9537 # DTB write misses
< system.cpu.dtb.write_acv 407 # DTB write access violations
< system.cpu.dtb.write_accesses 342637 # DTB write accesses
< system.cpu.dtb.data_hits 16946026 # DTB hits
< system.cpu.dtb.data_misses 50996 # DTB misses
---
> system.cpu.dtb.read_hits 10269214 # DTB read hits
> system.cpu.dtb.read_misses 41261 # DTB read misses
> system.cpu.dtb.read_acv 507 # DTB read access violations
> system.cpu.dtb.read_accesses 967301 # DTB read accesses
> system.cpu.dtb.write_hits 6648637 # DTB write hits
> system.cpu.dtb.write_misses 9303 # DTB write misses
> system.cpu.dtb.write_acv 402 # DTB write access violations
> system.cpu.dtb.write_accesses 342644 # DTB write accesses
> system.cpu.dtb.data_hits 16917851 # DTB hits
> system.cpu.dtb.data_misses 50564 # DTB misses
333,337c339,343
< system.cpu.dtb.data_accesses 1311019 # DTB accesses
< system.cpu.itb.fetch_hits 1769037 # ITB hits
< system.cpu.itb.fetch_misses 35976 # ITB misses
< system.cpu.itb.fetch_acv 675 # ITB acv
< system.cpu.itb.fetch_accesses 1805013 # ITB accesses
---
> system.cpu.dtb.data_accesses 1309945 # DTB accesses
> system.cpu.itb.fetch_hits 1769158 # ITB hits
> system.cpu.itb.fetch_misses 36068 # ITB misses
> system.cpu.itb.fetch_acv 660 # ITB acv
> system.cpu.itb.fetch_accesses 1805226 # ITB accesses
350c356
< system.cpu.numCycles 118253854 # number of cpu cycles simulated
---
> system.cpu.numCycles 122572361 # number of cpu cycles simulated
353,369c359,374
< system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total)
371,379c376,384
< system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total)
383,428c388,433
< system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle
430,438c435,443
< system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle
442c447
< system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle
444,474c449,479
< system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available
478,509c483,514
< system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued
< system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued
> system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued
511,523c516,528
< system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued
< system.cpu.iq.rate 0.486545 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued
> system.cpu.iq.rate 0.469435 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores
525,528c530,533
< system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed
531,532c536,537
< system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked
534,550c539,555
< system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute
552,560c557,565
< system.cpu.iew.exec_nop 3696550 # number of nop insts executed
< system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed
< system.cpu.iew.exec_branches 8972525 # Number of branches executed
< system.cpu.iew.exec_stores 6672811 # Number of stores executed
< system.cpu.iew.exec_rate 0.481583 # Inst execution rate
< system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 28889312 # num instructions producing a value
< system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 3706829 # number of nop insts executed
> system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed
> system.cpu.iew.exec_branches 8976912 # Number of branches executed
> system.cpu.iew.exec_stores 6673045 # Number of stores executed
> system.cpu.iew.exec_rate 0.464599 # Inst execution rate
> system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 28792537 # num instructions producing a value
> system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value
562,563c567,568
< system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back
565,570c570,575
< system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle
572,580c577,585
< system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle
584,586c589,591
< system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 56117715 # Number of instructions committed
< system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 56123349 # Number of instructions committed
> system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed
588,591c593,596
< system.cpu.commit.refs 15458158 # Number of memory references committed
< system.cpu.commit.loads 9084456 # Number of loads committed
< system.cpu.commit.membars 226347 # Number of memory barriers committed
< system.cpu.commit.branches 8434758 # Number of branches committed
---
> system.cpu.commit.refs 15459994 # Number of memory references committed
> system.cpu.commit.loads 9085408 # Number of loads committed
> system.cpu.commit.membars 226308 # Number of memory barriers committed
> system.cpu.commit.branches 8435685 # Number of branches committed
593,597c598,602
< system.cpu.commit.int_insts 51969244 # Number of committed integer instructions.
< system.cpu.commit.function_calls 739915 # Number of function calls committed.
< system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction
< system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction
---
> system.cpu.commit.int_insts 51974864 # Number of committed integer instructions.
> system.cpu.commit.function_calls 740049 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction
625,627c630,632
< system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction
< system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
629,630c634,635
< system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction
< system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
> system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
632,657c637,662
< system.cpu.rob.rob_reads 173330307 # The number of ROB reads
< system.cpu.rob.rob_writes 129976168 # The number of ROB writes
< system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 52929026 # Number of Instructions Simulated
< system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 74582639 # number of integer regfile reads
< system.cpu.int_regfile_writes 40531859 # number of integer regfile writes
< system.cpu.fp_regfile_reads 167323 # number of floating regfile reads
< system.cpu.fp_regfile_writes 167888 # number of floating regfile writes
< system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads
< system.cpu.misc_regfile_writes 939419 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 1404198 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy
---
> system.cpu.rob.rob_reads 177593269 # The number of ROB reads
> system.cpu.rob.rob_writes 130137832 # The number of ROB writes
> system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 52934565 # Number of Instructions Simulated
> system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 74599299 # number of integer regfile reads
> system.cpu.int_regfile_writes 40560409 # number of integer regfile writes
> system.cpu.fp_regfile_reads 167171 # number of floating regfile reads
> system.cpu.fp_regfile_writes 167579 # number of floating regfile writes
> system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads
> system.cpu.misc_regfile_writes 939349 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 1403663 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
660,661c665,666
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
663,739c668,744
< system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits
< system.cpu.dcache.overall_hits::total 11473712 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses
< system.cpu.dcache.overall_misses::total 3729145 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits
> system.cpu.dcache.overall_hits::total 11456366 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses
> system.cpu.dcache.overall_misses::total 3751566 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked
741,742c746,747
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked
745,810c750,815
< system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks
< system.cpu.dcache.writebacks::total 842396 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks
> system.cpu.dcache.writebacks::total 842087 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
818,826c823,831
< system.cpu.icache.tags.replacements 1034381 # number of replacements
< system.cpu.icache.tags.tagsinuse 509.395054 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 7933874 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1034889 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 7.666401 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 26421984250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 509.395054 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.994912 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.994912 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1032757 # number of replacements
> system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy
828,830c833,835
< system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id
832,870c837,875
< system.cpu.icache.tags.tag_accesses 10056110 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 10056110 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 7933875 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 7933875 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 7933875 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 7933875 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 7933875 # number of overall hits
< system.cpu.icache.overall_hits::total 7933875 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1087081 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1087081 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1087081 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1087081 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1087081 # number of overall misses
< system.cpu.icache.overall_misses::total 1087081 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15110067823 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15110067823 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15110067823 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15110067823 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15110067823 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15110067823 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 9020956 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 9020956 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 9020956 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 9020956 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 9020956 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 9020956 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120506 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.120506 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.120506 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.120506 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.120506 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.120506 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13899.670607 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13899.670607 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 3991 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits
> system.cpu.icache.overall_hits::total 7965142 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses
> system.cpu.icache.overall_misses::total 1086038 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked
872c877
< system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked
874c879
< system.cpu.icache.avg_blocked_cycles::no_mshrs 21.808743 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.115385 # average number of cycles each access was blocked
878,907c883,912
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51927 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 51927 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 51927 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 51927 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 51927 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 51927 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035154 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1035154 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1035154 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1035154 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1035154 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1035154 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12419429847 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12419429847 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12419429847 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12419429847 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12419429847 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12419429847 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114750 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.114750 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.114750 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52519 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 52519 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 52519 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 52519 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 52519 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 52519 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1033519 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1033519 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1033519 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1033519 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1033519 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1033519 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13013904297 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 13013904297 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13013904297 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 13013904297 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13013904297 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 13013904297 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114186 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.114186 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.114186 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency
910,935c915,940
< system.cpu.l2cache.tags.tagsinuse 65337.269998 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2574624 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 403501 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.380713 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 5350.111230 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6273.021020 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.819613 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081636 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.095719 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996968 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3501 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 26963891 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26963891 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1019836 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 829079 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1848915 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 842396 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 842396 # number of Writeback hits
---
> system.cpu.l2cache.tags.tagsinuse 65331.413764 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2572439 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 403497 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.375361 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 5986676750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 5347.510273 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6335.411477 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081597 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.096671 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996878 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 491 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2403 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55444 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 26943938 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26943938 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1018225 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits
938,1024c943,1029
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 20 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 186519 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 186519 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 1019836 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1015598 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2035434 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 1019836 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1015598 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2035434 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 15129 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 273823 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 288952 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 57 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 57 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 15129 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 389199 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 404328 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 15129 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 389199 # number of overall misses
< system.cpu.l2cache.overall_misses::total 404328 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1155504000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17984856500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 19140360500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331495 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 331495 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92996 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92996 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647937355 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9647937355 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1155504000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 27632793855 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28788297855 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1155504000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 27632793855 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28788297855 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1034965 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1102902 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2137867 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 842396 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 842396 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 88 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 301895 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1034965 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1404797 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2439762 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1034965 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1404797 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2439762 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014618 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248275 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.135159 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.647727 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.647727 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382173 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.382173 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014618 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.277050 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.165724 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014618 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.277050 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.165724 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76376.759865 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65680.591112 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 66240.623010 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5815.701754 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5815.701754 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11624.500000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11624.500000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83621.700830 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83621.700830 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71200.356777 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71200.356777 # average overall miss latency
---
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses
> system.cpu.l2cache.overall_misses::total 404332 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 301613 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 301613 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1033352 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1404270 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2437622 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1033352 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1404270 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency
1033,1034c1038,1039
< system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks
< system.cpu.l2cache.writebacks::total 75938 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks
> system.cpu.l2cache.writebacks::total 75945 # number of writebacks
1041,1106c1046,1111
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15128 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273823 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 288951 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 57 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 57 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 15128 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 389199 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 404327 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 15128 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 389199 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 404327 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964671250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14573298500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15537969750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 720554 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 720554 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80008 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80008 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8241634145 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8241634145 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964671250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22814932645 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23779603895 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964671250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22814932645 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23779603895 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333622500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333622500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884454000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884454000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218076500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218076500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.165724 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.165724 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63767.269302 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
1114,1115c1119,1120
< system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution
1118,1135c1123,1140
< system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 42071 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 42097 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram
1138,1139c1143,1144
< system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram
1143,1144c1148,1149
< system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks)
1148c1153
< system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks)
1150c1155
< system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks)
1223c1228
< system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks)
1229c1234
< system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks)
1232c1237
< system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use
1236,1239c1241,1244
< system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy
1253,1260c1258,1265
< system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles
1277,1285c1282,1290
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked
1287c1292
< system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked
1289c1294
< system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked
1303,1310c1308,1315
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles
1319,1326c1324,1331
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency
1328,1329c1333,1334
< system.membus.trans_dist::ReadReq 296054 # Transaction distribution
< system.membus.trans_dist::ReadResp 295968 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 296160 # Transaction distribution
> system.membus.trans_dist::ReadResp 296066 # Transaction distribution
1332c1337
< system.membus.trans_dist::Writeback 117450 # Transaction distribution
---
> system.membus.trans_dist::Writeback 117457 # Transaction distribution
1335,1340c1340,1345
< system.membus.trans_dist::UpgradeReq 203 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 211 # Transaction distribution
< system.membus.trans_dist::ReadExReq 115230 # Transaction distribution
< system.membus.trans_dist::ReadExResp 115230 # Transaction distribution
< system.membus.trans_dist::BadAddressError 86 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 190 # Transaction distribution
> system.membus.trans_dist::ReadExReq 115137 # Transaction distribution
> system.membus.trans_dist::ReadExResp 115137 # Transaction distribution
> system.membus.trans_dist::BadAddressError 94 # Transaction distribution
1342,1344c1347,1349
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes)
1347c1352
< system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes)
1349,1350c1354,1355
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes)
1353c1358
< system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes)
1355c1360
< system.membus.snoop_fanout::samples 563568 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 563651 # Request fanout histogram
1360c1365
< system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram
1365,1366c1370,1371
< system.membus.snoop_fanout::total 563568 # Request fanout histogram
< system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 563651 # Request fanout histogram
> system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks)
1368c1373
< system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks)
1370c1375
< system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks)
1372,1374c1377,1379
< system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks)
1408,1410c1413,1415
< system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl
1413,1415c1418,1420
< system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1418,1425c1423,1430
< system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl
1428,1429c1433,1434
< system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl
1468c1473
< system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed
1477,1482c1482,1487
< system.cpu.kern.callpal::total 191962 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1913
< system.cpu.kern.mode_good::user 1743
---
> system.cpu.kern.callpal::total 191942 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1911
> system.cpu.kern.mode_good::user 1741
1484c1489
< system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches
1486,1490c1491,1495
< system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode