7,11c7,11
< host_inst_rate 145866 # Simulator instruction rate (inst/s)
< host_op_rate 145866 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5123409698 # Simulator tick rate (ticks/s)
< host_mem_usage 320704 # Number of bytes of host memory used
< host_seconds 362.85 # Real time elapsed on the host
---
> host_inst_rate 164458 # Simulator instruction rate (inst/s)
> host_op_rate 164458 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5776457310 # Simulator tick rate (ticks/s)
> host_mem_usage 314484 # Number of bytes of host memory used
> host_seconds 321.83 # Real time elapsed on the host
423,424d422
< system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
439,440d436
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses
447,448c443,444
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency