1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.860192 # Number of seconds simulated
4sim_ticks 1860191785500 # Number of ticks simulated
5final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 128947 # Simulator instruction rate (inst/s)
8host_op_rate 128947 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4527634915 # Simulator tick rate (ticks/s)
10host_mem_usage 347764 # Number of bytes of host memory used
11host_seconds 410.85 # Real time elapsed on the host
12sim_insts 52978349 # Number of instructions simulated
13sim_ops 52978349 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 445200 # Number of read requests accepted
44system.physmem.writeReqs 117428 # Number of write requests accepted
45system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue
49system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 28210 # Per bank write bursts
56system.physmem.perBankRdBursts::1 27995 # Per bank write bursts
57system.physmem.perBankRdBursts::2 28357 # Per bank write bursts
58system.physmem.perBankRdBursts::3 27829 # Per bank write bursts
59system.physmem.perBankRdBursts::4 27761 # Per bank write bursts
60system.physmem.perBankRdBursts::5 27267 # Per bank write bursts
61system.physmem.perBankRdBursts::6 27371 # Per bank write bursts
62system.physmem.perBankRdBursts::7 27375 # Per bank write bursts
63system.physmem.perBankRdBursts::8 27696 # Per bank write bursts
64system.physmem.perBankRdBursts::9 27269 # Per bank write bursts
65system.physmem.perBankRdBursts::10 28017 # Per bank write bursts
66system.physmem.perBankRdBursts::11 27509 # Per bank write bursts
67system.physmem.perBankRdBursts::12 27546 # Per bank write bursts
68system.physmem.perBankRdBursts::13 28232 # Per bank write bursts
69system.physmem.perBankRdBursts::14 28342 # Per bank write bursts
70system.physmem.perBankRdBursts::15 28310 # Per bank write bursts
71system.physmem.perBankWrBursts::0 7920 # Per bank write bursts
72system.physmem.perBankWrBursts::1 7516 # Per bank write bursts
73system.physmem.perBankWrBursts::2 7873 # Per bank write bursts
74system.physmem.perBankWrBursts::3 7373 # Per bank write bursts
75system.physmem.perBankWrBursts::4 7309 # Per bank write bursts
76system.physmem.perBankWrBursts::5 6720 # Per bank write bursts
77system.physmem.perBankWrBursts::6 6881 # Per bank write bursts
78system.physmem.perBankWrBursts::7 6774 # Per bank write bursts
79system.physmem.perBankWrBursts::8 7136 # Per bank write bursts
80system.physmem.perBankWrBursts::9 6679 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7411 # Per bank write bursts
82system.physmem.perBankWrBursts::11 6967 # Per bank write bursts
83system.physmem.perBankWrBursts::12 7107 # Per bank write bursts
84system.physmem.perBankWrBursts::13 7877 # Per bank write bursts
85system.physmem.perBankWrBursts::14 8064 # Per bank write bursts
86system.physmem.perBankWrBursts::15 7795 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
89system.physmem.totGap 1860186344000 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 445200 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 117428 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see
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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 934 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 2202 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 3347 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 4688 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 4756 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 4816 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 4872 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads
268system.physmem.totQLat 10196532000 # Total ticks spent queuing
269system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM
270system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers
271system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks
272system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst
273system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst
274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
275system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst
276system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s
277system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
278system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s
279system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
281system.physmem.busUtil 0.15 # Data bus utilization in percentage
282system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
283system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
284system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing
285system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing
286system.physmem.readRowHits 402462 # Number of row buffer hits during reads
287system.physmem.writeRowHits 96189 # Number of row buffer hits during writes
288system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads
289system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes
290system.physmem.avgGap 3306245.59 # Average gap between requests
291system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined
292system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
293system.membus.throughput 19400105 # Throughput (bytes/s)
294system.membus.trans_dist::ReadReq 295926 # Transaction distribution
295system.membus.trans_dist::ReadResp 295846 # Transaction distribution
296system.membus.trans_dist::WriteReq 9597 # Transaction distribution
297system.membus.trans_dist::WriteResp 9597 # Transaction distribution
298system.membus.trans_dist::Writeback 117428 # Transaction distribution
299system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
300system.membus.trans_dist::UpgradeResp 181 # Transaction distribution
301system.membus.trans_dist::ReadExReq 156840 # Transaction distribution
302system.membus.trans_dist::ReadExResp 156840 # Transaction distribution
303system.membus.trans_dist::BadAddressError 80 # Transaction distribution
304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes)
306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes)
307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes)
308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
309system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
310system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes)
311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes)
313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes)
314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
315system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
316system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes)
317system.membus.data_through_bus 36052332 # Total data (bytes)
318system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
319system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks)
320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
321system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks)
322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
323system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks)
324system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
325system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks)
326system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
327system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks)
328system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
329system.iocache.tags.replacements 41685 # number of replacements
330system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use
331system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
332system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
333system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
334system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit.
335system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor
336system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy
337system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy
338system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
339system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
340system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
341system.iocache.tags.tag_accesses 375525 # Number of tag accesses
342system.iocache.tags.data_accesses 375525 # Number of data accesses
343system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
344system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
345system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
346system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
347system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
348system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
349system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
350system.iocache.overall_misses::total 41725 # number of overall misses
351system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles
352system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles
353system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles
354system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles
355system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles
356system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles
357system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles
358system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles
359system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
360system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
361system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
362system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
363system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
364system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
365system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
366system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
367system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
368system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
369system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
370system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
371system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
372system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
373system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
374system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
375system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency
376system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency
377system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency
378system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency
379system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency
380system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency
381system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency
382system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency
383system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked
384system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked
386system.iocache.blocked::no_targets 0 # number of cycles access was blocked
387system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked
388system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.iocache.fast_writes 0 # number of fast writes performed
390system.iocache.cache_copies 0 # number of cache copies performed
391system.iocache.writebacks::writebacks 41512 # number of writebacks
392system.iocache.writebacks::total 41512 # number of writebacks
393system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
394system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
395system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
396system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
397system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
398system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
399system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
400system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
401system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles
402system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles
403system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles
404system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles
405system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles
406system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles
407system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles
408system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles
409system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
410system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
411system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
412system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
413system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
414system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
415system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
416system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
417system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency
418system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency
419system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency
420system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency
421system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency
422system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency
423system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency
424system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency
425system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
426system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
427system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
428system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
429system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
430system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
431system.disk0.dma_write_txs 395 # Number of DMA write transactions.
432system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
433system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
434system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
435system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
436system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
437system.disk2.dma_write_txs 1 # Number of DMA write transactions.
438system.cpu.branchPred.lookups 13847711 # Number of BP lookups
439system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted
440system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect
441system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups
442system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits
443system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
444system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage
445system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target.
446system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions.
447system.cpu_clk_domain.clock 500 # Clock period in ticks
448system.cpu.dtb.fetch_hits 0 # ITB hits
449system.cpu.dtb.fetch_misses 0 # ITB misses
450system.cpu.dtb.fetch_acv 0 # ITB acv
451system.cpu.dtb.fetch_accesses 0 # ITB accesses
452system.cpu.dtb.read_hits 9926060 # DTB read hits
453system.cpu.dtb.read_misses 41229 # DTB read misses
454system.cpu.dtb.read_acv 545 # DTB read access violations
455system.cpu.dtb.read_accesses 943227 # DTB read accesses
456system.cpu.dtb.write_hits 6592681 # DTB write hits
457system.cpu.dtb.write_misses 10567 # DTB write misses
458system.cpu.dtb.write_acv 408 # DTB write access violations
459system.cpu.dtb.write_accesses 338977 # DTB write accesses
460system.cpu.dtb.data_hits 16518741 # DTB hits
461system.cpu.dtb.data_misses 51796 # DTB misses
462system.cpu.dtb.data_acv 953 # DTB access violations
463system.cpu.dtb.data_accesses 1282204 # DTB accesses
464system.cpu.itb.fetch_hits 1307907 # ITB hits
465system.cpu.itb.fetch_misses 36763 # ITB misses
466system.cpu.itb.fetch_acv 1058 # ITB acv
467system.cpu.itb.fetch_accesses 1344670 # ITB accesses
468system.cpu.itb.read_hits 0 # DTB read hits
469system.cpu.itb.read_misses 0 # DTB read misses
470system.cpu.itb.read_acv 0 # DTB read access violations
471system.cpu.itb.read_accesses 0 # DTB read accesses
472system.cpu.itb.write_hits 0 # DTB write hits
473system.cpu.itb.write_misses 0 # DTB write misses
474system.cpu.itb.write_acv 0 # DTB write access violations
475system.cpu.itb.write_accesses 0 # DTB write accesses
476system.cpu.itb.data_hits 0 # DTB hits
477system.cpu.itb.data_misses 0 # DTB misses
478system.cpu.itb.data_acv 0 # DTB access violations
479system.cpu.itb.data_accesses 0 # DTB accesses
480system.cpu.numCycles 122133073 # number of cpu cycles simulated
481system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
482system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
483system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss
484system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed
485system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered
486system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken
487system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked
488system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing
489system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked
490system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
491system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps
492system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions
493system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR
494system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched
495system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed
496system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total)
497system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total)
498system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total)
499system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
500system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total)
501system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total)
502system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total)
503system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total)
504system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total)
505system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total)
506system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total)
507system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total)
508system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total)
509system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
510system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
511system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
512system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total)
513system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle
514system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle
515system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle
516system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked
517system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running
518system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking
519system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing
520system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch
521system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction
522system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode
523system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode
524system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing
525system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle
526system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking
527system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst
528system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running
529system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking
530system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename
531system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full
532system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full
533system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full
534system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed
535system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made
536system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups
537system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups
538system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed
539system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing
540system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed
541system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed
542system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer
543system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit.
544system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit.
545system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads.
546system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores.
547system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec)
548system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ
549system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued
550system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued
551system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling
552system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph
553system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed
554system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle
555system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle
556system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle
557system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
558system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle
559system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle
560system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle
561system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle
562system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle
563system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle
564system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle
565system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle
566system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle
567system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
568system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
569system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
570system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle
571system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
572system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available
573system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available
574system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available
575system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available
576system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available
577system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available
578system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available
579system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available
580system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available
581system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available
582system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available
583system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available
584system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available
585system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available
586system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available
587system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available
588system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available
589system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available
590system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available
591system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available
592system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available
593system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available
594system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available
595system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available
596system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available
597system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available
598system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available
599system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available
600system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available
601system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available
602system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available
603system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
604system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
605system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
606system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued
607system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued
608system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued
609system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued
610system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued
611system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued
612system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued
613system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued
614system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued
615system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued
616system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued
617system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued
618system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued
619system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued
620system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued
621system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued
622system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued
623system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued
624system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued
625system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued
626system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued
627system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued
628system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued
629system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued
630system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued
631system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued
632system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
633system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
634system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
635system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued
636system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued
637system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued
638system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
639system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued
640system.cpu.iq.rate 0.464940 # Inst issue rate
641system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested
642system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst)
643system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads
644system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes
645system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses
646system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads
647system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes
648system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses
649system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses
650system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses
651system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores
652system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
653system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed
654system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed
655system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations
656system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed
657system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
658system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
659system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled
660system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked
661system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
662system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing
663system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking
664system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking
665system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ
666system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch
667system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions
668system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions
669system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions
670system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall
671system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall
672system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations
673system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly
674system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly
675system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute
676system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions
677system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed
678system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute
679system.cpu.iew.exec_swp 0 # number of swp insts executed
680system.cpu.iew.exec_nop 3521682 # number of nop insts executed
681system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed
682system.cpu.iew.exec_branches 8922207 # Number of branches executed
683system.cpu.iew.exec_stores 6618452 # Number of stores executed
684system.cpu.iew.exec_rate 0.461152 # Inst execution rate
685system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit
686system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back
687system.cpu.iew.wb_producers 27722224 # num instructions producing a value
688system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value
689system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
690system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle
691system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back
692system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
693system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit
694system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards
695system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted
696system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle
697system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle
698system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle
699system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
700system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle
701system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle
702system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle
703system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle
704system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle
705system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle
706system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle
707system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle
708system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle
709system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
710system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
711system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
712system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle
713system.cpu.commit.committedInsts 56169084 # Number of instructions committed
714system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed
715system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
716system.cpu.commit.refs 15469932 # Number of memory references committed
717system.cpu.commit.loads 9092119 # Number of loads committed
718system.cpu.commit.membars 226344 # Number of memory barriers committed
719system.cpu.commit.branches 8439731 # Number of branches committed
720system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
721system.cpu.commit.int_insts 52018783 # Number of committed integer instructions.
722system.cpu.commit.function_calls 740550 # Number of function calls committed.
723system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached
724system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
725system.cpu.rob.rob_reads 141516799 # The number of ROB reads
726system.cpu.rob.rob_writes 128475885 # The number of ROB writes
727system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself
728system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling
729system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
730system.cpu.committedInsts 52978349 # Number of Instructions Simulated
731system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated
732system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated
733system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction
734system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads
735system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle
736system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads
737system.cpu.int_regfile_reads 73853807 # number of integer regfile reads
738system.cpu.int_regfile_writes 40298046 # number of integer regfile writes
739system.cpu.fp_regfile_reads 166062 # number of floating regfile reads
740system.cpu.fp_regfile_writes 167446 # number of floating regfile writes
741system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads
742system.cpu.misc_regfile_writes 938942 # number of misc regfile writes
743system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
744system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
745system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
746system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
747system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
748system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
749system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
750system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

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766system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
767system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
768system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
769system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
770system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
771system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
772system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
773system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
774system.iobus.throughput 1454553 # Throughput (bytes/s)
775system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
776system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
777system.iobus.trans_dist::WriteReq 51149 # Transaction distribution
778system.iobus.trans_dist::WriteResp 51149 # Transaction distribution
779system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes)
780system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
781system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
782system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)

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826system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
827system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
828system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
829system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
830system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
831system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
832system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
833system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
834system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks)
835system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
836system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
837system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
838system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks)
839system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
840system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks)
841system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
842system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s)
843system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution
844system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution
845system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution
846system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution
847system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution
848system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution
849system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
850system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution
851system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution
852system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution
853system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution
854system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes)
855system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes)
856system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes)
857system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes)
858system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes)
859system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes)
860system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes)
861system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes)
862system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks)
863system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
864system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
865system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
866system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks)
867system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
868system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks)
869system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
870system.cpu.icache.tags.replacements 1008048 # number of replacements
871system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use
872system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks.
873system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks.
874system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks.
875system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit.
876system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor
877system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy
878system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy
879system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
880system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
881system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
882system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id
883system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
884system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses
885system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses
886system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits
887system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits
888system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits
889system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits
890system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits
891system.cpu.icache.overall_hits::total 7476651 # number of overall hits
892system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses
893system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses
894system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses
895system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses
896system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses
897system.cpu.icache.overall_misses::total 1064809 # number of overall misses
898system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles
899system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles
900system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles
901system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles
902system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles
903system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles
904system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # number of ReadReq accesses(hits+misses)
905system.cpu.icache.ReadReq_accesses::total 8541460 # number of ReadReq accesses(hits+misses)
906system.cpu.icache.demand_accesses::cpu.inst 8541460 # number of demand (read+write) accesses
907system.cpu.icache.demand_accesses::total 8541460 # number of demand (read+write) accesses
908system.cpu.icache.overall_accesses::cpu.inst 8541460 # number of overall (read+write) accesses
909system.cpu.icache.overall_accesses::total 8541460 # number of overall (read+write) accesses
910system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124664 # miss rate for ReadReq accesses
911system.cpu.icache.ReadReq_miss_rate::total 0.124664 # miss rate for ReadReq accesses
912system.cpu.icache.demand_miss_rate::cpu.inst 0.124664 # miss rate for demand accesses
913system.cpu.icache.demand_miss_rate::total 0.124664 # miss rate for demand accesses
914system.cpu.icache.overall_miss_rate::cpu.inst 0.124664 # miss rate for overall accesses
915system.cpu.icache.overall_miss_rate::total 0.124664 # miss rate for overall accesses
916system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459 # average ReadReq miss latency
917system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459 # average ReadReq miss latency
918system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency
919system.cpu.icache.demand_avg_miss_latency::total 13890.790459 # average overall miss latency
920system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459 # average overall miss latency
921system.cpu.icache.overall_avg_miss_latency::total 13890.790459 # average overall miss latency
922system.cpu.icache.blocked_cycles::no_mshrs 5929 # number of cycles access was blocked
923system.cpu.icache.blocked_cycles::no_targets 286 # number of cycles access was blocked
924system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
925system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
926system.cpu.icache.avg_blocked_cycles::no_mshrs 32.398907 # average number of cycles each access was blocked
927system.cpu.icache.avg_blocked_cycles::no_targets 286 # average number of cycles each access was blocked
928system.cpu.icache.fast_writes 0 # number of fast writes performed
929system.cpu.icache.cache_copies 0 # number of cache copies performed
930system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56033 # number of ReadReq MSHR hits
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932system.cpu.icache.demand_mshr_hits::cpu.inst 56033 # number of demand (read+write) MSHR hits
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934system.cpu.icache.overall_mshr_hits::cpu.inst 56033 # number of overall MSHR hits
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937system.cpu.icache.ReadReq_mshr_misses::total 1008776 # number of ReadReq MSHR misses
938system.cpu.icache.demand_mshr_misses::cpu.inst 1008776 # number of demand (read+write) MSHR misses
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940system.cpu.icache.overall_mshr_misses::cpu.inst 1008776 # number of overall MSHR misses
941system.cpu.icache.overall_mshr_misses::total 1008776 # number of overall MSHR misses
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943system.cpu.icache.ReadReq_mshr_miss_latency::total 12131918870 # number of ReadReq MSHR miss cycles
944system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12131918870 # number of demand (read+write) MSHR miss cycles
945system.cpu.icache.demand_mshr_miss_latency::total 12131918870 # number of demand (read+write) MSHR miss cycles
946system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12131918870 # number of overall MSHR miss cycles
947system.cpu.icache.overall_mshr_miss_latency::total 12131918870 # number of overall MSHR miss cycles
948system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for ReadReq accesses
949system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118103 # mshr miss rate for ReadReq accesses
950system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for demand accesses
951system.cpu.icache.demand_mshr_miss_rate::total 0.118103 # mshr miss rate for demand accesses
952system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118103 # mshr miss rate for overall accesses
953system.cpu.icache.overall_mshr_miss_rate::total 0.118103 # mshr miss rate for overall accesses
954system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399 # average ReadReq mshr miss latency
955system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399 # average ReadReq mshr miss latency
956system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency
957system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency
958system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399 # average overall mshr miss latency
959system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399 # average overall mshr miss latency
960system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
961system.cpu.l2cache.tags.replacements 338266 # number of replacements
962system.cpu.l2cache.tags.tagsinuse 65338.058683 # Cycle average of tags in use
963system.cpu.l2cache.tags.total_refs 2543929 # Total number of references to valid blocks.
964system.cpu.l2cache.tags.sampled_refs 403433 # Sample count of references to valid blocks.
965system.cpu.l2cache.tags.avg_refs 6.305704 # Average number of references to valid blocks.
966system.cpu.l2cache.tags.warmup_cycle 5551710750 # Cycle when the warmup percentage was hit.
967system.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722 # Average occupied blocks per requestor
968system.cpu.l2cache.tags.occ_blocks::cpu.inst 5304.345669 # Average occupied blocks per requestor
969system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.014293 # Average occupied blocks per requestor
970system.cpu.l2cache.tags.occ_percent::writebacks 0.820872 # Average percentage of cache occupancy
971system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080938 # Average percentage of cache occupancy
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973system.cpu.l2cache.tags.occ_percent::total 0.996980 # Average percentage of cache occupancy
974system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
975system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3493 # Occupied blocks per task id
977system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3306 # Occupied blocks per task id
978system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id
979system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55462 # Occupied blocks per task id
980system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
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982system.cpu.l2cache.tags.data_accesses 26707389 # Number of data accesses
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987system.cpu.l2cache.Writeback_hits::total 840541 # number of Writeback hits
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989system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
990system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
991system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
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993system.cpu.l2cache.ReadExReq_hits::total 185429 # number of ReadExReq hits
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999system.cpu.l2cache.overall_hits::total 2005499 # number of overall hits
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1002system.cpu.l2cache.ReadReq_misses::total 288824 # number of ReadReq misses
1003system.cpu.l2cache.UpgradeReq_misses::cpu.data 42 # number of UpgradeReq misses
1004system.cpu.l2cache.UpgradeReq_misses::total 42 # number of UpgradeReq misses
1005system.cpu.l2cache.ReadExReq_misses::cpu.data 115427 # number of ReadExReq misses
1006system.cpu.l2cache.ReadExReq_misses::total 115427 # number of ReadExReq misses
1007system.cpu.l2cache.demand_misses::cpu.inst 15053 # number of demand (read+write) misses
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1009system.cpu.l2cache.demand_misses::total 404251 # number of demand (read+write) misses
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1011system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses
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1014system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17964720233 # number of ReadReq miss cycles
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1016system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles
1017system.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles
1018system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9625411610 # number of ReadExReq miss cycles
1019system.cpu.l2cache.ReadExReq_miss_latency::total 9625411610 # number of ReadExReq miss cycles
1020system.cpu.l2cache.demand_miss_latency::cpu.inst 1161439993 # number of demand (read+write) miss cycles
1021system.cpu.l2cache.demand_miss_latency::cpu.data 27590131843 # number of demand (read+write) miss cycles
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1023system.cpu.l2cache.overall_miss_latency::cpu.inst 1161439993 # number of overall miss cycles
1024system.cpu.l2cache.overall_miss_latency::cpu.data 27590131843 # number of overall miss cycles
1025system.cpu.l2cache.overall_miss_latency::total 28751571836 # number of overall miss cycles
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1027system.cpu.l2cache.ReadReq_accesses::cpu.data 1100233 # number of ReadReq accesses(hits+misses)
1028system.cpu.l2cache.ReadReq_accesses::total 2108894 # number of ReadReq accesses(hits+misses)
1029system.cpu.l2cache.Writeback_accesses::writebacks 840541 # number of Writeback accesses(hits+misses)
1030system.cpu.l2cache.Writeback_accesses::total 840541 # number of Writeback accesses(hits+misses)
1031system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses)
1032system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses)
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1036system.cpu.l2cache.ReadExReq_accesses::total 300856 # number of ReadExReq accesses(hits+misses)
1037system.cpu.l2cache.demand_accesses::cpu.inst 1008661 # number of demand (read+write) accesses
1038system.cpu.l2cache.demand_accesses::cpu.data 1401089 # number of demand (read+write) accesses
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1040system.cpu.l2cache.overall_accesses::cpu.inst 1008661 # number of overall (read+write) accesses
1041system.cpu.l2cache.overall_accesses::cpu.data 1401089 # number of overall (read+write) accesses
1042system.cpu.l2cache.overall_accesses::total 2409750 # number of overall (read+write) accesses
1043system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014924 # miss rate for ReadReq accesses
1044system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248830 # miss rate for ReadReq accesses
1045system.cpu.l2cache.ReadReq_miss_rate::total 0.136955 # miss rate for ReadReq accesses
1046system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.677419 # miss rate for UpgradeReq accesses
1047system.cpu.l2cache.UpgradeReq_miss_rate::total 0.677419 # miss rate for UpgradeReq accesses
1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383662 # miss rate for ReadExReq accesses
1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.383662 # miss rate for ReadExReq accesses
1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014924 # miss rate for demand accesses
1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.277782 # miss rate for demand accesses
1052system.cpu.l2cache.demand_miss_rate::total 0.167756 # miss rate for demand accesses
1053system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014924 # miss rate for overall accesses
1054system.cpu.l2cache.overall_miss_rate::cpu.data 0.277782 # miss rate for overall accesses
1055system.cpu.l2cache.overall_miss_rate::total 0.167756 # miss rate for overall accesses
1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483 # average ReadReq miss latency
1057system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971 # average ReadReq miss latency
1058system.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457 # average ReadReq miss latency
1059system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6249.952381 # average UpgradeReq miss latency
1060system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6249.952381 # average UpgradeReq miss latency
1061system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173 # average ReadExReq miss latency
1062system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173 # average ReadExReq miss latency
1063system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency
1064system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency
1065system.cpu.l2cache.demand_avg_miss_latency::total 71123.069172 # average overall miss latency
1066system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483 # average overall miss latency
1067system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121 # average overall miss latency
1068system.cpu.l2cache.overall_avg_miss_latency::total 71123.069172 # average overall miss latency
1069system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1070system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1071system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1072system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1073system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1074system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1075system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1076system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1077system.cpu.l2cache.writebacks::writebacks 75916 # number of writebacks
1078system.cpu.l2cache.writebacks::total 75916 # number of writebacks
1079system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
1080system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1081system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1082system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
1083system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1084system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15052 # number of ReadReq MSHR misses
1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273771 # number of ReadReq MSHR misses
1087system.cpu.l2cache.ReadReq_mshr_misses::total 288823 # number of ReadReq MSHR misses
1088system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 42 # number of UpgradeReq MSHR misses
1089system.cpu.l2cache.UpgradeReq_mshr_misses::total 42 # number of UpgradeReq MSHR misses
1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115427 # number of ReadExReq MSHR misses
1091system.cpu.l2cache.ReadExReq_mshr_misses::total 115427 # number of ReadExReq MSHR misses
1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 15052 # number of demand (read+write) MSHR misses
1093system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::total 404250 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 15052 # number of overall MSHR misses
1096system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::total 404250 # number of overall MSHR misses
1098system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 971628757 # number of ReadReq MSHR miss cycles
1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14552447267 # number of ReadReq MSHR miss cycles
1100system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15524076024 # number of ReadReq MSHR miss cycles
1101system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 573037 # number of UpgradeReq MSHR miss cycles
1102system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 573037 # number of UpgradeReq MSHR miss cycles
1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8203174390 # number of ReadExReq MSHR miss cycles
1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8203174390 # number of ReadExReq MSHR miss cycles
1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 971628757 # number of demand (read+write) MSHR miss cycles
1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22755621657 # number of demand (read+write) MSHR miss cycles
1107system.cpu.l2cache.demand_mshr_miss_latency::total 23727250414 # number of demand (read+write) MSHR miss cycles
1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 971628757 # number of overall MSHR miss cycles
1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22755621657 # number of overall MSHR miss cycles
1110system.cpu.l2cache.overall_mshr_miss_latency::total 23727250414 # number of overall MSHR miss cycles
1111system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334007000 # number of ReadReq MSHR uncacheable cycles
1112system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334007000 # number of ReadReq MSHR uncacheable cycles
1113system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882413000 # number of WriteReq MSHR uncacheable cycles
1114system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882413000 # number of WriteReq MSHR uncacheable cycles
1115system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216420000 # number of overall MSHR uncacheable cycles
1116system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216420000 # number of overall MSHR uncacheable cycles
1117system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for ReadReq accesses
1118system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248830 # mshr miss rate for ReadReq accesses
1119system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136955 # mshr miss rate for ReadReq accesses
1120system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.677419 # mshr miss rate for UpgradeReq accesses
1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.677419 # mshr miss rate for UpgradeReq accesses
1122system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383662 # mshr miss rate for ReadExReq accesses
1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383662 # mshr miss rate for ReadExReq accesses
1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for demand accesses
1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277782 # mshr miss rate for demand accesses
1126system.cpu.l2cache.demand_mshr_miss_rate::total 0.167756 # mshr miss rate for demand accesses
1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014923 # mshr miss rate for overall accesses
1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277782 # mshr miss rate for overall accesses
1129system.cpu.l2cache.overall_mshr_miss_rate::total 0.167756 # mshr miss rate for overall accesses
1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64551.472030 # average ReadReq mshr miss latency
1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53155.547034 # average ReadReq mshr miss latency
1132system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53749.445245 # average ReadReq mshr miss latency
1133system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13643.738095 # average UpgradeReq mshr miss latency
1134system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095 # average UpgradeReq mshr miss latency
1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375 # average ReadExReq mshr miss latency
1136system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375 # average ReadExReq mshr miss latency
1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency
1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency
1139system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency
1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency
1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency
1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency
1143system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1144system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1145system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1146system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1147system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1148system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1149system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1150system.cpu.dcache.tags.replacements 1400496 # number of replacements
1151system.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use
1152system.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks.
1153system.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks.
1154system.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks.
1155system.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit.
1156system.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor
1157system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
1158system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
1159system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1160system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
1161system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
1162system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
1163system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1164system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses
1165system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses
1166system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits
1167system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits
1168system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits
1169system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits
1170system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits
1171system.cpu.dcache.LoadLockedReq_hits::total 186466 # number of LoadLockedReq hits
1172system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits
1173system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits
1174system.cpu.dcache.demand_hits::cpu.data 11409144 # number of demand (read+write) hits
1175system.cpu.dcache.demand_hits::total 11409144 # number of demand (read+write) hits
1176system.cpu.dcache.overall_hits::cpu.data 11409144 # number of overall hits
1177system.cpu.dcache.overall_hits::total 11409144 # number of overall hits
1178system.cpu.dcache.ReadReq_misses::cpu.data 1805019 # number of ReadReq misses
1179system.cpu.dcache.ReadReq_misses::total 1805019 # number of ReadReq misses
1180system.cpu.dcache.WriteReq_misses::cpu.data 1944584 # number of WriteReq misses
1181system.cpu.dcache.WriteReq_misses::total 1944584 # number of WriteReq misses
1182system.cpu.dcache.LoadLockedReq_misses::cpu.data 22688 # number of LoadLockedReq misses
1183system.cpu.dcache.LoadLockedReq_misses::total 22688 # number of LoadLockedReq misses
1184system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
1185system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
1186system.cpu.dcache.demand_misses::cpu.data 3749603 # number of demand (read+write) misses
1187system.cpu.dcache.demand_misses::total 3749603 # number of demand (read+write) misses
1188system.cpu.dcache.overall_misses::cpu.data 3749603 # number of overall misses
1189system.cpu.dcache.overall_misses::total 3749603 # number of overall misses
1190system.cpu.dcache.ReadReq_miss_latency::cpu.data 40356893890 # number of ReadReq miss cycles
1191system.cpu.dcache.ReadReq_miss_latency::total 40356893890 # number of ReadReq miss cycles
1192system.cpu.dcache.WriteReq_miss_latency::cpu.data 77719104532 # number of WriteReq miss cycles
1193system.cpu.dcache.WriteReq_miss_latency::total 77719104532 # number of WriteReq miss cycles
1194system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321753501 # number of LoadLockedReq miss cycles
1195system.cpu.dcache.LoadLockedReq_miss_latency::total 321753501 # number of LoadLockedReq miss cycles
1196system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
1197system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
1198system.cpu.dcache.demand_miss_latency::cpu.data 118075998422 # number of demand (read+write) miss cycles
1199system.cpu.dcache.demand_miss_latency::total 118075998422 # number of demand (read+write) miss cycles
1200system.cpu.dcache.overall_miss_latency::cpu.data 118075998422 # number of overall miss cycles
1201system.cpu.dcache.overall_miss_latency::total 118075998422 # number of overall miss cycles
1202system.cpu.dcache.ReadReq_accesses::cpu.data 9011151 # number of ReadReq accesses(hits+misses)
1203system.cpu.dcache.ReadReq_accesses::total 9011151 # number of ReadReq accesses(hits+misses)
1204system.cpu.dcache.WriteReq_accesses::cpu.data 6147596 # number of WriteReq accesses(hits+misses)
1205system.cpu.dcache.WriteReq_accesses::total 6147596 # number of WriteReq accesses(hits+misses)
1206system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209154 # number of LoadLockedReq accesses(hits+misses)
1207system.cpu.dcache.LoadLockedReq_accesses::total 209154 # number of LoadLockedReq accesses(hits+misses)
1208system.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses)
1209system.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses)
1210system.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses
1211system.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses
1212system.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses
1213system.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses
1214system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses
1215system.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses
1216system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses
1217system.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses
1218system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # miss rate for LoadLockedReq accesses
1219system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108475 # miss rate for LoadLockedReq accesses
1220system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
1221system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
1222system.cpu.dcache.demand_miss_rate::cpu.data 0.247356 # miss rate for demand accesses
1223system.cpu.dcache.demand_miss_rate::total 0.247356 # miss rate for demand accesses
1224system.cpu.dcache.overall_miss_rate::cpu.data 0.247356 # miss rate for overall accesses
1225system.cpu.dcache.overall_miss_rate::total 0.247356 # miss rate for overall accesses
1226system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618 # average ReadReq miss latency
1227system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618 # average ReadReq miss latency
1228system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702 # average WriteReq miss latency
1229system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702 # average WriteReq miss latency
1230system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952 # average LoadLockedReq miss latency
1231system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952 # average LoadLockedReq miss latency
1232system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
1233system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
1234system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency
1235system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency
1236system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency
1237system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency
1238system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked
1239system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked
1240system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked
1241system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
1242system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked
1243system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked
1244system.cpu.dcache.fast_writes 0 # number of fast writes performed
1245system.cpu.dcache.cache_copies 0 # number of cache copies performed
1246system.cpu.dcache.writebacks::writebacks 840541 # number of writebacks
1247system.cpu.dcache.writebacks::total 840541 # number of writebacks
1248system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721694 # number of ReadReq MSHR hits
1249system.cpu.dcache.ReadReq_mshr_hits::total 721694 # number of ReadReq MSHR hits
1250system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits
1251system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits
1252system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits
1253system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits
1254system.cpu.dcache.demand_mshr_hits::cpu.data 2366018 # number of demand (read+write) MSHR hits
1255system.cpu.dcache.demand_mshr_hits::total 2366018 # number of demand (read+write) MSHR hits
1256system.cpu.dcache.overall_mshr_hits::cpu.data 2366018 # number of overall MSHR hits
1257system.cpu.dcache.overall_mshr_hits::total 2366018 # number of overall MSHR hits
1258system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083325 # number of ReadReq MSHR misses
1259system.cpu.dcache.ReadReq_mshr_misses::total 1083325 # number of ReadReq MSHR misses
1260system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300260 # number of WriteReq MSHR misses
1261system.cpu.dcache.WriteReq_mshr_misses::total 300260 # number of WriteReq MSHR misses
1262system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17565 # number of LoadLockedReq MSHR misses
1263system.cpu.dcache.LoadLockedReq_mshr_misses::total 17565 # number of LoadLockedReq MSHR misses
1264system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
1265system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
1266system.cpu.dcache.demand_mshr_misses::cpu.data 1383585 # number of demand (read+write) MSHR misses
1267system.cpu.dcache.demand_mshr_misses::total 1383585 # number of demand (read+write) MSHR misses
1268system.cpu.dcache.overall_mshr_misses::cpu.data 1383585 # number of overall MSHR misses
1269system.cpu.dcache.overall_mshr_misses::total 1383585 # number of overall MSHR misses
1270system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27323478009 # number of ReadReq MSHR miss cycles
1271system.cpu.dcache.ReadReq_mshr_miss_latency::total 27323478009 # number of ReadReq MSHR miss cycles
1272system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11844407335 # number of WriteReq MSHR miss cycles
1273system.cpu.dcache.WriteReq_mshr_miss_latency::total 11844407335 # number of WriteReq MSHR miss cycles
1274system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200869499 # number of LoadLockedReq MSHR miss cycles
1275system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200869499 # number of LoadLockedReq MSHR miss cycles
1276system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
1277system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
1278system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles
1279system.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles
1280system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles
1281system.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles
1282system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles
1283system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles
1284system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles
1285system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles
1286system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles
1287system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles
1288system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses
1289system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses
1290system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses
1291system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses
1292system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses
1293system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses
1294system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
1295system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
1296system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses
1297system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses
1298system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses
1299system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses
1300system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency
1301system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency
1302system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency
1303system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency
1304system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency
1305system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency
1306system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
1307system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
1308system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency
1309system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency
1310system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency
1311system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency
1312system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1313system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1314system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1315system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1316system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1317system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1318system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1319system.cpu.kern.inst.arm 0 # number of arm instructions executed

--- 4 unchanged lines hidden (view full) ---

1324system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
1325system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl
1326system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl
1327system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1328system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
1329system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
1330system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
1331system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
1332system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl
1333system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl
1334system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl
1335system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl
1336system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl
1337system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
1338system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
1339system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1340system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl
1341system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl
1342system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
1343system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
1344system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed

--- 37 unchanged lines hidden (view full) ---

1382system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
1383system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
1384system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
1385system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
1386system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
1387system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
1388system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
1389system.cpu.kern.callpal::total 191963 # number of callpals executed
1390system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
1391system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
1392system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
1393system.cpu.kern.mode_good::kernel 1910
1394system.cpu.kern.mode_good::user 1740
1395system.cpu.kern.mode_good::idle 170
1396system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches
1397system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1398system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
1399system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
1400system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode
1401system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode
1402system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode
1403system.cpu.kern.swap_context 4177 # number of times the context was actually changed
1404
1405---------- End Simulation Statistics ----------