1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.854307 # Number of seconds simulated
4sim_ticks 1854307399500 # Number of ticks simulated
5final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 106006 # Simulator instruction rate (inst/s)
8host_op_rate 106006 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3711029376 # Simulator tick rate (ticks/s)
10host_mem_usage 333480 # Number of bytes of host memory used
11host_seconds 499.67 # Real time elapsed on the host
12sim_insts 52968721 # Number of instructions simulated
13sim_ops 52968721 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
17system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory
21system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory
24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.readReqs 445178 # Total number of read requests seen
42system.physmem.writeReqs 117206 # Total number of write requests seen
43system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady
44system.physmem.bytesRead 28491392 # Total number of bytes read from memory
45system.physmem.bytesWritten 7501184 # Total number of bytes written to memory
46system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize()
47system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize()
48system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q
49system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed
50system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis
66system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis
82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
83system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry
84system.physmem.totGap 1854301986000 # Total gap between requests
85system.physmem.readPktSize::0 0 # Categorize read packet sizes
86system.physmem.readPktSize::1 0 # Categorize read packet sizes
87system.physmem.readPktSize::2 0 # Categorize read packet sizes
88system.physmem.readPktSize::3 0 # Categorize read packet sizes
89system.physmem.readPktSize::4 0 # Categorize read packet sizes
90system.physmem.readPktSize::5 0 # Categorize read packet sizes
91system.physmem.readPktSize::6 445178 # Categorize read packet sizes
92system.physmem.writePktSize::0 0 # Categorize write packet sizes
93system.physmem.writePktSize::1 0 # Categorize write packet sizes
94system.physmem.writePktSize::2 0 # Categorize write packet sizes
95system.physmem.writePktSize::3 0 # Categorize write packet sizes
96system.physmem.writePktSize::4 0 # Categorize write packet sizes
97system.physmem.writePktSize::5 0 # Categorize write packet sizes
98system.physmem.writePktSize::6 117206 # Categorize write packet sizes
99system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
131system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
163system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays
164system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests
165system.physmem.totBusLat 2225595000 # Total cycles spent in databus access
166system.physmem.totBankLat 5484971250 # Total cycles spent in bank access
167system.physmem.avgQLat 16848.23 # Average queueing delay per request
168system.physmem.avgBankLat 12322.48 # Average bank access latency per request
169system.physmem.avgBusLat 5000.00 # Average bus latency per request
170system.physmem.avgMemAccLat 34170.72 # Average memory access latency
171system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s
172system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
173system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s
174system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
175system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
176system.physmem.busUtil 0.15 # Data bus utilization in percentage
177system.physmem.avgRdQLen 0.01 # Average read queue length over time
178system.physmem.avgWrQLen 14.44 # Average write queue length over time
179system.physmem.readRowHits 417746 # Number of row buffer hits during reads
180system.physmem.writeRowHits 91351 # Number of row buffer hits during writes
181system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads
182system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes
183system.physmem.avgGap 3297216.82 # Average gap between requests
184system.iocache.replacements 41685 # number of replacements
185system.iocache.tagsinuse 1.265036 # Cycle average of tags in use
186system.iocache.total_refs 0 # Total number of references to valid blocks.
187system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
188system.iocache.avg_refs 0 # Average number of references to valid blocks.
189system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit.
190system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor
191system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
192system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
193system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
194system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
195system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
196system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
197system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
198system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
199system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
200system.iocache.overall_misses::total 41725 # number of overall misses
201system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
202system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
203system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles
204system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles
205system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles
206system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles
207system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles
208system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles
209system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
210system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
211system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
212system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
213system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
214system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
215system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
216system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
217system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
218system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
219system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
220system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
221system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
222system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
223system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
224system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
225system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
226system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
227system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency
228system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency
229system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
230system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency
231system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency
232system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency
233system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked
234system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
235system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked
236system.iocache.blocked::no_targets 0 # number of cycles access was blocked
237system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked
238system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
239system.iocache.fast_writes 0 # number of fast writes performed
240system.iocache.cache_copies 0 # number of cache copies performed
241system.iocache.writebacks::writebacks 41512 # number of writebacks
242system.iocache.writebacks::total 41512 # number of writebacks
243system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
244system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
245system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
246system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
247system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
248system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
249system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
250system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
251system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
252system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
253system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles
254system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles
255system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles
256system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles
257system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles
258system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles
259system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
260system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
261system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
262system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
263system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
264system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
265system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
266system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
267system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
268system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
269system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency
270system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency
271system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
272system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
273system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency
274system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency
275system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
276system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
277system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
278system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
279system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
280system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
281system.disk0.dma_write_txs 395 # Number of DMA write transactions.
282system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
283system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
284system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
285system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
286system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
287system.disk2.dma_write_txs 1 # Number of DMA write transactions.
288system.cpu.branchPred.lookups 13852347 # Number of BP lookups
289system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted
290system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect
291system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups
292system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits
293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
294system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage
295system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target.
296system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions.
297system.cpu.dtb.fetch_hits 0 # ITB hits
298system.cpu.dtb.fetch_misses 0 # ITB misses
299system.cpu.dtb.fetch_acv 0 # ITB acv
300system.cpu.dtb.fetch_accesses 0 # ITB accesses
301system.cpu.dtb.read_hits 9912757 # DTB read hits
302system.cpu.dtb.read_misses 41466 # DTB read misses
303system.cpu.dtb.read_acv 543 # DTB read access violations
304system.cpu.dtb.read_accesses 941271 # DTB read accesses
305system.cpu.dtb.write_hits 6601987 # DTB write hits
306system.cpu.dtb.write_misses 10361 # DTB write misses
307system.cpu.dtb.write_acv 401 # DTB write access violations
308system.cpu.dtb.write_accesses 337783 # DTB write accesses
309system.cpu.dtb.data_hits 16514744 # DTB hits
310system.cpu.dtb.data_misses 51827 # DTB misses
311system.cpu.dtb.data_acv 944 # DTB access violations
312system.cpu.dtb.data_accesses 1279054 # DTB accesses
313system.cpu.itb.fetch_hits 1307981 # ITB hits
314system.cpu.itb.fetch_misses 36519 # ITB misses
315system.cpu.itb.fetch_acv 1105 # ITB acv
316system.cpu.itb.fetch_accesses 1344500 # ITB accesses
317system.cpu.itb.read_hits 0 # DTB read hits
318system.cpu.itb.read_misses 0 # DTB read misses
319system.cpu.itb.read_acv 0 # DTB read access violations
320system.cpu.itb.read_accesses 0 # DTB read accesses
321system.cpu.itb.write_hits 0 # DTB write hits
322system.cpu.itb.write_misses 0 # DTB write misses
323system.cpu.itb.write_acv 0 # DTB write access violations
324system.cpu.itb.write_accesses 0 # DTB write accesses
325system.cpu.itb.data_hits 0 # DTB hits
326system.cpu.itb.data_misses 0 # DTB misses
327system.cpu.itb.data_acv 0 # DTB access violations
328system.cpu.itb.data_accesses 0 # DTB accesses
329system.cpu.numCycles 108624305 # number of cpu cycles simulated
330system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
331system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
332system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss
333system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed
334system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered
335system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken
336system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked
337system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing
338system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked
339system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
340system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps
341system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions
342system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR
343system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched
344system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed
345system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total)
346system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total)
347system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total)
348system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
349system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total)
350system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle
363system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle
364system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle
365system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked
366system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running
367system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking
368system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing
369system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch
370system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction
371system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode
372system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode
373system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing
374system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle
375system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking
376system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst
377system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running
378system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking
379system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename
380system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full
381system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full
382system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full
383system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed
384system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made
385system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups
386system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups
387system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed
388system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing
389system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed
390system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed
391system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer
392system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit.
393system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit.
394system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads.
395system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores.
396system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec)
397system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ
398system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued
399system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued
400system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling
401system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph
402system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed
403system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle
406system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
407system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle
408system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle
409system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle
411system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle
412system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle
420system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
421system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available
422system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available
423system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available
424system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available
425system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available
426system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available
427system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available
428system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available
429system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available
450system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available
451system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available
452system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
453system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
454system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
455system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued
456system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued
457system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
458system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
459system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
460system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
461system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
462system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
463system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
482system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
483system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
484system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued
485system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued
486system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued
487system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
488system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued
489system.cpu.iq.rate 0.522989 # Inst issue rate
490system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested
491system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst)
492system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads
493system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes
494system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses
495system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads
496system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes
497system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses
498system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses
499system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses
500system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores
501system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
502system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed
503system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed
504system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations
505system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed
506system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
507system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
508system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled
509system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked
510system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
511system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing
512system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking
513system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking
514system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ
515system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch
516system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions
517system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions
518system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions
519system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall
520system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall
521system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations
522system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly
523system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly
524system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute
525system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions
526system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed
527system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute
528system.cpu.iew.exec_swp 0 # number of swp insts executed
529system.cpu.iew.exec_nop 3528457 # number of nop insts executed
530system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed
531system.cpu.iew.exec_branches 8925181 # Number of branches executed
532system.cpu.iew.exec_stores 6627584 # Number of stores executed
533system.cpu.iew.exec_rate 0.518660 # Inst execution rate
534system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit
535system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back
536system.cpu.iew.wb_producers 27773544 # num instructions producing a value
537system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value
538system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
539system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle
540system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back
541system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
542system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit
543system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards
544system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted
545system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle
546system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle
547system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle
548system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
549system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle
550system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle
551system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle
552system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle
553system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle
554system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle
562system.cpu.commit.committedInsts 56158922 # Number of instructions committed
563system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed
564system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
565system.cpu.commit.refs 15466723 # Number of memory references committed
566system.cpu.commit.loads 9090045 # Number of loads committed
567system.cpu.commit.membars 226335 # Number of memory barriers committed
568system.cpu.commit.branches 8439344 # Number of branches committed
569system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
570system.cpu.commit.int_insts 52009184 # Number of committed integer instructions.
571system.cpu.commit.function_calls 740395 # Number of function calls committed.
572system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached
573system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
574system.cpu.rob.rob_reads 140815408 # The number of ROB reads
575system.cpu.rob.rob_writes 128505533 # The number of ROB writes
576system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself
577system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling
578system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
579system.cpu.committedInsts 52968721 # Number of Instructions Simulated
580system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated
581system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated
582system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction
583system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads
584system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle
585system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads
586system.cpu.int_regfile_reads 73881531 # number of integer regfile reads
587system.cpu.int_regfile_writes 40312822 # number of integer regfile writes
588system.cpu.fp_regfile_reads 166061 # number of floating regfile reads
589system.cpu.fp_regfile_writes 167429 # number of floating regfile writes
590system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads
591system.cpu.misc_regfile_writes 938918 # number of misc regfile writes
592system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
593system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
594system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
595system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
596system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
597system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
598system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
599system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

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615system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
616system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
617system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
618system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
619system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
620system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
621system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
622system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
623system.cpu.icache.replacements 1008795 # number of replacements
624system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use
625system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks.
626system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks.
627system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks.
628system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit.
629system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor
630system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy
631system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy
632system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits
633system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits
634system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits
635system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits
636system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits
637system.cpu.icache.overall_hits::total 7484837 # number of overall hits
638system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses
639system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses
640system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses
641system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses
642system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses
643system.cpu.icache.overall_misses::total 1065140 # number of overall misses
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645system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles
646system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles
647system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles
648system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles
649system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles
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651system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses)
652system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses
653system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses
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655system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses
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657system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses
658system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses
659system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses
660system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses
661system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses
662system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency
663system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency
664system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency
665system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency
666system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency
667system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency
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669system.cpu.icache.blocked_cycles::no_targets 1606 # number of cycles access was blocked
670system.cpu.icache.blocked::no_mshrs 164 # number of cycles access was blocked
671system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
672system.cpu.icache.avg_blocked_cycles::no_mshrs 43.426829 # average number of cycles each access was blocked
673system.cpu.icache.avg_blocked_cycles::no_targets 803 # average number of cycles each access was blocked
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678system.cpu.icache.demand_mshr_hits::cpu.inst 55619 # number of demand (read+write) MSHR hits
679system.cpu.icache.demand_mshr_hits::total 55619 # number of demand (read+write) MSHR hits
680system.cpu.icache.overall_mshr_hits::cpu.inst 55619 # number of overall MSHR hits
681system.cpu.icache.overall_mshr_hits::total 55619 # number of overall MSHR hits
682system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009521 # number of ReadReq MSHR misses
683system.cpu.icache.ReadReq_mshr_misses::total 1009521 # number of ReadReq MSHR misses
684system.cpu.icache.demand_mshr_misses::cpu.inst 1009521 # number of demand (read+write) MSHR misses
685system.cpu.icache.demand_mshr_misses::total 1009521 # number of demand (read+write) MSHR misses
686system.cpu.icache.overall_mshr_misses::cpu.inst 1009521 # number of overall MSHR misses
687system.cpu.icache.overall_mshr_misses::total 1009521 # number of overall MSHR misses
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689system.cpu.icache.ReadReq_mshr_miss_latency::total 12035617996 # number of ReadReq MSHR miss cycles
690system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12035617996 # number of demand (read+write) MSHR miss cycles
691system.cpu.icache.demand_mshr_miss_latency::total 12035617996 # number of demand (read+write) MSHR miss cycles
692system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12035617996 # number of overall MSHR miss cycles
693system.cpu.icache.overall_mshr_miss_latency::total 12035617996 # number of overall MSHR miss cycles
694system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for ReadReq accesses
695system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118073 # mshr miss rate for ReadReq accesses
696system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for demand accesses
697system.cpu.icache.demand_mshr_miss_rate::total 0.118073 # mshr miss rate for demand accesses
698system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118073 # mshr miss rate for overall accesses
699system.cpu.icache.overall_mshr_miss_rate::total 0.118073 # mshr miss rate for overall accesses
700system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.107609 # average ReadReq mshr miss latency
701system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.107609 # average ReadReq mshr miss latency
702system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency
703system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency
704system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.107609 # average overall mshr miss latency
705system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.107609 # average overall mshr miss latency
706system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
707system.cpu.l2cache.replacements 338260 # number of replacements
708system.cpu.l2cache.tagsinuse 65365.866515 # Cycle average of tags in use
709system.cpu.l2cache.total_refs 2544525 # Total number of references to valid blocks.
710system.cpu.l2cache.sampled_refs 403426 # Sample count of references to valid blocks.
711system.cpu.l2cache.avg_refs 6.307291 # Average number of references to valid blocks.
712system.cpu.l2cache.warmup_cycle 4078120751 # Cycle when the warmup percentage was hit.
713system.cpu.l2cache.occ_blocks::writebacks 53972.516540 # Average occupied blocks per requestor
714system.cpu.l2cache.occ_blocks::cpu.inst 5322.981591 # Average occupied blocks per requestor
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716system.cpu.l2cache.occ_percent::writebacks 0.823555 # Average percentage of cache occupancy
717system.cpu.l2cache.occ_percent::cpu.inst 0.081222 # Average percentage of cache occupancy
718system.cpu.l2cache.occ_percent::cpu.data 0.092626 # Average percentage of cache occupancy
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723system.cpu.l2cache.Writeback_hits::writebacks 840320 # number of Writeback hits
724system.cpu.l2cache.Writeback_hits::total 840320 # number of Writeback hits
725system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits
726system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits
727system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
728system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
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730system.cpu.l2cache.ReadExReq_hits::total 185342 # number of ReadExReq hits
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740system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses
741system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses
742system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
743system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
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745system.cpu.l2cache.ReadExReq_misses::total 115395 # number of ReadExReq misses
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771system.cpu.l2cache.Writeback_accesses::total 840320 # number of Writeback accesses(hits+misses)
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792system.cpu.l2cache.ReadExReq_miss_rate::total 0.383707 # miss rate for ReadExReq accesses
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798system.cpu.l2cache.overall_miss_rate::total 0.167687 # miss rate for overall accesses
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802system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7435.897436 # average UpgradeReq miss latency
803system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7435.897436 # average UpgradeReq miss latency
804system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11500 # average SCUpgradeReq miss latency
805system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11500 # average SCUpgradeReq miss latency
806system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66026.725595 # average ReadExReq miss latency
807system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66026.725595 # average ReadExReq miss latency
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856system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles
857system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles
858system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles
859system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles
860system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles
861system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles
862system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles
863system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles
864system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles
865system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles
866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses
867system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses
868system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses
869system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses
870system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses
871system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
872system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
873system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses
874system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses
875system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses
876system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses
877system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses
878system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses
879system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses
880system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses
881system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency
882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency
883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency
884system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency
885system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency
886system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
887system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency
889system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency
890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency
891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency
892system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency
893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency
894system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency
895system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency
896system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
897system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
898system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
899system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
901system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
902system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
903system.cpu.dcache.replacements 1400597 # number of replacements
904system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use
905system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks.
906system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks.
907system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks.
908system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit.
909system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor
910system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
911system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
912system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits
913system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits
914system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits
915system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits
916system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits
917system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits
918system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits
919system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits
920system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits
921system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits
922system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits
923system.cpu.dcache.overall_hits::total 11402525 # number of overall hits
924system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses
925system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses
926system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses
927system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses
928system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses
929system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses
930system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
931system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
932system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses
933system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses
934system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses
935system.cpu.dcache.overall_misses::total 3745583 # number of overall misses
936system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles
937system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles
938system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles
939system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles
940system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles
941system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles
942system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles
943system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles
944system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles
945system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles
946system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles
947system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles
948system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses)
949system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses)
950system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses)
951system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses)
952system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses)
953system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses)
954system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses)
955system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses)
956system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses
957system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses
958system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses
959system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses
960system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses
961system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses
962system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses
963system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses
964system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses
965system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses
966system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses
967system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses
968system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses
969system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses
970system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses
971system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses
972system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency
973system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency
974system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency
975system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency
976system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency
977system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency
978system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency
979system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency
980system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
981system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency
982system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency
983system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency
984system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked
985system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked
986system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked
987system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
988system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked
989system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked
990system.cpu.dcache.fast_writes 0 # number of fast writes performed
991system.cpu.dcache.cache_copies 0 # number of cache copies performed
992system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks
993system.cpu.dcache.writebacks::total 840320 # number of writebacks
994system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits
995system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits
996system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits
997system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits
998system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits
999system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits
1000system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits
1001system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits
1002system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits
1003system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits
1004system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses
1005system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses
1006system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses
1007system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses
1008system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses
1009system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses
1010system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
1011system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
1012system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses
1013system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses
1014system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses
1015system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses
1016system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles
1017system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles
1018system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles
1019system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles
1020system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles
1021system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles
1022system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles
1023system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles
1024system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles
1025system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles
1026system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles
1027system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles
1028system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles
1029system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles
1030system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles
1031system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles
1032system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles
1033system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles
1034system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses
1035system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses
1036system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses
1037system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses
1038system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses
1039system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses
1040system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
1041system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
1042system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses
1043system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses
1044system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses
1045system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses
1046system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency
1047system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency
1048system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency
1049system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency
1050system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency
1051system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency
1052system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency
1053system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency
1054system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
1055system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
1056system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency
1057system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency
1058system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1059system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1060system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1061system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1062system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1063system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1064system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1065system.cpu.kern.inst.arm 0 # number of arm instructions executed
1066system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
1067system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed
1068system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl
1069system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
1070system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
1071system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl
1072system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl
1073system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1074system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
1075system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
1076system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl
1077system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl
1078system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl
1079system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl
1080system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl
1081system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl
1082system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl
1083system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
1084system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
1085system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1086system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl
1087system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl
1088system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
1089system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
1090system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
1091system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
1092system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
1093system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
1094system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
1095system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed

--- 22 unchanged lines hidden (view full) ---

1118system.cpu.kern.syscall::total 326 # number of syscalls executed
1119system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1120system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
1121system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
1122system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
1123system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
1124system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
1125system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
1126system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed
1127system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
1128system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
1129system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
1130system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
1131system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
1132system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
1133system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
1134system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
1135system.cpu.kern.callpal::total 191959 # number of callpals executed
1136system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
1137system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
1138system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
1139system.cpu.kern.mode_good::kernel 1910
1140system.cpu.kern.mode_good::user 1740
1141system.cpu.kern.mode_good::idle 170
1142system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches
1143system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1144system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
1145system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
1146system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode
1147system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode
1148system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode
1149system.cpu.kern.swap_context 4177 # number of times the context was actually changed
1150
1151---------- End Simulation Statistics ----------