1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.865014 # Number of seconds simulated
4sim_ticks 1865014104500 # Number of ticks simulated
5final_tick 1865014104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 231832 # Simulator instruction rate (inst/s)
8host_op_rate 231832 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 8163594872 # Simulator tick rate (ticks/s)
10host_mem_usage 339292 # Number of bytes of host memory used
11host_seconds 228.46 # Real time elapsed on the host
12sim_insts 52963270 # Number of instructions simulated
13sim_ops 52963270 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 962304 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory
19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20system.physmem.bytes_read::total 25843264 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 962304 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 962304 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7514304 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7514304 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 15036 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 403801 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 117411 # Number of write requests responded to by this memory
30system.physmem.num_writes::total 117411 # Number of write requests responded to by this memory
31system.physmem.bw_read::cpu.inst 515977 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.data 13340382 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 13856873 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 515977 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 515977 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 4029087 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 4029087 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 4029087 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.inst 515977 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.data 13340382 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::total 17885960 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.readReqs 403801 # Number of read requests accepted
45system.physmem.writeReqs 117411 # Number of write requests accepted
46system.physmem.readBursts 403801 # Number of DRAM read bursts, including those serviced by the write queue
47system.physmem.writeBursts 117411 # Number of DRAM write bursts, including those merged in the write queue
48system.physmem.bytesReadDRAM 25836480 # Total number of bytes read from DRAM
49system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue
50system.physmem.bytesWritten 7512704 # Total number of bytes written to DRAM
51system.physmem.bytesReadSys 25843264 # Total read bytes from the system interface side
52system.physmem.bytesWrittenSys 7514304 # Total written bytes from the system interface side
53system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue
54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
56system.physmem.perBankRdBursts::0 25442 # Per bank write bursts
57system.physmem.perBankRdBursts::1 25616 # Per bank write bursts
58system.physmem.perBankRdBursts::2 25500 # Per bank write bursts
59system.physmem.perBankRdBursts::3 25612 # Per bank write bursts
60system.physmem.perBankRdBursts::4 25113 # Per bank write bursts
61system.physmem.perBankRdBursts::5 25182 # Per bank write bursts
62system.physmem.perBankRdBursts::6 24743 # Per bank write bursts
63system.physmem.perBankRdBursts::7 24567 # Per bank write bursts
64system.physmem.perBankRdBursts::8 25026 # Per bank write bursts
65system.physmem.perBankRdBursts::9 25298 # Per bank write bursts
66system.physmem.perBankRdBursts::10 25283 # Per bank write bursts
67system.physmem.perBankRdBursts::11 25011 # Per bank write bursts
68system.physmem.perBankRdBursts::12 24384 # Per bank write bursts
69system.physmem.perBankRdBursts::13 25424 # Per bank write bursts
70system.physmem.perBankRdBursts::14 25804 # Per bank write bursts
71system.physmem.perBankRdBursts::15 25690 # Per bank write bursts
72system.physmem.perBankWrBursts::0 7803 # Per bank write bursts
73system.physmem.perBankWrBursts::1 7588 # Per bank write bursts
74system.physmem.perBankWrBursts::2 7778 # Per bank write bursts
75system.physmem.perBankWrBursts::3 7603 # Per bank write bursts
76system.physmem.perBankWrBursts::4 7231 # Per bank write bursts
77system.physmem.perBankWrBursts::5 7190 # Per bank write bursts
78system.physmem.perBankWrBursts::6 6745 # Per bank write bursts
79system.physmem.perBankWrBursts::7 6418 # Per bank write bursts
80system.physmem.perBankWrBursts::8 7146 # Per bank write bursts
81system.physmem.perBankWrBursts::9 6920 # Per bank write bursts
82system.physmem.perBankWrBursts::10 7197 # Per bank write bursts
83system.physmem.perBankWrBursts::11 7005 # Per bank write bursts
84system.physmem.perBankWrBursts::12 6963 # Per bank write bursts
85system.physmem.perBankWrBursts::13 7878 # Per bank write bursts
86system.physmem.perBankWrBursts::14 8018 # Per bank write bursts
87system.physmem.perBankWrBursts::15 7903 # Per bank write bursts
88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
89system.physmem.numWrRetry 61 # Number of times write queue was full causing retry
90system.physmem.totGap 1865008869500 # Total gap between requests
91system.physmem.readPktSize::0 0 # Read request sizes (log2)
92system.physmem.readPktSize::1 0 # Read request sizes (log2)
93system.physmem.readPktSize::2 0 # Read request sizes (log2)
94system.physmem.readPktSize::3 0 # Read request sizes (log2)
95system.physmem.readPktSize::4 0 # Read request sizes (log2)
96system.physmem.readPktSize::5 0 # Read request sizes (log2)
97system.physmem.readPktSize::6 403801 # Read request sizes (log2)
98system.physmem.writePktSize::0 0 # Write request sizes (log2)
99system.physmem.writePktSize::1 0 # Write request sizes (log2)
100system.physmem.writePktSize::2 0 # Write request sizes (log2)
101system.physmem.writePktSize::3 0 # Write request sizes (log2)
102system.physmem.writePktSize::4 0 # Write request sizes (log2)
103system.physmem.writePktSize::5 0 # Write request sizes (log2)
104system.physmem.writePktSize::6 117411 # Write request sizes (log2)
105system.physmem.rdQLenPdf::0 314099 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::1 36538 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::2 28723 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::3 24204 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::4 112 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see

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144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::15 1448 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::16 2637 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::17 3274 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::18 4234 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::19 5587 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::20 6330 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::21 7129 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::22 8248 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::23 6711 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::24 7309 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::25 7904 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::26 7622 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::27 6934 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::28 6969 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::29 6828 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::30 7215 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::31 6061 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::32 6274 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::33 775 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::38 294 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::39 279 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::40 270 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::41 240 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::42 260 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::43 347 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::44 358 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::49 355 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::53 196 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::56 291 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::57 216 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::59 341 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::60 267 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::61 194 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see
201system.physmem.bytesPerActivate::samples 61269 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::mean 544.301360 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::gmean 334.095290 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::stdev 417.294475 # Bytes accessed per row activation
205system.physmem.bytesPerActivate::0-127 13441 21.94% 21.94% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::128-255 10649 17.38% 39.32% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::256-383 4420 7.21% 46.53% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::384-511 2704 4.41% 50.95% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::512-639 2252 3.68% 54.62% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::640-767 1833 2.99% 57.61% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::768-895 1848 3.02% 60.63% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::896-1023 1534 2.50% 63.13% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::1024-1151 22588 36.87% 100.00% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::total 61269 # Bytes accessed per row activation
215system.physmem.rdPerTurnAround::samples 5165 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::mean 78.156438 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 2937.375866 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-8191 5162 99.94% 99.94% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::total 5165 # Reads before turning the bus around for writes
223system.physmem.wrPerTurnAround::samples 5165 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::mean 22.727202 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::gmean 18.973066 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::stdev 23.761118 # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::16-23 4630 89.64% 89.64% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::24-31 34 0.66% 90.30% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::32-39 183 3.54% 93.84% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::40-47 6 0.12% 93.96% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::48-55 3 0.06% 94.02% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::56-63 17 0.33% 94.35% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::64-71 10 0.19% 94.54% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::72-79 3 0.06% 94.60% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::80-87 30 0.58% 95.18% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::88-95 4 0.08% 95.26% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::96-103 158 3.06% 98.32% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::104-111 16 0.31% 98.63% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::112-119 13 0.25% 98.88% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::120-127 4 0.08% 98.95% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::128-135 6 0.12% 99.07% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::136-143 2 0.04% 99.11% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::144-151 1 0.02% 99.13% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::152-159 2 0.04% 99.17% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::160-167 3 0.06% 99.23% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::168-175 6 0.12% 99.34% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::176-183 6 0.12% 99.46% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::184-191 9 0.17% 99.63% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::192-199 8 0.15% 99.79% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::216-223 5 0.10% 99.92% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::total 5165 # Writes before turning the bus around for reads
256system.physmem.totQLat 7762770500 # Total ticks spent queuing
257system.physmem.totMemAccLat 15332051750 # Total ticks spent from burst creation until serviced by the DRAM
258system.physmem.totBusLat 2018475000 # Total ticks spent in databus transfers
259system.physmem.avgQLat 19229.30 # Average queueing delay per DRAM burst
260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
261system.physmem.avgMemAccLat 37979.30 # Average memory access latency per DRAM burst
262system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s
263system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
264system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s
265system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s
266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
267system.physmem.busUtil 0.14 # Data bus utilization in percentage
268system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
269system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
270system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing
271system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing
272system.physmem.readRowHits 364450 # Number of row buffer hits during reads
273system.physmem.writeRowHits 95361 # Number of row buffer hits during writes
274system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
275system.physmem.writeRowHitRate 81.22 # Row buffer hit rate for writes
276system.physmem.avgGap 3578215.52 # Average gap between requests
277system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined
278system.physmem_0.actEnergy 215406660 # Energy for activate commands per rank (pJ)
279system.physmem_0.preEnergy 114491355 # Energy for precharge commands per rank (pJ)
280system.physmem_0.readEnergy 1440673500 # Energy for read commands per rank (pJ)
281system.physmem_0.writeEnergy 304618320 # Energy for write commands per rank (pJ)
282system.physmem_0.refreshEnergy 3636824880.000001 # Energy for refresh commands per rank (pJ)
283system.physmem_0.actBackEnergy 4141323030 # Energy for active background per rank (pJ)
284system.physmem_0.preBackEnergy 240547200 # Energy for precharge background per rank (pJ)
285system.physmem_0.actPowerDownEnergy 8014976340 # Energy for active power-down per rank (pJ)
286system.physmem_0.prePowerDownEnergy 4268063520 # Energy for precharge power-down per rank (pJ)
287system.physmem_0.selfRefreshEnergy 438971983965 # Energy for self refresh per rank (pJ)
288system.physmem_0.totalEnergy 461349368400 # Total energy per rank (pJ)
289system.physmem_0.averagePower 247.370445 # Core power per rank (mW)
290system.physmem_0.totalIdleTime 1855266278000 # Total Idle time Per DRAM Rank
291system.physmem_0.memoryStateTime::IDLE 380549250 # Time in different power states
292system.physmem_0.memoryStateTime::REF 1544966000 # Time in different power states
293system.physmem_0.memoryStateTime::SREF 1826613361750 # Time in different power states
294system.physmem_0.memoryStateTime::PRE_PDN 11114845500 # Time in different power states
295system.physmem_0.memoryStateTime::ACT 7783583250 # Time in different power states
296system.physmem_0.memoryStateTime::ACT_PDN 17576798750 # Time in different power states
297system.physmem_1.actEnergy 222061140 # Energy for activate commands per rank (pJ)
298system.physmem_1.preEnergy 118024500 # Energy for precharge commands per rank (pJ)
299system.physmem_1.readEnergy 1441708800 # Energy for read commands per rank (pJ)
300system.physmem_1.writeEnergy 308136600 # Energy for write commands per rank (pJ)
301system.physmem_1.refreshEnergy 3631907760.000001 # Energy for refresh commands per rank (pJ)
302system.physmem_1.actBackEnergy 4166934840 # Energy for active background per rank (pJ)
303system.physmem_1.preBackEnergy 235115520 # Energy for precharge background per rank (pJ)
304system.physmem_1.actPowerDownEnergy 8062896810 # Energy for active power-down per rank (pJ)
305system.physmem_1.prePowerDownEnergy 4253243040 # Energy for precharge power-down per rank (pJ)
306system.physmem_1.selfRefreshEnergy 438933503490 # Energy for self refresh per rank (pJ)
307system.physmem_1.totalEnergy 461375149740 # Total energy per rank (pJ)
308system.physmem_1.averagePower 247.384267 # Core power per rank (mW)
309system.physmem_1.totalIdleTime 1855254817500 # Total Idle time Per DRAM Rank
310system.physmem_1.memoryStateTime::IDLE 370314000 # Time in different power states
311system.physmem_1.memoryStateTime::REF 1542730000 # Time in different power states
312system.physmem_1.memoryStateTime::SREF 1826502260750 # Time in different power states
313system.physmem_1.memoryStateTime::PRE_PDN 11076094000 # Time in different power states
314system.physmem_1.memoryStateTime::ACT 7841044250 # Time in different power states
315system.physmem_1.memoryStateTime::ACT_PDN 17681661500 # Time in different power states
316system.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
317system.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
318system.cpu.branchPred.lookups 19565204 # Number of BP lookups
319system.cpu.branchPred.condPredicted 16626727 # Number of conditional branches predicted
320system.cpu.branchPred.condIncorrect 606351 # Number of conditional branches incorrect
321system.cpu.branchPred.BTBLookups 12911299 # Number of BTB lookups
322system.cpu.branchPred.BTBHits 5422453 # Number of BTB hits
323system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
324system.cpu.branchPred.BTBHitPct 41.997734 # BTB Hit Percentage
325system.cpu.branchPred.usedRAS 1125914 # Number of times the RAS was used to get a target.
326system.cpu.branchPred.RASInCorrect 42947 # Number of incorrect RAS predictions.
327system.cpu.branchPred.indirectLookups 6343232 # Number of indirect predictor lookups.
328system.cpu.branchPred.indirectHits 564019 # Number of indirect target hits.
329system.cpu.branchPred.indirectMisses 5779213 # Number of indirect misses.
330system.cpu.branchPredindirectMispredicted 264491 # Number of mispredicted indirect branches.
331system.cpu_clk_domain.clock 500 # Clock period in ticks
332system.cpu.dtb.fetch_hits 0 # ITB hits
333system.cpu.dtb.fetch_misses 0 # ITB misses
334system.cpu.dtb.fetch_acv 0 # ITB acv
335system.cpu.dtb.fetch_accesses 0 # ITB accesses
336system.cpu.dtb.read_hits 11109232 # DTB read hits
337system.cpu.dtb.read_misses 50748 # DTB read misses
338system.cpu.dtb.read_acv 615 # DTB read access violations
339system.cpu.dtb.read_accesses 993788 # DTB read accesses
340system.cpu.dtb.write_hits 6757496 # DTB write hits
341system.cpu.dtb.write_misses 12693 # DTB write misses
342system.cpu.dtb.write_acv 420 # DTB write access violations
343system.cpu.dtb.write_accesses 345501 # DTB write accesses
344system.cpu.dtb.data_hits 17866728 # DTB hits
345system.cpu.dtb.data_misses 63441 # DTB misses
346system.cpu.dtb.data_acv 1035 # DTB access violations
347system.cpu.dtb.data_accesses 1339289 # DTB accesses
348system.cpu.itb.fetch_hits 1817930 # ITB hits
349system.cpu.itb.fetch_misses 10423 # ITB misses
350system.cpu.itb.fetch_acv 754 # ITB acv
351system.cpu.itb.fetch_accesses 1828353 # ITB accesses
352system.cpu.itb.read_hits 0 # DTB read hits
353system.cpu.itb.read_misses 0 # DTB read misses
354system.cpu.itb.read_acv 0 # DTB read access violations
355system.cpu.itb.read_accesses 0 # DTB read accesses
356system.cpu.itb.write_hits 0 # DTB write hits
357system.cpu.itb.write_misses 0 # DTB write misses
358system.cpu.itb.write_acv 0 # DTB write access violations
359system.cpu.itb.write_accesses 0 # DTB write accesses
360system.cpu.itb.data_hits 0 # DTB hits
361system.cpu.itb.data_misses 0 # DTB misses
362system.cpu.itb.data_acv 0 # DTB access violations
363system.cpu.itb.data_accesses 0 # DTB accesses
364system.cpu.numPwrStateTransitions 12882 # Number of power state transitions
365system.cpu.pwrStateClkGateDist::samples 6441 # Distribution of time spent in the clock gated state
366system.cpu.pwrStateClkGateDist::mean 279499621.875485 # Distribution of time spent in the clock gated state
367system.cpu.pwrStateClkGateDist::stdev 438940062.434372 # Distribution of time spent in the clock gated state
368system.cpu.pwrStateClkGateDist::1000-5e+10 6441 100.00% 100.00% # Distribution of time spent in the clock gated state
369system.cpu.pwrStateClkGateDist::min_value 80500 # Distribution of time spent in the clock gated state
370system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
371system.cpu.pwrStateClkGateDist::total 6441 # Distribution of time spent in the clock gated state
372system.cpu.pwrStateResidencyTicks::ON 64757040000 # Cumulative time (in ticks) in various power states
373system.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500 # Cumulative time (in ticks) in various power states
374system.cpu.numCycles 129520522 # number of cpu cycles simulated
375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
377system.cpu.fetch.icacheStallCycles 30117726 # Number of cycles fetch is stalled on an Icache miss
378system.cpu.fetch.Insts 85842784 # Number of instructions fetch has processed
379system.cpu.fetch.Branches 19565204 # Number of branches that fetch encountered
380system.cpu.fetch.predictedBranches 7112386 # Number of branches that fetch has predicted taken
381system.cpu.fetch.Cycles 91831627 # Number of cycles fetch has run and was not squashing or blocked
382system.cpu.fetch.SquashCycles 1707334 # Number of cycles fetch has spent squashing
383system.cpu.fetch.TlbCycles 94 # Number of cycles fetch has spent waiting for tlb
384system.cpu.fetch.MiscStallCycles 30324 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
385system.cpu.fetch.PendingTrapStallCycles 206515 # Number of stall cycles due to pending traps
386system.cpu.fetch.PendingQuiesceStallCycles 432806 # Number of stall cycles due to pending quiesce instructions
387system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR
388system.cpu.fetch.CacheLines 9953050 # Number of cache lines fetched
389system.cpu.fetch.IcacheSquashes 416768 # Number of outstanding Icache misses that were squashed
390system.cpu.fetch.rateDist::samples 123473258 # Number of instructions fetched each cycle (Total)
391system.cpu.fetch.rateDist::mean 0.695234 # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.rateDist::stdev 2.025215 # Number of instructions fetched each cycle (Total)
393system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
394system.cpu.fetch.rateDist::0 107617936 87.16% 87.16% # Number of instructions fetched each cycle (Total)
395system.cpu.fetch.rateDist::1 1029887 0.83% 87.99% # Number of instructions fetched each cycle (Total)
396system.cpu.fetch.rateDist::2 2106014 1.71% 89.70% # Number of instructions fetched each cycle (Total)
397system.cpu.fetch.rateDist::3 969195 0.78% 90.48% # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::4 2907839 2.36% 92.84% # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::5 668408 0.54% 93.38% # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::6 818971 0.66% 94.04% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::7 1034002 0.84% 94.88% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::8 6321006 5.12% 100.00% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::total 123473258 # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.branchRate 0.151059 # Number of branch fetches per cycle
408system.cpu.fetch.rate 0.662774 # Number of inst fetches per cycle
409system.cpu.decode.IdleCycles 24152038 # Number of cycles decode is idle
410system.cpu.decode.BlockedCycles 86201336 # Number of cycles decode is blocked
411system.cpu.decode.RunCycles 10258063 # Number of cycles decode is running
412system.cpu.decode.UnblockCycles 2042752 # Number of cycles decode is unblocking
413system.cpu.decode.SquashCycles 819068 # Number of cycles decode is squashing
414system.cpu.decode.BranchResolved 5235547 # Number of times decode resolved a branch
415system.cpu.decode.BranchMispred 36008 # Number of times decode detected a branch misprediction
416system.cpu.decode.DecodedInsts 74118733 # Number of instructions handled by decode
417system.cpu.decode.SquashedInsts 112337 # Number of squashed instructions handled by decode
418system.cpu.rename.SquashCycles 819068 # Number of cycles rename is squashing
419system.cpu.rename.IdleCycles 25161583 # Number of cycles rename is idle
420system.cpu.rename.BlockCycles 56623083 # Number of cycles rename is blocking
421system.cpu.rename.serializeStallCycles 20020475 # count of cycles rename stalled for serializing inst
422system.cpu.rename.RunCycles 11228852 # Number of cycles rename is running
423system.cpu.rename.UnblockCycles 9620195 # Number of cycles rename is unblocking
424system.cpu.rename.RenamedInsts 71027053 # Number of instructions processed by rename
425system.cpu.rename.ROBFullEvents 203339 # Number of times rename has blocked due to ROB full
426system.cpu.rename.IQFullEvents 2122213 # Number of times rename has blocked due to IQ full
427system.cpu.rename.LQFullEvents 263594 # Number of times rename has blocked due to LQ full
428system.cpu.rename.SQFullEvents 5326402 # Number of times rename has blocked due to SQ full
429system.cpu.rename.RenamedOperands 47839712 # Number of destination operands rename has renamed
430system.cpu.rename.RenameLookups 85552570 # Number of register rename lookups that rename has made
431system.cpu.rename.int_rename_lookups 85371726 # Number of integer rename lookups
432system.cpu.rename.fp_rename_lookups 168391 # Number of floating rename lookups
433system.cpu.rename.CommittedMaps 38166163 # Number of HB maps that are committed
434system.cpu.rename.UndoneMaps 9673541 # Number of HB maps that are undone due to squashing
435system.cpu.rename.serializingInsts 1731851 # count of serializing insts renamed
436system.cpu.rename.tempSerializingInsts 279206 # count of temporary serializing insts renamed
437system.cpu.rename.skidInsts 13863805 # count of insts added to the skid buffer
438system.cpu.memDep0.insertedLoads 11669742 # Number of loads inserted to the mem dependence unit.
439system.cpu.memDep0.insertedStores 7218714 # Number of stores inserted to the mem dependence unit.
440system.cpu.memDep0.conflictingLoads 1729922 # Number of conflicting loads.
441system.cpu.memDep0.conflictingStores 1107908 # Number of conflicting stores.
442system.cpu.iq.iqInstsAdded 62661067 # Number of instructions added to the IQ (excludes non-spec)
443system.cpu.iq.iqNonSpecInstsAdded 2212545 # Number of non-speculative instructions added to the IQ
444system.cpu.iq.iqInstsIssued 60426230 # Number of instructions issued
445system.cpu.iq.iqSquashedInstsIssued 90696 # Number of squashed instructions issued
446system.cpu.iq.iqSquashedInstsExamined 11910337 # Number of squashed instructions iterated over during squash; mainly for profiling
447system.cpu.iq.iqSquashedOperandsExamined 5399466 # Number of squashed operands that are examined and possibly removed from graph
448system.cpu.iq.iqSquashedNonSpecRemoved 1551308 # Number of squashed non-spec instructions that were removed
449system.cpu.iq.issued_per_cycle::samples 123473258 # Number of insts issued each cycle
450system.cpu.iq.issued_per_cycle::mean 0.489387 # Number of insts issued each cycle
451system.cpu.iq.issued_per_cycle::stdev 1.234720 # Number of insts issued each cycle
452system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
453system.cpu.iq.issued_per_cycle::0 98959132 80.15% 80.15% # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::1 10414953 8.43% 88.58% # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::2 4418122 3.58% 92.16% # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::3 3174360 2.57% 94.73% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::4 3248671 2.63% 97.36% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::5 1596633 1.29% 98.65% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::6 1092968 0.89% 99.54% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::7 431056 0.35% 99.89% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::8 137363 0.11% 100.00% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::total 123473258 # Number of insts issued each cycle
466system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
467system.cpu.iq.fu_full::IntAlu 204093 16.54% 16.54% # attempts to use FU when none available
468system.cpu.iq.fu_full::IntMult 0 0.00% 16.54% # attempts to use FU when none available
469system.cpu.iq.fu_full::IntDiv 0 0.00% 16.54% # attempts to use FU when none available
470system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.54% # attempts to use FU when none available
471system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.54% # attempts to use FU when none available
472system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.54% # attempts to use FU when none available
473system.cpu.iq.fu_full::FloatMult 0 0.00% 16.54% # attempts to use FU when none available
474system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available
475system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.54% # attempts to use FU when none available
476system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.54% # attempts to use FU when none available
477system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.54% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.54% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.54% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.54% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.54% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.54% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.54% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdMult 0 0.00% 16.54% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.54% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdShift 0 0.00% 16.54% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.54% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.54% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.54% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.54% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.54% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.54% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.54% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.54% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.54% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.54% # attempts to use FU when none available
498system.cpu.iq.fu_full::MemRead 604376 48.98% 65.52% # attempts to use FU when none available
499system.cpu.iq.fu_full::MemWrite 366984 29.74% 95.26% # attempts to use FU when none available
500system.cpu.iq.fu_full::FloatMemRead 31970 2.59% 97.85% # attempts to use FU when none available
501system.cpu.iq.fu_full::FloatMemWrite 26536 2.15% 100.00% # attempts to use FU when none available
502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
504system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued
505system.cpu.iq.FU_type_0::IntAlu 40835249 67.58% 67.59% # Type of FU issued
506system.cpu.iq.FU_type_0::IntMult 62139 0.10% 67.69% # Type of FU issued
507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued
508system.cpu.iq.FU_type_0::FloatAdd 38557 0.06% 67.76% # Type of FU issued
509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
512system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued
513system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.76% # Type of FU issued
514system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.76% # Type of FU issued
515system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
535system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
536system.cpu.iq.FU_type_0::MemRead 11506324 19.04% 86.81% # Type of FU issued
537system.cpu.iq.FU_type_0::MemWrite 6726484 11.13% 97.94% # Type of FU issued
538system.cpu.iq.FU_type_0::FloatMemRead 156184 0.26% 98.20% # Type of FU issued
539system.cpu.iq.FU_type_0::FloatMemWrite 141292 0.23% 98.43% # Type of FU issued
540system.cpu.iq.FU_type_0::IprAccess 949086 1.57% 100.00% # Type of FU issued
541system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
542system.cpu.iq.FU_type_0::total 60426230 # Type of FU issued
543system.cpu.iq.rate 0.466538 # Inst issue rate
544system.cpu.iq.fu_busy_cnt 1233959 # FU busy when requested
545system.cpu.iq.fu_busy_rate 0.020421 # FU busy rate (busy events/executed inst)
546system.cpu.iq.int_inst_queue_reads 244910582 # Number of integer instruction queue reads
547system.cpu.iq.int_inst_queue_writes 76445733 # Number of integer instruction queue writes
548system.cpu.iq.int_inst_queue_wakeup_accesses 58177679 # Number of integer instruction queue wakeup accesses
549system.cpu.iq.fp_inst_queue_reads 739790 # Number of floating instruction queue reads
550system.cpu.iq.fp_inst_queue_writes 359586 # Number of floating instruction queue writes
551system.cpu.iq.fp_inst_queue_wakeup_accesses 336759 # Number of floating instruction queue wakeup accesses
552system.cpu.iq.int_alu_accesses 61254735 # Number of integer alu accesses
553system.cpu.iq.fp_alu_accesses 398175 # Number of floating point alu accesses
554system.cpu.iew.lsq.thread0.forwLoads 690768 # Number of loads that had data forwarded from stores
555system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
556system.cpu.iew.lsq.thread0.squashedLoads 2579745 # Number of loads squashed
557system.cpu.iew.lsq.thread0.ignoredResponses 4605 # Number of memory responses ignored because the instruction is squashed
558system.cpu.iew.lsq.thread0.memOrderViolation 21941 # Number of memory ordering violations
559system.cpu.iew.lsq.thread0.squashedStores 842112 # Number of stores squashed
560system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
561system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
562system.cpu.iew.lsq.thread0.rescheduledLoads 18009 # Number of loads that were rescheduled
563system.cpu.iew.lsq.thread0.cacheBlocked 459546 # Number of times an access to memory failed due to the cache being blocked
564system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
565system.cpu.iew.iewSquashCycles 819068 # Number of cycles IEW is squashing
566system.cpu.iew.iewBlockCycles 52732826 # Number of cycles IEW is blocking
567system.cpu.iew.iewUnblockCycles 1310921 # Number of cycles IEW is unblocking
568system.cpu.iew.iewDispatchedInsts 68860028 # Number of instructions dispatched to IQ
569system.cpu.iew.iewDispSquashedInsts 210874 # Number of squashed instructions skipped by dispatch
570system.cpu.iew.iewDispLoadInsts 11669742 # Number of dispatched load instructions
571system.cpu.iew.iewDispStoreInsts 7218714 # Number of dispatched store instructions
572system.cpu.iew.iewDispNonSpecInsts 1962223 # Number of dispatched non-speculative instructions
573system.cpu.iew.iewIQFullEvents 46667 # Number of times the IQ has become full, causing a stall
574system.cpu.iew.iewLSQFullEvents 1061185 # Number of times the LSQ has become full, causing a stall
575system.cpu.iew.memOrderViolationEvents 21941 # Number of memory order violations
576system.cpu.iew.predictedTakenIncorrect 239076 # Number of branches that were predicted taken incorrectly
577system.cpu.iew.predictedNotTakenIncorrect 633747 # Number of branches that were predicted not taken incorrectly
578system.cpu.iew.branchMispredicts 872823 # Number of branch mispredicts detected at execute
579system.cpu.iew.iewExecutedInsts 59548676 # Number of executed instructions
580system.cpu.iew.iewExecLoadInsts 11192398 # Number of load instructions executed
581system.cpu.iew.iewExecSquashedInsts 877553 # Number of squashed instructions skipped in execute
582system.cpu.iew.exec_swp 0 # number of swp insts executed
583system.cpu.iew.exec_nop 3986416 # number of nop insts executed
584system.cpu.iew.exec_refs 17982691 # number of memory reference insts executed
585system.cpu.iew.exec_branches 9367788 # Number of branches executed
586system.cpu.iew.exec_stores 6790293 # Number of stores executed
587system.cpu.iew.exec_rate 0.459762 # Inst execution rate
588system.cpu.iew.wb_sent 58762094 # cumulative count of insts sent to commit
589system.cpu.iew.wb_count 58514438 # cumulative count of insts written-back
590system.cpu.iew.wb_producers 29700638 # num instructions producing a value
591system.cpu.iew.wb_consumers 41179298 # num instructions consuming a value
592system.cpu.iew.wb_rate 0.451777 # insts written-back per cycle
593system.cpu.iew.wb_fanout 0.721252 # average fanout of values written-back
594system.cpu.commit.commitSquashedInsts 12514858 # The number of squashed insts skipped by commit
595system.cpu.commit.commitNonSpecStalls 661237 # The number of times commit has been forced to stall to communicate backwards
596system.cpu.commit.branchMispredicts 782772 # The number of times a branch was mispredicted
597system.cpu.commit.committed_per_cycle::samples 121281996 # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::mean 0.462997 # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::stdev 1.395862 # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::0 101434078 83.63% 83.63% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::1 7974018 6.57% 90.21% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::2 4186796 3.45% 93.66% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::3 2256770 1.86% 95.52% # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::4 1754187 1.45% 96.97% # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::5 639315 0.53% 97.50% # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::6 479528 0.40% 97.89% # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::7 513600 0.42% 98.31% # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::8 2043704 1.69% 100.00% # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
611system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
612system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
613system.cpu.commit.committed_per_cycle::total 121281996 # Number of insts commited each cycle
614system.cpu.commit.committedInsts 56153243 # Number of instructions committed
615system.cpu.commit.committedOps 56153243 # Number of ops (including micro ops) committed
616system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
617system.cpu.commit.refs 15466599 # Number of memory references committed
618system.cpu.commit.loads 9089997 # Number of loads committed
619system.cpu.commit.membars 226363 # Number of memory barriers committed
620system.cpu.commit.branches 8438860 # Number of branches committed
621system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
622system.cpu.commit.int_insts 52003390 # Number of committed integer instructions.
623system.cpu.commit.function_calls 740372 # Number of function calls committed.
624system.cpu.commit.op_class_0::No_OpClass 3197246 5.69% 5.69% # Class of committed instruction
625system.cpu.commit.op_class_0::IntAlu 36205593 64.48% 70.17% # Class of committed instruction
626system.cpu.commit.op_class_0::IntMult 60678 0.11% 70.28% # Class of committed instruction
627system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction
628system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction
629system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction
630system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction
631system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction
632system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction
633system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction
634system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction

--- 13 unchanged lines hidden (view full) ---

648system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction
649system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction
650system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction
651system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction
652system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction
653system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction
654system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction
655system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction
656system.cpu.commit.op_class_0::MemRead 9171764 16.33% 86.69% # Class of committed instruction
657system.cpu.commit.op_class_0::MemWrite 6244492 11.12% 97.81% # Class of committed instruction
658system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction
659system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction
660system.cpu.commit.op_class_0::IprAccess 949086 1.69% 100.00% # Class of committed instruction
661system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
662system.cpu.commit.op_class_0::total 56153243 # Class of committed instruction
663system.cpu.commit.bw_lim_events 2043704 # number cycles where commit BW limit reached
664system.cpu.rob.rob_reads 187656858 # The number of ROB reads
665system.cpu.rob.rob_writes 139533948 # The number of ROB writes
666system.cpu.timesIdled 550447 # Number of times that the entire CPU went into an idle state and unscheduled itself
667system.cpu.idleCycles 6047264 # Total number of cycles that the CPU has spent unscheduled due to idling
668system.cpu.quiesceCycles 3600507688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
669system.cpu.committedInsts 52963270 # Number of Instructions Simulated
670system.cpu.committedOps 52963270 # Number of Ops (including micro ops) Simulated
671system.cpu.cpi 2.445478 # CPI: Cycles Per Instruction
672system.cpu.cpi_total 2.445478 # CPI: Total CPI of All Threads
673system.cpu.ipc 0.408918 # IPC: Instructions Per Cycle
674system.cpu.ipc_total 0.408918 # IPC: Total IPC of All Threads
675system.cpu.int_regfile_reads 77682847 # number of integer regfile reads
676system.cpu.int_regfile_writes 42491451 # number of integer regfile writes
677system.cpu.fp_regfile_reads 166573 # number of floating regfile reads
678system.cpu.fp_regfile_writes 175777 # number of floating regfile writes
679system.cpu.misc_regfile_reads 2001872 # number of misc regfile reads
680system.cpu.misc_regfile_writes 939479 # number of misc regfile writes
681system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
682system.cpu.dcache.tags.replacements 1405824 # number of replacements
683system.cpu.dcache.tags.tagsinuse 511.994108 # Cycle average of tags in use
684system.cpu.dcache.tags.total_refs 12609719 # Total number of references to valid blocks.
685system.cpu.dcache.tags.sampled_refs 1406336 # Sample count of references to valid blocks.
686system.cpu.dcache.tags.avg_refs 8.966363 # Average number of references to valid blocks.
687system.cpu.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit.
688system.cpu.dcache.tags.occ_blocks::cpu.data 511.994108 # Average occupied blocks per requestor
689system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy
690system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy
691system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
692system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
693system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
694system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
695system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
696system.cpu.dcache.tags.tag_accesses 67057386 # Number of tag accesses
697system.cpu.dcache.tags.data_accesses 67057386 # Number of data accesses
698system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
699system.cpu.dcache.ReadReq_hits::cpu.data 8001397 # number of ReadReq hits
700system.cpu.dcache.ReadReq_hits::total 8001397 # number of ReadReq hits
701system.cpu.dcache.WriteReq_hits::cpu.data 4179263 # number of WriteReq hits
702system.cpu.dcache.WriteReq_hits::total 4179263 # number of WriteReq hits
703system.cpu.dcache.LoadLockedReq_hits::cpu.data 213150 # number of LoadLockedReq hits
704system.cpu.dcache.LoadLockedReq_hits::total 213150 # number of LoadLockedReq hits
705system.cpu.dcache.StoreCondReq_hits::cpu.data 215702 # number of StoreCondReq hits
706system.cpu.dcache.StoreCondReq_hits::total 215702 # number of StoreCondReq hits
707system.cpu.dcache.demand_hits::cpu.data 12180660 # number of demand (read+write) hits
708system.cpu.dcache.demand_hits::total 12180660 # number of demand (read+write) hits
709system.cpu.dcache.overall_hits::cpu.data 12180660 # number of overall hits
710system.cpu.dcache.overall_hits::total 12180660 # number of overall hits
711system.cpu.dcache.ReadReq_misses::cpu.data 1813374 # number of ReadReq misses
712system.cpu.dcache.ReadReq_misses::total 1813374 # number of ReadReq misses
713system.cpu.dcache.WriteReq_misses::cpu.data 1966870 # number of WriteReq misses
714system.cpu.dcache.WriteReq_misses::total 1966870 # number of WriteReq misses
715system.cpu.dcache.LoadLockedReq_misses::cpu.data 22944 # number of LoadLockedReq misses
716system.cpu.dcache.LoadLockedReq_misses::total 22944 # number of LoadLockedReq misses
717system.cpu.dcache.StoreCondReq_misses::cpu.data 62 # number of StoreCondReq misses
718system.cpu.dcache.StoreCondReq_misses::total 62 # number of StoreCondReq misses
719system.cpu.dcache.demand_misses::cpu.data 3780244 # number of demand (read+write) misses
720system.cpu.dcache.demand_misses::total 3780244 # number of demand (read+write) misses
721system.cpu.dcache.overall_misses::cpu.data 3780244 # number of overall misses
722system.cpu.dcache.overall_misses::total 3780244 # number of overall misses
723system.cpu.dcache.ReadReq_miss_latency::cpu.data 45111482000 # number of ReadReq miss cycles
724system.cpu.dcache.ReadReq_miss_latency::total 45111482000 # number of ReadReq miss cycles
725system.cpu.dcache.WriteReq_miss_latency::cpu.data 92228872060 # number of WriteReq miss cycles
726system.cpu.dcache.WriteReq_miss_latency::total 92228872060 # number of WriteReq miss cycles
727system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 421566000 # number of LoadLockedReq miss cycles
728system.cpu.dcache.LoadLockedReq_miss_latency::total 421566000 # number of LoadLockedReq miss cycles
729system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 865000 # number of StoreCondReq miss cycles
730system.cpu.dcache.StoreCondReq_miss_latency::total 865000 # number of StoreCondReq miss cycles
731system.cpu.dcache.demand_miss_latency::cpu.data 137340354060 # number of demand (read+write) miss cycles
732system.cpu.dcache.demand_miss_latency::total 137340354060 # number of demand (read+write) miss cycles
733system.cpu.dcache.overall_miss_latency::cpu.data 137340354060 # number of overall miss cycles
734system.cpu.dcache.overall_miss_latency::total 137340354060 # number of overall miss cycles
735system.cpu.dcache.ReadReq_accesses::cpu.data 9814771 # number of ReadReq accesses(hits+misses)
736system.cpu.dcache.ReadReq_accesses::total 9814771 # number of ReadReq accesses(hits+misses)
737system.cpu.dcache.WriteReq_accesses::cpu.data 6146133 # number of WriteReq accesses(hits+misses)
738system.cpu.dcache.WriteReq_accesses::total 6146133 # number of WriteReq accesses(hits+misses)
739system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236094 # number of LoadLockedReq accesses(hits+misses)
740system.cpu.dcache.LoadLockedReq_accesses::total 236094 # number of LoadLockedReq accesses(hits+misses)
741system.cpu.dcache.StoreCondReq_accesses::cpu.data 215764 # number of StoreCondReq accesses(hits+misses)
742system.cpu.dcache.StoreCondReq_accesses::total 215764 # number of StoreCondReq accesses(hits+misses)
743system.cpu.dcache.demand_accesses::cpu.data 15960904 # number of demand (read+write) accesses
744system.cpu.dcache.demand_accesses::total 15960904 # number of demand (read+write) accesses
745system.cpu.dcache.overall_accesses::cpu.data 15960904 # number of overall (read+write) accesses
746system.cpu.dcache.overall_accesses::total 15960904 # number of overall (read+write) accesses
747system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184760 # miss rate for ReadReq accesses
748system.cpu.dcache.ReadReq_miss_rate::total 0.184760 # miss rate for ReadReq accesses
749system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320017 # miss rate for WriteReq accesses
750system.cpu.dcache.WriteReq_miss_rate::total 0.320017 # miss rate for WriteReq accesses
751system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.097182 # miss rate for LoadLockedReq accesses
752system.cpu.dcache.LoadLockedReq_miss_rate::total 0.097182 # miss rate for LoadLockedReq accesses
753system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000287 # miss rate for StoreCondReq accesses
754system.cpu.dcache.StoreCondReq_miss_rate::total 0.000287 # miss rate for StoreCondReq accesses
755system.cpu.dcache.demand_miss_rate::cpu.data 0.236844 # miss rate for demand accesses
756system.cpu.dcache.demand_miss_rate::total 0.236844 # miss rate for demand accesses
757system.cpu.dcache.overall_miss_rate::cpu.data 0.236844 # miss rate for overall accesses
758system.cpu.dcache.overall_miss_rate::total 0.236844 # miss rate for overall accesses
759system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24877.097609 # average ReadReq miss latency
760system.cpu.dcache.ReadReq_avg_miss_latency::total 24877.097609 # average ReadReq miss latency
761system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46891.188569 # average WriteReq miss latency
762system.cpu.dcache.WriteReq_avg_miss_latency::total 46891.188569 # average WriteReq miss latency
763system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18373.692469 # average LoadLockedReq miss latency
764system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18373.692469 # average LoadLockedReq miss latency
765system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13951.612903 # average StoreCondReq miss latency
766system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13951.612903 # average StoreCondReq miss latency
767system.cpu.dcache.demand_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency
768system.cpu.dcache.demand_avg_miss_latency::total 36331.081819 # average overall miss latency
769system.cpu.dcache.overall_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency
770system.cpu.dcache.overall_avg_miss_latency::total 36331.081819 # average overall miss latency
771system.cpu.dcache.blocked_cycles::no_mshrs 4936405 # number of cycles access was blocked
772system.cpu.dcache.blocked_cycles::no_targets 4609 # number of cycles access was blocked
773system.cpu.dcache.blocked::no_mshrs 132646 # number of cycles access was blocked
774system.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked
775system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.214880 # average number of cycles each access was blocked
776system.cpu.dcache.avg_blocked_cycles::no_targets 153.633333 # average number of cycles each access was blocked
777system.cpu.dcache.writebacks::writebacks 843338 # number of writebacks
778system.cpu.dcache.writebacks::total 843338 # number of writebacks
779system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712674 # number of ReadReq MSHR hits
780system.cpu.dcache.ReadReq_mshr_hits::total 712674 # number of ReadReq MSHR hits
781system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677487 # number of WriteReq MSHR hits
782system.cpu.dcache.WriteReq_mshr_hits::total 1677487 # number of WriteReq MSHR hits
783system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6576 # number of LoadLockedReq MSHR hits
784system.cpu.dcache.LoadLockedReq_mshr_hits::total 6576 # number of LoadLockedReq MSHR hits
785system.cpu.dcache.demand_mshr_hits::cpu.data 2390161 # number of demand (read+write) MSHR hits
786system.cpu.dcache.demand_mshr_hits::total 2390161 # number of demand (read+write) MSHR hits
787system.cpu.dcache.overall_mshr_hits::cpu.data 2390161 # number of overall MSHR hits
788system.cpu.dcache.overall_mshr_hits::total 2390161 # number of overall MSHR hits
789system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100700 # number of ReadReq MSHR misses
790system.cpu.dcache.ReadReq_mshr_misses::total 1100700 # number of ReadReq MSHR misses
791system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289383 # number of WriteReq MSHR misses
792system.cpu.dcache.WriteReq_mshr_misses::total 289383 # number of WriteReq MSHR misses
793system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16368 # number of LoadLockedReq MSHR misses
794system.cpu.dcache.LoadLockedReq_mshr_misses::total 16368 # number of LoadLockedReq MSHR misses
795system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 62 # number of StoreCondReq MSHR misses
796system.cpu.dcache.StoreCondReq_mshr_misses::total 62 # number of StoreCondReq MSHR misses
797system.cpu.dcache.demand_mshr_misses::cpu.data 1390083 # number of demand (read+write) MSHR misses
798system.cpu.dcache.demand_mshr_misses::total 1390083 # number of demand (read+write) MSHR misses
799system.cpu.dcache.overall_mshr_misses::cpu.data 1390083 # number of overall MSHR misses
800system.cpu.dcache.overall_mshr_misses::total 1390083 # number of overall MSHR misses
801system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
802system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
803system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
804system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
805system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses
806system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
807system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33019179500 # number of ReadReq MSHR miss cycles
808system.cpu.dcache.ReadReq_mshr_miss_latency::total 33019179500 # number of ReadReq MSHR miss cycles
809system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14332081529 # number of WriteReq MSHR miss cycles
810system.cpu.dcache.WriteReq_mshr_miss_latency::total 14332081529 # number of WriteReq MSHR miss cycles
811system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205108500 # number of LoadLockedReq MSHR miss cycles
812system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205108500 # number of LoadLockedReq MSHR miss cycles
813system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 803000 # number of StoreCondReq MSHR miss cycles
814system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 803000 # number of StoreCondReq MSHR miss cycles
815system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47351261029 # number of demand (read+write) MSHR miss cycles
816system.cpu.dcache.demand_mshr_miss_latency::total 47351261029 # number of demand (read+write) MSHR miss cycles
817system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47351261029 # number of overall MSHR miss cycles
818system.cpu.dcache.overall_mshr_miss_latency::total 47351261029 # number of overall MSHR miss cycles
819system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535277500 # number of ReadReq MSHR uncacheable cycles
820system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535277500 # number of ReadReq MSHR uncacheable cycles
821system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535277500 # number of overall MSHR uncacheable cycles
822system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535277500 # number of overall MSHR uncacheable cycles
823system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.112147 # mshr miss rate for ReadReq accesses
824system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.112147 # mshr miss rate for ReadReq accesses
825system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047084 # mshr miss rate for WriteReq accesses
826system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047084 # mshr miss rate for WriteReq accesses
827system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.069328 # mshr miss rate for LoadLockedReq accesses
828system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.069328 # mshr miss rate for LoadLockedReq accesses
829system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000287 # mshr miss rate for StoreCondReq accesses
830system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000287 # mshr miss rate for StoreCondReq accesses
831system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for demand accesses
832system.cpu.dcache.demand_mshr_miss_rate::total 0.087093 # mshr miss rate for demand accesses
833system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for overall accesses
834system.cpu.dcache.overall_mshr_miss_rate::total 0.087093 # mshr miss rate for overall accesses
835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053 # average ReadReq mshr miss latency
836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053 # average ReadReq mshr miss latency
837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353 # average WriteReq mshr miss latency
838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353 # average WriteReq mshr miss latency
839system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716 # average LoadLockedReq mshr miss latency
840system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716 # average LoadLockedReq mshr miss latency
841system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903 # average StoreCondReq mshr miss latency
842system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903 # average StoreCondReq mshr miss latency
843system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency
844system.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency
845system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency
846system.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency
847system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791 # average ReadReq mshr uncacheable latency
848system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791 # average ReadReq mshr uncacheable latency
849system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773 # average overall mshr uncacheable latency
850system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773 # average overall mshr uncacheable latency
851system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
852system.cpu.icache.tags.replacements 1070370 # number of replacements
853system.cpu.icache.tags.tagsinuse 509.026702 # Cycle average of tags in use
854system.cpu.icache.tags.total_refs 8813001 # Total number of references to valid blocks.
855system.cpu.icache.tags.sampled_refs 1070878 # Sample count of references to valid blocks.
856system.cpu.icache.tags.avg_refs 8.229697 # Average number of references to valid blocks.
857system.cpu.icache.tags.warmup_cycle 30284278500 # Cycle when the warmup percentage was hit.
858system.cpu.icache.tags.occ_blocks::cpu.inst 509.026702 # Average occupied blocks per requestor
859system.cpu.icache.tags.occ_percent::cpu.inst 0.994193 # Average percentage of cache occupancy
860system.cpu.icache.tags.occ_percent::total 0.994193 # Average percentage of cache occupancy
861system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
862system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
863system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
864system.cpu.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
865system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
866system.cpu.icache.tags.tag_accesses 11024191 # Number of tag accesses
867system.cpu.icache.tags.data_accesses 11024191 # Number of data accesses
868system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
869system.cpu.icache.ReadReq_hits::cpu.inst 8813002 # number of ReadReq hits
870system.cpu.icache.ReadReq_hits::total 8813002 # number of ReadReq hits
871system.cpu.icache.demand_hits::cpu.inst 8813002 # number of demand (read+write) hits
872system.cpu.icache.demand_hits::total 8813002 # number of demand (read+write) hits
873system.cpu.icache.overall_hits::cpu.inst 8813002 # number of overall hits
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903system.cpu.icache.overall_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency
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906system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
907system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
908system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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910system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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912system.cpu.icache.writebacks::total 1070370 # number of writebacks
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927system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14349436996 # number of demand (read+write) MSHR miss cycles
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933system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for demand accesses
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935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for overall accesses
936system.cpu.icache.overall_mshr_miss_rate::total 0.107620 # mshr miss rate for overall accesses
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938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13396.290899 # average ReadReq mshr miss latency
939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency
940system.cpu.icache.demand_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency
941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency
942system.cpu.icache.overall_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency
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945system.cpu.l2cache.tags.tagsinuse 65420.352754 # Cycle average of tags in use
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948system.cpu.l2cache.tags.avg_refs 11.251538 # Average number of references to valid blocks.
949system.cpu.l2cache.tags.warmup_cycle 6414124000 # Cycle when the warmup percentage was hit.
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951system.cpu.l2cache.tags.occ_blocks::cpu.inst 5307.615094 # Average occupied blocks per requestor
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958system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
959system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id
960system.cpu.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id
961system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5606 # Occupied blocks per task id
962system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58575 # Occupied blocks per task id
963system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
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1008system.cpu.l2cache.ReadSharedReq_miss_latency::total 22383517000 # number of ReadSharedReq miss cycles
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1014system.cpu.l2cache.overall_miss_latency::total 35915266500 # number of overall miss cycles
1015system.cpu.l2cache.WritebackDirty_accesses::writebacks 843338 # number of WritebackDirty accesses(hits+misses)
1016system.cpu.l2cache.WritebackDirty_accesses::total 843338 # number of WritebackDirty accesses(hits+misses)
1017system.cpu.l2cache.WritebackClean_accesses::writebacks 1069837 # number of WritebackClean accesses(hits+misses)
1018system.cpu.l2cache.WritebackClean_accesses::total 1069837 # number of WritebackClean accesses(hits+misses)
1019system.cpu.l2cache.UpgradeReq_accesses::cpu.data 70 # number of UpgradeReq accesses(hits+misses)
1020system.cpu.l2cache.UpgradeReq_accesses::total 70 # number of UpgradeReq accesses(hits+misses)
1021system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 62 # number of SCUpgradeReq accesses(hits+misses)
1022system.cpu.l2cache.SCUpgradeReq_accesses::total 62 # number of SCUpgradeReq accesses(hits+misses)
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1036system.cpu.l2cache.UpgradeReq_miss_rate::total 0.142857 # miss rate for UpgradeReq accesses
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1038system.cpu.l2cache.ReadExReq_miss_rate::total 0.382640 # miss rate for ReadExReq accesses
1039system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014041 # miss rate for ReadCleanReq accesses
1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014041 # miss rate for ReadCleanReq accesses
1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248050 # miss rate for ReadSharedReq accesses
1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248050 # miss rate for ReadSharedReq accesses
1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014041 # miss rate for demand accesses
1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.276738 # miss rate for demand accesses
1045system.cpu.l2cache.demand_miss_rate::total 0.163176 # miss rate for demand accesses
1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014041 # miss rate for overall accesses
1047system.cpu.l2cache.overall_miss_rate::cpu.data 0.276738 # miss rate for overall accesses
1048system.cpu.l2cache.overall_miss_rate::total 0.163176 # miss rate for overall accesses
1049system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 44800 # average UpgradeReq miss latency
1050system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 44800 # average UpgradeReq miss latency
1051system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104726.182173 # average ReadExReq miss latency
1052system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104726.182173 # average ReadExReq miss latency
1053system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101033.284565 # average ReadCleanReq miss latency
1054system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101033.284565 # average ReadCleanReq miss latency
1055system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81544.055287 # average ReadSharedReq miss latency
1056system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81544.055287 # average ReadSharedReq miss latency
1057system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency
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1060system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency
1061system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency
1062system.cpu.l2cache.overall_avg_miss_latency::total 88847.053832 # average overall miss latency
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1064system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1065system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1066system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1067system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1068system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1069system.cpu.l2cache.writebacks::writebacks 75899 # number of writebacks
1070system.cpu.l2cache.writebacks::total 75899 # number of writebacks
1071system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses
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1075system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses
1076system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses
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1078system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274496 # number of ReadSharedReq MSHR misses
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1086system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
1087system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable
1088system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable
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1090system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses
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1108system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448637000 # number of overall MSHR uncacheable cycles
1109system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for UpgradeReq accesses
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1111system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382640 # mshr miss rate for ReadExReq accesses
1112system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382640 # mshr miss rate for ReadExReq accesses
1113system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for ReadCleanReq accesses
1114system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014041 # mshr miss rate for ReadCleanReq accesses
1115system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248050 # mshr miss rate for ReadSharedReq accesses
1116system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248050 # mshr miss rate for ReadSharedReq accesses
1117system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for demand accesses
1118system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for demand accesses
1119system.cpu.l2cache.demand_mshr_miss_rate::total 0.163176 # mshr miss rate for demand accesses
1120system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for overall accesses
1121system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for overall accesses
1122system.cpu.l2cache.overall_mshr_miss_rate::total 0.163176 # mshr miss rate for overall accesses
1123system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 34800 # average UpgradeReq mshr miss latency
1124system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34800 # average UpgradeReq mshr miss latency
1125system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173 # average ReadExReq mshr miss latency
1126system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173 # average ReadExReq mshr miss latency
1127system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565 # average ReadCleanReq mshr miss latency
1128system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565 # average ReadCleanReq mshr miss latency
1129system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234 # average ReadSharedReq mshr miss latency
1130system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234 # average ReadSharedReq mshr miss latency
1131system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency
1132system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency
1133system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency
1134system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency
1135system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency
1136system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency
1137system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139 # average ReadReq mshr uncacheable latency
1138system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139 # average ReadReq mshr uncacheable latency
1139system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110 # average overall mshr uncacheable latency
1140system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110 # average overall mshr uncacheable latency
1141system.cpu.toL2Bus.snoop_filter.tot_requests 4953861 # Total number of requests made to the snoop filter.
1142system.cpu.toL2Bus.snoop_filter.hit_single_requests 2476312 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1143system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4344 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1144system.cpu.toL2Bus.snoop_filter.tot_snoops 953 # Total number of snoops made to the snoop filter.
1145system.cpu.toL2Bus.snoop_filter.hit_single_snoops 953 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1146system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1147system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1148system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
1149system.cpu.toL2Bus.trans_dist::ReadResp 2184804 # Transaction distribution
1150system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution
1151system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution
1152system.cpu.toL2Bus.trans_dist::WritebackDirty 919237 # Transaction distribution
1153system.cpu.toL2Bus.trans_dist::WritebackClean 1070370 # Transaction distribution
1154system.cpu.toL2Bus.trans_dist::CleanEvict 825198 # Transaction distribution
1155system.cpu.toL2Bus.trans_dist::UpgradeReq 70 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::SCUpgradeReq 62 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::ReadExReq 299770 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::ReadExResp 299770 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::ReadCleanReq 1071150 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106776 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution
1163system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
1164system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution
1165system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3212444 # Packet count per connected master and slave (bytes)
1166system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252074 # Packet count per connected master and slave (bytes)
1167system.cpu.toL2Bus.pkt_count::total 7464518 # Packet count per connected master and slave (bytes)
1168system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137042816 # Cumulative packet size per connected master and slave (bytes)
1169system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144033404 # Cumulative packet size per connected master and slave (bytes)
1170system.cpu.toL2Bus.pkt_size::total 281076220 # Cumulative packet size per connected master and slave (bytes)
1171system.cpu.toL2Bus.snoops 339392 # Total snoops (count)
1172system.cpu.toL2Bus.snoopTraffic 4881984 # Total snoop traffic (bytes)
1173system.cpu.toL2Bus.snoop_fanout::samples 2833204 # Request fanout histogram
1174system.cpu.toL2Bus.snoop_fanout::mean 0.001872 # Request fanout histogram
1175system.cpu.toL2Bus.snoop_fanout::stdev 0.043223 # Request fanout histogram
1176system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1177system.cpu.toL2Bus.snoop_fanout::0 2827901 99.81% 99.81% # Request fanout histogram
1178system.cpu.toL2Bus.snoop_fanout::1 5303 0.19% 100.00% # Request fanout histogram
1179system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1180system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1181system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1182system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1183system.cpu.toL2Bus.snoop_fanout::total 2833204 # Request fanout histogram
1184system.cpu.toL2Bus.reqLayer0.occupancy 4403702500 # Layer occupancy (ticks)
1185system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1186system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks)
1187system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1188system.cpu.toL2Bus.respLayer0.occupancy 1607637172 # Layer occupancy (ticks)
1189system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1190system.cpu.toL2Bus.respLayer1.occupancy 2121526099 # Layer occupancy (ticks)
1191system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1192system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1193system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1194system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1195system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1196system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1197system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1198system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1199system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1200system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1201system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1202system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1203system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1204system.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1205system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
1206system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
1207system.iobus.trans_dist::WriteReq 51151 # Transaction distribution
1208system.iobus.trans_dist::WriteResp 51151 # Transaction distribution
1209system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes)
1210system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
1211system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1212system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)

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1227system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
1228system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
1229system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1230system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1231system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes)
1232system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
1233system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
1234system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes)
1235system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks)
1236system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1237system.iobus.reqLayer1.occupancy 815500 # Layer occupancy (ticks)
1238system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1239system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks)
1240system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1241system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
1242system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1243system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks)
1244system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1245system.iobus.reqLayer23.occupancy 14072500 # Layer occupancy (ticks)
1246system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1247system.iobus.reqLayer24.occupancy 2178500 # Layer occupancy (ticks)
1248system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1249system.iobus.reqLayer25.occupancy 6063000 # Layer occupancy (ticks)
1250system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1251system.iobus.reqLayer26.occupancy 93500 # Layer occupancy (ticks)
1252system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1253system.iobus.reqLayer27.occupancy 216225034 # Layer occupancy (ticks)
1254system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1255system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks)
1256system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1257system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1258system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1259system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1260system.iocache.tags.replacements 41685 # number of replacements
1261system.iocache.tags.tagsinuse 1.265440 # Cycle average of tags in use
1262system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1263system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1264system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1265system.iocache.tags.warmup_cycle 1714255689000 # Cycle when the warmup percentage was hit.
1266system.iocache.tags.occ_blocks::tsunami.ide 1.265440 # Average occupied blocks per requestor
1267system.iocache.tags.occ_percent::tsunami.ide 0.079090 # Average percentage of cache occupancy
1268system.iocache.tags.occ_percent::total 0.079090 # Average percentage of cache occupancy
1269system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1270system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1271system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1272system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1273system.iocache.tags.data_accesses 375525 # Number of data accesses
1274system.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1275system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1276system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1277system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1278system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1279system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1280system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1281system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1282system.iocache.overall_misses::total 41725 # number of overall misses
1283system.iocache.ReadReq_miss_latency::tsunami.ide 21944883 # number of ReadReq miss cycles
1284system.iocache.ReadReq_miss_latency::total 21944883 # number of ReadReq miss cycles
1285system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931807151 # number of WriteLineReq miss cycles
1286system.iocache.WriteLineReq_miss_latency::total 4931807151 # number of WriteLineReq miss cycles
1287system.iocache.demand_miss_latency::tsunami.ide 4953752034 # number of demand (read+write) miss cycles
1288system.iocache.demand_miss_latency::total 4953752034 # number of demand (read+write) miss cycles
1289system.iocache.overall_miss_latency::tsunami.ide 4953752034 # number of overall miss cycles
1290system.iocache.overall_miss_latency::total 4953752034 # number of overall miss cycles
1291system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1292system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1293system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1294system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1295system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
1296system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
1297system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
1298system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1299system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1300system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1301system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1302system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1303system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1304system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1305system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1306system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1307system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682 # average ReadReq miss latency
1308system.iocache.ReadReq_avg_miss_latency::total 126849.034682 # average ReadReq miss latency
1309system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522 # average WriteLineReq miss latency
1310system.iocache.WriteLineReq_avg_miss_latency::total 118690.006522 # average WriteLineReq miss latency
1311system.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency
1312system.iocache.demand_avg_miss_latency::total 118723.835446 # average overall miss latency
1313system.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency
1314system.iocache.overall_avg_miss_latency::total 118723.835446 # average overall miss latency
1315system.iocache.blocked_cycles::no_mshrs 1219 # number of cycles access was blocked
1316system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1317system.iocache.blocked::no_mshrs 12 # number of cycles access was blocked
1318system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1319system.iocache.avg_blocked_cycles::no_mshrs 101.583333 # average number of cycles each access was blocked
1320system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1321system.iocache.writebacks::writebacks 41512 # number of writebacks
1322system.iocache.writebacks::total 41512 # number of writebacks
1323system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1324system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1325system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1326system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1327system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
1328system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
1329system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
1330system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1331system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294883 # number of ReadReq MSHR miss cycles
1332system.iocache.ReadReq_mshr_miss_latency::total 13294883 # number of ReadReq MSHR miss cycles
1333system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851781783 # number of WriteLineReq MSHR miss cycles
1334system.iocache.WriteLineReq_mshr_miss_latency::total 2851781783 # number of WriteLineReq MSHR miss cycles
1335system.iocache.demand_mshr_miss_latency::tsunami.ide 2865076666 # number of demand (read+write) MSHR miss cycles
1336system.iocache.demand_mshr_miss_latency::total 2865076666 # number of demand (read+write) MSHR miss cycles
1337system.iocache.overall_mshr_miss_latency::tsunami.ide 2865076666 # number of overall MSHR miss cycles
1338system.iocache.overall_mshr_miss_latency::total 2865076666 # number of overall MSHR miss cycles
1339system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1340system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1341system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1342system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1343system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1344system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1345system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1346system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1347system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682 # average ReadReq mshr miss latency
1348system.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682 # average ReadReq mshr miss latency
1349system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057 # average WriteLineReq mshr miss latency
1350system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057 # average WriteLineReq mshr miss latency
1351system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency
1352system.iocache.demand_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency
1353system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency
1354system.iocache.overall_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency
1355system.membus.snoop_filter.tot_requests 825536 # Total number of requests made to the snoop filter.
1356system.membus.snoop_filter.hit_single_requests 380380 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1357system.membus.snoop_filter.hit_multi_requests 527 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1358system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1359system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1360system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1361system.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1362system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1363system.membus.trans_dist::ReadResp 296589 # Transaction distribution
1364system.membus.trans_dist::WriteReq 9599 # Transaction distribution
1365system.membus.trans_dist::WriteResp 9599 # Transaction distribution
1366system.membus.trans_dist::WritebackDirty 117411 # Transaction distribution
1367system.membus.trans_dist::CleanEvict 262092 # Transaction distribution
1368system.membus.trans_dist::UpgradeReq 137 # Transaction distribution
1369system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
1370system.membus.trans_dist::ReadExReq 114577 # Transaction distribution
1371system.membus.trans_dist::ReadExResp 114577 # Transaction distribution
1372system.membus.trans_dist::ReadSharedReq 289706 # Transaction distribution
1373system.membus.trans_dist::BadAddressError 47 # Transaction distribution
1374system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1375system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
1376system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes)
1377system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145804 # Packet count per connected master and slave (bytes)
1378system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes)
1379system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178956 # Packet count per connected master and slave (bytes)
1380system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes)
1381system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes)
1382system.membus.pkt_count::total 1262381 # Packet count per connected master and slave (bytes)
1383system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes)
1384system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699840 # Cumulative packet size per connected master and slave (bytes)
1385system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30743996 # Cumulative packet size per connected master and slave (bytes)
1386system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes)
1387system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
1388system.membus.pkt_size::total 33401724 # Cumulative packet size per connected master and slave (bytes)
1389system.membus.snoops 562 # Total snoops (count)
1390system.membus.snoopTraffic 27840 # Total snoop traffic (bytes)
1391system.membus.snoop_fanout::samples 462501 # Request fanout histogram
1392system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram
1393system.membus.snoop_fanout::stdev 0.038231 # Request fanout histogram
1394system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1395system.membus.snoop_fanout::0 461824 99.85% 99.85% # Request fanout histogram
1396system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram
1397system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1398system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1399system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1400system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1401system.membus.snoop_fanout::total 462501 # Request fanout histogram
1402system.membus.reqLayer0.occupancy 28785000 # Layer occupancy (ticks)
1403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1404system.membus.reqLayer1.occupancy 1313532070 # Layer occupancy (ticks)
1405system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1406system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks)
1407system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1408system.membus.respLayer1.occupancy 2137876500 # Layer occupancy (ticks)
1409system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1410system.membus.respLayer2.occupancy 1057021 # Layer occupancy (ticks)
1411system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1412system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1413system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1414system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1415system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1416system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1417system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1418system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1419system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1420system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1421system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1422system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1423system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1424system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

1440system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1441system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1442system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1443system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1444system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1445system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1446system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1447system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1448system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1449system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1450system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1451system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1452system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1453system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1454system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1455system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1456system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1457system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1458system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1459system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1460system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1461system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1462system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1463system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1464system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1465system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1466system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1467system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1468system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1469system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1470system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states
1471system.cpu.kern.inst.arm 0 # number of arm instructions executed
1472system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
1473system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed
1474system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl
1475system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
1476system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl
1477system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl
1478system.cpu.kern.ipl_count::total 182250 # number of times we switched to this ipl
1479system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl
1480system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
1481system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl
1482system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl
1483system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl
1484system.cpu.kern.ipl_ticks::0 1819143935000 97.54% 97.54% # number of cycles we spent at this ipl
1485system.cpu.kern.ipl_ticks::21 67422000 0.00% 97.54% # number of cycles we spent at this ipl
1486system.cpu.kern.ipl_ticks::22 565966500 0.03% 97.57% # number of cycles we spent at this ipl
1487system.cpu.kern.ipl_ticks::31 45235960500 2.43% 100.00% # number of cycles we spent at this ipl
1488system.cpu.kern.ipl_ticks::total 1865013284000 # number of cycles we spent at this ipl
1489system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
1490system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
1491system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1492system.cpu.kern.ipl_used::31 0.694287 # fraction of swpipl calls that actually changed the ipl
1493system.cpu.kern.ipl_used::total 0.815407 # fraction of swpipl calls that actually changed the ipl
1494system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1495system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
1496system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
1497system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
1498system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
1499system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
1500system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
1501system.cpu.kern.callpal::swpipl 175131 91.22% 93.43% # number of callpals executed
1502system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed
1503system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
1504system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
1505system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
1506system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
1507system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed
1508system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
1509system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
1510system.cpu.kern.callpal::total 191978 # number of callpals executed
1511system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches
1512system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
1513system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
1514system.cpu.kern.mode_good::kernel 1908
1515system.cpu.kern.mode_good::user 1738
1516system.cpu.kern.mode_good::idle 170
1517system.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches
1518system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1519system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
1520system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches
1521system.cpu.kern.mode_ticks::kernel 29665976500 1.59% 1.59% # number of ticks spent at the given mode
1522system.cpu.kern.mode_ticks::user 2757716000 0.15% 1.74% # number of ticks spent at the given mode
1523system.cpu.kern.mode_ticks::idle 1832589583500 98.26% 100.00% # number of ticks spent at the given mode
1524system.cpu.kern.swap_context 4177 # number of times the context was actually changed
1525
1526---------- End Simulation Statistics ----------