| stats.txt (9620:89aa34e10625) | stats.txt (9625:47591444a7c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.900727 # Number of seconds simulated 4sim_ticks 1900727015500 # Number of ticks simulated 5final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.900728 # Number of seconds simulated 4sim_ticks 1900727697500 # Number of ticks simulated 5final_tick 1900727697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 47037 # Simulator instruction rate (inst/s) 8host_op_rate 47037 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1570523818 # Simulator tick rate (ticks/s) 10host_mem_usage 354648 # Number of bytes of host memory used 11host_seconds 1210.25 # Real time elapsed on the host 12sim_insts 56926994 # Number of instructions simulated 13sim_ops 56926994 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory | 7host_inst_rate 95395 # Simulator instruction rate (inst/s) 8host_op_rate 95395 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3185234659 # Simulator tick rate (ticks/s) 10host_mem_usage 355712 # Number of bytes of host memory used 11host_seconds 596.73 # Real time elapsed on the host 12sim_insts 56925219 # Number of instructions simulated 13sim_ops 56925219 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 854208 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24595840 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu1.inst 123328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 541952 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28767232 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 854208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 123328 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7730048 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7730048 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13347 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 384310 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_reads::cpu1.inst 1927 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8468 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 449488 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120782 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120782 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 449411 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12940223 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_read::cpu1.inst 64885 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 285129 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15134852 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 449411 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 64885 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 514296 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4066889 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4066889 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4066889 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 449411 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12940223 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 449493 # Total number of read requests seen 52system.physmem.writeReqs 120791 # Total number of write requests seen 53system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28767552 # Total number of bytes read from memory 55system.physmem.bytesWritten 7730624 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis | 48system.physmem.bw_total::cpu1.inst 64885 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 285129 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19201740 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 449488 # Total number of read requests seen 52system.physmem.writeReqs 120782 # Total number of write requests seen 53system.physmem.cpureqs 575881 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28767232 # Total number of bytes read from memory 55system.physmem.bytesWritten 7730048 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28767232 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7730048 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 76 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 5601 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28386 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28227 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28192 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27982 # Track reads on a per bank basis |
| 64system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis | 64system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis |
| 65system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis | 65system.physmem.perBankRdReqs::5 28241 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28220 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28022 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28087 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28039 # Track reads on a per bank basis |
| 70system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis | 70system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis |
| 71system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7707 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7701 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis | 71system.physmem.perBankRdReqs::11 27938 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27835 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28000 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27859 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27848 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7706 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7703 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7519 # Track writes on a per bank basis |
| 80system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis | 80system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis |
| 81system.physmem.perBankWrReqs::5 7578 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7608 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7520 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7649 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7589 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7579 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7352 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7235 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7444 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7276 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7350 # Track writes on a per bank basis | 81system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7606 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7518 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7651 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7586 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7578 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7350 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7241 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7443 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7270 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7347 # Track writes on a per bank basis |
| 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 93system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1900722456000 # Total gap between requests | 93system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1900723138000 # Total gap between requests |
| 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 101system.physmem.readPktSize::6 449493 # Categorize read packet sizes | 101system.physmem.readPktSize::6 449488 # Categorize read packet sizes |
| 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes | 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 108system.physmem.writePktSize::6 120791 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 7610 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 2961 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 2698 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 2655 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1511 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1447 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 1362 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 1348 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 1369 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 1521 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see | 108system.physmem.writePktSize::6 120782 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 319759 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 59264 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 32659 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 7637 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 2957 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 2688 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 2676 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 2637 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 2595 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1524 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1455 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 1389 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1622 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 1546 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 914 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see |
| 129system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see | 129system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see | 130system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::0 3171 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3801 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4360 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4877 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5224 # What write queue length does an incoming req see | 141system.physmem.wrQLenPdf::0 3169 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3807 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4327 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4374 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4886 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5229 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::7 5238 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5240 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5252 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5252 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5252 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5252 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5252 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5252 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5252 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5252 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5252 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::7 5236 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5239 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5251 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5251 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5251 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5251 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5251 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5251 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5251 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5251 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5251 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::23 2081 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1451 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 955 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see | 164system.physmem.wrQLenPdf::23 2083 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1445 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 878 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 366 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see |
| 171system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see 173system.physmem.totQLat 7695436000 # Total cycles spent in queuing delays 174system.physmem.totMemAccLat 15487088500 # Sum of mem lat for all requests 175system.physmem.totBusLat 2247130000 # Total cycles spent in databus access 176system.physmem.totBankLat 5544522500 # Total cycles spent in bank access 177system.physmem.avgQLat 17122.81 # Average queueing delay per request 178system.physmem.avgBankLat 12336.90 # Average bank access latency per request | 171system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see 173system.physmem.totQLat 7717714750 # Total cycles spent in queuing delays 174system.physmem.totMemAccLat 15508692250 # Sum of mem lat for all requests 175system.physmem.totBusLat 2247060000 # Total cycles spent in databus access 176system.physmem.totBankLat 5543917500 # Total cycles spent in bank access 177system.physmem.avgQLat 17172.92 # Average queueing delay per request 178system.physmem.avgBankLat 12335.94 # Average bank access latency per request |
| 179system.physmem.avgBusLat 5000.00 # Average bus latency per request | 179system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 180system.physmem.avgMemAccLat 34459.71 # Average memory access latency 181system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s | 180system.physmem.avgMemAccLat 34508.85 # Average memory access latency 181system.physmem.avgRdBW 15.13 # Average achieved read bandwidth in MB/s |
| 182system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s | 182system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s |
| 183system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s | 183system.physmem.avgConsumedRdBW 15.13 # Average consumed read bandwidth in MB/s |
| 184system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s 185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 186system.physmem.busUtil 0.15 # Data bus utilization in percentage 187system.physmem.avgRdQLen 0.01 # Average read queue length over time | 184system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s 185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 186system.physmem.busUtil 0.15 # Data bus utilization in percentage 187system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 188system.physmem.avgWrQLen 9.46 # Average write queue length over time 189system.physmem.readRowHits 421587 # Number of row buffer hits during reads 190system.physmem.writeRowHits 92850 # Number of row buffer hits during writes 191system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads 192system.physmem.writeRowHitRate 76.87 # Row buffer hit rate for writes 193system.physmem.avgGap 3332940.18 # Average gap between requests 194system.l2c.replacements 342617 # number of replacements 195system.l2c.tagsinuse 65285.001346 # Cycle average of tags in use 196system.l2c.total_refs 2569094 # Total number of references to valid blocks. | 188system.physmem.avgWrQLen 9.47 # Average write queue length over time 189system.physmem.readRowHits 421565 # Number of row buffer hits during reads 190system.physmem.writeRowHits 92877 # Number of row buffer hits during writes 191system.physmem.readRowHitRate 93.80 # Row buffer hit rate for reads 192system.physmem.writeRowHitRate 76.90 # Row buffer hit rate for writes 193system.physmem.avgGap 3333023.20 # Average gap between requests 194system.l2c.replacements 342612 # number of replacements 195system.l2c.tagsinuse 65284.978501 # Cycle average of tags in use 196system.l2c.total_refs 2568846 # Total number of references to valid blocks. |
| 197system.l2c.sampled_refs 407591 # Sample count of references to valid blocks. | 197system.l2c.sampled_refs 407591 # Sample count of references to valid blocks. |
| 198system.l2c.avg_refs 6.303118 # Average number of references to valid blocks. | 198system.l2c.avg_refs 6.302509 # Average number of references to valid blocks. |
| 199system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. | 199system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. |
| 200system.l2c.occ_blocks::writebacks 53776.663341 # Average occupied blocks per requestor 201system.l2c.occ_blocks::cpu0.inst 5305.450361 # Average occupied blocks per requestor 202system.l2c.occ_blocks::cpu0.data 5913.032495 # Average occupied blocks per requestor 203system.l2c.occ_blocks::cpu1.inst 209.604016 # Average occupied blocks per requestor 204system.l2c.occ_blocks::cpu1.data 80.251133 # Average occupied blocks per requestor 205system.l2c.occ_percent::writebacks 0.820567 # Average percentage of cache occupancy 206system.l2c.occ_percent::cpu0.inst 0.080955 # Average percentage of cache occupancy 207system.l2c.occ_percent::cpu0.data 0.090226 # Average percentage of cache occupancy 208system.l2c.occ_percent::cpu1.inst 0.003198 # Average percentage of cache occupancy | 200system.l2c.occ_blocks::writebacks 53776.613719 # Average occupied blocks per requestor 201system.l2c.occ_blocks::cpu0.inst 5305.208058 # Average occupied blocks per requestor 202system.l2c.occ_blocks::cpu0.data 5913.214949 # Average occupied blocks per requestor 203system.l2c.occ_blocks::cpu1.inst 209.652371 # Average occupied blocks per requestor 204system.l2c.occ_blocks::cpu1.data 80.289403 # Average occupied blocks per requestor 205system.l2c.occ_percent::writebacks 0.820566 # Average percentage of cache occupancy 206system.l2c.occ_percent::cpu0.inst 0.080951 # Average percentage of cache occupancy 207system.l2c.occ_percent::cpu0.data 0.090228 # Average percentage of cache occupancy 208system.l2c.occ_percent::cpu1.inst 0.003199 # Average percentage of cache occupancy |
| 209system.l2c.occ_percent::cpu1.data 0.001225 # Average percentage of cache occupancy 210system.l2c.occ_percent::total 0.996170 # Average percentage of cache occupancy | 209system.l2c.occ_percent::cpu1.data 0.001225 # Average percentage of cache occupancy 210system.l2c.occ_percent::total 0.996170 # Average percentage of cache occupancy |
| 211system.l2c.ReadReq_hits::cpu0.inst 815796 # number of ReadReq hits 212system.l2c.ReadReq_hits::cpu0.data 714354 # number of ReadReq hits 213system.l2c.ReadReq_hits::cpu1.inst 262043 # number of ReadReq hits 214system.l2c.ReadReq_hits::cpu1.data 83568 # number of ReadReq hits 215system.l2c.ReadReq_hits::total 1875761 # number of ReadReq hits 216system.l2c.Writeback_hits::writebacks 814734 # number of Writeback hits 217system.l2c.Writeback_hits::total 814734 # number of Writeback hits 218system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits 219system.l2c.UpgradeReq_hits::cpu1.data 351 # number of UpgradeReq hits 220system.l2c.UpgradeReq_hits::total 525 # number of UpgradeReq hits | 211system.l2c.ReadReq_hits::cpu0.inst 815517 # number of ReadReq hits 212system.l2c.ReadReq_hits::cpu0.data 714323 # number of ReadReq hits 213system.l2c.ReadReq_hits::cpu1.inst 262022 # number of ReadReq hits 214system.l2c.ReadReq_hits::cpu1.data 83603 # number of ReadReq hits 215system.l2c.ReadReq_hits::total 1875465 # number of ReadReq hits 216system.l2c.Writeback_hits::writebacks 814738 # number of Writeback hits 217system.l2c.Writeback_hits::total 814738 # number of Writeback hits 218system.l2c.UpgradeReq_hits::cpu0.data 171 # number of UpgradeReq hits 219system.l2c.UpgradeReq_hits::cpu1.data 348 # number of UpgradeReq hits 220system.l2c.UpgradeReq_hits::total 519 # number of UpgradeReq hits |
| 221system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits | 221system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits |
| 222system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits 223system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits 224system.l2c.ReadExReq_hits::cpu0.data 146833 # number of ReadExReq hits 225system.l2c.ReadExReq_hits::cpu1.data 31831 # number of ReadExReq hits 226system.l2c.ReadExReq_hits::total 178664 # number of ReadExReq hits 227system.l2c.demand_hits::cpu0.inst 815796 # number of demand (read+write) hits 228system.l2c.demand_hits::cpu0.data 861187 # number of demand (read+write) hits 229system.l2c.demand_hits::cpu1.inst 262043 # number of demand (read+write) hits 230system.l2c.demand_hits::cpu1.data 115399 # number of demand (read+write) hits 231system.l2c.demand_hits::total 2054425 # number of demand (read+write) hits 232system.l2c.overall_hits::cpu0.inst 815796 # number of overall hits 233system.l2c.overall_hits::cpu0.data 861187 # number of overall hits 234system.l2c.overall_hits::cpu1.inst 262043 # number of overall hits 235system.l2c.overall_hits::cpu1.data 115399 # number of overall hits 236system.l2c.overall_hits::total 2054425 # number of overall hits 237system.l2c.ReadReq_misses::cpu0.inst 13356 # number of ReadReq misses 238system.l2c.ReadReq_misses::cpu0.data 272983 # number of ReadReq misses 239system.l2c.ReadReq_misses::cpu1.inst 1945 # number of ReadReq misses 240system.l2c.ReadReq_misses::cpu1.data 897 # number of ReadReq misses 241system.l2c.ReadReq_misses::total 289181 # number of ReadReq misses 242system.l2c.UpgradeReq_misses::cpu0.data 2769 # number of UpgradeReq misses 243system.l2c.UpgradeReq_misses::cpu1.data 1340 # number of UpgradeReq misses 244system.l2c.UpgradeReq_misses::total 4109 # number of UpgradeReq misses | 222system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits 223system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits 224system.l2c.ReadExReq_hits::cpu0.data 146870 # number of ReadExReq hits 225system.l2c.ReadExReq_hits::cpu1.data 31835 # number of ReadExReq hits 226system.l2c.ReadExReq_hits::total 178705 # number of ReadExReq hits 227system.l2c.demand_hits::cpu0.inst 815517 # number of demand (read+write) hits 228system.l2c.demand_hits::cpu0.data 861193 # number of demand (read+write) hits 229system.l2c.demand_hits::cpu1.inst 262022 # number of demand (read+write) hits 230system.l2c.demand_hits::cpu1.data 115438 # number of demand (read+write) hits 231system.l2c.demand_hits::total 2054170 # number of demand (read+write) hits 232system.l2c.overall_hits::cpu0.inst 815517 # number of overall hits 233system.l2c.overall_hits::cpu0.data 861193 # number of overall hits 234system.l2c.overall_hits::cpu1.inst 262022 # number of overall hits 235system.l2c.overall_hits::cpu1.data 115438 # number of overall hits 236system.l2c.overall_hits::total 2054170 # number of overall hits 237system.l2c.ReadReq_misses::cpu0.inst 13350 # number of ReadReq misses 238system.l2c.ReadReq_misses::cpu0.data 272975 # number of ReadReq misses 239system.l2c.ReadReq_misses::cpu1.inst 1943 # number of ReadReq misses 240system.l2c.ReadReq_misses::cpu1.data 909 # number of ReadReq misses 241system.l2c.ReadReq_misses::total 289177 # number of ReadReq misses 242system.l2c.UpgradeReq_misses::cpu0.data 2763 # number of UpgradeReq misses 243system.l2c.UpgradeReq_misses::cpu1.data 1336 # number of UpgradeReq misses 244system.l2c.UpgradeReq_misses::total 4099 # number of UpgradeReq misses |
| 245system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses 246system.l2c.SCUpgradeReq_misses::cpu1.data 587 # number of SCUpgradeReq misses 247system.l2c.SCUpgradeReq_misses::total 1147 # number of SCUpgradeReq misses | 245system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses 246system.l2c.SCUpgradeReq_misses::cpu1.data 587 # number of SCUpgradeReq misses 247system.l2c.SCUpgradeReq_misses::total 1147 # number of SCUpgradeReq misses |
| 248system.l2c.ReadExReq_misses::cpu0.data 111939 # number of ReadExReq misses 249system.l2c.ReadExReq_misses::cpu1.data 7676 # number of ReadExReq misses 250system.l2c.ReadExReq_misses::total 119615 # number of ReadExReq misses 251system.l2c.demand_misses::cpu0.inst 13356 # number of demand (read+write) misses 252system.l2c.demand_misses::cpu0.data 384922 # number of demand (read+write) misses 253system.l2c.demand_misses::cpu1.inst 1945 # number of demand (read+write) misses 254system.l2c.demand_misses::cpu1.data 8573 # number of demand (read+write) misses 255system.l2c.demand_misses::total 408796 # number of demand (read+write) misses 256system.l2c.overall_misses::cpu0.inst 13356 # number of overall misses 257system.l2c.overall_misses::cpu0.data 384922 # number of overall misses 258system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses 259system.l2c.overall_misses::cpu1.data 8573 # number of overall misses 260system.l2c.overall_misses::total 408796 # number of overall misses 261system.l2c.ReadReq_miss_latency::cpu0.inst 905864000 # number of ReadReq miss cycles 262system.l2c.ReadReq_miss_latency::cpu0.data 11898970000 # number of ReadReq miss cycles 263system.l2c.ReadReq_miss_latency::cpu1.inst 151230500 # number of ReadReq miss cycles 264system.l2c.ReadReq_miss_latency::cpu1.data 68201999 # number of ReadReq miss cycles 265system.l2c.ReadReq_miss_latency::total 13024266499 # number of ReadReq miss cycles 266system.l2c.UpgradeReq_miss_latency::cpu0.data 960000 # number of UpgradeReq miss cycles 267system.l2c.UpgradeReq_miss_latency::cpu1.data 6372986 # number of UpgradeReq miss cycles 268system.l2c.UpgradeReq_miss_latency::total 7332986 # number of UpgradeReq miss cycles 269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 888499 # number of SCUpgradeReq miss cycles 270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136000 # number of SCUpgradeReq miss cycles 271system.l2c.SCUpgradeReq_miss_latency::total 1024499 # number of SCUpgradeReq miss cycles 272system.l2c.ReadExReq_miss_latency::cpu0.data 7329049500 # number of ReadExReq miss cycles 273system.l2c.ReadExReq_miss_latency::cpu1.data 758770499 # number of ReadExReq miss cycles 274system.l2c.ReadExReq_miss_latency::total 8087819999 # number of ReadExReq miss cycles 275system.l2c.demand_miss_latency::cpu0.inst 905864000 # number of demand (read+write) miss cycles 276system.l2c.demand_miss_latency::cpu0.data 19228019500 # number of demand (read+write) miss cycles 277system.l2c.demand_miss_latency::cpu1.inst 151230500 # number of demand (read+write) miss cycles 278system.l2c.demand_miss_latency::cpu1.data 826972498 # number of demand (read+write) miss cycles 279system.l2c.demand_miss_latency::total 21112086498 # number of demand (read+write) miss cycles 280system.l2c.overall_miss_latency::cpu0.inst 905864000 # number of overall miss cycles 281system.l2c.overall_miss_latency::cpu0.data 19228019500 # number of overall miss cycles 282system.l2c.overall_miss_latency::cpu1.inst 151230500 # number of overall miss cycles 283system.l2c.overall_miss_latency::cpu1.data 826972498 # number of overall miss cycles 284system.l2c.overall_miss_latency::total 21112086498 # number of overall miss cycles 285system.l2c.ReadReq_accesses::cpu0.inst 829152 # number of ReadReq accesses(hits+misses) 286system.l2c.ReadReq_accesses::cpu0.data 987337 # number of ReadReq accesses(hits+misses) 287system.l2c.ReadReq_accesses::cpu1.inst 263988 # number of ReadReq accesses(hits+misses) 288system.l2c.ReadReq_accesses::cpu1.data 84465 # number of ReadReq accesses(hits+misses) 289system.l2c.ReadReq_accesses::total 2164942 # number of ReadReq accesses(hits+misses) 290system.l2c.Writeback_accesses::writebacks 814734 # number of Writeback accesses(hits+misses) 291system.l2c.Writeback_accesses::total 814734 # number of Writeback accesses(hits+misses) 292system.l2c.UpgradeReq_accesses::cpu0.data 2943 # number of UpgradeReq accesses(hits+misses) 293system.l2c.UpgradeReq_accesses::cpu1.data 1691 # number of UpgradeReq accesses(hits+misses) 294system.l2c.UpgradeReq_accesses::total 4634 # number of UpgradeReq accesses(hits+misses) | 248system.l2c.ReadExReq_misses::cpu0.data 111935 # number of ReadExReq misses 249system.l2c.ReadExReq_misses::cpu1.data 7677 # number of ReadExReq misses 250system.l2c.ReadExReq_misses::total 119612 # number of ReadExReq misses 251system.l2c.demand_misses::cpu0.inst 13350 # number of demand (read+write) misses 252system.l2c.demand_misses::cpu0.data 384910 # number of demand (read+write) misses 253system.l2c.demand_misses::cpu1.inst 1943 # number of demand (read+write) misses 254system.l2c.demand_misses::cpu1.data 8586 # number of demand (read+write) misses 255system.l2c.demand_misses::total 408789 # number of demand (read+write) misses 256system.l2c.overall_misses::cpu0.inst 13350 # number of overall misses 257system.l2c.overall_misses::cpu0.data 384910 # number of overall misses 258system.l2c.overall_misses::cpu1.inst 1943 # number of overall misses 259system.l2c.overall_misses::cpu1.data 8586 # number of overall misses 260system.l2c.overall_misses::total 408789 # number of overall misses 261system.l2c.ReadReq_miss_latency::cpu0.inst 905376000 # number of ReadReq miss cycles 262system.l2c.ReadReq_miss_latency::cpu0.data 11896032500 # number of ReadReq miss cycles 263system.l2c.ReadReq_miss_latency::cpu1.inst 147196500 # number of ReadReq miss cycles 264system.l2c.ReadReq_miss_latency::cpu1.data 67006500 # number of ReadReq miss cycles 265system.l2c.ReadReq_miss_latency::total 13015611500 # number of ReadReq miss cycles 266system.l2c.UpgradeReq_miss_latency::cpu0.data 1013500 # number of UpgradeReq miss cycles 267system.l2c.UpgradeReq_miss_latency::cpu1.data 6347986 # number of UpgradeReq miss cycles 268system.l2c.UpgradeReq_miss_latency::total 7361486 # number of UpgradeReq miss cycles 269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 894999 # number of SCUpgradeReq miss cycles 270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 135500 # number of SCUpgradeReq miss cycles 271system.l2c.SCUpgradeReq_miss_latency::total 1030499 # number of SCUpgradeReq miss cycles 272system.l2c.ReadExReq_miss_latency::cpu0.data 7317066000 # number of ReadExReq miss cycles 273system.l2c.ReadExReq_miss_latency::cpu1.data 777197999 # number of ReadExReq miss cycles 274system.l2c.ReadExReq_miss_latency::total 8094263999 # number of ReadExReq miss cycles 275system.l2c.demand_miss_latency::cpu0.inst 905376000 # number of demand (read+write) miss cycles 276system.l2c.demand_miss_latency::cpu0.data 19213098500 # number of demand (read+write) miss cycles 277system.l2c.demand_miss_latency::cpu1.inst 147196500 # number of demand (read+write) miss cycles 278system.l2c.demand_miss_latency::cpu1.data 844204499 # number of demand (read+write) miss cycles 279system.l2c.demand_miss_latency::total 21109875499 # number of demand (read+write) miss cycles 280system.l2c.overall_miss_latency::cpu0.inst 905376000 # number of overall miss cycles 281system.l2c.overall_miss_latency::cpu0.data 19213098500 # number of overall miss cycles 282system.l2c.overall_miss_latency::cpu1.inst 147196500 # number of overall miss cycles 283system.l2c.overall_miss_latency::cpu1.data 844204499 # number of overall miss cycles 284system.l2c.overall_miss_latency::total 21109875499 # number of overall miss cycles 285system.l2c.ReadReq_accesses::cpu0.inst 828867 # number of ReadReq accesses(hits+misses) 286system.l2c.ReadReq_accesses::cpu0.data 987298 # number of ReadReq accesses(hits+misses) 287system.l2c.ReadReq_accesses::cpu1.inst 263965 # number of ReadReq accesses(hits+misses) 288system.l2c.ReadReq_accesses::cpu1.data 84512 # number of ReadReq accesses(hits+misses) 289system.l2c.ReadReq_accesses::total 2164642 # number of ReadReq accesses(hits+misses) 290system.l2c.Writeback_accesses::writebacks 814738 # number of Writeback accesses(hits+misses) 291system.l2c.Writeback_accesses::total 814738 # number of Writeback accesses(hits+misses) 292system.l2c.UpgradeReq_accesses::cpu0.data 2934 # number of UpgradeReq accesses(hits+misses) 293system.l2c.UpgradeReq_accesses::cpu1.data 1684 # number of UpgradeReq accesses(hits+misses) 294system.l2c.UpgradeReq_accesses::total 4618 # number of UpgradeReq accesses(hits+misses) |
| 295system.l2c.SCUpgradeReq_accesses::cpu0.data 608 # number of SCUpgradeReq accesses(hits+misses) | 295system.l2c.SCUpgradeReq_accesses::cpu0.data 608 # number of SCUpgradeReq accesses(hits+misses) |
| 296system.l2c.SCUpgradeReq_accesses::cpu1.data 615 # number of SCUpgradeReq accesses(hits+misses) 297system.l2c.SCUpgradeReq_accesses::total 1223 # number of SCUpgradeReq accesses(hits+misses) 298system.l2c.ReadExReq_accesses::cpu0.data 258772 # number of ReadExReq accesses(hits+misses) 299system.l2c.ReadExReq_accesses::cpu1.data 39507 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_accesses::total 298279 # number of ReadExReq accesses(hits+misses) 301system.l2c.demand_accesses::cpu0.inst 829152 # number of demand (read+write) accesses 302system.l2c.demand_accesses::cpu0.data 1246109 # number of demand (read+write) accesses 303system.l2c.demand_accesses::cpu1.inst 263988 # number of demand (read+write) accesses 304system.l2c.demand_accesses::cpu1.data 123972 # number of demand (read+write) accesses 305system.l2c.demand_accesses::total 2463221 # number of demand (read+write) accesses 306system.l2c.overall_accesses::cpu0.inst 829152 # number of overall (read+write) accesses 307system.l2c.overall_accesses::cpu0.data 1246109 # number of overall (read+write) accesses 308system.l2c.overall_accesses::cpu1.inst 263988 # number of overall (read+write) accesses 309system.l2c.overall_accesses::cpu1.data 123972 # number of overall (read+write) accesses 310system.l2c.overall_accesses::total 2463221 # number of overall (read+write) accesses 311system.l2c.ReadReq_miss_rate::cpu0.inst 0.016108 # miss rate for ReadReq accesses 312system.l2c.ReadReq_miss_rate::cpu0.data 0.276484 # miss rate for ReadReq accesses 313system.l2c.ReadReq_miss_rate::cpu1.inst 0.007368 # miss rate for ReadReq accesses 314system.l2c.ReadReq_miss_rate::cpu1.data 0.010620 # miss rate for ReadReq accesses 315system.l2c.ReadReq_miss_rate::total 0.133574 # miss rate for ReadReq accesses 316system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940877 # miss rate for UpgradeReq accesses 317system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792431 # miss rate for UpgradeReq accesses 318system.l2c.UpgradeReq_miss_rate::total 0.886707 # miss rate for UpgradeReq accesses | 296system.l2c.SCUpgradeReq_accesses::cpu1.data 614 # number of SCUpgradeReq accesses(hits+misses) 297system.l2c.SCUpgradeReq_accesses::total 1222 # number of SCUpgradeReq accesses(hits+misses) 298system.l2c.ReadExReq_accesses::cpu0.data 258805 # number of ReadExReq accesses(hits+misses) 299system.l2c.ReadExReq_accesses::cpu1.data 39512 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_accesses::total 298317 # number of ReadExReq accesses(hits+misses) 301system.l2c.demand_accesses::cpu0.inst 828867 # number of demand (read+write) accesses 302system.l2c.demand_accesses::cpu0.data 1246103 # number of demand (read+write) accesses 303system.l2c.demand_accesses::cpu1.inst 263965 # number of demand (read+write) accesses 304system.l2c.demand_accesses::cpu1.data 124024 # number of demand (read+write) accesses 305system.l2c.demand_accesses::total 2462959 # number of demand (read+write) accesses 306system.l2c.overall_accesses::cpu0.inst 828867 # number of overall (read+write) accesses 307system.l2c.overall_accesses::cpu0.data 1246103 # number of overall (read+write) accesses 308system.l2c.overall_accesses::cpu1.inst 263965 # number of overall (read+write) accesses 309system.l2c.overall_accesses::cpu1.data 124024 # number of overall (read+write) accesses 310system.l2c.overall_accesses::total 2462959 # number of overall (read+write) accesses 311system.l2c.ReadReq_miss_rate::cpu0.inst 0.016106 # miss rate for ReadReq accesses 312system.l2c.ReadReq_miss_rate::cpu0.data 0.276487 # miss rate for ReadReq accesses 313system.l2c.ReadReq_miss_rate::cpu1.inst 0.007361 # miss rate for ReadReq accesses 314system.l2c.ReadReq_miss_rate::cpu1.data 0.010756 # miss rate for ReadReq accesses 315system.l2c.ReadReq_miss_rate::total 0.133591 # miss rate for ReadReq accesses 316system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941718 # miss rate for UpgradeReq accesses 317system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793349 # miss rate for UpgradeReq accesses 318system.l2c.UpgradeReq_miss_rate::total 0.887614 # miss rate for UpgradeReq accesses |
| 319system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921053 # miss rate for SCUpgradeReq accesses | 319system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921053 # miss rate for SCUpgradeReq accesses |
| 320system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.954472 # miss rate for SCUpgradeReq accesses 321system.l2c.SCUpgradeReq_miss_rate::total 0.937858 # miss rate for SCUpgradeReq accesses 322system.l2c.ReadExReq_miss_rate::cpu0.data 0.432578 # miss rate for ReadExReq accesses | 320system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956026 # miss rate for SCUpgradeReq accesses 321system.l2c.SCUpgradeReq_miss_rate::total 0.938625 # miss rate for SCUpgradeReq accesses 322system.l2c.ReadExReq_miss_rate::cpu0.data 0.432507 # miss rate for ReadExReq accesses |
| 323system.l2c.ReadExReq_miss_rate::cpu1.data 0.194295 # miss rate for ReadExReq accesses | 323system.l2c.ReadExReq_miss_rate::cpu1.data 0.194295 # miss rate for ReadExReq accesses |
| 324system.l2c.ReadExReq_miss_rate::total 0.401017 # miss rate for ReadExReq accesses 325system.l2c.demand_miss_rate::cpu0.inst 0.016108 # miss rate for demand accesses 326system.l2c.demand_miss_rate::cpu0.data 0.308899 # miss rate for demand accesses 327system.l2c.demand_miss_rate::cpu1.inst 0.007368 # miss rate for demand accesses 328system.l2c.demand_miss_rate::cpu1.data 0.069153 # miss rate for demand accesses 329system.l2c.demand_miss_rate::total 0.165960 # miss rate for demand accesses 330system.l2c.overall_miss_rate::cpu0.inst 0.016108 # miss rate for overall accesses 331system.l2c.overall_miss_rate::cpu0.data 0.308899 # miss rate for overall accesses 332system.l2c.overall_miss_rate::cpu1.inst 0.007368 # miss rate for overall accesses 333system.l2c.overall_miss_rate::cpu1.data 0.069153 # miss rate for overall accesses 334system.l2c.overall_miss_rate::total 0.165960 # miss rate for overall accesses 335system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67824.498353 # average ReadReq miss latency 336system.l2c.ReadReq_avg_miss_latency::cpu0.data 43588.685010 # average ReadReq miss latency 337system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77753.470437 # average ReadReq miss latency 338system.l2c.ReadReq_avg_miss_latency::cpu1.data 76033.443701 # average ReadReq miss latency 339system.l2c.ReadReq_avg_miss_latency::total 45038.458609 # average ReadReq miss latency 340system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 346.695558 # average UpgradeReq miss latency 341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4755.959701 # average UpgradeReq miss latency 342system.l2c.UpgradeReq_avg_miss_latency::total 1784.615722 # average UpgradeReq miss latency 343system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1586.605357 # average SCUpgradeReq miss latency 344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 231.686542 # average SCUpgradeReq miss latency 345system.l2c.SCUpgradeReq_avg_miss_latency::total 893.198779 # average SCUpgradeReq miss latency 346system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65473.601694 # average ReadExReq miss latency 347system.l2c.ReadExReq_avg_miss_latency::cpu1.data 98849.726290 # average ReadExReq miss latency 348system.l2c.ReadExReq_avg_miss_latency::total 67615.432839 # average ReadExReq miss latency 349system.l2c.demand_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency 350system.l2c.demand_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency 351system.l2c.demand_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency 352system.l2c.demand_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency 353system.l2c.demand_avg_miss_latency::total 51644.552535 # average overall miss latency 354system.l2c.overall_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency 355system.l2c.overall_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency 356system.l2c.overall_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency 357system.l2c.overall_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency 358system.l2c.overall_avg_miss_latency::total 51644.552535 # average overall miss latency | 324system.l2c.ReadExReq_miss_rate::total 0.400956 # miss rate for ReadExReq accesses 325system.l2c.demand_miss_rate::cpu0.inst 0.016106 # miss rate for demand accesses 326system.l2c.demand_miss_rate::cpu0.data 0.308891 # miss rate for demand accesses 327system.l2c.demand_miss_rate::cpu1.inst 0.007361 # miss rate for demand accesses 328system.l2c.demand_miss_rate::cpu1.data 0.069229 # miss rate for demand accesses 329system.l2c.demand_miss_rate::total 0.165975 # miss rate for demand accesses 330system.l2c.overall_miss_rate::cpu0.inst 0.016106 # miss rate for overall accesses 331system.l2c.overall_miss_rate::cpu0.data 0.308891 # miss rate for overall accesses 332system.l2c.overall_miss_rate::cpu1.inst 0.007361 # miss rate for overall accesses 333system.l2c.overall_miss_rate::cpu1.data 0.069229 # miss rate for overall accesses 334system.l2c.overall_miss_rate::total 0.165975 # miss rate for overall accesses 335system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67818.426966 # average ReadReq miss latency 336system.l2c.ReadReq_avg_miss_latency::cpu0.data 43579.201392 # average ReadReq miss latency 337system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75757.334020 # average ReadReq miss latency 338system.l2c.ReadReq_avg_miss_latency::cpu1.data 73714.521452 # average ReadReq miss latency 339system.l2c.ReadReq_avg_miss_latency::total 45009.151834 # average ReadReq miss latency 340system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 366.811437 # average UpgradeReq miss latency 341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4751.486527 # average UpgradeReq miss latency 342system.l2c.UpgradeReq_avg_miss_latency::total 1795.922420 # average UpgradeReq miss latency 343system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1598.212500 # average SCUpgradeReq miss latency 344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 230.834753 # average SCUpgradeReq miss latency 345system.l2c.SCUpgradeReq_avg_miss_latency::total 898.429817 # average SCUpgradeReq miss latency 346system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65368.883727 # average ReadExReq miss latency 347system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101237.201902 # average ReadExReq miss latency 348system.l2c.ReadExReq_avg_miss_latency::total 67671.002901 # average ReadExReq miss latency 349system.l2c.demand_avg_miss_latency::cpu0.inst 67818.426966 # average overall miss latency 350system.l2c.demand_avg_miss_latency::cpu0.data 49915.820581 # average overall miss latency 351system.l2c.demand_avg_miss_latency::cpu1.inst 75757.334020 # average overall miss latency 352system.l2c.demand_avg_miss_latency::cpu1.data 98323.375146 # average overall miss latency 353system.l2c.demand_avg_miss_latency::total 51640.028227 # average overall miss latency 354system.l2c.overall_avg_miss_latency::cpu0.inst 67818.426966 # average overall miss latency 355system.l2c.overall_avg_miss_latency::cpu0.data 49915.820581 # average overall miss latency 356system.l2c.overall_avg_miss_latency::cpu1.inst 75757.334020 # average overall miss latency 357system.l2c.overall_avg_miss_latency::cpu1.data 98323.375146 # average overall miss latency 358system.l2c.overall_avg_miss_latency::total 51640.028227 # average overall miss latency |
| 359system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 362system.l2c.blocked::no_targets 0 # number of cycles access was blocked 363system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.l2c.fast_writes 0 # number of fast writes performed 366system.l2c.cache_copies 0 # number of cache copies performed | 359system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 362system.l2c.blocked::no_targets 0 # number of cycles access was blocked 363system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.l2c.fast_writes 0 # number of fast writes performed 366system.l2c.cache_copies 0 # number of cache copies performed |
| 367system.l2c.writebacks::writebacks 79271 # number of writebacks 368system.l2c.writebacks::total 79271 # number of writebacks | 367system.l2c.writebacks::writebacks 79262 # number of writebacks 368system.l2c.writebacks::total 79262 # number of writebacks |
| 369system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 370system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 371system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 372system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 373system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 374system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 375system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 376system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 377system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 378system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 379system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 380system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits | 369system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 370system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 371system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 372system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 373system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 374system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 375system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 376system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 377system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 378system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 379system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 380system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits |
| 381system.l2c.ReadReq_mshr_misses::cpu0.inst 13355 # number of ReadReq MSHR misses 382system.l2c.ReadReq_mshr_misses::cpu0.data 272983 # number of ReadReq MSHR misses 383system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses 384system.l2c.ReadReq_mshr_misses::cpu1.data 896 # number of ReadReq MSHR misses 385system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses 386system.l2c.UpgradeReq_mshr_misses::cpu0.data 2769 # number of UpgradeReq MSHR misses 387system.l2c.UpgradeReq_mshr_misses::cpu1.data 1340 # number of UpgradeReq MSHR misses 388system.l2c.UpgradeReq_mshr_misses::total 4109 # number of UpgradeReq MSHR misses | 381system.l2c.ReadReq_mshr_misses::cpu0.inst 13349 # number of ReadReq MSHR misses 382system.l2c.ReadReq_mshr_misses::cpu0.data 272975 # number of ReadReq MSHR misses 383system.l2c.ReadReq_mshr_misses::cpu1.inst 1927 # number of ReadReq MSHR misses 384system.l2c.ReadReq_mshr_misses::cpu1.data 908 # number of ReadReq MSHR misses 385system.l2c.ReadReq_mshr_misses::total 289159 # number of ReadReq MSHR misses 386system.l2c.UpgradeReq_mshr_misses::cpu0.data 2763 # number of UpgradeReq MSHR misses 387system.l2c.UpgradeReq_mshr_misses::cpu1.data 1336 # number of UpgradeReq MSHR misses 388system.l2c.UpgradeReq_mshr_misses::total 4099 # number of UpgradeReq MSHR misses |
| 389system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses 390system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 587 # number of SCUpgradeReq MSHR misses 391system.l2c.SCUpgradeReq_mshr_misses::total 1147 # number of SCUpgradeReq MSHR misses | 389system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses 390system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 587 # number of SCUpgradeReq MSHR misses 391system.l2c.SCUpgradeReq_mshr_misses::total 1147 # number of SCUpgradeReq MSHR misses |
| 392system.l2c.ReadExReq_mshr_misses::cpu0.data 111939 # number of ReadExReq MSHR misses 393system.l2c.ReadExReq_mshr_misses::cpu1.data 7676 # number of ReadExReq MSHR misses 394system.l2c.ReadExReq_mshr_misses::total 119615 # number of ReadExReq MSHR misses 395system.l2c.demand_mshr_misses::cpu0.inst 13355 # number of demand (read+write) MSHR misses 396system.l2c.demand_mshr_misses::cpu0.data 384922 # number of demand (read+write) MSHR misses 397system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses 398system.l2c.demand_mshr_misses::cpu1.data 8572 # number of demand (read+write) MSHR misses 399system.l2c.demand_mshr_misses::total 408778 # number of demand (read+write) MSHR misses 400system.l2c.overall_mshr_misses::cpu0.inst 13355 # number of overall MSHR misses 401system.l2c.overall_mshr_misses::cpu0.data 384922 # number of overall MSHR misses 402system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses 403system.l2c.overall_mshr_misses::cpu1.data 8572 # number of overall MSHR misses 404system.l2c.overall_mshr_misses::total 408778 # number of overall MSHR misses 405system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 739303821 # number of ReadReq MSHR miss cycles 406system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8556722771 # number of ReadReq MSHR miss cycles 407system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 126469885 # number of ReadReq MSHR miss cycles 408system.l2c.ReadReq_mshr_miss_latency::cpu1.data 57202686 # number of ReadReq MSHR miss cycles 409system.l2c.ReadReq_mshr_miss_latency::total 9479699163 # number of ReadReq MSHR miss cycles 410system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27888734 # number of UpgradeReq MSHR miss cycles 411system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13415324 # number of UpgradeReq MSHR miss cycles 412system.l2c.UpgradeReq_mshr_miss_latency::total 41304058 # number of UpgradeReq MSHR miss cycles 413system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5612547 # number of SCUpgradeReq MSHR miss cycles | 392system.l2c.ReadExReq_mshr_misses::cpu0.data 111935 # number of ReadExReq MSHR misses 393system.l2c.ReadExReq_mshr_misses::cpu1.data 7677 # number of ReadExReq MSHR misses 394system.l2c.ReadExReq_mshr_misses::total 119612 # number of ReadExReq MSHR misses 395system.l2c.demand_mshr_misses::cpu0.inst 13349 # number of demand (read+write) MSHR misses 396system.l2c.demand_mshr_misses::cpu0.data 384910 # number of demand (read+write) MSHR misses 397system.l2c.demand_mshr_misses::cpu1.inst 1927 # number of demand (read+write) MSHR misses 398system.l2c.demand_mshr_misses::cpu1.data 8585 # number of demand (read+write) MSHR misses 399system.l2c.demand_mshr_misses::total 408771 # number of demand (read+write) MSHR misses 400system.l2c.overall_mshr_misses::cpu0.inst 13349 # number of overall MSHR misses 401system.l2c.overall_mshr_misses::cpu0.data 384910 # number of overall MSHR misses 402system.l2c.overall_mshr_misses::cpu1.inst 1927 # number of overall MSHR misses 403system.l2c.overall_mshr_misses::cpu1.data 8585 # number of overall MSHR misses 404system.l2c.overall_mshr_misses::total 408771 # number of overall MSHR misses 405system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 738885342 # number of ReadReq MSHR miss cycles 406system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8553784026 # number of ReadReq MSHR miss cycles 407system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122441645 # number of ReadReq MSHR miss cycles 408system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55847948 # number of ReadReq MSHR miss cycles 409system.l2c.ReadReq_mshr_miss_latency::total 9470958961 # number of ReadReq MSHR miss cycles 410system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27836728 # number of UpgradeReq MSHR miss cycles 411system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13416820 # number of UpgradeReq MSHR miss cycles 412system.l2c.UpgradeReq_mshr_miss_latency::total 41253548 # number of UpgradeReq MSHR miss cycles 413system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5620046 # number of SCUpgradeReq MSHR miss cycles |
| 414system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5879586 # number of SCUpgradeReq MSHR miss cycles | 414system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5879586 # number of SCUpgradeReq MSHR miss cycles |
| 415system.l2c.SCUpgradeReq_mshr_miss_latency::total 11492133 # number of SCUpgradeReq MSHR miss cycles 416system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5964907547 # number of ReadExReq MSHR miss cycles 417system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 664977742 # number of ReadExReq MSHR miss cycles 418system.l2c.ReadExReq_mshr_miss_latency::total 6629885289 # number of ReadExReq MSHR miss cycles 419system.l2c.demand_mshr_miss_latency::cpu0.inst 739303821 # number of demand (read+write) MSHR miss cycles 420system.l2c.demand_mshr_miss_latency::cpu0.data 14521630318 # number of demand (read+write) MSHR miss cycles 421system.l2c.demand_mshr_miss_latency::cpu1.inst 126469885 # number of demand (read+write) MSHR miss cycles 422system.l2c.demand_mshr_miss_latency::cpu1.data 722180428 # number of demand (read+write) MSHR miss cycles 423system.l2c.demand_mshr_miss_latency::total 16109584452 # number of demand (read+write) MSHR miss cycles 424system.l2c.overall_mshr_miss_latency::cpu0.inst 739303821 # number of overall MSHR miss cycles 425system.l2c.overall_mshr_miss_latency::cpu0.data 14521630318 # number of overall MSHR miss cycles 426system.l2c.overall_mshr_miss_latency::cpu1.inst 126469885 # number of overall MSHR miss cycles 427system.l2c.overall_mshr_miss_latency::cpu1.data 722180428 # number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::total 16109584452 # number of overall MSHR miss cycles 429system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1362723500 # number of ReadReq MSHR uncacheable cycles 430system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28760000 # number of ReadReq MSHR uncacheable cycles 431system.l2c.ReadReq_mshr_uncacheable_latency::total 1391483500 # number of ReadReq MSHR uncacheable cycles 432system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2034614500 # number of WriteReq MSHR uncacheable cycles 433system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637502000 # number of WriteReq MSHR uncacheable cycles 434system.l2c.WriteReq_mshr_uncacheable_latency::total 2672116500 # number of WriteReq MSHR uncacheable cycles 435system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3397338000 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::cpu1.data 666262000 # number of overall MSHR uncacheable cycles 437system.l2c.overall_mshr_uncacheable_latency::total 4063600000 # number of overall MSHR uncacheable cycles 438system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276484 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010608 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::total 0.133566 # mshr miss rate for ReadReq accesses 443system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940877 # mshr miss rate for UpgradeReq accesses 444system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792431 # mshr miss rate for UpgradeReq accesses 445system.l2c.UpgradeReq_mshr_miss_rate::total 0.886707 # mshr miss rate for UpgradeReq accesses | 415system.l2c.SCUpgradeReq_mshr_miss_latency::total 11499632 # number of SCUpgradeReq MSHR miss cycles 416system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5952955820 # number of ReadExReq MSHR miss cycles 417system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 683390713 # number of ReadExReq MSHR miss cycles 418system.l2c.ReadExReq_mshr_miss_latency::total 6636346533 # number of ReadExReq MSHR miss cycles 419system.l2c.demand_mshr_miss_latency::cpu0.inst 738885342 # number of demand (read+write) MSHR miss cycles 420system.l2c.demand_mshr_miss_latency::cpu0.data 14506739846 # number of demand (read+write) MSHR miss cycles 421system.l2c.demand_mshr_miss_latency::cpu1.inst 122441645 # number of demand (read+write) MSHR miss cycles 422system.l2c.demand_mshr_miss_latency::cpu1.data 739238661 # number of demand (read+write) MSHR miss cycles 423system.l2c.demand_mshr_miss_latency::total 16107305494 # number of demand (read+write) MSHR miss cycles 424system.l2c.overall_mshr_miss_latency::cpu0.inst 738885342 # number of overall MSHR miss cycles 425system.l2c.overall_mshr_miss_latency::cpu0.data 14506739846 # number of overall MSHR miss cycles 426system.l2c.overall_mshr_miss_latency::cpu1.inst 122441645 # number of overall MSHR miss cycles 427system.l2c.overall_mshr_miss_latency::cpu1.data 739238661 # number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::total 16107305494 # number of overall MSHR miss cycles 429system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1360324000 # number of ReadReq MSHR uncacheable cycles 430system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28759000 # number of ReadReq MSHR uncacheable cycles 431system.l2c.ReadReq_mshr_uncacheable_latency::total 1389083000 # number of ReadReq MSHR uncacheable cycles 432system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2032921000 # number of WriteReq MSHR uncacheable cycles 433system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637490500 # number of WriteReq MSHR uncacheable cycles 434system.l2c.WriteReq_mshr_uncacheable_latency::total 2670411500 # number of WriteReq MSHR uncacheable cycles 435system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3393245000 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::cpu1.data 666249500 # number of overall MSHR uncacheable cycles 437system.l2c.overall_mshr_uncacheable_latency::total 4059494500 # number of overall MSHR uncacheable cycles 438system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276487 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010744 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::total 0.133583 # mshr miss rate for ReadReq accesses 443system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941718 # mshr miss rate for UpgradeReq accesses 444system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.793349 # mshr miss rate for UpgradeReq accesses 445system.l2c.UpgradeReq_mshr_miss_rate::total 0.887614 # mshr miss rate for UpgradeReq accesses |
| 446system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921053 # mshr miss rate for SCUpgradeReq accesses | 446system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921053 # mshr miss rate for SCUpgradeReq accesses |
| 447system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954472 # mshr miss rate for SCUpgradeReq accesses 448system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.937858 # mshr miss rate for SCUpgradeReq accesses 449system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.432578 # mshr miss rate for ReadExReq accesses | 447system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956026 # mshr miss rate for SCUpgradeReq accesses 448system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.938625 # mshr miss rate for SCUpgradeReq accesses 449system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.432507 # mshr miss rate for ReadExReq accesses |
| 450system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.194295 # mshr miss rate for ReadExReq accesses | 450system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.194295 # mshr miss rate for ReadExReq accesses |
| 451system.l2c.ReadExReq_mshr_miss_rate::total 0.401017 # mshr miss rate for ReadExReq accesses 452system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for demand accesses 453system.l2c.demand_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for demand accesses 454system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for demand accesses 455system.l2c.demand_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::total 0.165953 # mshr miss rate for demand accesses 457system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for overall accesses 458system.l2c.overall_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for overall accesses 459system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for overall accesses 460system.l2c.overall_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for overall accesses 461system.l2c.overall_mshr_miss_rate::total 0.165953 # mshr miss rate for overall accesses 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31345.258756 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average ReadReq mshr miss latency 465system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63842.283482 # average ReadReq mshr miss latency 466system.l2c.ReadReq_avg_mshr_miss_latency::total 32783.237008 # average ReadReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.771036 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.435821 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.094914 # average UpgradeReq mshr miss latency 470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.405357 # average SCUpgradeReq mshr miss latency | 451system.l2c.ReadExReq_mshr_miss_rate::total 0.400956 # mshr miss rate for ReadExReq accesses 452system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for demand accesses 453system.l2c.demand_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for demand accesses 454system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for demand accesses 455system.l2c.demand_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::total 0.165967 # mshr miss rate for demand accesses 457system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for overall accesses 458system.l2c.overall_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for overall accesses 459system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for overall accesses 460system.l2c.overall_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for overall accesses 461system.l2c.overall_mshr_miss_rate::total 0.165967 # mshr miss rate for overall accesses 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31335.411763 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average ReadReq mshr miss latency 465system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61506.550661 # average ReadReq mshr miss latency 466system.l2c.ReadReq_avg_mshr_miss_latency::total 32753.464222 # average ReadReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10074.820123 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.529940 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10064.295682 # average UpgradeReq mshr miss latency 470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.796429 # average SCUpgradeReq mshr miss latency |
| 471system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494 # average SCUpgradeReq mshr miss latency | 471system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494 # average SCUpgradeReq mshr miss latency |
| 472system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10019.296425 # average SCUpgradeReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53287.125551 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86630.763679 # average ReadExReq mshr miss latency 475system.l2c.ReadExReq_avg_mshr_miss_latency::total 55426.871956 # average ReadExReq mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency | 472system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.834350 # average SCUpgradeReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53182.255952 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89017.938387 # average ReadExReq mshr miss latency 475system.l2c.ReadExReq_avg_mshr_miss_latency::total 55482.280482 # average ReadExReq mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency |
| 486system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 487system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 489system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 490system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 491system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 492system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 493system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 494system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 495system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 496system.iocache.replacements 41699 # number of replacements | 486system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 487system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 489system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 490system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 491system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 492system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 493system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 494system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 495system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 496system.iocache.replacements 41699 # number of replacements |
| 497system.iocache.tagsinuse 0.509415 # Cycle average of tags in use | 497system.iocache.tagsinuse 0.509421 # Cycle average of tags in use |
| 498system.iocache.total_refs 0 # Total number of references to valid blocks. 499system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. 500system.iocache.avg_refs 0 # Average number of references to valid blocks. 501system.iocache.warmup_cycle 1705456216000 # Cycle when the warmup percentage was hit. | 498system.iocache.total_refs 0 # Total number of references to valid blocks. 499system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. 500system.iocache.avg_refs 0 # Average number of references to valid blocks. 501system.iocache.warmup_cycle 1705456216000 # Cycle when the warmup percentage was hit. |
| 502system.iocache.occ_blocks::tsunami.ide 0.509415 # Average occupied blocks per requestor 503system.iocache.occ_percent::tsunami.ide 0.031838 # Average percentage of cache occupancy 504system.iocache.occ_percent::total 0.031838 # Average percentage of cache occupancy | 502system.iocache.occ_blocks::tsunami.ide 0.509421 # Average occupied blocks per requestor 503system.iocache.occ_percent::tsunami.ide 0.031839 # Average percentage of cache occupancy 504system.iocache.occ_percent::total 0.031839 # Average percentage of cache occupancy |
| 505system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 506system.iocache.ReadReq_misses::total 179 # number of ReadReq misses 507system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 508system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 509system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 510system.iocache.demand_misses::total 41731 # number of demand (read+write) misses 511system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 512system.iocache.overall_misses::total 41731 # number of overall misses | 505system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 506system.iocache.ReadReq_misses::total 179 # number of ReadReq misses 507system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 508system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 509system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 510system.iocache.demand_misses::total 41731 # number of demand (read+write) misses 511system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 512system.iocache.overall_misses::total 41731 # number of overall misses |
| 513system.iocache.ReadReq_miss_latency::tsunami.ide 21612998 # number of ReadReq miss cycles 514system.iocache.ReadReq_miss_latency::total 21612998 # number of ReadReq miss cycles 515system.iocache.WriteReq_miss_latency::tsunami.ide 10624659943 # number of WriteReq miss cycles 516system.iocache.WriteReq_miss_latency::total 10624659943 # number of WriteReq miss cycles 517system.iocache.demand_miss_latency::tsunami.ide 10646272941 # number of demand (read+write) miss cycles 518system.iocache.demand_miss_latency::total 10646272941 # number of demand (read+write) miss cycles 519system.iocache.overall_miss_latency::tsunami.ide 10646272941 # number of overall miss cycles 520system.iocache.overall_miss_latency::total 10646272941 # number of overall miss cycles | 513system.iocache.ReadReq_miss_latency::tsunami.ide 21615998 # number of ReadReq miss cycles 514system.iocache.ReadReq_miss_latency::total 21615998 # number of ReadReq miss cycles 515system.iocache.WriteReq_miss_latency::tsunami.ide 10647231164 # number of WriteReq miss cycles 516system.iocache.WriteReq_miss_latency::total 10647231164 # number of WriteReq miss cycles 517system.iocache.demand_miss_latency::tsunami.ide 10668847162 # number of demand (read+write) miss cycles 518system.iocache.demand_miss_latency::total 10668847162 # number of demand (read+write) miss cycles 519system.iocache.overall_miss_latency::tsunami.ide 10668847162 # number of overall miss cycles 520system.iocache.overall_miss_latency::total 10668847162 # number of overall miss cycles |
| 521system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 522system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 523system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 524system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 525system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 526system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 527system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 528system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 529system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 530system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 531system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 532system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 533system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 534system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 535system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 536system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 521system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 522system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) 523system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 524system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 525system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 526system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 527system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 528system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses 529system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 530system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 531system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 532system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 533system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 534system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 535system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 536system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 537system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120743.005587 # average ReadReq miss latency 538system.iocache.ReadReq_avg_miss_latency::total 120743.005587 # average ReadReq miss latency 539system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255695.512683 # average WriteReq miss latency 540system.iocache.WriteReq_avg_miss_latency::total 255695.512683 # average WriteReq miss latency 541system.iocache.demand_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency 542system.iocache.demand_avg_miss_latency::total 255116.650476 # average overall miss latency 543system.iocache.overall_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency 544system.iocache.overall_avg_miss_latency::total 255116.650476 # average overall miss latency 545system.iocache.blocked_cycles::no_mshrs 284705 # number of cycles access was blocked | 537system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120759.765363 # average ReadReq miss latency 538system.iocache.ReadReq_avg_miss_latency::total 120759.765363 # average ReadReq miss latency 539system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885 # average WriteReq miss latency 540system.iocache.WriteReq_avg_miss_latency::total 256238.716885 # average WriteReq miss latency 541system.iocache.demand_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency 542system.iocache.demand_avg_miss_latency::total 255657.596559 # average overall miss latency 543system.iocache.overall_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency 544system.iocache.overall_avg_miss_latency::total 255657.596559 # average overall miss latency 545system.iocache.blocked_cycles::no_mshrs 286486 # number of cycles access was blocked |
| 546system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 546system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 547system.iocache.blocked::no_mshrs 27170 # number of cycles access was blocked | 547system.iocache.blocked::no_mshrs 27218 # number of cycles access was blocked |
| 548system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 548system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 549system.iocache.avg_blocked_cycles::no_mshrs 10.478653 # average number of cycles each access was blocked | 549system.iocache.avg_blocked_cycles::no_mshrs 10.525608 # average number of cycles each access was blocked |
| 550system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.iocache.fast_writes 0 # number of fast writes performed 552system.iocache.cache_copies 0 # number of cache copies performed 553system.iocache.writebacks::writebacks 41520 # number of writebacks 554system.iocache.writebacks::total 41520 # number of writebacks 555system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 556system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 557system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 558system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 559system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 560system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 561system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 562system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses | 550system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.iocache.fast_writes 0 # number of fast writes performed 552system.iocache.cache_copies 0 # number of cache copies performed 553system.iocache.writebacks::writebacks 41520 # number of writebacks 554system.iocache.writebacks::total 41520 # number of writebacks 555system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 556system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses 557system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 558system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 559system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 560system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 561system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 562system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses |
| 563system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12304249 # number of ReadReq MSHR miss cycles 564system.iocache.ReadReq_mshr_miss_latency::total 12304249 # number of ReadReq MSHR miss cycles 565system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8462672446 # number of WriteReq MSHR miss cycles 566system.iocache.WriteReq_mshr_miss_latency::total 8462672446 # number of WriteReq MSHR miss cycles 567system.iocache.demand_mshr_miss_latency::tsunami.ide 8474976695 # number of demand (read+write) MSHR miss cycles 568system.iocache.demand_mshr_miss_latency::total 8474976695 # number of demand (read+write) MSHR miss cycles 569system.iocache.overall_mshr_miss_latency::tsunami.ide 8474976695 # number of overall MSHR miss cycles 570system.iocache.overall_mshr_miss_latency::total 8474976695 # number of overall MSHR miss cycles | 563system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12307249 # number of ReadReq MSHR miss cycles 564system.iocache.ReadReq_mshr_miss_latency::total 12307249 # number of ReadReq MSHR miss cycles 565system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8485239667 # number of WriteReq MSHR miss cycles 566system.iocache.WriteReq_mshr_miss_latency::total 8485239667 # number of WriteReq MSHR miss cycles 567system.iocache.demand_mshr_miss_latency::tsunami.ide 8497546916 # number of demand (read+write) MSHR miss cycles 568system.iocache.demand_mshr_miss_latency::total 8497546916 # number of demand (read+write) MSHR miss cycles 569system.iocache.overall_mshr_miss_latency::tsunami.ide 8497546916 # number of overall MSHR miss cycles 570system.iocache.overall_mshr_miss_latency::total 8497546916 # number of overall MSHR miss cycles |
| 571system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 572system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 573system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 574system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 575system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 576system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 577system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 578system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 571system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 572system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 573system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 574system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 575system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 576system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 577system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 578system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 579system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency 580system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency 581system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency 582system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency 583system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency 584system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency 585system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency 586system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency | 579system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68755.581006 # average ReadReq mshr miss latency 580system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006 # average ReadReq mshr miss latency 581system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204207.731686 # average WriteReq mshr miss latency 582system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686 # average WriteReq mshr miss latency 583system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency 584system.iocache.demand_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency 585system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency 586system.iocache.overall_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency |
| 587system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 589system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 590system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 591system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 592system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 593system.disk0.dma_write_txs 395 # Number of DMA write transactions. 594system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 595system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 596system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 597system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 598system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 599system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 587system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 589system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 590system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 591system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 592system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 593system.disk0.dma_write_txs 395 # Number of DMA write transactions. 594system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 595system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 596system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 597system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 598system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 599system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 600system.cpu0.branchPred.lookups 12043910 # Number of BP lookups 601system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted 602system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect 603system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups 604system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits | 600system.cpu0.branchPred.lookups 12035820 # Number of BP lookups 601system.cpu0.branchPred.condPredicted 10146181 # Number of conditional branches predicted 602system.cpu0.branchPred.condIncorrect 320311 # Number of conditional branches incorrect 603system.cpu0.branchPred.BTBLookups 7799891 # Number of BTB lookups 604system.cpu0.branchPred.BTBHits 5138186 # Number of BTB hits |
| 605system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 605system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 606system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage 607system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target. 608system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions. | 606system.cpu0.branchPred.BTBHitPct 65.875100 # BTB Hit Percentage 607system.cpu0.branchPred.usedRAS 760204 # Number of times the RAS was used to get a target. 608system.cpu0.branchPred.RASInCorrect 30176 # Number of incorrect RAS predictions. |
| 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 613system.cpu0.dtb.read_hits 8552844 # DTB read hits 614system.cpu0.dtb.read_misses 30306 # DTB read misses 615system.cpu0.dtb.read_acv 545 # DTB read access violations 616system.cpu0.dtb.read_accesses 625084 # DTB read accesses 617system.cpu0.dtb.write_hits 5600708 # DTB write hits 618system.cpu0.dtb.write_misses 7703 # DTB write misses 619system.cpu0.dtb.write_acv 337 # DTB write access violations 620system.cpu0.dtb.write_accesses 207517 # DTB write accesses 621system.cpu0.dtb.data_hits 14153552 # DTB hits 622system.cpu0.dtb.data_misses 38009 # DTB misses 623system.cpu0.dtb.data_acv 882 # DTB access violations 624system.cpu0.dtb.data_accesses 832601 # DTB accesses 625system.cpu0.itb.fetch_hits 972187 # ITB hits 626system.cpu0.itb.fetch_misses 27447 # ITB misses 627system.cpu0.itb.fetch_acv 929 # ITB acv 628system.cpu0.itb.fetch_accesses 999634 # ITB accesses | 613system.cpu0.dtb.read_hits 8551483 # DTB read hits 614system.cpu0.dtb.read_misses 30199 # DTB read misses 615system.cpu0.dtb.read_acv 541 # DTB read access violations 616system.cpu0.dtb.read_accesses 624803 # DTB read accesses 617system.cpu0.dtb.write_hits 5601236 # DTB write hits 618system.cpu0.dtb.write_misses 7972 # DTB write misses 619system.cpu0.dtb.write_acv 345 # DTB write access violations 620system.cpu0.dtb.write_accesses 208308 # DTB write accesses 621system.cpu0.dtb.data_hits 14152719 # DTB hits 622system.cpu0.dtb.data_misses 38171 # DTB misses 623system.cpu0.dtb.data_acv 886 # DTB access violations 624system.cpu0.dtb.data_accesses 833111 # DTB accesses 625system.cpu0.itb.fetch_hits 970030 # ITB hits 626system.cpu0.itb.fetch_misses 28776 # ITB misses 627system.cpu0.itb.fetch_acv 920 # ITB acv 628system.cpu0.itb.fetch_accesses 998806 # ITB accesses |
| 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses | 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses |
| 641system.cpu0.numCycles 100158206 # number of cpu cycles simulated | 641system.cpu0.numCycles 100119117 # number of cpu cycles simulated |
| 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 644system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss 645system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed 646system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered 647system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken 648system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked 649system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing 650system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked 651system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 652system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps 653system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions 654system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR 655system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched 656system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed 657system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total) 658system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total) 659system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total) | 644system.cpu0.fetch.icacheStallCycles 24086973 # Number of cycles fetch is stalled on an Icache miss 645system.cpu0.fetch.Insts 61837518 # Number of instructions fetch has processed 646system.cpu0.fetch.Branches 12035820 # Number of branches that fetch encountered 647system.cpu0.fetch.predictedBranches 5898390 # Number of branches that fetch has predicted taken 648system.cpu0.fetch.Cycles 11653378 # Number of cycles fetch has run and was not squashing or blocked 649system.cpu0.fetch.SquashCycles 1636628 # Number of cycles fetch has spent squashing 650system.cpu0.fetch.BlockedCycles 36048574 # Number of cycles fetch has spent blocked 651system.cpu0.fetch.MiscStallCycles 32004 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 652system.cpu0.fetch.PendingTrapStallCycles 195358 # Number of stall cycles due to pending traps 653system.cpu0.fetch.PendingQuiesceStallCycles 286105 # Number of stall cycles due to pending quiesce instructions 654system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR 655system.cpu0.fetch.CacheLines 7499654 # Number of cache lines fetched 656system.cpu0.fetch.IcacheSquashes 215735 # Number of outstanding Icache misses that were squashed 657system.cpu0.fetch.rateDist::samples 73358875 # Number of instructions fetched each cycle (Total) 658system.cpu0.fetch.rateDist::mean 0.842945 # Number of instructions fetched each cycle (Total) 659system.cpu0.fetch.rateDist::stdev 2.179502 # Number of instructions fetched each cycle (Total) |
| 660system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 660system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 661system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total) 662system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total) 663system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total) 664system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total) 665system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total) 666system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total) 667system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total) 668system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total) 669system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total) | 661system.cpu0.fetch.rateDist::0 61705497 84.11% 84.11% # Number of instructions fetched each cycle (Total) 662system.cpu0.fetch.rateDist::1 747609 1.02% 85.13% # Number of instructions fetched each cycle (Total) 663system.cpu0.fetch.rateDist::2 1536097 2.09% 87.23% # Number of instructions fetched each cycle (Total) 664system.cpu0.fetch.rateDist::3 679694 0.93% 88.15% # Number of instructions fetched each cycle (Total) 665system.cpu0.fetch.rateDist::4 2532720 3.45% 91.61% # Number of instructions fetched each cycle (Total) 666system.cpu0.fetch.rateDist::5 506441 0.69% 92.30% # Number of instructions fetched each cycle (Total) 667system.cpu0.fetch.rateDist::6 557934 0.76% 93.06% # Number of instructions fetched each cycle (Total) 668system.cpu0.fetch.rateDist::7 775120 1.06% 94.11% # Number of instructions fetched each cycle (Total) 669system.cpu0.fetch.rateDist::8 4317763 5.89% 100.00% # Number of instructions fetched each cycle (Total) |
| 670system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 671system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 670system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 671system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 673system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle 675system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle 676system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle 677system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked 678system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running 679system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking 680system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing 681system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch 682system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction 683system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode 684system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode 685system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing 686system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle 687system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking 688system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst 689system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running 690system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking 691system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename 692system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full 693system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full 694system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full 695system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed 696system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made 697system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups 698system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups 699system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed 700system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing 701system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed 702system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed 703system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer 704system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit. 705system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit. 706system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads. 707system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores. 708system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec) 709system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ 710system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued 711system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued 712system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling 713system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph 714system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed 715system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle 716system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle 717system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle | 673system.cpu0.fetch.rateDist::total 73358875 # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.branchRate 0.120215 # Number of branch fetches per cycle 675system.cpu0.fetch.rate 0.617639 # Number of inst fetches per cycle 676system.cpu0.decode.IdleCycles 25314409 # Number of cycles decode is idle 677system.cpu0.decode.BlockedCycles 35520182 # Number of cycles decode is blocked 678system.cpu0.decode.RunCycles 10594612 # Number of cycles decode is running 679system.cpu0.decode.UnblockCycles 907065 # Number of cycles decode is unblocking 680system.cpu0.decode.SquashCycles 1022606 # Number of cycles decode is squashing 681system.cpu0.decode.BranchResolved 498090 # Number of times decode resolved a branch 682system.cpu0.decode.BranchMispred 33900 # Number of times decode detected a branch misprediction 683system.cpu0.decode.DecodedInsts 60717129 # Number of instructions handled by decode 684system.cpu0.decode.SquashedInsts 100549 # Number of squashed instructions handled by decode 685system.cpu0.rename.SquashCycles 1022606 # Number of cycles rename is squashing 686system.cpu0.rename.IdleCycles 26293542 # Number of cycles rename is idle 687system.cpu0.rename.BlockCycles 14517617 # Number of cycles rename is blocking 688system.cpu0.rename.serializeStallCycles 17593984 # count of cycles rename stalled for serializing inst 689system.cpu0.rename.RunCycles 9931348 # Number of cycles rename is running 690system.cpu0.rename.UnblockCycles 3999776 # Number of cycles rename is unblocking 691system.cpu0.rename.RenamedInsts 57516764 # Number of instructions processed by rename 692system.cpu0.rename.ROBFullEvents 6773 # Number of times rename has blocked due to ROB full 693system.cpu0.rename.IQFullEvents 634732 # Number of times rename has blocked due to IQ full 694system.cpu0.rename.LSQFullEvents 1395914 # Number of times rename has blocked due to LSQ full 695system.cpu0.rename.RenamedOperands 38573698 # Number of destination operands rename has renamed 696system.cpu0.rename.RenameLookups 70135572 # Number of register rename lookups that rename has made 697system.cpu0.rename.int_rename_lookups 69772127 # Number of integer rename lookups 698system.cpu0.rename.fp_rename_lookups 363445 # Number of floating rename lookups 699system.cpu0.rename.CommittedMaps 33935332 # Number of HB maps that are committed 700system.cpu0.rename.UndoneMaps 4638358 # Number of HB maps that are undone due to squashing 701system.cpu0.rename.serializingInsts 1391962 # count of serializing insts renamed 702system.cpu0.rename.tempSerializingInsts 201915 # count of temporary serializing insts renamed 703system.cpu0.rename.skidInsts 10849961 # count of insts added to the skid buffer 704system.cpu0.memDep0.insertedLoads 8944130 # Number of loads inserted to the mem dependence unit. 705system.cpu0.memDep0.insertedStores 5848227 # Number of stores inserted to the mem dependence unit. 706system.cpu0.memDep0.conflictingLoads 1106835 # Number of conflicting loads. 707system.cpu0.memDep0.conflictingStores 734658 # Number of conflicting stores. 708system.cpu0.iq.iqInstsAdded 51076458 # Number of instructions added to the IQ (excludes non-spec) 709system.cpu0.iq.iqNonSpecInstsAdded 1725873 # Number of non-speculative instructions added to the IQ 710system.cpu0.iq.iqInstsIssued 49974476 # Number of instructions issued 711system.cpu0.iq.iqSquashedInstsIssued 73247 # Number of squashed instructions issued 712system.cpu0.iq.iqSquashedInstsExamined 5675710 # Number of squashed instructions iterated over during squash; mainly for profiling 713system.cpu0.iq.iqSquashedOperandsExamined 2876244 # Number of squashed operands that are examined and possibly removed from graph 714system.cpu0.iq.iqSquashedNonSpecRemoved 1167818 # Number of squashed non-spec instructions that were removed 715system.cpu0.iq.issued_per_cycle::samples 73358875 # Number of insts issued each cycle 716system.cpu0.iq.issued_per_cycle::mean 0.681233 # Number of insts issued each cycle 717system.cpu0.iq.issued_per_cycle::stdev 1.330312 # Number of insts issued each cycle |
| 718system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 718system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 719system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle 720system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle 721system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle 722system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle 723system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle 724system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle 725system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle 726system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle 727system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle | 719system.cpu0.iq.issued_per_cycle::0 51151747 69.73% 69.73% # Number of insts issued each cycle 720system.cpu0.iq.issued_per_cycle::1 10102031 13.77% 83.50% # Number of insts issued each cycle 721system.cpu0.iq.issued_per_cycle::2 4555933 6.21% 89.71% # Number of insts issued each cycle 722system.cpu0.iq.issued_per_cycle::3 2996125 4.08% 93.79% # Number of insts issued each cycle 723system.cpu0.iq.issued_per_cycle::4 2381484 3.25% 97.04% # Number of insts issued each cycle 724system.cpu0.iq.issued_per_cycle::5 1187378 1.62% 98.66% # Number of insts issued each cycle 725system.cpu0.iq.issued_per_cycle::6 631915 0.86% 99.52% # Number of insts issued each cycle 726system.cpu0.iq.issued_per_cycle::7 300208 0.41% 99.93% # Number of insts issued each cycle 727system.cpu0.iq.issued_per_cycle::8 52054 0.07% 100.00% # Number of insts issued each cycle |
| 728system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 729system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 728system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 729system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 731system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle | 731system.cpu0.iq.issued_per_cycle::total 73358875 # Number of insts issued each cycle |
| 732system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 732system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 733system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available 734system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available 736system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available 737system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available 738system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available 741system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available 745system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available 746system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available 747system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available 748system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available 749system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available 750system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available 751system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available 752system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available 753system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available 754system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available 755system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available 762system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available 763system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available | 733system.cpu0.iq.fu_full::IntAlu 82701 12.59% 12.59% # attempts to use FU when none available 734system.cpu0.iq.fu_full::IntMult 0 0.00% 12.59% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.59% # attempts to use FU when none available 736system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.59% # attempts to use FU when none available 737system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available 738system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available 741system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available 745system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available 746system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available 747system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available 748system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available 749system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available 750system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available 751system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available 752system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available 753system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available 754system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available 755system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available 762system.cpu0.iq.fu_full::MemRead 300975 45.82% 58.41% # attempts to use FU when none available 763system.cpu0.iq.fu_full::MemWrite 273171 41.59% 100.00% # attempts to use FU when none available |
| 764system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 765system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 766system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued | 764system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 765system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 766system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued |
| 767system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued 768system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued | 767system.cpu0.iq.FU_type_0::IntAlu 34554089 69.14% 69.15% # Type of FU issued 768system.cpu0.iq.FU_type_0::IntMult 54830 0.11% 69.26% # Type of FU issued |
| 769system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued 770system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued 771system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued 772system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued 773system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued 774system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued 775system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 788system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued | 769system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued 770system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued 771system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued 772system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued 773system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued 774system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued 775system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 788system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued |
| 796system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued 797system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued 798system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued | 796system.cpu0.iq.FU_type_0::MemRead 8894109 17.80% 87.09% # Type of FU issued 797system.cpu0.iq.FU_type_0::MemWrite 5667707 11.34% 98.43% # Type of FU issued 798system.cpu0.iq.FU_type_0::IprAccess 782820 1.57% 100.00% # Type of FU issued |
| 799system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 799system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 800system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued 801system.cpu0.iq.rate 0.498985 # Inst issue rate 802system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested 803system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst) 804system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads 805system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes 806system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses 807system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads 808system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes 809system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses 810system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses 811system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses 812system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores | 800system.cpu0.iq.FU_type_0::total 49974476 # Type of FU issued 801system.cpu0.iq.rate 0.499150 # Inst issue rate 802system.cpu0.iq.fu_busy_cnt 656847 # FU busy when requested 803system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) 804system.cpu0.iq.int_inst_queue_reads 173517181 # Number of integer instruction queue reads 805system.cpu0.iq.int_inst_queue_writes 58238103 # Number of integer instruction queue writes 806system.cpu0.iq.int_inst_queue_wakeup_accesses 48994356 # Number of integer instruction queue wakeup accesses 807system.cpu0.iq.fp_inst_queue_reads 520739 # Number of floating instruction queue reads 808system.cpu0.iq.fp_inst_queue_writes 252277 # Number of floating instruction queue writes 809system.cpu0.iq.fp_inst_queue_wakeup_accesses 246003 # Number of floating instruction queue wakeup accesses 810system.cpu0.iq.int_alu_accesses 50355146 # Number of integer alu accesses 811system.cpu0.iq.fp_alu_accesses 272403 # Number of floating point alu accesses 812system.cpu0.iew.lsq.thread0.forwLoads 532794 # Number of loads that had data forwarded from stores |
| 813system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 813system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 814system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed 815system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed 816system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations 817system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed | 814system.cpu0.iew.lsq.thread0.squashedLoads 1055829 # Number of loads squashed 815system.cpu0.iew.lsq.thread0.ignoredResponses 3465 # Number of memory responses ignored because the instruction is squashed 816system.cpu0.iew.lsq.thread0.memOrderViolation 12581 # Number of memory ordering violations 817system.cpu0.iew.lsq.thread0.squashedStores 434891 # Number of stores squashed |
| 818system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 819system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 818system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 819system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 820system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled 821system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked | 820system.cpu0.iew.lsq.thread0.rescheduledLoads 18411 # Number of loads that were rescheduled 821system.cpu0.iew.lsq.thread0.cacheBlocked 121190 # Number of times an access to memory failed due to the cache being blocked |
| 822system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 822system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 823system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing 824system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking 825system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking 826system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ 827system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch 828system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions 829system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions 830system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions 831system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall 832system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall 833system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations 834system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly 835system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly 836system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute 837system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions 838system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed 839system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute | 823system.cpu0.iew.iewSquashCycles 1022606 # Number of cycles IEW is squashing 824system.cpu0.iew.iewBlockCycles 10355478 # Number of cycles IEW is blocking 825system.cpu0.iew.iewUnblockCycles 778603 # Number of cycles IEW is unblocking 826system.cpu0.iew.iewDispatchedInsts 55935625 # Number of instructions dispatched to IQ 827system.cpu0.iew.iewDispSquashedInsts 586886 # Number of squashed instructions skipped by dispatch 828system.cpu0.iew.iewDispLoadInsts 8944130 # Number of dispatched load instructions 829system.cpu0.iew.iewDispStoreInsts 5848227 # Number of dispatched store instructions 830system.cpu0.iew.iewDispNonSpecInsts 1520110 # Number of dispatched non-speculative instructions 831system.cpu0.iew.iewIQFullEvents 566642 # Number of times the IQ has become full, causing a stall 832system.cpu0.iew.iewLSQFullEvents 4768 # Number of times the LSQ has become full, causing a stall 833system.cpu0.iew.memOrderViolationEvents 12581 # Number of memory order violations 834system.cpu0.iew.predictedTakenIncorrect 160372 # Number of branches that were predicted taken incorrectly 835system.cpu0.iew.predictedNotTakenIncorrect 334885 # Number of branches that were predicted not taken incorrectly 836system.cpu0.iew.branchMispredicts 495257 # Number of branch mispredicts detected at execute 837system.cpu0.iew.iewExecutedInsts 49597141 # Number of executed instructions 838system.cpu0.iew.iewExecLoadInsts 8604090 # Number of load instructions executed 839system.cpu0.iew.iewExecSquashedInsts 377334 # Number of squashed instructions skipped in execute |
| 840system.cpu0.iew.exec_swp 0 # number of swp insts executed | 840system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 841system.cpu0.iew.exec_nop 3133489 # number of nop insts executed 842system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed 843system.cpu0.iew.exec_branches 7905275 # Number of branches executed 844system.cpu0.iew.exec_stores 5621640 # Number of stores executed 845system.cpu0.iew.exec_rate 0.495223 # Inst execution rate 846system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit 847system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back 848system.cpu0.iew.wb_producers 24627791 # num instructions producing a value 849system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value | 841system.cpu0.iew.exec_nop 3133294 # number of nop insts executed 842system.cpu0.iew.exec_refs 14226525 # number of memory reference insts executed 843system.cpu0.iew.exec_branches 7904799 # Number of branches executed 844system.cpu0.iew.exec_stores 5622435 # Number of stores executed 845system.cpu0.iew.exec_rate 0.495381 # Inst execution rate 846system.cpu0.iew.wb_sent 49326582 # cumulative count of insts sent to commit 847system.cpu0.iew.wb_count 49240359 # cumulative count of insts written-back 848system.cpu0.iew.wb_producers 24624844 # num instructions producing a value 849system.cpu0.iew.wb_consumers 33143444 # num instructions consuming a value |
| 850system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 850system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 851system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle | 851system.cpu0.iew.wb_rate 0.491818 # insts written-back per cycle |
| 852system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back 853system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 852system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back 853system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 854system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit 855system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards 856system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted 857system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle 858system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle 859system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle | 854system.cpu0.commit.commitSquashedInsts 6108836 # The number of squashed insts skipped by commit 855system.cpu0.commit.commitNonSpecStalls 558055 # The number of times commit has been forced to stall to communicate backwards 856system.cpu0.commit.branchMispredicts 462633 # The number of times a branch was mispredicted 857system.cpu0.commit.committed_per_cycle::samples 72336269 # Number of insts commited each cycle 858system.cpu0.commit.committed_per_cycle::mean 0.687326 # Number of insts commited each cycle 859system.cpu0.commit.committed_per_cycle::stdev 1.603373 # Number of insts commited each cycle |
| 860system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 860system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 861system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle 862system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle 863system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle 864system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle 865system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle 866system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle 867system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle 868system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle 869system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle | 861system.cpu0.commit.committed_per_cycle::0 53637775 74.15% 74.15% # Number of insts commited each cycle 862system.cpu0.commit.committed_per_cycle::1 7794815 10.78% 84.93% # Number of insts commited each cycle 863system.cpu0.commit.committed_per_cycle::2 4279099 5.92% 90.84% # Number of insts commited each cycle 864system.cpu0.commit.committed_per_cycle::3 2307939 3.19% 94.03% # Number of insts commited each cycle 865system.cpu0.commit.committed_per_cycle::4 1284633 1.78% 95.81% # Number of insts commited each cycle 866system.cpu0.commit.committed_per_cycle::5 537599 0.74% 96.55% # Number of insts commited each cycle 867system.cpu0.commit.committed_per_cycle::6 458507 0.63% 97.19% # Number of insts commited each cycle 868system.cpu0.commit.committed_per_cycle::7 423032 0.58% 97.77% # Number of insts commited each cycle 869system.cpu0.commit.committed_per_cycle::8 1612870 2.23% 100.00% # Number of insts commited each cycle |
| 870system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 871system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 870system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 871system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 873system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle 874system.cpu0.commit.committedInsts 49720528 # Number of instructions committed 875system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed | 873system.cpu0.commit.committed_per_cycle::total 72336269 # Number of insts commited each cycle 874system.cpu0.commit.committedInsts 49718583 # Number of instructions committed 875system.cpu0.commit.committedOps 49718583 # Number of ops (including micro ops) committed |
| 876system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 876system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 877system.cpu0.commit.refs 13302179 # Number of memory references committed 878system.cpu0.commit.loads 7888682 # Number of loads committed 879system.cpu0.commit.membars 189617 # Number of memory barriers committed 880system.cpu0.commit.branches 7516247 # Number of branches committed | 877system.cpu0.commit.refs 13301637 # Number of memory references committed 878system.cpu0.commit.loads 7888301 # Number of loads committed 879system.cpu0.commit.membars 189589 # Number of memory barriers committed 880system.cpu0.commit.branches 7515884 # Number of branches committed |
| 881system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions. | 881system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions. |
| 882system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions. 883system.cpu0.commit.function_calls 629253 # Number of function calls committed. 884system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached | 882system.cpu0.commit.int_insts 46055357 # Number of committed integer instructions. 883system.cpu0.commit.function_calls 629203 # Number of function calls committed. 884system.cpu0.commit.bw_lim_events 1612870 # number cycles where commit BW limit reached |
| 885system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 885system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 886system.cpu0.rob.rob_reads 126376352 # The number of ROB reads 887system.cpu0.rob.rob_writes 112693596 # The number of ROB writes 888system.cpu0.timesIdled 1033507 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 26786615 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 3701289214 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 46865102 # Number of Instructions Simulated 892system.cpu0.committedOps 46865102 # Number of Ops (including micro ops) Simulated 893system.cpu0.committedInsts_total 46865102 # Number of Instructions Simulated 894system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction 895system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads 896system.cpu0.ipc 0.467911 # IPC: Instructions Per Cycle 897system.cpu0.ipc_total 0.467911 # IPC: Total IPC of All Threads 898system.cpu0.int_regfile_reads 65365755 # number of integer regfile reads 899system.cpu0.int_regfile_writes 35683177 # number of integer regfile writes 900system.cpu0.fp_regfile_reads 120752 # number of floating regfile reads 901system.cpu0.fp_regfile_writes 122064 # number of floating regfile writes 902system.cpu0.misc_regfile_reads 1632145 # number of misc regfile reads 903system.cpu0.misc_regfile_writes 781535 # number of misc regfile writes | 886system.cpu0.rob.rob_reads 126355419 # The number of ROB reads 887system.cpu0.rob.rob_writes 112677687 # The number of ROB writes 888system.cpu0.timesIdled 1033455 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 26760242 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 3701329669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 46863203 # Number of Instructions Simulated 892system.cpu0.committedOps 46863203 # Number of Ops (including micro ops) Simulated 893system.cpu0.committedInsts_total 46863203 # Number of Instructions Simulated 894system.cpu0.cpi 2.136412 # CPI: Cycles Per Instruction 895system.cpu0.cpi_total 2.136412 # CPI: Total CPI of All Threads 896system.cpu0.ipc 0.468074 # IPC: Instructions Per Cycle 897system.cpu0.ipc_total 0.468074 # IPC: Total IPC of All Threads 898system.cpu0.int_regfile_reads 65361385 # number of integer regfile reads 899system.cpu0.int_regfile_writes 35679513 # number of integer regfile writes 900system.cpu0.fp_regfile_reads 120846 # number of floating regfile reads 901system.cpu0.fp_regfile_writes 122066 # number of floating regfile writes 902system.cpu0.misc_regfile_reads 1631915 # number of misc regfile reads 903system.cpu0.misc_regfile_writes 781460 # number of misc regfile writes |
| 904system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 905system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 906system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 907system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 908system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 909system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 910system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 911system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 927system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 928system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 929system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 930system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 931system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 932system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 933system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 934system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 904system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 905system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 906system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 907system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 908system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 909system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 910system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 911system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 927system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 928system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 929system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 930system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 931system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 932system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 933system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 934system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 935system.cpu0.icache.replacements 828572 # number of replacements 936system.cpu0.icache.tagsinuse 510.309366 # Cycle average of tags in use 937system.cpu0.icache.total_refs 6631345 # Total number of references to valid blocks. 938system.cpu0.icache.sampled_refs 829084 # Sample count of references to valid blocks. 939system.cpu0.icache.avg_refs 7.998399 # Average number of references to valid blocks. | 935system.cpu0.icache.replacements 828283 # number of replacements 936system.cpu0.icache.tagsinuse 510.309737 # Cycle average of tags in use 937system.cpu0.icache.total_refs 6629306 # Total number of references to valid blocks. 938system.cpu0.icache.sampled_refs 828795 # Sample count of references to valid blocks. 939system.cpu0.icache.avg_refs 7.998728 # Average number of references to valid blocks. |
| 940system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit. | 940system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit. |
| 941system.cpu0.icache.occ_blocks::cpu0.inst 510.309366 # Average occupied blocks per requestor 942system.cpu0.icache.occ_percent::cpu0.inst 0.996698 # Average percentage of cache occupancy 943system.cpu0.icache.occ_percent::total 0.996698 # Average percentage of cache occupancy 944system.cpu0.icache.ReadReq_hits::cpu0.inst 6631345 # number of ReadReq hits 945system.cpu0.icache.ReadReq_hits::total 6631345 # number of ReadReq hits 946system.cpu0.icache.demand_hits::cpu0.inst 6631345 # number of demand (read+write) hits 947system.cpu0.icache.demand_hits::total 6631345 # number of demand (read+write) hits 948system.cpu0.icache.overall_hits::cpu0.inst 6631345 # number of overall hits 949system.cpu0.icache.overall_hits::total 6631345 # number of overall hits 950system.cpu0.icache.ReadReq_misses::cpu0.inst 870628 # number of ReadReq misses 951system.cpu0.icache.ReadReq_misses::total 870628 # number of ReadReq misses 952system.cpu0.icache.demand_misses::cpu0.inst 870628 # number of demand (read+write) misses 953system.cpu0.icache.demand_misses::total 870628 # number of demand (read+write) misses 954system.cpu0.icache.overall_misses::cpu0.inst 870628 # number of overall misses 955system.cpu0.icache.overall_misses::total 870628 # number of overall misses 956system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12335909994 # number of ReadReq miss cycles 957system.cpu0.icache.ReadReq_miss_latency::total 12335909994 # number of ReadReq miss cycles 958system.cpu0.icache.demand_miss_latency::cpu0.inst 12335909994 # number of demand (read+write) miss cycles 959system.cpu0.icache.demand_miss_latency::total 12335909994 # number of demand (read+write) miss cycles 960system.cpu0.icache.overall_miss_latency::cpu0.inst 12335909994 # number of overall miss cycles 961system.cpu0.icache.overall_miss_latency::total 12335909994 # number of overall miss cycles 962system.cpu0.icache.ReadReq_accesses::cpu0.inst 7501973 # number of ReadReq accesses(hits+misses) 963system.cpu0.icache.ReadReq_accesses::total 7501973 # number of ReadReq accesses(hits+misses) 964system.cpu0.icache.demand_accesses::cpu0.inst 7501973 # number of demand (read+write) accesses 965system.cpu0.icache.demand_accesses::total 7501973 # number of demand (read+write) accesses 966system.cpu0.icache.overall_accesses::cpu0.inst 7501973 # number of overall (read+write) accesses 967system.cpu0.icache.overall_accesses::total 7501973 # number of overall (read+write) accesses 968system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116053 # miss rate for ReadReq accesses 969system.cpu0.icache.ReadReq_miss_rate::total 0.116053 # miss rate for ReadReq accesses 970system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116053 # miss rate for demand accesses 971system.cpu0.icache.demand_miss_rate::total 0.116053 # miss rate for demand accesses 972system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116053 # miss rate for overall accesses 973system.cpu0.icache.overall_miss_rate::total 0.116053 # miss rate for overall accesses 974system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14168.979167 # average ReadReq miss latency 975system.cpu0.icache.ReadReq_avg_miss_latency::total 14168.979167 # average ReadReq miss latency 976system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency 977system.cpu0.icache.demand_avg_miss_latency::total 14168.979167 # average overall miss latency 978system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency 979system.cpu0.icache.overall_avg_miss_latency::total 14168.979167 # average overall miss latency 980system.cpu0.icache.blocked_cycles::no_mshrs 2773 # number of cycles access was blocked | 941system.cpu0.icache.occ_blocks::cpu0.inst 510.309737 # Average occupied blocks per requestor 942system.cpu0.icache.occ_percent::cpu0.inst 0.996699 # Average percentage of cache occupancy 943system.cpu0.icache.occ_percent::total 0.996699 # Average percentage of cache occupancy 944system.cpu0.icache.ReadReq_hits::cpu0.inst 6629306 # number of ReadReq hits 945system.cpu0.icache.ReadReq_hits::total 6629306 # number of ReadReq hits 946system.cpu0.icache.demand_hits::cpu0.inst 6629306 # number of demand (read+write) hits 947system.cpu0.icache.demand_hits::total 6629306 # number of demand (read+write) hits 948system.cpu0.icache.overall_hits::cpu0.inst 6629306 # number of overall hits 949system.cpu0.icache.overall_hits::total 6629306 # number of overall hits 950system.cpu0.icache.ReadReq_misses::cpu0.inst 870348 # number of ReadReq misses 951system.cpu0.icache.ReadReq_misses::total 870348 # number of ReadReq misses 952system.cpu0.icache.demand_misses::cpu0.inst 870348 # number of demand (read+write) misses 953system.cpu0.icache.demand_misses::total 870348 # number of demand (read+write) misses 954system.cpu0.icache.overall_misses::cpu0.inst 870348 # number of overall misses 955system.cpu0.icache.overall_misses::total 870348 # number of overall misses 956system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12313538494 # number of ReadReq miss cycles 957system.cpu0.icache.ReadReq_miss_latency::total 12313538494 # number of ReadReq miss cycles 958system.cpu0.icache.demand_miss_latency::cpu0.inst 12313538494 # number of demand (read+write) miss cycles 959system.cpu0.icache.demand_miss_latency::total 12313538494 # number of demand (read+write) miss cycles 960system.cpu0.icache.overall_miss_latency::cpu0.inst 12313538494 # number of overall miss cycles 961system.cpu0.icache.overall_miss_latency::total 12313538494 # number of overall miss cycles 962system.cpu0.icache.ReadReq_accesses::cpu0.inst 7499654 # number of ReadReq accesses(hits+misses) 963system.cpu0.icache.ReadReq_accesses::total 7499654 # number of ReadReq accesses(hits+misses) 964system.cpu0.icache.demand_accesses::cpu0.inst 7499654 # number of demand (read+write) accesses 965system.cpu0.icache.demand_accesses::total 7499654 # number of demand (read+write) accesses 966system.cpu0.icache.overall_accesses::cpu0.inst 7499654 # number of overall (read+write) accesses 967system.cpu0.icache.overall_accesses::total 7499654 # number of overall (read+write) accesses 968system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116052 # miss rate for ReadReq accesses 969system.cpu0.icache.ReadReq_miss_rate::total 0.116052 # miss rate for ReadReq accesses 970system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116052 # miss rate for demand accesses 971system.cpu0.icache.demand_miss_rate::total 0.116052 # miss rate for demand accesses 972system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116052 # miss rate for overall accesses 973system.cpu0.icache.overall_miss_rate::total 0.116052 # miss rate for overall accesses 974system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388 # average ReadReq miss latency 975system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388 # average ReadReq miss latency 976system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency 977system.cpu0.icache.demand_avg_miss_latency::total 14147.833388 # average overall miss latency 978system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency 979system.cpu0.icache.overall_avg_miss_latency::total 14147.833388 # average overall miss latency 980system.cpu0.icache.blocked_cycles::no_mshrs 3221 # number of cycles access was blocked |
| 981system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked | 981system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked |
| 982system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked | 982system.cpu0.icache.blocked::no_mshrs 147 # number of cycles access was blocked |
| 983system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked | 983system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked |
| 984system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.124138 # average number of cycles each access was blocked | 984system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.911565 # average number of cycles each access was blocked |
| 985system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked 986system.cpu0.icache.fast_writes 0 # number of fast writes performed 987system.cpu0.icache.cache_copies 0 # number of cache copies performed | 985system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked 986system.cpu0.icache.fast_writes 0 # number of fast writes performed 987system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 988system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41361 # number of ReadReq MSHR hits 989system.cpu0.icache.ReadReq_mshr_hits::total 41361 # number of ReadReq MSHR hits 990system.cpu0.icache.demand_mshr_hits::cpu0.inst 41361 # number of demand (read+write) MSHR hits 991system.cpu0.icache.demand_mshr_hits::total 41361 # number of demand (read+write) MSHR hits 992system.cpu0.icache.overall_mshr_hits::cpu0.inst 41361 # number of overall MSHR hits 993system.cpu0.icache.overall_mshr_hits::total 41361 # number of overall MSHR hits 994system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 829267 # number of ReadReq MSHR misses 995system.cpu0.icache.ReadReq_mshr_misses::total 829267 # number of ReadReq MSHR misses 996system.cpu0.icache.demand_mshr_misses::cpu0.inst 829267 # number of demand (read+write) MSHR misses 997system.cpu0.icache.demand_mshr_misses::total 829267 # number of demand (read+write) MSHR misses 998system.cpu0.icache.overall_mshr_misses::cpu0.inst 829267 # number of overall MSHR misses 999system.cpu0.icache.overall_mshr_misses::total 829267 # number of overall MSHR misses 1000system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10145672495 # number of ReadReq MSHR miss cycles 1001system.cpu0.icache.ReadReq_mshr_miss_latency::total 10145672495 # number of ReadReq MSHR miss cycles 1002system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10145672495 # number of demand (read+write) MSHR miss cycles 1003system.cpu0.icache.demand_mshr_miss_latency::total 10145672495 # number of demand (read+write) MSHR miss cycles 1004system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10145672495 # number of overall MSHR miss cycles 1005system.cpu0.icache.overall_mshr_miss_latency::total 10145672495 # number of overall MSHR miss cycles 1006system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for ReadReq accesses 1007system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110540 # mshr miss rate for ReadReq accesses 1008system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for demand accesses 1009system.cpu0.icache.demand_mshr_miss_rate::total 0.110540 # mshr miss rate for demand accesses 1010system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for overall accesses 1011system.cpu0.icache.overall_mshr_miss_rate::total 0.110540 # mshr miss rate for overall accesses 1012system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average ReadReq mshr miss latency 1013system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.506492 # average ReadReq mshr miss latency 1014system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency 1015system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency 1016system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency 1017system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency | 988system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41379 # number of ReadReq MSHR hits 989system.cpu0.icache.ReadReq_mshr_hits::total 41379 # number of ReadReq MSHR hits 990system.cpu0.icache.demand_mshr_hits::cpu0.inst 41379 # number of demand (read+write) MSHR hits 991system.cpu0.icache.demand_mshr_hits::total 41379 # number of demand (read+write) MSHR hits 992system.cpu0.icache.overall_mshr_hits::cpu0.inst 41379 # number of overall MSHR hits 993system.cpu0.icache.overall_mshr_hits::total 41379 # number of overall MSHR hits 994system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 828969 # number of ReadReq MSHR misses 995system.cpu0.icache.ReadReq_mshr_misses::total 828969 # number of ReadReq MSHR misses 996system.cpu0.icache.demand_mshr_misses::cpu0.inst 828969 # number of demand (read+write) MSHR misses 997system.cpu0.icache.demand_mshr_misses::total 828969 # number of demand (read+write) MSHR misses 998system.cpu0.icache.overall_mshr_misses::cpu0.inst 828969 # number of overall MSHR misses 999system.cpu0.icache.overall_mshr_misses::total 828969 # number of overall MSHR misses 1000system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10141631994 # number of ReadReq MSHR miss cycles 1001system.cpu0.icache.ReadReq_mshr_miss_latency::total 10141631994 # number of ReadReq MSHR miss cycles 1002system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10141631994 # number of demand (read+write) MSHR miss cycles 1003system.cpu0.icache.demand_mshr_miss_latency::total 10141631994 # number of demand (read+write) MSHR miss cycles 1004system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10141631994 # number of overall MSHR miss cycles 1005system.cpu0.icache.overall_mshr_miss_latency::total 10141631994 # number of overall MSHR miss cycles 1006system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for ReadReq accesses 1007system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110534 # mshr miss rate for ReadReq accesses 1008system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for demand accesses 1009system.cpu0.icache.demand_mshr_miss_rate::total 0.110534 # mshr miss rate for demand accesses 1010system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for overall accesses 1011system.cpu0.icache.overall_mshr_miss_rate::total 0.110534 # mshr miss rate for overall accesses 1012system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average ReadReq mshr miss latency 1013system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.030457 # average ReadReq mshr miss latency 1014system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency 1015system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency 1016system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency 1017system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency |
| 1018system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1018system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1019system.cpu0.dcache.replacements 1248443 # number of replacements 1020system.cpu0.dcache.tagsinuse 505.648747 # Cycle average of tags in use 1021system.cpu0.dcache.total_refs 10075338 # Total number of references to valid blocks. 1022system.cpu0.dcache.sampled_refs 1248955 # Sample count of references to valid blocks. 1023system.cpu0.dcache.avg_refs 8.067014 # Average number of references to valid blocks. | 1019system.cpu0.dcache.replacements 1248455 # number of replacements 1020system.cpu0.dcache.tagsinuse 505.645673 # Cycle average of tags in use 1021system.cpu0.dcache.total_refs 10073371 # Total number of references to valid blocks. 1022system.cpu0.dcache.sampled_refs 1248967 # Sample count of references to valid blocks. 1023system.cpu0.dcache.avg_refs 8.065362 # Average number of references to valid blocks. |
| 1024system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. | 1024system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. |
| 1025system.cpu0.dcache.occ_blocks::cpu0.data 505.648747 # Average occupied blocks per requestor 1026system.cpu0.dcache.occ_percent::cpu0.data 0.987595 # Average percentage of cache occupancy 1027system.cpu0.dcache.occ_percent::total 0.987595 # Average percentage of cache occupancy 1028system.cpu0.dcache.ReadReq_hits::cpu0.data 6210455 # number of ReadReq hits 1029system.cpu0.dcache.ReadReq_hits::total 6210455 # number of ReadReq hits 1030system.cpu0.dcache.WriteReq_hits::cpu0.data 3519332 # number of WriteReq hits 1031system.cpu0.dcache.WriteReq_hits::total 3519332 # number of WriteReq hits 1032system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154524 # number of LoadLockedReq hits 1033system.cpu0.dcache.LoadLockedReq_hits::total 154524 # number of LoadLockedReq hits 1034system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177828 # number of StoreCondReq hits 1035system.cpu0.dcache.StoreCondReq_hits::total 177828 # number of StoreCondReq hits 1036system.cpu0.dcache.demand_hits::cpu0.data 9729787 # number of demand (read+write) hits 1037system.cpu0.dcache.demand_hits::total 9729787 # number of demand (read+write) hits 1038system.cpu0.dcache.overall_hits::cpu0.data 9729787 # number of overall hits 1039system.cpu0.dcache.overall_hits::total 9729787 # number of overall hits 1040system.cpu0.dcache.ReadReq_misses::cpu0.data 1542913 # number of ReadReq misses 1041system.cpu0.dcache.ReadReq_misses::total 1542913 # number of ReadReq misses 1042system.cpu0.dcache.WriteReq_misses::cpu0.data 1697969 # number of WriteReq misses 1043system.cpu0.dcache.WriteReq_misses::total 1697969 # number of WriteReq misses | 1025system.cpu0.dcache.occ_blocks::cpu0.data 505.645673 # Average occupied blocks per requestor 1026system.cpu0.dcache.occ_percent::cpu0.data 0.987589 # Average percentage of cache occupancy 1027system.cpu0.dcache.occ_percent::total 0.987589 # Average percentage of cache occupancy 1028system.cpu0.dcache.ReadReq_hits::cpu0.data 6208704 # number of ReadReq hits 1029system.cpu0.dcache.ReadReq_hits::total 6208704 # number of ReadReq hits 1030system.cpu0.dcache.WriteReq_hits::cpu0.data 3519183 # number of WriteReq hits 1031system.cpu0.dcache.WriteReq_hits::total 3519183 # number of WriteReq hits 1032system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154511 # number of LoadLockedReq hits 1033system.cpu0.dcache.LoadLockedReq_hits::total 154511 # number of LoadLockedReq hits 1034system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177820 # number of StoreCondReq hits 1035system.cpu0.dcache.StoreCondReq_hits::total 177820 # number of StoreCondReq hits 1036system.cpu0.dcache.demand_hits::cpu0.data 9727887 # number of demand (read+write) hits 1037system.cpu0.dcache.demand_hits::total 9727887 # number of demand (read+write) hits 1038system.cpu0.dcache.overall_hits::cpu0.data 9727887 # number of overall hits 1039system.cpu0.dcache.overall_hits::total 9727887 # number of overall hits 1040system.cpu0.dcache.ReadReq_misses::cpu0.data 1543041 # number of ReadReq misses 1041system.cpu0.dcache.ReadReq_misses::total 1543041 # number of ReadReq misses 1042system.cpu0.dcache.WriteReq_misses::cpu0.data 1697976 # number of WriteReq misses 1043system.cpu0.dcache.WriteReq_misses::total 1697976 # number of WriteReq misses |
| 1044system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses 1045system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses | 1044system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses 1045system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses |
| 1046system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3731 # number of StoreCondReq misses 1047system.cpu0.dcache.StoreCondReq_misses::total 3731 # number of StoreCondReq misses 1048system.cpu0.dcache.demand_misses::cpu0.data 3240882 # number of demand (read+write) misses 1049system.cpu0.dcache.demand_misses::total 3240882 # number of demand (read+write) misses 1050system.cpu0.dcache.overall_misses::cpu0.data 3240882 # number of overall misses 1051system.cpu0.dcache.overall_misses::total 3240882 # number of overall misses 1052system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33525948000 # number of ReadReq miss cycles 1053system.cpu0.dcache.ReadReq_miss_latency::total 33525948000 # number of ReadReq miss cycles 1054system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65021398230 # number of WriteReq miss cycles 1055system.cpu0.dcache.WriteReq_miss_latency::total 65021398230 # number of WriteReq miss cycles 1056system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277810500 # number of LoadLockedReq miss cycles 1057system.cpu0.dcache.LoadLockedReq_miss_latency::total 277810500 # number of LoadLockedReq miss cycles 1058system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27308500 # number of StoreCondReq miss cycles 1059system.cpu0.dcache.StoreCondReq_miss_latency::total 27308500 # number of StoreCondReq miss cycles 1060system.cpu0.dcache.demand_miss_latency::cpu0.data 98547346230 # number of demand (read+write) miss cycles 1061system.cpu0.dcache.demand_miss_latency::total 98547346230 # number of demand (read+write) miss cycles 1062system.cpu0.dcache.overall_miss_latency::cpu0.data 98547346230 # number of overall miss cycles 1063system.cpu0.dcache.overall_miss_latency::total 98547346230 # number of overall miss cycles 1064system.cpu0.dcache.ReadReq_accesses::cpu0.data 7753368 # number of ReadReq accesses(hits+misses) 1065system.cpu0.dcache.ReadReq_accesses::total 7753368 # number of ReadReq accesses(hits+misses) 1066system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217301 # number of WriteReq accesses(hits+misses) 1067system.cpu0.dcache.WriteReq_accesses::total 5217301 # number of WriteReq accesses(hits+misses) 1068system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174253 # number of LoadLockedReq accesses(hits+misses) 1069system.cpu0.dcache.LoadLockedReq_accesses::total 174253 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181559 # number of StoreCondReq accesses(hits+misses) 1071system.cpu0.dcache.StoreCondReq_accesses::total 181559 # number of StoreCondReq accesses(hits+misses) 1072system.cpu0.dcache.demand_accesses::cpu0.data 12970669 # number of demand (read+write) accesses 1073system.cpu0.dcache.demand_accesses::total 12970669 # number of demand (read+write) accesses 1074system.cpu0.dcache.overall_accesses::cpu0.data 12970669 # number of overall (read+write) accesses 1075system.cpu0.dcache.overall_accesses::total 12970669 # number of overall (read+write) accesses 1076system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198999 # miss rate for ReadReq accesses 1077system.cpu0.dcache.ReadReq_miss_rate::total 0.198999 # miss rate for ReadReq accesses 1078system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325450 # miss rate for WriteReq accesses 1079system.cpu0.dcache.WriteReq_miss_rate::total 0.325450 # miss rate for WriteReq accesses 1080system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113220 # miss rate for LoadLockedReq accesses 1081system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113220 # miss rate for LoadLockedReq accesses 1082system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020550 # miss rate for StoreCondReq accesses 1083system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020550 # miss rate for StoreCondReq accesses 1084system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249862 # miss rate for demand accesses 1085system.cpu0.dcache.demand_miss_rate::total 0.249862 # miss rate for demand accesses 1086system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249862 # miss rate for overall accesses 1087system.cpu0.dcache.overall_miss_rate::total 0.249862 # miss rate for overall accesses 1088system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21728.994441 # average ReadReq miss latency 1089system.cpu0.dcache.ReadReq_avg_miss_latency::total 21728.994441 # average ReadReq miss latency 1090system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.630938 # average WriteReq miss latency 1091system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.630938 # average WriteReq miss latency 1092system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14081.326981 # average LoadLockedReq miss latency 1093system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14081.326981 # average LoadLockedReq miss latency 1094system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7319.351380 # average StoreCondReq miss latency 1095system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7319.351380 # average StoreCondReq miss latency 1096system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency 1097system.cpu0.dcache.demand_avg_miss_latency::total 30407.569986 # average overall miss latency 1098system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency 1099system.cpu0.dcache.overall_avg_miss_latency::total 30407.569986 # average overall miss latency 1100system.cpu0.dcache.blocked_cycles::no_mshrs 2105320 # number of cycles access was blocked | 1046system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3730 # number of StoreCondReq misses 1047system.cpu0.dcache.StoreCondReq_misses::total 3730 # number of StoreCondReq misses 1048system.cpu0.dcache.demand_misses::cpu0.data 3241017 # number of demand (read+write) misses 1049system.cpu0.dcache.demand_misses::total 3241017 # number of demand (read+write) misses 1050system.cpu0.dcache.overall_misses::cpu0.data 3241017 # number of overall misses 1051system.cpu0.dcache.overall_misses::total 3241017 # number of overall misses 1052system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33524463000 # number of ReadReq miss cycles 1053system.cpu0.dcache.ReadReq_miss_latency::total 33524463000 # number of ReadReq miss cycles 1054system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64948533233 # number of WriteReq miss cycles 1055system.cpu0.dcache.WriteReq_miss_latency::total 64948533233 # number of WriteReq miss cycles 1056system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277752500 # number of LoadLockedReq miss cycles 1057system.cpu0.dcache.LoadLockedReq_miss_latency::total 277752500 # number of LoadLockedReq miss cycles 1058system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27309500 # number of StoreCondReq miss cycles 1059system.cpu0.dcache.StoreCondReq_miss_latency::total 27309500 # number of StoreCondReq miss cycles 1060system.cpu0.dcache.demand_miss_latency::cpu0.data 98472996233 # number of demand (read+write) miss cycles 1061system.cpu0.dcache.demand_miss_latency::total 98472996233 # number of demand (read+write) miss cycles 1062system.cpu0.dcache.overall_miss_latency::cpu0.data 98472996233 # number of overall miss cycles 1063system.cpu0.dcache.overall_miss_latency::total 98472996233 # number of overall miss cycles 1064system.cpu0.dcache.ReadReq_accesses::cpu0.data 7751745 # number of ReadReq accesses(hits+misses) 1065system.cpu0.dcache.ReadReq_accesses::total 7751745 # number of ReadReq accesses(hits+misses) 1066system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217159 # number of WriteReq accesses(hits+misses) 1067system.cpu0.dcache.WriteReq_accesses::total 5217159 # number of WriteReq accesses(hits+misses) 1068system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174240 # number of LoadLockedReq accesses(hits+misses) 1069system.cpu0.dcache.LoadLockedReq_accesses::total 174240 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181550 # number of StoreCondReq accesses(hits+misses) 1071system.cpu0.dcache.StoreCondReq_accesses::total 181550 # number of StoreCondReq accesses(hits+misses) 1072system.cpu0.dcache.demand_accesses::cpu0.data 12968904 # number of demand (read+write) accesses 1073system.cpu0.dcache.demand_accesses::total 12968904 # number of demand (read+write) accesses 1074system.cpu0.dcache.overall_accesses::cpu0.data 12968904 # number of overall (read+write) accesses 1075system.cpu0.dcache.overall_accesses::total 12968904 # number of overall (read+write) accesses 1076system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199057 # miss rate for ReadReq accesses 1077system.cpu0.dcache.ReadReq_miss_rate::total 0.199057 # miss rate for ReadReq accesses 1078system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325460 # miss rate for WriteReq accesses 1079system.cpu0.dcache.WriteReq_miss_rate::total 0.325460 # miss rate for WriteReq accesses 1080system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113229 # miss rate for LoadLockedReq accesses 1081system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113229 # miss rate for LoadLockedReq accesses 1082system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020545 # miss rate for StoreCondReq accesses 1083system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020545 # miss rate for StoreCondReq accesses 1084system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249907 # miss rate for demand accesses 1085system.cpu0.dcache.demand_miss_rate::total 0.249907 # miss rate for demand accesses 1086system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249907 # miss rate for overall accesses 1087system.cpu0.dcache.overall_miss_rate::total 0.249907 # miss rate for overall accesses 1088system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21726.229569 # average ReadReq miss latency 1089system.cpu0.dcache.ReadReq_avg_miss_latency::total 21726.229569 # average ReadReq miss latency 1090system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38250.560216 # average WriteReq miss latency 1091system.cpu0.dcache.WriteReq_avg_miss_latency::total 38250.560216 # average WriteReq miss latency 1092system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14078.387146 # average LoadLockedReq miss latency 1093system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146 # average LoadLockedReq miss latency 1094system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7321.581769 # average StoreCondReq miss latency 1095system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7321.581769 # average StoreCondReq miss latency 1096system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency 1097system.cpu0.dcache.demand_avg_miss_latency::total 30383.363072 # average overall miss latency 1098system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency 1099system.cpu0.dcache.overall_avg_miss_latency::total 30383.363072 # average overall miss latency 1100system.cpu0.dcache.blocked_cycles::no_mshrs 2097721 # number of cycles access was blocked |
| 1101system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked | 1101system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked |
| 1102system.cpu0.dcache.blocked::no_mshrs 47301 # number of cycles access was blocked | 1102system.cpu0.dcache.blocked::no_mshrs 47310 # number of cycles access was blocked |
| 1103system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked | 1103system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 1104system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.508996 # average number of cycles each access was blocked | 1104system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.339907 # average number of cycles each access was blocked |
| 1105system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked 1106system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1107system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1105system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked 1106system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1107system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1108system.cpu0.dcache.writebacks::writebacks 729881 # number of writebacks 1109system.cpu0.dcache.writebacks::total 729881 # number of writebacks 1110system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558235 # number of ReadReq MSHR hits 1111system.cpu0.dcache.ReadReq_mshr_hits::total 558235 # number of ReadReq MSHR hits 1112system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432207 # number of WriteReq MSHR hits 1113system.cpu0.dcache.WriteReq_mshr_hits::total 1432207 # number of WriteReq MSHR hits 1114system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4308 # number of LoadLockedReq MSHR hits 1115system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4308 # number of LoadLockedReq MSHR hits 1116system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990442 # number of demand (read+write) MSHR hits 1117system.cpu0.dcache.demand_mshr_hits::total 1990442 # number of demand (read+write) MSHR hits 1118system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990442 # number of overall MSHR hits 1119system.cpu0.dcache.overall_mshr_hits::total 1990442 # number of overall MSHR hits 1120system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984678 # number of ReadReq MSHR misses 1121system.cpu0.dcache.ReadReq_mshr_misses::total 984678 # number of ReadReq MSHR misses 1122system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265762 # number of WriteReq MSHR misses 1123system.cpu0.dcache.WriteReq_mshr_misses::total 265762 # number of WriteReq MSHR misses 1124system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15421 # number of LoadLockedReq MSHR misses 1125system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15421 # number of LoadLockedReq MSHR misses 1126system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3731 # number of StoreCondReq MSHR misses 1127system.cpu0.dcache.StoreCondReq_mshr_misses::total 3731 # number of StoreCondReq MSHR misses 1128system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250440 # number of demand (read+write) MSHR misses 1129system.cpu0.dcache.demand_mshr_misses::total 1250440 # number of demand (read+write) MSHR misses 1130system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250440 # number of overall MSHR misses 1131system.cpu0.dcache.overall_mshr_misses::total 1250440 # number of overall MSHR misses 1132system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21285796500 # number of ReadReq MSHR miss cycles 1133system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21285796500 # number of ReadReq MSHR miss cycles 1134system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9471560262 # number of WriteReq MSHR miss cycles 1135system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9471560262 # number of WriteReq MSHR miss cycles 1136system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170594000 # number of LoadLockedReq MSHR miss cycles 1137system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170594000 # number of LoadLockedReq MSHR miss cycles 1138system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19846500 # number of StoreCondReq MSHR miss cycles 1139system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19846500 # number of StoreCondReq MSHR miss cycles 1140system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30757356762 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.dcache.demand_mshr_miss_latency::total 30757356762 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30757356762 # number of overall MSHR miss cycles 1143system.cpu0.dcache.overall_mshr_miss_latency::total 30757356762 # number of overall MSHR miss cycles 1144system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454223000 # number of ReadReq MSHR uncacheable cycles 1145system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454223000 # number of ReadReq MSHR uncacheable cycles 1146system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2157391999 # number of WriteReq MSHR uncacheable cycles 1147system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles 1148system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles 1149system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles 1150system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses 1151system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses 1152system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses 1153system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses 1154system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses 1155system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses 1156system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses 1157system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses 1158system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses 1159system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses 1160system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses 1161system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses 1162system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency 1163system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency 1164system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency 1165system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency 1166system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency 1167system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency 1168system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency 1169system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency 1170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency 1171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency 1172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency 1173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency | 1108system.cpu0.dcache.writebacks::writebacks 729852 # number of writebacks 1109system.cpu0.dcache.writebacks::total 729852 # number of writebacks 1110system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558383 # number of ReadReq MSHR hits 1111system.cpu0.dcache.ReadReq_mshr_hits::total 558383 # number of ReadReq MSHR hits 1112system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432185 # number of WriteReq MSHR hits 1113system.cpu0.dcache.WriteReq_mshr_hits::total 1432185 # number of WriteReq MSHR hits 1114system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4312 # number of LoadLockedReq MSHR hits 1115system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4312 # number of LoadLockedReq MSHR hits 1116system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990568 # number of demand (read+write) MSHR hits 1117system.cpu0.dcache.demand_mshr_hits::total 1990568 # number of demand (read+write) MSHR hits 1118system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990568 # number of overall MSHR hits 1119system.cpu0.dcache.overall_mshr_hits::total 1990568 # number of overall MSHR hits 1120system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984658 # number of ReadReq MSHR misses 1121system.cpu0.dcache.ReadReq_mshr_misses::total 984658 # number of ReadReq MSHR misses 1122system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265791 # number of WriteReq MSHR misses 1123system.cpu0.dcache.WriteReq_mshr_misses::total 265791 # number of WriteReq MSHR misses 1124system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15417 # number of LoadLockedReq MSHR misses 1125system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15417 # number of LoadLockedReq MSHR misses 1126system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3730 # number of StoreCondReq MSHR misses 1127system.cpu0.dcache.StoreCondReq_mshr_misses::total 3730 # number of StoreCondReq MSHR misses 1128system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250449 # number of demand (read+write) MSHR misses 1129system.cpu0.dcache.demand_mshr_misses::total 1250449 # number of demand (read+write) MSHR misses 1130system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250449 # number of overall MSHR misses 1131system.cpu0.dcache.overall_mshr_misses::total 1250449 # number of overall MSHR misses 1132system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21282308500 # number of ReadReq MSHR miss cycles 1133system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21282308500 # number of ReadReq MSHR miss cycles 1134system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9459587261 # number of WriteReq MSHR miss cycles 1135system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9459587261 # number of WriteReq MSHR miss cycles 1136system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170557000 # number of LoadLockedReq MSHR miss cycles 1137system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170557000 # number of LoadLockedReq MSHR miss cycles 1138system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19849500 # number of StoreCondReq MSHR miss cycles 1139system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19849500 # number of StoreCondReq MSHR miss cycles 1140system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30741895761 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.dcache.demand_mshr_miss_latency::total 30741895761 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30741895761 # number of overall MSHR miss cycles 1143system.cpu0.dcache.overall_mshr_miss_latency::total 30741895761 # number of overall MSHR miss cycles 1144system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451668000 # number of ReadReq MSHR uncacheable cycles 1145system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451668000 # number of ReadReq MSHR uncacheable cycles 1146system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2155602499 # number of WriteReq MSHR uncacheable cycles 1147system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2155602499 # number of WriteReq MSHR uncacheable cycles 1148system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607270499 # number of overall MSHR uncacheable cycles 1149system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607270499 # number of overall MSHR uncacheable cycles 1150system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127024 # mshr miss rate for ReadReq accesses 1151system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127024 # mshr miss rate for ReadReq accesses 1152system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050946 # mshr miss rate for WriteReq accesses 1153system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050946 # mshr miss rate for WriteReq accesses 1154system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088481 # mshr miss rate for LoadLockedReq accesses 1155system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088481 # mshr miss rate for LoadLockedReq accesses 1156system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020545 # mshr miss rate for StoreCondReq accesses 1157system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020545 # mshr miss rate for StoreCondReq accesses 1158system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for demand accesses 1159system.cpu0.dcache.demand_mshr_miss_rate::total 0.096419 # mshr miss rate for demand accesses 1160system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for overall accesses 1161system.cpu0.dcache.overall_mshr_miss_rate::total 0.096419 # mshr miss rate for overall accesses 1162system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093 # average ReadReq mshr miss latency 1163system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093 # average ReadReq mshr miss latency 1164system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948 # average WriteReq mshr miss latency 1165system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948 # average WriteReq mshr miss latency 1166system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559 # average LoadLockedReq mshr miss latency 1167system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559 # average LoadLockedReq mshr miss latency 1168system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5321.581769 # average StoreCondReq mshr miss latency 1169system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5321.581769 # average StoreCondReq mshr miss latency 1170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency 1171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency 1172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency 1173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency |
| 1174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1181system.cpu1.branchPred.lookups 2951549 # Number of BP lookups 1182system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted 1183system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect 1184system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups 1185system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits | 1181system.cpu1.branchPred.lookups 2951275 # Number of BP lookups 1182system.cpu1.branchPred.condPredicted 2437405 # Number of conditional branches predicted 1183system.cpu1.branchPred.condIncorrect 83356 # Number of conditional branches incorrect 1184system.cpu1.branchPred.BTBLookups 1836683 # Number of BTB lookups 1185system.cpu1.branchPred.BTBHits 994148 # Number of BTB hits |
| 1186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1187system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage 1188system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target. 1189system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions. | 1187system.cpu1.branchPred.BTBHitPct 54.127359 # BTB Hit Percentage 1188system.cpu1.branchPred.usedRAS 203977 # Number of times the RAS was used to get a target. 1189system.cpu1.branchPred.RASInCorrect 9132 # Number of incorrect RAS predictions. |
| 1190system.cpu1.dtb.fetch_hits 0 # ITB hits 1191system.cpu1.dtb.fetch_misses 0 # ITB misses 1192system.cpu1.dtb.fetch_acv 0 # ITB acv 1193system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1190system.cpu1.dtb.fetch_hits 0 # ITB hits 1191system.cpu1.dtb.fetch_misses 0 # ITB misses 1192system.cpu1.dtb.fetch_acv 0 # ITB acv 1193system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1194system.cpu1.dtb.read_hits 2175312 # DTB read hits 1195system.cpu1.dtb.read_misses 10933 # DTB read misses 1196system.cpu1.dtb.read_acv 25 # DTB read access violations 1197system.cpu1.dtb.read_accesses 324345 # DTB read accesses 1198system.cpu1.dtb.write_hits 1433020 # DTB write hits 1199system.cpu1.dtb.write_misses 2283 # DTB write misses | 1194system.cpu1.dtb.read_hits 2175721 # DTB read hits 1195system.cpu1.dtb.read_misses 10990 # DTB read misses 1196system.cpu1.dtb.read_acv 22 # DTB read access violations 1197system.cpu1.dtb.read_accesses 324709 # DTB read accesses 1198system.cpu1.dtb.write_hits 1432957 # DTB write hits 1199system.cpu1.dtb.write_misses 2208 # DTB write misses |
| 1200system.cpu1.dtb.write_acv 64 # DTB write access violations | 1200system.cpu1.dtb.write_acv 64 # DTB write access violations |
| 1201system.cpu1.dtb.write_accesses 133154 # DTB write accesses 1202system.cpu1.dtb.data_hits 3608332 # DTB hits 1203system.cpu1.dtb.data_misses 13216 # DTB misses 1204system.cpu1.dtb.data_acv 89 # DTB access violations 1205system.cpu1.dtb.data_accesses 457499 # DTB accesses 1206system.cpu1.itb.fetch_hits 457840 # ITB hits 1207system.cpu1.itb.fetch_misses 7553 # ITB misses 1208system.cpu1.itb.fetch_acv 250 # ITB acv 1209system.cpu1.itb.fetch_accesses 465393 # ITB accesses | 1201system.cpu1.dtb.write_accesses 133156 # DTB write accesses 1202system.cpu1.dtb.data_hits 3608678 # DTB hits 1203system.cpu1.dtb.data_misses 13198 # DTB misses 1204system.cpu1.dtb.data_acv 86 # DTB access violations 1205system.cpu1.dtb.data_accesses 457865 # DTB accesses 1206system.cpu1.itb.fetch_hits 458401 # ITB hits 1207system.cpu1.itb.fetch_misses 7664 # ITB misses 1208system.cpu1.itb.fetch_acv 238 # ITB acv 1209system.cpu1.itb.fetch_accesses 466065 # ITB accesses |
| 1210system.cpu1.itb.read_hits 0 # DTB read hits 1211system.cpu1.itb.read_misses 0 # DTB read misses 1212system.cpu1.itb.read_acv 0 # DTB read access violations 1213system.cpu1.itb.read_accesses 0 # DTB read accesses 1214system.cpu1.itb.write_hits 0 # DTB write hits 1215system.cpu1.itb.write_misses 0 # DTB write misses 1216system.cpu1.itb.write_acv 0 # DTB write access violations 1217system.cpu1.itb.write_accesses 0 # DTB write accesses 1218system.cpu1.itb.data_hits 0 # DTB hits 1219system.cpu1.itb.data_misses 0 # DTB misses 1220system.cpu1.itb.data_acv 0 # DTB access violations 1221system.cpu1.itb.data_accesses 0 # DTB accesses | 1210system.cpu1.itb.read_hits 0 # DTB read hits 1211system.cpu1.itb.read_misses 0 # DTB read misses 1212system.cpu1.itb.read_acv 0 # DTB read access violations 1213system.cpu1.itb.read_accesses 0 # DTB read accesses 1214system.cpu1.itb.write_hits 0 # DTB write hits 1215system.cpu1.itb.write_misses 0 # DTB write misses 1216system.cpu1.itb.write_acv 0 # DTB write access violations 1217system.cpu1.itb.write_accesses 0 # DTB write accesses 1218system.cpu1.itb.data_hits 0 # DTB hits 1219system.cpu1.itb.data_misses 0 # DTB misses 1220system.cpu1.itb.data_acv 0 # DTB access violations 1221system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1222system.cpu1.numCycles 18134862 # number of cpu cycles simulated | 1222system.cpu1.numCycles 18142763 # number of cpu cycles simulated |
| 1223system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1224system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1223system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1224system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1225system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss 1226system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed 1227system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered 1228system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken 1229system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked 1230system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing 1231system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked 1232system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1233system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps 1234system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions 1235system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR 1236system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched 1237system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed 1238system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total) 1239system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total) 1240system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total) | 1225system.cpu1.fetch.icacheStallCycles 7059665 # Number of cycles fetch is stalled on an Icache miss 1226system.cpu1.fetch.Insts 13904860 # Number of instructions fetch has processed 1227system.cpu1.fetch.Branches 2951275 # Number of branches that fetch encountered 1228system.cpu1.fetch.predictedBranches 1198125 # Number of branches that fetch has predicted taken 1229system.cpu1.fetch.Cycles 2489767 # Number of cycles fetch has run and was not squashing or blocked 1230system.cpu1.fetch.SquashCycles 435348 # Number of cycles fetch has spent squashing 1231system.cpu1.fetch.BlockedCycles 7028149 # Number of cycles fetch has spent blocked 1232system.cpu1.fetch.MiscStallCycles 27735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1233system.cpu1.fetch.PendingTrapStallCycles 66683 # Number of stall cycles due to pending traps 1234system.cpu1.fetch.PendingQuiesceStallCycles 53717 # Number of stall cycles due to pending quiesce instructions 1235system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR 1236system.cpu1.fetch.CacheLines 1666090 # Number of cache lines fetched 1237system.cpu1.fetch.IcacheSquashes 56854 # Number of outstanding Icache misses that were squashed 1238system.cpu1.fetch.rateDist::samples 17001992 # Number of instructions fetched each cycle (Total) 1239system.cpu1.fetch.rateDist::mean 0.817837 # Number of instructions fetched each cycle (Total) 1240system.cpu1.fetch.rateDist::stdev 2.192062 # Number of instructions fetched each cycle (Total) |
| 1241system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1241system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1242system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total) 1243system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total) 1244system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total) 1245system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total) 1246system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total) 1247system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total) 1248system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total) 1250system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total) | 1242system.cpu1.fetch.rateDist::0 14512225 85.36% 85.36% # Number of instructions fetched each cycle (Total) 1243system.cpu1.fetch.rateDist::1 164132 0.97% 86.32% # Number of instructions fetched each cycle (Total) 1244system.cpu1.fetch.rateDist::2 264549 1.56% 87.88% # Number of instructions fetched each cycle (Total) 1245system.cpu1.fetch.rateDist::3 196224 1.15% 89.03% # Number of instructions fetched each cycle (Total) 1246system.cpu1.fetch.rateDist::4 340931 2.01% 91.04% # Number of instructions fetched each cycle (Total) 1247system.cpu1.fetch.rateDist::5 130664 0.77% 91.81% # Number of instructions fetched each cycle (Total) 1248system.cpu1.fetch.rateDist::6 146583 0.86% 92.67% # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::7 247056 1.45% 94.12% # Number of instructions fetched each cycle (Total) 1250system.cpu1.fetch.rateDist::8 999628 5.88% 100.00% # Number of instructions fetched each cycle (Total) |
| 1251system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1251system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1254system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle 1256system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle 1257system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle 1258system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked 1259system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running 1260system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking 1261system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing 1262system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch 1263system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction 1264system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode 1265system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode 1266system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing 1267system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle 1268system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking 1269system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst 1270system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running 1271system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking 1272system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename 1273system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full 1274system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full 1275system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full 1276system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed 1277system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made 1278system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups 1279system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups 1280system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed 1281system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing 1282system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed 1283system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed 1284system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer 1285system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit. 1286system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit. 1287system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads. 1288system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores. 1289system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec) 1290system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ 1291system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued 1292system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued 1293system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling 1294system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph 1295system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed 1296system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle 1297system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle 1298system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle | 1254system.cpu1.fetch.rateDist::total 17001992 # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.branchRate 0.162670 # Number of branch fetches per cycle 1256system.cpu1.fetch.rate 0.766414 # Number of inst fetches per cycle 1257system.cpu1.decode.IdleCycles 6935204 # Number of cycles decode is idle 1258system.cpu1.decode.BlockedCycles 7342187 # Number of cycles decode is blocked 1259system.cpu1.decode.RunCycles 2328189 # Number of cycles decode is running 1260system.cpu1.decode.UnblockCycles 128213 # Number of cycles decode is unblocking 1261system.cpu1.decode.SquashCycles 268198 # Number of cycles decode is squashing 1262system.cpu1.decode.BranchResolved 130237 # Number of times decode resolved a branch 1263system.cpu1.decode.BranchMispred 8176 # Number of times decode detected a branch misprediction 1264system.cpu1.decode.DecodedInsts 13648246 # Number of instructions handled by decode 1265system.cpu1.decode.SquashedInsts 24564 # Number of squashed instructions handled by decode 1266system.cpu1.rename.SquashCycles 268198 # Number of cycles rename is squashing 1267system.cpu1.rename.IdleCycles 7169583 # Number of cycles rename is idle 1268system.cpu1.rename.BlockCycles 530321 # Number of cycles rename is blocking 1269system.cpu1.rename.serializeStallCycles 6090332 # count of cycles rename stalled for serializing inst 1270system.cpu1.rename.RunCycles 2220482 # Number of cycles rename is running 1271system.cpu1.rename.UnblockCycles 723074 # Number of cycles rename is unblocking 1272system.cpu1.rename.RenamedInsts 12659443 # Number of instructions processed by rename 1273system.cpu1.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full 1274system.cpu1.rename.IQFullEvents 62425 # Number of times rename has blocked due to IQ full 1275system.cpu1.rename.LSQFullEvents 176745 # Number of times rename has blocked due to LSQ full 1276system.cpu1.rename.RenamedOperands 8295078 # Number of destination operands rename has renamed 1277system.cpu1.rename.RenameLookups 15050859 # Number of register rename lookups that rename has made 1278system.cpu1.rename.int_rename_lookups 14876046 # Number of integer rename lookups 1279system.cpu1.rename.fp_rename_lookups 174813 # Number of floating rename lookups 1280system.cpu1.rename.CommittedMaps 7154813 # Number of HB maps that are committed 1281system.cpu1.rename.UndoneMaps 1140265 # Number of HB maps that are undone due to squashing 1282system.cpu1.rename.serializingInsts 506846 # count of serializing insts renamed 1283system.cpu1.rename.tempSerializingInsts 51390 # count of temporary serializing insts renamed 1284system.cpu1.rename.skidInsts 2247067 # count of insts added to the skid buffer 1285system.cpu1.memDep0.insertedLoads 2298271 # Number of loads inserted to the mem dependence unit. 1286system.cpu1.memDep0.insertedStores 1513317 # Number of stores inserted to the mem dependence unit. 1287system.cpu1.memDep0.conflictingLoads 213048 # Number of conflicting loads. 1288system.cpu1.memDep0.conflictingStores 119189 # Number of conflicting stores. 1289system.cpu1.iq.iqInstsAdded 11099753 # Number of instructions added to the IQ (excludes non-spec) 1290system.cpu1.iq.iqNonSpecInstsAdded 565057 # Number of non-speculative instructions added to the IQ 1291system.cpu1.iq.iqInstsIssued 10829119 # Number of instructions issued 1292system.cpu1.iq.iqSquashedInstsIssued 31632 # Number of squashed instructions issued 1293system.cpu1.iq.iqSquashedInstsExamined 1536258 # Number of squashed instructions iterated over during squash; mainly for profiling 1294system.cpu1.iq.iqSquashedOperandsExamined 758334 # Number of squashed operands that are examined and possibly removed from graph 1295system.cpu1.iq.iqSquashedNonSpecRemoved 401417 # Number of squashed non-spec instructions that were removed 1296system.cpu1.iq.issued_per_cycle::samples 17001992 # Number of insts issued each cycle 1297system.cpu1.iq.issued_per_cycle::mean 0.636932 # Number of insts issued each cycle 1298system.cpu1.iq.issued_per_cycle::stdev 1.310611 # Number of insts issued each cycle |
| 1299system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1299system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1300system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle 1301system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle 1302system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle 1303system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle 1304system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle 1305system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle 1306system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle 1308system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle | 1300system.cpu1.iq.issued_per_cycle::0 12225446 71.91% 71.91% # Number of insts issued each cycle 1301system.cpu1.iq.issued_per_cycle::1 2205450 12.97% 84.88% # Number of insts issued each cycle 1302system.cpu1.iq.issued_per_cycle::2 929224 5.47% 90.34% # Number of insts issued each cycle 1303system.cpu1.iq.issued_per_cycle::3 621702 3.66% 94.00% # Number of insts issued each cycle 1304system.cpu1.iq.issued_per_cycle::4 537509 3.16% 97.16% # Number of insts issued each cycle 1305system.cpu1.iq.issued_per_cycle::5 242497 1.43% 98.59% # Number of insts issued each cycle 1306system.cpu1.iq.issued_per_cycle::6 153407 0.90% 99.49% # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::7 76904 0.45% 99.94% # Number of insts issued each cycle 1308system.cpu1.iq.issued_per_cycle::8 9853 0.06% 100.00% # Number of insts issued each cycle |
| 1309system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1309system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1312system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle | 1312system.cpu1.iq.issued_per_cycle::total 17001992 # Number of insts issued each cycle |
| 1313system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1313system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1314system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available 1315system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available 1316system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available 1317system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available | 1314system.cpu1.iq.fu_full::IntAlu 3913 1.80% 1.80% # attempts to use FU when none available 1315system.cpu1.iq.fu_full::IntMult 0 0.00% 1.80% # attempts to use FU when none available 1316system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.80% # attempts to use FU when none available 1317system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.80% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.80% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.80% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.80% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.80% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.80% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.80% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.80% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.80% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.80% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.80% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.80% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.80% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.80% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.80% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.80% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.80% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.80% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.80% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.80% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.80% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.80% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.80% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.80% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.80% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.80% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::MemRead 115549 53.23% 55.03% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::MemWrite 97618 44.97% 100.00% # attempts to use FU when none available |
| 1345system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1347system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued | 1345system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1347system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued |
| 1348system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued 1349system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued 1350system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued 1351system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued 1352system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued 1353system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued 1354system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued | 1348system.cpu1.iq.FU_type_0::IntAlu 6756968 62.40% 62.43% # Type of FU issued 1349system.cpu1.iq.FU_type_0::IntMult 17928 0.17% 62.59% # Type of FU issued 1350system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued 1351system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.70% # Type of FU issued 1352system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued 1353system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued 1354system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued |
| 1355system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued 1356system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued 1357system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued 1358system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued 1359system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued 1360system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued 1361system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued 1362system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 1369system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued | 1355system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued 1356system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued 1357system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued 1358system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued 1359system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued 1360system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued 1361system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued 1362system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 1369system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued |
| 1377system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued 1378system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued | 1377system.cpu1.iq.FU_type_0::MemRead 2278200 21.04% 83.75% # Type of FU issued 1378system.cpu1.iq.FU_type_0::MemWrite 1457808 13.46% 97.22% # Type of FU issued |
| 1379system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued 1380system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1379system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued 1380system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1381system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued 1382system.cpu1.iq.rate 0.597126 # Inst issue rate 1383system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested 1384system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst) 1385system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads 1386system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes 1387system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses 1388system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads 1389system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes 1390system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses 1391system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses 1392system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses 1393system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores | 1381system.cpu1.iq.FU_type_0::total 10829119 # Type of FU issued 1382system.cpu1.iq.rate 0.596884 # Inst issue rate 1383system.cpu1.iq.fu_busy_cnt 217080 # FU busy when requested 1384system.cpu1.iq.fu_busy_rate 0.020046 # FU busy rate (busy events/executed inst) 1385system.cpu1.iq.int_inst_queue_reads 38657394 # Number of integer instruction queue reads 1386system.cpu1.iq.int_inst_queue_writes 13080099 # Number of integer instruction queue writes 1387system.cpu1.iq.int_inst_queue_wakeup_accesses 10523969 # Number of integer instruction queue wakeup accesses 1388system.cpu1.iq.fp_inst_queue_reads 251548 # Number of floating instruction queue reads 1389system.cpu1.iq.fp_inst_queue_writes 122819 # Number of floating instruction queue writes 1390system.cpu1.iq.fp_inst_queue_wakeup_accesses 119141 # Number of floating instruction queue wakeup accesses 1391system.cpu1.iq.int_alu_accesses 10911695 # Number of integer alu accesses 1392system.cpu1.iq.fp_alu_accesses 130978 # Number of floating point alu accesses 1393system.cpu1.iew.lsq.thread0.forwLoads 103489 # Number of loads that had data forwarded from stores |
| 1394system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1394system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1395system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed 1396system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed 1397system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations 1398system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed | 1395system.cpu1.iew.lsq.thread0.squashedLoads 301882 # Number of loads squashed 1396system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed 1397system.cpu1.iew.lsq.thread0.memOrderViolation 1924 # Number of memory ordering violations 1398system.cpu1.iew.lsq.thread0.squashedStores 130297 # Number of stores squashed |
| 1399system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1400system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1399system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1400system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1401system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled 1402system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked | 1401system.cpu1.iew.lsq.thread0.rescheduledLoads 383 # Number of loads that were rescheduled 1402system.cpu1.iew.lsq.thread0.cacheBlocked 9692 # Number of times an access to memory failed due to the cache being blocked |
| 1403system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1403system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1404system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing 1405system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking 1406system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking 1407system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ 1408system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch 1409system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions 1410system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions 1411system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions 1412system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall 1413system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall 1414system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations 1415system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly 1416system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly 1417system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute 1418system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions 1419system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed 1420system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute | 1404system.cpu1.iew.iewSquashCycles 268198 # Number of cycles IEW is squashing 1405system.cpu1.iew.iewBlockCycles 347966 # Number of cycles IEW is blocking 1406system.cpu1.iew.iewUnblockCycles 52179 # Number of cycles IEW is unblocking 1407system.cpu1.iew.iewDispatchedInsts 12265641 # Number of instructions dispatched to IQ 1408system.cpu1.iew.iewDispSquashedInsts 165598 # Number of squashed instructions skipped by dispatch 1409system.cpu1.iew.iewDispLoadInsts 2298271 # Number of dispatched load instructions 1410system.cpu1.iew.iewDispStoreInsts 1513317 # Number of dispatched store instructions 1411system.cpu1.iew.iewDispNonSpecInsts 508976 # Number of dispatched non-speculative instructions 1412system.cpu1.iew.iewIQFullEvents 44383 # Number of times the IQ has become full, causing a stall 1413system.cpu1.iew.iewLSQFullEvents 2331 # Number of times the LSQ has become full, causing a stall 1414system.cpu1.iew.memOrderViolationEvents 1924 # Number of memory order violations 1415system.cpu1.iew.predictedTakenIncorrect 37819 # Number of branches that were predicted taken incorrectly 1416system.cpu1.iew.predictedNotTakenIncorrect 111790 # Number of branches that were predicted not taken incorrectly 1417system.cpu1.iew.branchMispredicts 149609 # Number of branch mispredicts detected at execute 1418system.cpu1.iew.iewExecutedInsts 10726333 # Number of executed instructions 1419system.cpu1.iew.iewExecLoadInsts 2195343 # Number of load instructions executed 1420system.cpu1.iew.iewExecSquashedInsts 102786 # Number of squashed instructions skipped in execute |
| 1421system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1421system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1422system.cpu1.iew.exec_nop 600729 # number of nop insts executed 1423system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed 1424system.cpu1.iew.exec_branches 1609931 # Number of branches executed 1425system.cpu1.iew.exec_stores 1442207 # Number of stores executed 1426system.cpu1.iew.exec_rate 0.591458 # Inst execution rate 1427system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit 1428system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back 1429system.cpu1.iew.wb_producers 4954529 # num instructions producing a value 1430system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value | 1422system.cpu1.iew.exec_nop 600831 # number of nop insts executed 1423system.cpu1.iew.exec_refs 3637407 # number of memory reference insts executed 1424system.cpu1.iew.exec_branches 1609945 # Number of branches executed 1425system.cpu1.iew.exec_stores 1442064 # Number of stores executed 1426system.cpu1.iew.exec_rate 0.591218 # Inst execution rate 1427system.cpu1.iew.wb_sent 10671459 # cumulative count of insts sent to commit 1428system.cpu1.iew.wb_count 10643110 # cumulative count of insts written-back 1429system.cpu1.iew.wb_producers 4954176 # num instructions producing a value 1430system.cpu1.iew.wb_consumers 6965889 # num instructions consuming a value |
| 1431system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1431system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1432system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle 1433system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back | 1432system.cpu1.iew.wb_rate 0.586631 # insts written-back per cycle 1433system.cpu1.iew.wb_fanout 0.711205 # average fanout of values written-back |
| 1434system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1434system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1435system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit 1436system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards 1437system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted 1438system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle 1439system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle 1440system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle | 1435system.cpu1.commit.commitSquashedInsts 1581528 # The number of squashed insts skipped by commit 1436system.cpu1.commit.commitNonSpecStalls 163640 # The number of times commit has been forced to stall to communicate backwards 1437system.cpu1.commit.branchMispredicts 139954 # The number of times a branch was mispredicted 1438system.cpu1.commit.committed_per_cycle::samples 16733794 # Number of insts commited each cycle 1439system.cpu1.commit.committed_per_cycle::mean 0.633013 # Number of insts commited each cycle 1440system.cpu1.commit.committed_per_cycle::stdev 1.579692 # Number of insts commited each cycle |
| 1441system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1441system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1442system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle 1443system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle 1444system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle 1445system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle 1446system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle 1447system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle 1448system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle | 1442system.cpu1.commit.committed_per_cycle::0 12789139 76.43% 76.43% # Number of insts commited each cycle 1443system.cpu1.commit.committed_per_cycle::1 1829893 10.94% 87.36% # Number of insts commited each cycle 1444system.cpu1.commit.committed_per_cycle::2 688745 4.12% 91.48% # Number of insts commited each cycle 1445system.cpu1.commit.committed_per_cycle::3 420012 2.51% 93.99% # Number of insts commited each cycle 1446system.cpu1.commit.committed_per_cycle::4 300647 1.80% 95.78% # Number of insts commited each cycle 1447system.cpu1.commit.committed_per_cycle::5 117990 0.71% 96.49% # Number of insts commited each cycle 1448system.cpu1.commit.committed_per_cycle::6 119790 0.72% 97.21% # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::7 126616 0.76% 97.96% # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::8 340962 2.04% 100.00% # Number of insts commited each cycle |
| 1451system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1451system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1454system.cpu1.commit.committed_per_cycle::total 16732673 # Number of insts commited each cycle 1455system.cpu1.commit.committedInsts 10592581 # Number of instructions committed 1456system.cpu1.commit.committedOps 10592581 # Number of ops (including micro ops) committed | 1454system.cpu1.commit.committed_per_cycle::total 16733794 # Number of insts commited each cycle 1455system.cpu1.commit.committedInsts 10592705 # Number of instructions committed 1456system.cpu1.commit.committedOps 10592705 # Number of ops (including micro ops) committed |
| 1457system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1457system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1458system.cpu1.commit.refs 3379323 # Number of memory references committed 1459system.cpu1.commit.loads 1996302 # Number of loads committed | 1458system.cpu1.commit.refs 3379409 # Number of memory references committed 1459system.cpu1.commit.loads 1996389 # Number of loads committed |
| 1460system.cpu1.commit.membars 53397 # Number of memory barriers committed | 1460system.cpu1.commit.membars 53397 # Number of memory barriers committed |
| 1461system.cpu1.commit.branches 1516852 # Number of branches committed | 1461system.cpu1.commit.branches 1516939 # Number of branches committed |
| 1462system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions. | 1462system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions. |
| 1463system.cpu1.commit.int_insts 9798554 # Number of committed integer instructions. | 1463system.cpu1.commit.int_insts 9798676 # Number of committed integer instructions. |
| 1464system.cpu1.commit.function_calls 169964 # Number of function calls committed. | 1464system.cpu1.commit.function_calls 169964 # Number of function calls committed. |
| 1465system.cpu1.commit.bw_lim_events 341197 # number cycles where commit BW limit reached | 1465system.cpu1.commit.bw_lim_events 340962 # number cycles where commit BW limit reached |
| 1466system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1466system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1467system.cpu1.rob.rob_reads 28468767 # The number of ROB reads 1468system.cpu1.rob.rob_writes 24605693 # The number of ROB writes 1469system.cpu1.timesIdled 153691 # Number of times that the entire CPU went into an idle state and unscheduled itself 1470system.cpu1.idleCycles 1134548 # Total number of cycles that the CPU has spent unscheduled due to idling 1471system.cpu1.quiesceCycles 3782736336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1472system.cpu1.committedInsts 10061892 # Number of Instructions Simulated 1473system.cpu1.committedOps 10061892 # Number of Ops (including micro ops) Simulated 1474system.cpu1.committedInsts_total 10061892 # Number of Instructions Simulated 1475system.cpu1.cpi 1.802331 # CPI: Cycles Per Instruction 1476system.cpu1.cpi_total 1.802331 # CPI: Total CPI of All Threads 1477system.cpu1.ipc 0.554837 # IPC: Instructions Per Cycle 1478system.cpu1.ipc_total 0.554837 # IPC: Total IPC of All Threads 1479system.cpu1.int_regfile_reads 13798288 # number of integer regfile reads 1480system.cpu1.int_regfile_writes 7546279 # number of integer regfile writes 1481system.cpu1.fp_regfile_reads 63929 # number of floating regfile reads 1482system.cpu1.fp_regfile_writes 63981 # number of floating regfile writes 1483system.cpu1.misc_regfile_reads 608468 # number of misc regfile reads | 1467system.cpu1.rob.rob_reads 28474562 # The number of ROB reads 1468system.cpu1.rob.rob_writes 24615096 # The number of ROB writes 1469system.cpu1.timesIdled 153586 # Number of times that the entire CPU went into an idle state and unscheduled itself 1470system.cpu1.idleCycles 1140771 # Total number of cycles that the CPU has spent unscheduled due to idling 1471system.cpu1.quiesceCycles 3782727730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1472system.cpu1.committedInsts 10062016 # Number of Instructions Simulated 1473system.cpu1.committedOps 10062016 # Number of Ops (including micro ops) Simulated 1474system.cpu1.committedInsts_total 10062016 # Number of Instructions Simulated 1475system.cpu1.cpi 1.803094 # CPI: Cycles Per Instruction 1476system.cpu1.cpi_total 1.803094 # CPI: Total CPI of All Threads 1477system.cpu1.ipc 0.554602 # IPC: Instructions Per Cycle 1478system.cpu1.ipc_total 0.554602 # IPC: Total IPC of All Threads 1479system.cpu1.int_regfile_reads 13798564 # number of integer regfile reads 1480system.cpu1.int_regfile_writes 7546386 # number of integer regfile writes 1481system.cpu1.fp_regfile_reads 63884 # number of floating regfile reads 1482system.cpu1.fp_regfile_writes 63971 # number of floating regfile writes 1483system.cpu1.misc_regfile_reads 608483 # number of misc regfile reads |
| 1484system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes | 1484system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes |
| 1485system.cpu1.icache.replacements 263438 # number of replacements 1486system.cpu1.icache.tagsinuse 470.047000 # Cycle average of tags in use 1487system.cpu1.icache.total_refs 1391700 # Total number of references to valid blocks. 1488system.cpu1.icache.sampled_refs 263950 # Sample count of references to valid blocks. 1489system.cpu1.icache.avg_refs 5.272590 # Average number of references to valid blocks. 1490system.cpu1.icache.warmup_cycle 1875178456000 # Cycle when the warmup percentage was hit. 1491system.cpu1.icache.occ_blocks::cpu1.inst 470.047000 # Average occupied blocks per requestor | 1485system.cpu1.icache.replacements 263412 # number of replacements 1486system.cpu1.icache.tagsinuse 470.047023 # Cycle average of tags in use 1487system.cpu1.icache.total_refs 1392951 # Total number of references to valid blocks. 1488system.cpu1.icache.sampled_refs 263924 # Sample count of references to valid blocks. 1489system.cpu1.icache.avg_refs 5.277849 # Average number of references to valid blocks. 1490system.cpu1.icache.warmup_cycle 1875177958000 # Cycle when the warmup percentage was hit. 1491system.cpu1.icache.occ_blocks::cpu1.inst 470.047023 # Average occupied blocks per requestor |
| 1492system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy 1493system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy | 1492system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy 1493system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy |
| 1494system.cpu1.icache.ReadReq_hits::cpu1.inst 1391700 # number of ReadReq hits 1495system.cpu1.icache.ReadReq_hits::total 1391700 # number of ReadReq hits 1496system.cpu1.icache.demand_hits::cpu1.inst 1391700 # number of demand (read+write) hits 1497system.cpu1.icache.demand_hits::total 1391700 # number of demand (read+write) hits 1498system.cpu1.icache.overall_hits::cpu1.inst 1391700 # number of overall hits 1499system.cpu1.icache.overall_hits::total 1391700 # number of overall hits 1500system.cpu1.icache.ReadReq_misses::cpu1.inst 273170 # number of ReadReq misses 1501system.cpu1.icache.ReadReq_misses::total 273170 # number of ReadReq misses 1502system.cpu1.icache.demand_misses::cpu1.inst 273170 # number of demand (read+write) misses 1503system.cpu1.icache.demand_misses::total 273170 # number of demand (read+write) misses 1504system.cpu1.icache.overall_misses::cpu1.inst 273170 # number of overall misses 1505system.cpu1.icache.overall_misses::total 273170 # number of overall misses 1506system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3762343999 # number of ReadReq miss cycles 1507system.cpu1.icache.ReadReq_miss_latency::total 3762343999 # number of ReadReq miss cycles 1508system.cpu1.icache.demand_miss_latency::cpu1.inst 3762343999 # number of demand (read+write) miss cycles 1509system.cpu1.icache.demand_miss_latency::total 3762343999 # number of demand (read+write) miss cycles 1510system.cpu1.icache.overall_miss_latency::cpu1.inst 3762343999 # number of overall miss cycles 1511system.cpu1.icache.overall_miss_latency::total 3762343999 # number of overall miss cycles 1512system.cpu1.icache.ReadReq_accesses::cpu1.inst 1664870 # number of ReadReq accesses(hits+misses) 1513system.cpu1.icache.ReadReq_accesses::total 1664870 # number of ReadReq accesses(hits+misses) 1514system.cpu1.icache.demand_accesses::cpu1.inst 1664870 # number of demand (read+write) accesses 1515system.cpu1.icache.demand_accesses::total 1664870 # number of demand (read+write) accesses 1516system.cpu1.icache.overall_accesses::cpu1.inst 1664870 # number of overall (read+write) accesses 1517system.cpu1.icache.overall_accesses::total 1664870 # number of overall (read+write) accesses 1518system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164079 # miss rate for ReadReq accesses 1519system.cpu1.icache.ReadReq_miss_rate::total 0.164079 # miss rate for ReadReq accesses 1520system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164079 # miss rate for demand accesses 1521system.cpu1.icache.demand_miss_rate::total 0.164079 # miss rate for demand accesses 1522system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164079 # miss rate for overall accesses 1523system.cpu1.icache.overall_miss_rate::total 0.164079 # miss rate for overall accesses 1524system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13772.903317 # average ReadReq miss latency 1525system.cpu1.icache.ReadReq_avg_miss_latency::total 13772.903317 # average ReadReq miss latency 1526system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency 1527system.cpu1.icache.demand_avg_miss_latency::total 13772.903317 # average overall miss latency 1528system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency 1529system.cpu1.icache.overall_avg_miss_latency::total 13772.903317 # average overall miss latency 1530system.cpu1.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked | 1494system.cpu1.icache.ReadReq_hits::cpu1.inst 1392951 # number of ReadReq hits 1495system.cpu1.icache.ReadReq_hits::total 1392951 # number of ReadReq hits 1496system.cpu1.icache.demand_hits::cpu1.inst 1392951 # number of demand (read+write) hits 1497system.cpu1.icache.demand_hits::total 1392951 # number of demand (read+write) hits 1498system.cpu1.icache.overall_hits::cpu1.inst 1392951 # number of overall hits 1499system.cpu1.icache.overall_hits::total 1392951 # number of overall hits 1500system.cpu1.icache.ReadReq_misses::cpu1.inst 273139 # number of ReadReq misses 1501system.cpu1.icache.ReadReq_misses::total 273139 # number of ReadReq misses 1502system.cpu1.icache.demand_misses::cpu1.inst 273139 # number of demand (read+write) misses 1503system.cpu1.icache.demand_misses::total 273139 # number of demand (read+write) misses 1504system.cpu1.icache.overall_misses::cpu1.inst 273139 # number of overall misses 1505system.cpu1.icache.overall_misses::total 273139 # number of overall misses 1506system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3753112000 # number of ReadReq miss cycles 1507system.cpu1.icache.ReadReq_miss_latency::total 3753112000 # number of ReadReq miss cycles 1508system.cpu1.icache.demand_miss_latency::cpu1.inst 3753112000 # number of demand (read+write) miss cycles 1509system.cpu1.icache.demand_miss_latency::total 3753112000 # number of demand (read+write) miss cycles 1510system.cpu1.icache.overall_miss_latency::cpu1.inst 3753112000 # number of overall miss cycles 1511system.cpu1.icache.overall_miss_latency::total 3753112000 # number of overall miss cycles 1512system.cpu1.icache.ReadReq_accesses::cpu1.inst 1666090 # number of ReadReq accesses(hits+misses) 1513system.cpu1.icache.ReadReq_accesses::total 1666090 # number of ReadReq accesses(hits+misses) 1514system.cpu1.icache.demand_accesses::cpu1.inst 1666090 # number of demand (read+write) accesses 1515system.cpu1.icache.demand_accesses::total 1666090 # number of demand (read+write) accesses 1516system.cpu1.icache.overall_accesses::cpu1.inst 1666090 # number of overall (read+write) accesses 1517system.cpu1.icache.overall_accesses::total 1666090 # number of overall (read+write) accesses 1518system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163940 # miss rate for ReadReq accesses 1519system.cpu1.icache.ReadReq_miss_rate::total 0.163940 # miss rate for ReadReq accesses 1520system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163940 # miss rate for demand accesses 1521system.cpu1.icache.demand_miss_rate::total 0.163940 # miss rate for demand accesses 1522system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163940 # miss rate for overall accesses 1523system.cpu1.icache.overall_miss_rate::total 0.163940 # miss rate for overall accesses 1524system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13740.666840 # average ReadReq miss latency 1525system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840 # average ReadReq miss latency 1526system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency 1527system.cpu1.icache.demand_avg_miss_latency::total 13740.666840 # average overall miss latency 1528system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency 1529system.cpu1.icache.overall_avg_miss_latency::total 13740.666840 # average overall miss latency 1530system.cpu1.icache.blocked_cycles::no_mshrs 264 # number of cycles access was blocked |
| 1531system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1531system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1532system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked | 1532system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked |
| 1533system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1533system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1534system.cpu1.icache.avg_blocked_cycles::no_mshrs 42.857143 # average number of cycles each access was blocked | 1534system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.666667 # average number of cycles each access was blocked |
| 1535system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1536system.cpu1.icache.fast_writes 0 # number of fast writes performed 1537system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1535system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1536system.cpu1.icache.fast_writes 0 # number of fast writes performed 1537system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1538system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9145 # number of ReadReq MSHR hits 1539system.cpu1.icache.ReadReq_mshr_hits::total 9145 # number of ReadReq MSHR hits 1540system.cpu1.icache.demand_mshr_hits::cpu1.inst 9145 # number of demand (read+write) MSHR hits 1541system.cpu1.icache.demand_mshr_hits::total 9145 # number of demand (read+write) MSHR hits 1542system.cpu1.icache.overall_mshr_hits::cpu1.inst 9145 # number of overall MSHR hits 1543system.cpu1.icache.overall_mshr_hits::total 9145 # number of overall MSHR hits 1544system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 264025 # number of ReadReq MSHR misses 1545system.cpu1.icache.ReadReq_mshr_misses::total 264025 # number of ReadReq MSHR misses 1546system.cpu1.icache.demand_mshr_misses::cpu1.inst 264025 # number of demand (read+write) MSHR misses 1547system.cpu1.icache.demand_mshr_misses::total 264025 # number of demand (read+write) MSHR misses 1548system.cpu1.icache.overall_mshr_misses::cpu1.inst 264025 # number of overall MSHR misses 1549system.cpu1.icache.overall_mshr_misses::total 264025 # number of overall MSHR misses 1550system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3130972999 # number of ReadReq MSHR miss cycles 1551system.cpu1.icache.ReadReq_mshr_miss_latency::total 3130972999 # number of ReadReq MSHR miss cycles 1552system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3130972999 # number of demand (read+write) MSHR miss cycles 1553system.cpu1.icache.demand_mshr_miss_latency::total 3130972999 # number of demand (read+write) MSHR miss cycles 1554system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3130972999 # number of overall MSHR miss cycles 1555system.cpu1.icache.overall_mshr_miss_latency::total 3130972999 # number of overall MSHR miss cycles 1556system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158586 # mshr miss rate for ReadReq accesses 1558system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for demand accesses 1559system.cpu1.icache.demand_mshr_miss_rate::total 0.158586 # mshr miss rate for demand accesses 1560system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for overall accesses 1561system.cpu1.icache.overall_mshr_miss_rate::total 0.158586 # mshr miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average ReadReq mshr miss latency 1563system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.623233 # average ReadReq mshr miss latency 1564system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency 1565system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency 1566system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency 1567system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency | 1538system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9144 # number of ReadReq MSHR hits 1539system.cpu1.icache.ReadReq_mshr_hits::total 9144 # number of ReadReq MSHR hits 1540system.cpu1.icache.demand_mshr_hits::cpu1.inst 9144 # number of demand (read+write) MSHR hits 1541system.cpu1.icache.demand_mshr_hits::total 9144 # number of demand (read+write) MSHR hits 1542system.cpu1.icache.overall_mshr_hits::cpu1.inst 9144 # number of overall MSHR hits 1543system.cpu1.icache.overall_mshr_hits::total 9144 # number of overall MSHR hits 1544system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 263995 # number of ReadReq MSHR misses 1545system.cpu1.icache.ReadReq_mshr_misses::total 263995 # number of ReadReq MSHR misses 1546system.cpu1.icache.demand_mshr_misses::cpu1.inst 263995 # number of demand (read+write) MSHR misses 1547system.cpu1.icache.demand_mshr_misses::total 263995 # number of demand (read+write) MSHR misses 1548system.cpu1.icache.overall_mshr_misses::cpu1.inst 263995 # number of overall MSHR misses 1549system.cpu1.icache.overall_mshr_misses::total 263995 # number of overall MSHR misses 1550system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3126547000 # number of ReadReq MSHR miss cycles 1551system.cpu1.icache.ReadReq_mshr_miss_latency::total 3126547000 # number of ReadReq MSHR miss cycles 1552system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3126547000 # number of demand (read+write) MSHR miss cycles 1553system.cpu1.icache.demand_mshr_miss_latency::total 3126547000 # number of demand (read+write) MSHR miss cycles 1554system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3126547000 # number of overall MSHR miss cycles 1555system.cpu1.icache.overall_mshr_miss_latency::total 3126547000 # number of overall MSHR miss cycles 1556system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158452 # mshr miss rate for ReadReq accesses 1558system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for demand accesses 1559system.cpu1.icache.demand_mshr_miss_rate::total 0.158452 # mshr miss rate for demand accesses 1560system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for overall accesses 1561system.cpu1.icache.overall_mshr_miss_rate::total 0.158452 # mshr miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average ReadReq mshr miss latency 1563system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364 # average ReadReq mshr miss latency 1564system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency 1565system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency 1566system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency 1567system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency |
| 1568system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1568system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1569system.cpu1.dcache.replacements 126485 # number of replacements 1570system.cpu1.dcache.tagsinuse 490.826755 # Cycle average of tags in use 1571system.cpu1.dcache.total_refs 2951833 # Total number of references to valid blocks. 1572system.cpu1.dcache.sampled_refs 126890 # Sample count of references to valid blocks. 1573system.cpu1.dcache.avg_refs 23.262929 # Average number of references to valid blocks. | 1569system.cpu1.dcache.replacements 126526 # number of replacements 1570system.cpu1.dcache.tagsinuse 490.827782 # Cycle average of tags in use 1571system.cpu1.dcache.total_refs 2952051 # Total number of references to valid blocks. 1572system.cpu1.dcache.sampled_refs 126931 # Sample count of references to valid blocks. 1573system.cpu1.dcache.avg_refs 23.257132 # Average number of references to valid blocks. |
| 1574system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit. | 1574system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit. |
| 1575system.cpu1.dcache.occ_blocks::cpu1.data 490.826755 # Average occupied blocks per requestor 1576system.cpu1.dcache.occ_percent::cpu1.data 0.958646 # Average percentage of cache occupancy 1577system.cpu1.dcache.occ_percent::total 0.958646 # Average percentage of cache occupancy 1578system.cpu1.dcache.ReadReq_hits::cpu1.data 1783497 # number of ReadReq hits 1579system.cpu1.dcache.ReadReq_hits::total 1783497 # number of ReadReq hits 1580system.cpu1.dcache.WriteReq_hits::cpu1.data 1082553 # number of WriteReq hits 1581system.cpu1.dcache.WriteReq_hits::total 1082553 # number of WriteReq hits 1582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39938 # number of LoadLockedReq hits 1583system.cpu1.dcache.LoadLockedReq_hits::total 39938 # number of LoadLockedReq hits 1584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38621 # number of StoreCondReq hits 1585system.cpu1.dcache.StoreCondReq_hits::total 38621 # number of StoreCondReq hits 1586system.cpu1.dcache.demand_hits::cpu1.data 2866050 # number of demand (read+write) hits 1587system.cpu1.dcache.demand_hits::total 2866050 # number of demand (read+write) hits 1588system.cpu1.dcache.overall_hits::cpu1.data 2866050 # number of overall hits 1589system.cpu1.dcache.overall_hits::total 2866050 # number of overall hits 1590system.cpu1.dcache.ReadReq_misses::cpu1.data 242860 # number of ReadReq misses 1591system.cpu1.dcache.ReadReq_misses::total 242860 # number of ReadReq misses 1592system.cpu1.dcache.WriteReq_misses::cpu1.data 251463 # number of WriteReq misses 1593system.cpu1.dcache.WriteReq_misses::total 251463 # number of WriteReq misses 1594system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6629 # number of LoadLockedReq misses 1595system.cpu1.dcache.LoadLockedReq_misses::total 6629 # number of LoadLockedReq misses 1596system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3956 # number of StoreCondReq misses 1597system.cpu1.dcache.StoreCondReq_misses::total 3956 # number of StoreCondReq misses 1598system.cpu1.dcache.demand_misses::cpu1.data 494323 # number of demand (read+write) misses 1599system.cpu1.dcache.demand_misses::total 494323 # number of demand (read+write) misses 1600system.cpu1.dcache.overall_misses::cpu1.data 494323 # number of overall misses 1601system.cpu1.dcache.overall_misses::total 494323 # number of overall misses 1602system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3676780500 # number of ReadReq miss cycles 1603system.cpu1.dcache.ReadReq_miss_latency::total 3676780500 # number of ReadReq miss cycles 1604system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8111413586 # number of WriteReq miss cycles 1605system.cpu1.dcache.WriteReq_miss_latency::total 8111413586 # number of WriteReq miss cycles 1606system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67692000 # number of LoadLockedReq miss cycles 1607system.cpu1.dcache.LoadLockedReq_miss_latency::total 67692000 # number of LoadLockedReq miss cycles 1608system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29045500 # number of StoreCondReq miss cycles 1609system.cpu1.dcache.StoreCondReq_miss_latency::total 29045500 # number of StoreCondReq miss cycles 1610system.cpu1.dcache.demand_miss_latency::cpu1.data 11788194086 # number of demand (read+write) miss cycles 1611system.cpu1.dcache.demand_miss_latency::total 11788194086 # number of demand (read+write) miss cycles 1612system.cpu1.dcache.overall_miss_latency::cpu1.data 11788194086 # number of overall miss cycles 1613system.cpu1.dcache.overall_miss_latency::total 11788194086 # number of overall miss cycles 1614system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026357 # number of ReadReq accesses(hits+misses) 1615system.cpu1.dcache.ReadReq_accesses::total 2026357 # number of ReadReq accesses(hits+misses) | 1575system.cpu1.dcache.occ_blocks::cpu1.data 490.827782 # Average occupied blocks per requestor 1576system.cpu1.dcache.occ_percent::cpu1.data 0.958648 # Average percentage of cache occupancy 1577system.cpu1.dcache.occ_percent::total 0.958648 # Average percentage of cache occupancy 1578system.cpu1.dcache.ReadReq_hits::cpu1.data 1783702 # number of ReadReq hits 1579system.cpu1.dcache.ReadReq_hits::total 1783702 # number of ReadReq hits 1580system.cpu1.dcache.WriteReq_hits::cpu1.data 1082593 # number of WriteReq hits 1581system.cpu1.dcache.WriteReq_hits::total 1082593 # number of WriteReq hits 1582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39936 # number of LoadLockedReq hits 1583system.cpu1.dcache.LoadLockedReq_hits::total 39936 # number of LoadLockedReq hits 1584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38619 # number of StoreCondReq hits 1585system.cpu1.dcache.StoreCondReq_hits::total 38619 # number of StoreCondReq hits 1586system.cpu1.dcache.demand_hits::cpu1.data 2866295 # number of demand (read+write) hits 1587system.cpu1.dcache.demand_hits::total 2866295 # number of demand (read+write) hits 1588system.cpu1.dcache.overall_hits::cpu1.data 2866295 # number of overall hits 1589system.cpu1.dcache.overall_hits::total 2866295 # number of overall hits 1590system.cpu1.dcache.ReadReq_misses::cpu1.data 242985 # number of ReadReq misses 1591system.cpu1.dcache.ReadReq_misses::total 242985 # number of ReadReq misses 1592system.cpu1.dcache.WriteReq_misses::cpu1.data 251423 # number of WriteReq misses 1593system.cpu1.dcache.WriteReq_misses::total 251423 # number of WriteReq misses 1594system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6626 # number of LoadLockedReq misses 1595system.cpu1.dcache.LoadLockedReq_misses::total 6626 # number of LoadLockedReq misses 1596system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3957 # number of StoreCondReq misses 1597system.cpu1.dcache.StoreCondReq_misses::total 3957 # number of StoreCondReq misses 1598system.cpu1.dcache.demand_misses::cpu1.data 494408 # number of demand (read+write) misses 1599system.cpu1.dcache.demand_misses::total 494408 # number of demand (read+write) misses 1600system.cpu1.dcache.overall_misses::cpu1.data 494408 # number of overall misses 1601system.cpu1.dcache.overall_misses::total 494408 # number of overall misses 1602system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3665622000 # number of ReadReq miss cycles 1603system.cpu1.dcache.ReadReq_miss_latency::total 3665622000 # number of ReadReq miss cycles 1604system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8223225631 # number of WriteReq miss cycles 1605system.cpu1.dcache.WriteReq_miss_latency::total 8223225631 # number of WriteReq miss cycles 1606system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67675500 # number of LoadLockedReq miss cycles 1607system.cpu1.dcache.LoadLockedReq_miss_latency::total 67675500 # number of LoadLockedReq miss cycles 1608system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29039500 # number of StoreCondReq miss cycles 1609system.cpu1.dcache.StoreCondReq_miss_latency::total 29039500 # number of StoreCondReq miss cycles 1610system.cpu1.dcache.demand_miss_latency::cpu1.data 11888847631 # number of demand (read+write) miss cycles 1611system.cpu1.dcache.demand_miss_latency::total 11888847631 # number of demand (read+write) miss cycles 1612system.cpu1.dcache.overall_miss_latency::cpu1.data 11888847631 # number of overall miss cycles 1613system.cpu1.dcache.overall_miss_latency::total 11888847631 # number of overall miss cycles 1614system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026687 # number of ReadReq accesses(hits+misses) 1615system.cpu1.dcache.ReadReq_accesses::total 2026687 # number of ReadReq accesses(hits+misses) |
| 1616system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses) 1617system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses) | 1616system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses) 1617system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses) |
| 1618system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46567 # number of LoadLockedReq accesses(hits+misses) 1619system.cpu1.dcache.LoadLockedReq_accesses::total 46567 # number of LoadLockedReq accesses(hits+misses) 1620system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42577 # number of StoreCondReq accesses(hits+misses) 1621system.cpu1.dcache.StoreCondReq_accesses::total 42577 # number of StoreCondReq accesses(hits+misses) 1622system.cpu1.dcache.demand_accesses::cpu1.data 3360373 # number of demand (read+write) accesses 1623system.cpu1.dcache.demand_accesses::total 3360373 # number of demand (read+write) accesses 1624system.cpu1.dcache.overall_accesses::cpu1.data 3360373 # number of overall (read+write) accesses 1625system.cpu1.dcache.overall_accesses::total 3360373 # number of overall (read+write) accesses 1626system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119851 # miss rate for ReadReq accesses 1627system.cpu1.dcache.ReadReq_miss_rate::total 0.119851 # miss rate for ReadReq accesses 1628system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188501 # miss rate for WriteReq accesses 1629system.cpu1.dcache.WriteReq_miss_rate::total 0.188501 # miss rate for WriteReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142354 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142354 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092914 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092914 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147104 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.147104 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147104 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.147104 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15139.506300 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 15139.506300 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32256.887041 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 32256.887041 # average WriteReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10211.494946 # average LoadLockedReq miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10211.494946 # average LoadLockedReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.138524 # average StoreCondReq miss latency 1645system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.138524 # average StoreCondReq miss latency 1646system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency 1647system.cpu1.dcache.demand_avg_miss_latency::total 23847.148698 # average overall miss latency 1648system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency 1649system.cpu1.dcache.overall_avg_miss_latency::total 23847.148698 # average overall miss latency 1650system.cpu1.dcache.blocked_cycles::no_mshrs 244071 # number of cycles access was blocked | 1618system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46562 # number of LoadLockedReq accesses(hits+misses) 1619system.cpu1.dcache.LoadLockedReq_accesses::total 46562 # number of LoadLockedReq accesses(hits+misses) 1620system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42576 # number of StoreCondReq accesses(hits+misses) 1621system.cpu1.dcache.StoreCondReq_accesses::total 42576 # number of StoreCondReq accesses(hits+misses) 1622system.cpu1.dcache.demand_accesses::cpu1.data 3360703 # number of demand (read+write) accesses 1623system.cpu1.dcache.demand_accesses::total 3360703 # number of demand (read+write) accesses 1624system.cpu1.dcache.overall_accesses::cpu1.data 3360703 # number of overall (read+write) accesses 1625system.cpu1.dcache.overall_accesses::total 3360703 # number of overall (read+write) accesses 1626system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119893 # miss rate for ReadReq accesses 1627system.cpu1.dcache.ReadReq_miss_rate::total 0.119893 # miss rate for ReadReq accesses 1628system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188471 # miss rate for WriteReq accesses 1629system.cpu1.dcache.WriteReq_miss_rate::total 0.188471 # miss rate for WriteReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142305 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142305 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092940 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092940 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147114 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.147114 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147114 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.147114 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15085.795419 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32706.735784 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784 # average WriteReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10213.628132 # average LoadLockedReq miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132 # average LoadLockedReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7338.766742 # average StoreCondReq miss latency 1645system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7338.766742 # average StoreCondReq miss latency 1646system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency 1647system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803 # average overall miss latency 1648system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency 1649system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803 # average overall miss latency 1650system.cpu1.dcache.blocked_cycles::no_mshrs 255815 # number of cycles access was blocked |
| 1651system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1651system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1652system.cpu1.dcache.blocked::no_mshrs 4071 # number of cycles access was blocked | 1652system.cpu1.dcache.blocked::no_mshrs 3992 # number of cycles access was blocked |
| 1653system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1653system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1654system.cpu1.dcache.avg_blocked_cycles::no_mshrs 59.953574 # average number of cycles each access was blocked | 1654system.cpu1.dcache.avg_blocked_cycles::no_mshrs 64.081914 # average number of cycles each access was blocked |
| 1655system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1656system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1657system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1655system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1656system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1657system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1658system.cpu1.dcache.writebacks::writebacks 84853 # number of writebacks 1659system.cpu1.dcache.writebacks::total 84853 # number of writebacks 1660system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150731 # number of ReadReq MSHR hits 1661system.cpu1.dcache.ReadReq_mshr_hits::total 150731 # number of ReadReq MSHR hits 1662system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205632 # number of WriteReq MSHR hits 1663system.cpu1.dcache.WriteReq_mshr_hits::total 205632 # number of WriteReq MSHR hits 1664system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 643 # number of LoadLockedReq MSHR hits 1665system.cpu1.dcache.LoadLockedReq_mshr_hits::total 643 # number of LoadLockedReq MSHR hits 1666system.cpu1.dcache.demand_mshr_hits::cpu1.data 356363 # number of demand (read+write) MSHR hits 1667system.cpu1.dcache.demand_mshr_hits::total 356363 # number of demand (read+write) MSHR hits 1668system.cpu1.dcache.overall_mshr_hits::cpu1.data 356363 # number of overall MSHR hits 1669system.cpu1.dcache.overall_mshr_hits::total 356363 # number of overall MSHR hits 1670system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92129 # number of ReadReq MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_misses::total 92129 # number of ReadReq MSHR misses 1672system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45831 # number of WriteReq MSHR misses 1673system.cpu1.dcache.WriteReq_mshr_misses::total 45831 # number of WriteReq MSHR misses 1674system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5986 # number of LoadLockedReq MSHR misses 1675system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5986 # number of LoadLockedReq MSHR misses 1676system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3956 # number of StoreCondReq MSHR misses 1677system.cpu1.dcache.StoreCondReq_mshr_misses::total 3956 # number of StoreCondReq MSHR misses 1678system.cpu1.dcache.demand_mshr_misses::cpu1.data 137960 # number of demand (read+write) MSHR misses 1679system.cpu1.dcache.demand_mshr_misses::total 137960 # number of demand (read+write) MSHR misses 1680system.cpu1.dcache.overall_mshr_misses::cpu1.data 137960 # number of overall MSHR misses 1681system.cpu1.dcache.overall_mshr_misses::total 137960 # number of overall MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1123159500 # number of ReadReq MSHR miss cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1123159500 # number of ReadReq MSHR miss cycles 1684system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1210930487 # number of WriteReq MSHR miss cycles 1685system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1210930487 # number of WriteReq MSHR miss cycles 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47601500 # number of LoadLockedReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47601500 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21133500 # number of StoreCondReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21133500 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2334089987 # number of demand (read+write) MSHR miss cycles 1691system.cpu1.dcache.demand_mshr_miss_latency::total 2334089987 # number of demand (read+write) MSHR miss cycles 1692system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2334089987 # number of overall MSHR miss cycles 1693system.cpu1.dcache.overall_mshr_miss_latency::total 2334089987 # number of overall MSHR miss cycles 1694system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30974500 # number of ReadReq MSHR uncacheable cycles 1695system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30974500 # number of ReadReq MSHR uncacheable cycles 1696system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675233500 # number of WriteReq MSHR uncacheable cycles 1697system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675233500 # number of WriteReq MSHR uncacheable cycles 1698system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706208000 # number of overall MSHR uncacheable cycles 1699system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706208000 # number of overall MSHR uncacheable cycles 1700system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045465 # mshr miss rate for ReadReq accesses 1701system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045465 # mshr miss rate for ReadReq accesses 1702system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034356 # mshr miss rate for WriteReq accesses 1703system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034356 # mshr miss rate for WriteReq accesses 1704system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128546 # mshr miss rate for LoadLockedReq accesses 1705system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128546 # mshr miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092914 # mshr miss rate for StoreCondReq accesses 1707system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092914 # mshr miss rate for StoreCondReq accesses 1708system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for demand accesses 1709system.cpu1.dcache.demand_mshr_miss_rate::total 0.041055 # mshr miss rate for demand accesses 1710system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for overall accesses 1711system.cpu1.dcache.overall_mshr_miss_rate::total 0.041055 # mshr miss rate for overall accesses 1712system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12191.161306 # average ReadReq mshr miss latency 1713system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12191.161306 # average ReadReq mshr miss latency 1714system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency 1715system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency 1716system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency 1717system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency 1718system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency 1719system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency 1720system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency 1721system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency 1722system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency 1723system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency | 1658system.cpu1.dcache.writebacks::writebacks 84886 # number of writebacks 1659system.cpu1.dcache.writebacks::total 84886 # number of writebacks 1660system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150812 # number of ReadReq MSHR hits 1661system.cpu1.dcache.ReadReq_mshr_hits::total 150812 # number of ReadReq MSHR hits 1662system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205594 # number of WriteReq MSHR hits 1663system.cpu1.dcache.WriteReq_mshr_hits::total 205594 # number of WriteReq MSHR hits 1664system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 644 # number of LoadLockedReq MSHR hits 1665system.cpu1.dcache.LoadLockedReq_mshr_hits::total 644 # number of LoadLockedReq MSHR hits 1666system.cpu1.dcache.demand_mshr_hits::cpu1.data 356406 # number of demand (read+write) MSHR hits 1667system.cpu1.dcache.demand_mshr_hits::total 356406 # number of demand (read+write) MSHR hits 1668system.cpu1.dcache.overall_mshr_hits::cpu1.data 356406 # number of overall MSHR hits 1669system.cpu1.dcache.overall_mshr_hits::total 356406 # number of overall MSHR hits 1670system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92173 # number of ReadReq MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_misses::total 92173 # number of ReadReq MSHR misses 1672system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45829 # number of WriteReq MSHR misses 1673system.cpu1.dcache.WriteReq_mshr_misses::total 45829 # number of WriteReq MSHR misses 1674system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5982 # number of LoadLockedReq MSHR misses 1675system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5982 # number of LoadLockedReq MSHR misses 1676system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3957 # number of StoreCondReq MSHR misses 1677system.cpu1.dcache.StoreCondReq_mshr_misses::total 3957 # number of StoreCondReq MSHR misses 1678system.cpu1.dcache.demand_mshr_misses::cpu1.data 138002 # number of demand (read+write) MSHR misses 1679system.cpu1.dcache.demand_mshr_misses::total 138002 # number of demand (read+write) MSHR misses 1680system.cpu1.dcache.overall_mshr_misses::cpu1.data 138002 # number of overall MSHR misses 1681system.cpu1.dcache.overall_mshr_misses::total 138002 # number of overall MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1122474000 # number of ReadReq MSHR miss cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1122474000 # number of ReadReq MSHR miss cycles 1684system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1228877987 # number of WriteReq MSHR miss cycles 1685system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1228877987 # number of WriteReq MSHR miss cycles 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47579000 # number of LoadLockedReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47579000 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21125500 # number of StoreCondReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21125500 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2351351987 # number of demand (read+write) MSHR miss cycles 1691system.cpu1.dcache.demand_mshr_miss_latency::total 2351351987 # number of demand (read+write) MSHR miss cycles 1692system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2351351987 # number of overall MSHR miss cycles 1693system.cpu1.dcache.overall_mshr_miss_latency::total 2351351987 # number of overall MSHR miss cycles 1694system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30976000 # number of ReadReq MSHR uncacheable cycles 1695system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30976000 # number of ReadReq MSHR uncacheable cycles 1696system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675219000 # number of WriteReq MSHR uncacheable cycles 1697system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675219000 # number of WriteReq MSHR uncacheable cycles 1698system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706195000 # number of overall MSHR uncacheable cycles 1699system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706195000 # number of overall MSHR uncacheable cycles 1700system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045480 # mshr miss rate for ReadReq accesses 1701system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045480 # mshr miss rate for ReadReq accesses 1702system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034354 # mshr miss rate for WriteReq accesses 1703system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034354 # mshr miss rate for WriteReq accesses 1704system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128474 # mshr miss rate for LoadLockedReq accesses 1705system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128474 # mshr miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092940 # mshr miss rate for StoreCondReq accesses 1707system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092940 # mshr miss rate for StoreCondReq accesses 1708system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for demand accesses 1709system.cpu1.dcache.demand_mshr_miss_rate::total 0.041063 # mshr miss rate for demand accesses 1710system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for overall accesses 1711system.cpu1.dcache.overall_mshr_miss_rate::total 0.041063 # mshr miss rate for overall accesses 1712system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592 # average ReadReq mshr miss latency 1713system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592 # average ReadReq mshr miss latency 1714system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534 # average WriteReq mshr miss latency 1715system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534 # average WriteReq mshr miss latency 1716system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7953.694417 # average LoadLockedReq mshr miss latency 1717system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7953.694417 # average LoadLockedReq mshr miss latency 1718system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5338.766742 # average StoreCondReq mshr miss latency 1719system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5338.766742 # average StoreCondReq mshr miss latency 1720system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency 1721system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency 1722system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency 1723system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency |
| 1724system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1725system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1727system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1729system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1731system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1724system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1725system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1727system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1729system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1731system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1732system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed 1733system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed 1734system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl 1735system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl | 1732system.cpu0.kern.inst.quiesce 6610 # number of quiesce instructions executed 1733system.cpu0.kern.inst.hwrei 175912 # number of hwrei instructions executed 1734system.cpu0.kern.ipl_count::0 61740 40.36% 40.36% # number of times we switched to this ipl 1735system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl |
| 1736system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl | 1736system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl |
| 1737system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl 1738system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl 1739system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl 1740system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl 1741system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl | 1737system.cpu0.kern.ipl_count::30 255 0.17% 41.88% # number of times we switched to this ipl 1738system.cpu0.kern.ipl_count::31 88907 58.12% 100.00% # number of times we switched to this ipl 1739system.cpu0.kern.ipl_count::total 152961 # number of times we switched to this ipl 1740system.cpu0.kern.ipl_good::0 60876 49.17% 49.17% # number of times we switched to this ipl from a different ipl 1741system.cpu0.kern.ipl_good::21 131 0.11% 49.27% # number of times we switched to this ipl from a different ipl |
| 1742system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl 1743system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl | 1742system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl 1743system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl |
| 1744system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl 1745system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl 1746system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl 1747system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl 1748system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl 1749system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl 1750system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl 1751system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl | 1744system.cpu0.kern.ipl_good::31 60621 48.96% 100.00% # number of times we switched to this ipl from a different ipl 1745system.cpu0.kern.ipl_good::total 123811 # number of times we switched to this ipl from a different ipl 1746system.cpu0.kern.ipl_ticks::0 1865672058500 98.16% 98.16% # number of cycles we spent at this ipl 1747system.cpu0.kern.ipl_ticks::21 62377000 0.00% 98.16% # number of cycles we spent at this ipl 1748system.cpu0.kern.ipl_ticks::22 564179500 0.03% 98.19% # number of cycles we spent at this ipl 1749system.cpu0.kern.ipl_ticks::30 124028500 0.01% 98.20% # number of cycles we spent at this ipl 1750system.cpu0.kern.ipl_ticks::31 34304214500 1.80% 100.00% # number of cycles we spent at this ipl 1751system.cpu0.kern.ipl_ticks::total 1900726858000 # number of cycles we spent at this ipl |
| 1752system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl 1753system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1754system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1755system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1752system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl 1753system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1754system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1755system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1756system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl 1757system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl | 1756system.cpu0.kern.ipl_used::31 0.681847 # fraction of swpipl calls that actually changed the ipl 1757system.cpu0.kern.ipl_used::total 0.809429 # fraction of swpipl calls that actually changed the ipl |
| 1758system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 1759system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 1760system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 1761system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 1762system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 1763system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 1764system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 1765system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 1785system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 1786system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 1787system.cpu0.kern.syscall::total 202 # number of syscalls executed 1788system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1789system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed 1790system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed 1791system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed 1792system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed | 1758system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 1759system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 1760system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 1761system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 1762system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 1763system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 1764system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 1765system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 1785system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 1786system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 1787system.cpu0.kern.syscall::total 202 # number of syscalls executed 1788system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1789system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed 1790system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed 1791system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed 1792system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed |
| 1793system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed | 1793system.cpu0.kern.callpal::swpctx 3342 2.08% 2.30% # number of callpals executed |
| 1794system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed 1795system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed | 1794system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed 1795system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed |
| 1796system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed | 1796system.cpu0.kern.callpal::swpipl 146221 90.79% 93.12% # number of callpals executed |
| 1797system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed 1798system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed 1799system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed 1800system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed 1801system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed | 1797system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed 1798system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed 1799system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed 1800system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed 1801system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed |
| 1802system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed | 1802system.cpu0.kern.callpal::rti 4425 2.75% 99.71% # number of callpals executed |
| 1803system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed 1804system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed | 1803system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed 1804system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed |
| 1805system.cpu0.kern.callpal::total 161075 # number of callpals executed 1806system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches 1807system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches | 1805system.cpu0.kern.callpal::total 161059 # number of callpals executed 1806system.cpu0.kern.mode_switch::kernel 6926 # number of protection mode switches 1807system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches |
| 1808system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 1808system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 1809system.cpu0.kern.mode_good::kernel 1258 1810system.cpu0.kern.mode_good::user 1259 | 1809system.cpu0.kern.mode_good::kernel 1256 1810system.cpu0.kern.mode_good::user 1257 |
| 1811system.cpu0.kern.mode_good::idle 0 | 1811system.cpu0.kern.mode_good::idle 0 |
| 1812system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches | 1812system.cpu0.kern.mode_switch_good::kernel 0.181346 # fraction of useful protection mode switches |
| 1813system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1814system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 1813system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1814system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 1815system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches 1816system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode 1817system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode | 1815system.cpu0.kern.mode_switch_good::total 0.307100 # fraction of useful protection mode switches 1816system.cpu0.kern.mode_ticks::kernel 1898828643000 99.90% 99.90% # number of ticks spent at the given mode 1817system.cpu0.kern.mode_ticks::user 1898207000 0.10% 100.00% # number of ticks spent at the given mode |
| 1818system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1819system.cpu0.kern.swap_context 3343 # number of times the context was actually changed 1820system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1818system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1819system.cpu0.kern.swap_context 3343 # number of times the context was actually changed 1820system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1821system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed | 1821system.cpu1.kern.inst.quiesce 2523 # number of quiesce instructions executed |
| 1822system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed 1823system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl 1824system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl 1825system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl 1826system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl 1827system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl 1828system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl 1829system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl 1830system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl 1831system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl 1832system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl | 1822system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed 1823system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl 1824system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl 1825system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl 1826system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl 1827system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl 1828system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl 1829system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl 1830system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl 1831system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl 1832system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl |
| 1833system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl 1834system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl 1835system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl 1836system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl 1837system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl | 1833system.cpu1.kern.ipl_ticks::0 1875010715500 98.66% 98.66% # number of cycles we spent at this ipl 1834system.cpu1.kern.ipl_ticks::22 532408500 0.03% 98.69% # number of cycles we spent at this ipl 1835system.cpu1.kern.ipl_ticks::30 162327000 0.01% 98.70% # number of cycles we spent at this ipl 1836system.cpu1.kern.ipl_ticks::31 24731034000 1.30% 100.00% # number of cycles we spent at this ipl 1837system.cpu1.kern.ipl_ticks::total 1900436485000 # number of cycles we spent at this ipl |
| 1838system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl 1839system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1840system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1841system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl 1842system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl 1843system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 1844system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 1845system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed --- 39 unchanged lines hidden (view full) --- 1885system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches 1886system.cpu1.kern.mode_good::kernel 771 1887system.cpu1.kern.mode_good::user 488 1888system.cpu1.kern.mode_good::idle 283 1889system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches 1890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1891system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches 1892system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches | 1838system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl 1839system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1840system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1841system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl 1842system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl 1843system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 1844system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 1845system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed --- 39 unchanged lines hidden (view full) --- 1885system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches 1886system.cpu1.kern.mode_good::kernel 771 1887system.cpu1.kern.mode_good::user 488 1888system.cpu1.kern.mode_good::idle 283 1889system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches 1890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1891system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches 1892system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches |
| 1893system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode 1894system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode 1895system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode | 1893system.cpu1.kern.mode_ticks::kernel 5768410500 0.30% 0.30% # number of ticks spent at the given mode 1894system.cpu1.kern.mode_ticks::user 833727500 0.04% 0.35% # number of ticks spent at the given mode 1895system.cpu1.kern.mode_ticks::idle 1893823776000 99.65% 100.00% # number of ticks spent at the given mode |
| 1896system.cpu1.kern.swap_context 1394 # number of times the context was actually changed 1897 1898---------- End Simulation Statistics ---------- | 1896system.cpu1.kern.swap_context 1394 # number of times the context was actually changed 1897 1898---------- End Simulation Statistics ---------- |