| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.898811 # Number of seconds simulated 4sim_ticks 1898811181000 # Number of ticks simulated 5final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.899762 # Number of seconds simulated 4sim_ticks 1899762444000 # Number of ticks simulated 5final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 163774 # Simulator instruction rate (inst/s) 8host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5540525376 # Simulator tick rate (ticks/s) 10host_mem_usage 339592 # Number of bytes of host memory used 11host_seconds 342.71 # Real time elapsed on the host 12sim_insts 56127436 # Number of instructions simulated 13sim_ops 56127436 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 450881 # Total number of read requests seen 52system.physmem.writeReqs 122253 # Total number of write requests seen 53system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28856384 # Total number of bytes read from memory 55system.physmem.bytesWritten 7824192 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis | 7host_inst_rate 165662 # Simulator instruction rate (inst/s) 8host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5547317951 # Simulator tick rate (ticks/s) 10host_mem_usage 338604 # Number of bytes of host memory used 11host_seconds 342.47 # Real time elapsed on the host 12sim_insts 56733550 # Number of instructions simulated 13sim_ops 56733550 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 450402 # Total number of read requests seen 52system.physmem.writeReqs 121804 # Total number of write requests seen 53system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28825728 # Total number of bytes read from memory 55system.physmem.bytesWritten 7795456 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis |
| 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 93system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1898811160000 # Total gap between requests | 93system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1899757983000 # Total gap between requests |
| 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 101system.physmem.readPktSize::6 450881 # Categorize read packet sizes 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes 110system.physmem.writePktSize::6 124126 # categorize write packet sizes 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 122system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see | 101system.physmem.readPktSize::6 450402 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes 108system.physmem.writePktSize::6 121804 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see |
| 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 131system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests 190system.physmem.totBusLat 2254075000 # Total cycles spent in databus access 191system.physmem.totBankLat 5576518750 # Total cycles spent in bank access 192system.physmem.avgQLat 18325.99 # Average queueing delay per request 193system.physmem.avgBankLat 12369.86 # Average bank access latency per request | 141system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5296 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5296 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5296 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5296 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5296 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5296 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5296 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5296 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 5296 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 2114 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1475 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see 173system.physmem.totQLat 7756175500 # Total cycles spent in queuing delays 174system.physmem.totMemAccLat 15561175500 # Sum of mem lat for all requests 175system.physmem.totBusLat 2251705000 # Total cycles spent in databus access 176system.physmem.totBankLat 5553295000 # Total cycles spent in bank access 177system.physmem.avgQLat 17222.89 # Average queueing delay per request 178system.physmem.avgBankLat 12331.31 # Average bank access latency per request |
| 194system.physmem.avgBusLat 5000.00 # Average bus latency per request | 179system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 195system.physmem.avgMemAccLat 35695.85 # Average memory access latency 196system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s | 180system.physmem.avgMemAccLat 34554.21 # Average memory access latency 181system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s 182system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s 183system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s 184system.physmem.avgConsumedWrBW 4.10 # Average consumed write bandwidth in MB/s |
| 200system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.15 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time | 185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 186system.physmem.busUtil 0.15 # Data bus utilization in percentage 187system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 203system.physmem.avgWrQLen 8.51 # Average write queue length over time 204system.physmem.readRowHits 422765 # Number of row buffer hits during reads 205system.physmem.writeRowHits 93696 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 93.78 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes 208system.physmem.avgGap 3313031.79 # Average gap between requests 209system.l2c.replacements 343964 # number of replacements 210system.l2c.tagsinuse 65331.328526 # Cycle average of tags in use 211system.l2c.total_refs 2620978 # Total number of references to valid blocks. 212system.l2c.sampled_refs 408975 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.408651 # Average number of references to valid blocks. 214system.l2c.warmup_cycle 5576145752 # Cycle when the warmup percentage was hit. 215system.l2c.occ_blocks::writebacks 53755.791166 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4185.940391 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 5467.030556 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 1355.812299 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 566.754114 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.820248 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.063872 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.083420 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.020688 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.008648 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.996877 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 717909 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 533580 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 356656 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 291510 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1899655 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 844133 # number of Writeback hits 232system.l2c.Writeback_hits::total 844133 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 124 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 89 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 213 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 138119 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 53788 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 191907 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 717909 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 671699 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 356656 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 345298 # number of demand (read+write) hits 246system.l2c.demand_hits::total 2091562 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 717909 # number of overall hits 248system.l2c.overall_hits::cpu0.data 671699 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 356656 # number of overall hits 250system.l2c.overall_hits::cpu1.data 345298 # number of overall hits 251system.l2c.overall_hits::total 2091562 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 11558 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 272086 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 3797 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 1924 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 289365 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2537 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 537 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 3074 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 59 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 99 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 158 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 105872 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 14967 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 120839 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 11558 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 377958 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 3797 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 16891 # number of demand (read+write) misses 270system.l2c.demand_misses::total 410204 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 11558 # number of overall misses 272system.l2c.overall_misses::cpu0.data 377958 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 3797 # number of overall misses 274system.l2c.overall_misses::cpu1.data 16891 # number of overall misses 275system.l2c.overall_misses::total 410204 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 785741000 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 12284482500 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 291007000 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 130325998 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 13491556498 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 572500 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 1115999 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 1688499 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 252000 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68000 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 320000 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 6919340499 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 1319798500 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 8239138999 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 785741000 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 19203822999 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 291007000 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 1450124498 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 21730695497 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 785741000 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 19203822999 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 291007000 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 1450124498 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 21730695497 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 729467 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 805666 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 360453 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 293434 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2189020 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 844133 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 844133 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 2661 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 626 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 3287 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 92 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 132 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 224 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 243991 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 68755 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 312746 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 729467 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1049657 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 360453 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 362189 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2501766 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 729467 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1049657 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 360453 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 362189 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2501766 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.015844 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.337716 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.010534 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.006557 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.132189 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953401 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.857827 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.935199 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.641304 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750000 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.705357 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.433918 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.217686 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.386381 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.015844 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.360078 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.010534 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.046636 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.163966 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.015844 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.360078 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.010534 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.046636 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.163966 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67982.436408 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 45149.263468 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76641.295760 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 67737.005198 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 46624.700631 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 225.660229 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2078.210428 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 549.283995 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4271.186441 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 686.868687 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 2025.316456 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65355.717272 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88180.563907 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 68182.780385 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 67982.436408 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 50809.410038 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 76641.295760 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 85851.903262 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 52975.337873 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 67982.436408 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 50809.410038 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 76641.295760 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 85851.903262 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 52975.337873 # average overall miss latency | 188system.physmem.avgWrQLen 10.95 # Average write queue length over time 189system.physmem.readRowHits 422281 # Number of row buffer hits during reads 190system.physmem.writeRowHits 93689 # Number of row buffer hits during writes 191system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads 192system.physmem.writeRowHitRate 76.92 # Row buffer hit rate for writes 193system.physmem.avgGap 3320059.53 # Average gap between requests 194system.l2c.replacements 343507 # number of replacements 195system.l2c.tagsinuse 65280.658491 # Cycle average of tags in use 196system.l2c.total_refs 2577629 # Total number of references to valid blocks. 197system.l2c.sampled_refs 408521 # Sample count of references to valid blocks. 198system.l2c.avg_refs 6.309661 # Average number of references to valid blocks. 199system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit. 200system.l2c.occ_blocks::writebacks 53803.217874 # Average occupied blocks per requestor 201system.l2c.occ_blocks::cpu0.inst 5298.496684 # Average occupied blocks per requestor 202system.l2c.occ_blocks::cpu0.data 5899.097985 # Average occupied blocks per requestor 203system.l2c.occ_blocks::cpu1.inst 206.030699 # Average occupied blocks per requestor 204system.l2c.occ_blocks::cpu1.data 73.815249 # Average occupied blocks per requestor 205system.l2c.occ_percent::writebacks 0.820972 # Average percentage of cache occupancy 206system.l2c.occ_percent::cpu0.inst 0.080849 # Average percentage of cache occupancy 207system.l2c.occ_percent::cpu0.data 0.090013 # Average percentage of cache occupancy 208system.l2c.occ_percent::cpu1.inst 0.003144 # Average percentage of cache occupancy 209system.l2c.occ_percent::cpu1.data 0.001126 # Average percentage of cache occupancy 210system.l2c.occ_percent::total 0.996104 # Average percentage of cache occupancy 211system.l2c.ReadReq_hits::cpu0.inst 850473 # number of ReadReq hits 212system.l2c.ReadReq_hits::cpu0.data 731190 # number of ReadReq hits 213system.l2c.ReadReq_hits::cpu1.inst 225422 # number of ReadReq hits 214system.l2c.ReadReq_hits::cpu1.data 71980 # number of ReadReq hits 215system.l2c.ReadReq_hits::total 1879065 # number of ReadReq hits 216system.l2c.Writeback_hits::writebacks 820673 # number of Writeback hits 217system.l2c.Writeback_hits::total 820673 # number of Writeback hits 218system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits 219system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits 220system.l2c.UpgradeReq_hits::total 443 # number of UpgradeReq hits 221system.l2c.SCUpgradeReq_hits::cpu0.data 45 # number of SCUpgradeReq hits 222system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 223system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits 224system.l2c.ReadExReq_hits::cpu0.data 153356 # number of ReadExReq hits 225system.l2c.ReadExReq_hits::cpu1.data 26453 # number of ReadExReq hits 226system.l2c.ReadExReq_hits::total 179809 # number of ReadExReq hits 227system.l2c.demand_hits::cpu0.inst 850473 # number of demand (read+write) hits 228system.l2c.demand_hits::cpu0.data 884546 # number of demand (read+write) hits 229system.l2c.demand_hits::cpu1.inst 225422 # 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number of overall misses 257system.l2c.overall_misses::cpu0.data 385863 # number of overall misses 258system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses 259system.l2c.overall_misses::cpu1.data 8504 # number of overall misses 260system.l2c.overall_misses::total 409644 # number of overall misses 261system.l2c.ReadReq_miss_latency::cpu0.inst 919052500 # number of ReadReq miss cycles 262system.l2c.ReadReq_miss_latency::cpu0.data 11905171000 # number of ReadReq miss cycles 263system.l2c.ReadReq_miss_latency::cpu1.inst 147649500 # number of ReadReq miss cycles 264system.l2c.ReadReq_miss_latency::cpu1.data 64290999 # number of ReadReq miss cycles 265system.l2c.ReadReq_miss_latency::total 13036163999 # number of ReadReq miss cycles 266system.l2c.UpgradeReq_miss_latency::cpu0.data 1055000 # number of UpgradeReq miss cycles 267system.l2c.UpgradeReq_miss_latency::cpu1.data 5020958 # number of UpgradeReq miss cycles 268system.l2c.UpgradeReq_miss_latency::total 6075958 # number of UpgradeReq miss cycles 269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147998 # number of SCUpgradeReq miss cycles 270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles 271system.l2c.SCUpgradeReq_miss_latency::total 1306998 # number of SCUpgradeReq miss cycles 272system.l2c.ReadExReq_miss_latency::cpu0.data 7474090498 # number of ReadExReq miss cycles 273system.l2c.ReadExReq_miss_latency::cpu1.data 738521500 # number of ReadExReq miss cycles 274system.l2c.ReadExReq_miss_latency::total 8212611998 # number of ReadExReq miss cycles 275system.l2c.demand_miss_latency::cpu0.inst 919052500 # number of demand (read+write) miss cycles 276system.l2c.demand_miss_latency::cpu0.data 19379261498 # number of demand (read+write) miss cycles 277system.l2c.demand_miss_latency::cpu1.inst 147649500 # number of demand (read+write) miss cycles 278system.l2c.demand_miss_latency::cpu1.data 802812499 # number of demand (read+write) miss cycles 279system.l2c.demand_miss_latency::total 21248775997 # number of demand (read+write) miss cycles 280system.l2c.overall_miss_latency::cpu0.inst 919052500 # number of overall miss cycles 281system.l2c.overall_miss_latency::cpu0.data 19379261498 # number of overall miss cycles 282system.l2c.overall_miss_latency::cpu1.inst 147649500 # number of overall miss cycles 283system.l2c.overall_miss_latency::cpu1.data 802812499 # number of overall miss cycles 284system.l2c.overall_miss_latency::total 21248775997 # number of overall miss cycles 285system.l2c.ReadReq_accesses::cpu0.inst 863805 # number of ReadReq accesses(hits+misses) 286system.l2c.ReadReq_accesses::cpu0.data 1004209 # number of ReadReq accesses(hits+misses) 287system.l2c.ReadReq_accesses::cpu1.inst 227367 # number of ReadReq accesses(hits+misses) 288system.l2c.ReadReq_accesses::cpu1.data 72865 # number of ReadReq accesses(hits+misses) 289system.l2c.ReadReq_accesses::total 2168246 # number of ReadReq accesses(hits+misses) 290system.l2c.Writeback_accesses::writebacks 820673 # number of Writeback accesses(hits+misses) 291system.l2c.Writeback_accesses::total 820673 # number of Writeback accesses(hits+misses) 292system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses) 293system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) 294system.l2c.UpgradeReq_accesses::total 4288 # number of UpgradeReq accesses(hits+misses) 295system.l2c.SCUpgradeReq_accesses::cpu0.data 485 # number of SCUpgradeReq accesses(hits+misses) 296system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) 297system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) 298system.l2c.ReadExReq_accesses::cpu0.data 266200 # number of ReadExReq accesses(hits+misses) 299system.l2c.ReadExReq_accesses::cpu1.data 34072 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_accesses::total 300272 # number of ReadExReq accesses(hits+misses) 301system.l2c.demand_accesses::cpu0.inst 863805 # number of demand (read+write) accesses 302system.l2c.demand_accesses::cpu0.data 1270409 # number of demand (read+write) accesses 303system.l2c.demand_accesses::cpu1.inst 227367 # number of demand (read+write) accesses 304system.l2c.demand_accesses::cpu1.data 106937 # number of demand (read+write) accesses 305system.l2c.demand_accesses::total 2468518 # number of demand (read+write) accesses 306system.l2c.overall_accesses::cpu0.inst 863805 # number of overall (read+write) accesses 307system.l2c.overall_accesses::cpu0.data 1270409 # number of overall (read+write) accesses 308system.l2c.overall_accesses::cpu1.inst 227367 # number of overall (read+write) accesses 309system.l2c.overall_accesses::cpu1.data 106937 # number of overall (read+write) accesses 310system.l2c.overall_accesses::total 2468518 # number of overall (read+write) accesses 311system.l2c.ReadReq_miss_rate::cpu0.inst 0.015434 # miss rate for ReadReq accesses 312system.l2c.ReadReq_miss_rate::cpu0.data 0.271875 # miss rate for ReadReq accesses 313system.l2c.ReadReq_miss_rate::cpu1.inst 0.008554 # miss rate for ReadReq accesses 314system.l2c.ReadReq_miss_rate::cpu1.data 0.012146 # miss rate for ReadReq accesses 315system.l2c.ReadReq_miss_rate::total 0.133371 # miss rate for ReadReq accesses 316system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940870 # miss rate for UpgradeReq accesses 317system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806794 # miss rate for UpgradeReq accesses 318system.l2c.UpgradeReq_miss_rate::total 0.896688 # miss rate for UpgradeReq accesses 319system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.907216 # miss rate for SCUpgradeReq accesses 320system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.952381 # miss rate for SCUpgradeReq accesses 321system.l2c.SCUpgradeReq_miss_rate::total 0.929752 # miss rate for SCUpgradeReq accesses 322system.l2c.ReadExReq_miss_rate::cpu0.data 0.423907 # miss rate for ReadExReq accesses 323system.l2c.ReadExReq_miss_rate::cpu1.data 0.223615 # miss rate for ReadExReq accesses 324system.l2c.ReadExReq_miss_rate::total 0.401180 # miss rate for ReadExReq accesses 325system.l2c.demand_miss_rate::cpu0.inst 0.015434 # miss rate for demand accesses 326system.l2c.demand_miss_rate::cpu0.data 0.303731 # miss rate for demand accesses 327system.l2c.demand_miss_rate::cpu1.inst 0.008554 # miss rate for demand accesses 328system.l2c.demand_miss_rate::cpu1.data 0.079523 # miss rate for demand accesses 329system.l2c.demand_miss_rate::total 0.165947 # miss rate for demand accesses 330system.l2c.overall_miss_rate::cpu0.inst 0.015434 # miss rate for overall accesses 331system.l2c.overall_miss_rate::cpu0.data 0.303731 # miss rate for overall accesses 332system.l2c.overall_miss_rate::cpu1.inst 0.008554 # miss rate for overall accesses 333system.l2c.overall_miss_rate::cpu1.data 0.079523 # miss rate for overall accesses 334system.l2c.overall_miss_rate::total 0.165947 # miss rate for overall accesses 335system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68935.831083 # average ReadReq miss latency 336system.l2c.ReadReq_avg_miss_latency::cpu0.data 43605.650156 # average ReadReq miss latency 337system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75912.339332 # average ReadReq miss latency 338system.l2c.ReadReq_avg_miss_latency::cpu1.data 72645.196610 # average ReadReq miss latency 339system.l2c.ReadReq_avg_miss_latency::total 45079.600662 # average ReadReq miss latency 340system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 390.018484 # average UpgradeReq miss latency 341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4404.349123 # average UpgradeReq miss latency 342system.l2c.UpgradeReq_avg_miss_latency::total 1580.223147 # average UpgradeReq miss latency 343system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2609.086364 # average SCUpgradeReq miss latency 344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 345.652174 # average SCUpgradeReq miss latency 345system.l2c.SCUpgradeReq_avg_miss_latency::total 1452.220000 # average SCUpgradeReq miss latency 346system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66233.831644 # average ReadExReq miss latency 347system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96931.552697 # average ReadExReq miss latency 348system.l2c.ReadExReq_avg_miss_latency::total 68175.389937 # average ReadExReq miss latency 349system.l2c.demand_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency 350system.l2c.demand_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency 351system.l2c.demand_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency 352system.l2c.demand_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency 353system.l2c.demand_avg_miss_latency::total 51871.322409 # average overall miss latency 354system.l2c.overall_avg_miss_latency::cpu0.inst 68935.831083 # average overall miss latency 355system.l2c.overall_avg_miss_latency::cpu0.data 50223.165989 # average overall miss latency 356system.l2c.overall_avg_miss_latency::cpu1.inst 75912.339332 # average overall miss latency 357system.l2c.overall_avg_miss_latency::cpu1.data 94404.103833 # average overall miss latency 358system.l2c.overall_avg_miss_latency::total 51871.322409 # average overall miss latency |
| 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed | 359system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 362system.l2c.blocked::no_targets 0 # number of cycles access was blocked 363system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.l2c.fast_writes 0 # number of fast writes performed 366system.l2c.cache_copies 0 # number of cache copies performed |
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number of overall MSHR miss cycles 441system.l2c.overall_mshr_miss_latency::cpu1.inst 243130799 # number of overall MSHR miss cycles 442system.l2c.overall_mshr_miss_latency::cpu1.data 1271826886 # number of overall MSHR miss cycles 443system.l2c.overall_mshr_miss_latency::total 16736965237 # number of overall MSHR miss cycles 444system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929565000 # number of ReadReq MSHR uncacheable cycles 445system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460091000 # number of ReadReq MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_uncacheable_latency::total 1389656000 # number of ReadReq MSHR uncacheable cycles 447system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1573030500 # number of WriteReq MSHR uncacheable cycles 448system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890243000 # number of WriteReq MSHR uncacheable cycles 449system.l2c.WriteReq_mshr_uncacheable_latency::total 2463273500 # number of WriteReq MSHR uncacheable cycles 450system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2502595500 # number of overall MSHR uncacheable cycles 451system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350334000 # number of overall MSHR uncacheable cycles 452system.l2c.overall_mshr_uncacheable_latency::total 3852929500 # number of overall MSHR uncacheable cycles 453system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.337716 # mshr miss rate for ReadReq accesses 455system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for ReadReq accesses 456system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006553 # mshr miss rate for ReadReq accesses 457system.l2c.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses 458system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.953401 # mshr miss rate for UpgradeReq accesses 459system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857827 # mshr miss rate for UpgradeReq accesses 460system.l2c.UpgradeReq_mshr_miss_rate::total 0.935199 # mshr miss rate for UpgradeReq accesses 461system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.641304 # mshr miss rate for SCUpgradeReq accesses 462system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses 463system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.705357 # mshr miss rate for SCUpgradeReq accesses 464system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433918 # mshr miss rate for ReadExReq accesses 465system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.217686 # mshr miss rate for ReadExReq accesses 466system.l2c.ReadExReq_mshr_miss_rate::total 0.386381 # mshr miss rate for ReadExReq accesses 467system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu0.data 0.360078 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.data 0.046633 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::total 0.163959 # mshr miss rate for demand accesses 472system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015843 # mshr miss rate for overall accesses 473system.l2c.overall_mshr_miss_rate::cpu0.data 0.360078 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010490 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu1.data 0.046633 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::total 0.163959 # mshr miss rate for overall accesses 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 32897.729710 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70157.619865 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 34459.231725 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.819078 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.951583 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10023.920625 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10526.355932 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.101010 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10266.791139 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53171.529130 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75961.367208 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 55994.256118 # average ReadExReq mshr miss latency 491system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38576.740850 # average overall mshr miss latency 493system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75300.585317 # average overall mshr miss latency 495system.l2c.demand_avg_mshr_miss_latency::total 40803.355641 # average overall mshr miss latency 496system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55517.844942 # average overall mshr miss latency 497system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38576.740850 # average overall mshr miss latency 498system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64303.305739 # average overall mshr miss latency 499system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75300.585317 # average overall mshr miss latency 500system.l2c.overall_avg_mshr_miss_latency::total 40803.355641 # average overall mshr miss latency | 381system.l2c.ReadReq_mshr_misses::cpu0.inst 13331 # number of ReadReq MSHR misses 382system.l2c.ReadReq_mshr_misses::cpu0.data 273019 # number of ReadReq MSHR misses 383system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses 384system.l2c.ReadReq_mshr_misses::cpu1.data 884 # number of ReadReq MSHR misses 385system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses 386system.l2c.UpgradeReq_mshr_misses::cpu0.data 2705 # number of UpgradeReq MSHR misses 387system.l2c.UpgradeReq_mshr_misses::cpu1.data 1140 # number of UpgradeReq MSHR misses 388system.l2c.UpgradeReq_mshr_misses::total 3845 # number of UpgradeReq MSHR misses 389system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 440 # number of SCUpgradeReq MSHR misses 390system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses 391system.l2c.SCUpgradeReq_mshr_misses::total 900 # number of SCUpgradeReq MSHR misses 392system.l2c.ReadExReq_mshr_misses::cpu0.data 112844 # number of ReadExReq MSHR misses 393system.l2c.ReadExReq_mshr_misses::cpu1.data 7619 # number of ReadExReq MSHR misses 394system.l2c.ReadExReq_mshr_misses::total 120463 # number of ReadExReq MSHR misses 395system.l2c.demand_mshr_misses::cpu0.inst 13331 # number of demand (read+write) MSHR misses 396system.l2c.demand_mshr_misses::cpu0.data 385863 # number of demand (read+write) MSHR misses 397system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses 398system.l2c.demand_mshr_misses::cpu1.data 8503 # number of demand (read+write) MSHR misses 399system.l2c.demand_mshr_misses::total 409626 # number of demand (read+write) MSHR misses 400system.l2c.overall_mshr_misses::cpu0.inst 13331 # number of overall MSHR misses 401system.l2c.overall_mshr_misses::cpu0.data 385863 # number of overall MSHR misses 402system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses 403system.l2c.overall_mshr_misses::cpu1.data 8503 # number of overall MSHR misses 404system.l2c.overall_mshr_misses::total 409626 # number of overall MSHR misses 405system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 752774551 # number of ReadReq MSHR miss cycles 406system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8562507308 # number of ReadReq MSHR miss cycles 407system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122885880 # number of ReadReq MSHR miss cycles 408system.l2c.ReadReq_mshr_miss_latency::cpu1.data 53311432 # number of ReadReq MSHR miss cycles 409system.l2c.ReadReq_mshr_miss_latency::total 9491479171 # number of ReadReq MSHR miss cycles 410system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27258667 # number of UpgradeReq MSHR miss cycles 411system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11426097 # number of UpgradeReq MSHR miss cycles 412system.l2c.UpgradeReq_mshr_miss_latency::total 38684764 # number of UpgradeReq MSHR miss cycles 413system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4415934 # number of SCUpgradeReq MSHR miss cycles 414system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604459 # number of SCUpgradeReq MSHR miss cycles 415system.l2c.SCUpgradeReq_mshr_miss_latency::total 9020393 # number of SCUpgradeReq MSHR miss cycles 416system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6098954840 # number of ReadExReq MSHR miss cycles 417system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 645340483 # number of ReadExReq MSHR miss cycles 418system.l2c.ReadExReq_mshr_miss_latency::total 6744295323 # number of ReadExReq MSHR miss cycles 419system.l2c.demand_mshr_miss_latency::cpu0.inst 752774551 # number of demand (read+write) MSHR miss cycles 420system.l2c.demand_mshr_miss_latency::cpu0.data 14661462148 # number of demand (read+write) MSHR miss cycles 421system.l2c.demand_mshr_miss_latency::cpu1.inst 122885880 # number of demand (read+write) MSHR miss cycles 422system.l2c.demand_mshr_miss_latency::cpu1.data 698651915 # number of demand (read+write) MSHR miss cycles 423system.l2c.demand_mshr_miss_latency::total 16235774494 # number of demand (read+write) MSHR miss cycles 424system.l2c.overall_mshr_miss_latency::cpu0.inst 752774551 # number of overall MSHR miss cycles 425system.l2c.overall_mshr_miss_latency::cpu0.data 14661462148 # number of overall MSHR miss cycles 426system.l2c.overall_mshr_miss_latency::cpu1.inst 122885880 # number of overall MSHR miss cycles 427system.l2c.overall_mshr_miss_latency::cpu1.data 698651915 # number of overall MSHR miss cycles 428system.l2c.overall_mshr_miss_latency::total 16235774494 # number of overall MSHR miss cycles 429system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363373000 # number of ReadReq MSHR uncacheable cycles 430system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28764500 # number of ReadReq MSHR uncacheable cycles 431system.l2c.ReadReq_mshr_uncacheable_latency::total 1392137500 # number of ReadReq MSHR uncacheable cycles 432system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2009193000 # number of WriteReq MSHR uncacheable cycles 433system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 611400000 # number of WriteReq MSHR uncacheable cycles 434system.l2c.WriteReq_mshr_uncacheable_latency::total 2620593000 # number of WriteReq MSHR uncacheable cycles 435system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3372566000 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::cpu1.data 640164500 # number of overall MSHR uncacheable cycles 437system.l2c.overall_mshr_uncacheable_latency::total 4012730500 # number of overall MSHR uncacheable cycles 438system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271875 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012132 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::total 0.133363 # mshr miss rate for ReadReq accesses 443system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940870 # mshr miss rate for UpgradeReq accesses 444system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806794 # mshr miss rate for UpgradeReq accesses 445system.l2c.UpgradeReq_mshr_miss_rate::total 0.896688 # mshr miss rate for UpgradeReq accesses 446system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.907216 # mshr miss rate for SCUpgradeReq accesses 447system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952381 # mshr miss rate for SCUpgradeReq accesses 448system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929752 # mshr miss rate for SCUpgradeReq accesses 449system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.423907 # mshr miss rate for ReadExReq accesses 450system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.223615 # mshr miss rate for ReadExReq accesses 451system.l2c.ReadExReq_mshr_miss_rate::total 0.401180 # mshr miss rate for ReadExReq accesses 452system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for demand accesses 453system.l2c.demand_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for demand accesses 454system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for demand accesses 455system.l2c.demand_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::total 0.165940 # mshr miss rate for demand accesses 457system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for overall accesses 458system.l2c.overall_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for overall accesses 459system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for overall accesses 460system.l2c.overall_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for overall accesses 461system.l2c.overall_mshr_miss_rate::total 0.165940 # mshr miss rate for overall accesses 462system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average ReadReq mshr miss latency 463system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31362.312909 # average ReadReq mshr miss latency 464system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average ReadReq mshr miss latency 465system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60307.049774 # average ReadReq mshr miss latency 466system.l2c.ReadReq_avg_mshr_miss_latency::total 32823.975305 # average ReadReq mshr miss latency 467system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.141220 # average UpgradeReq mshr miss latency 468system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892105 # average UpgradeReq mshr miss latency 469system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.056957 # average UpgradeReq mshr miss latency 470system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10036.213636 # average SCUpgradeReq mshr miss latency 471system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.693478 # average SCUpgradeReq mshr miss latency 472system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.658889 # average SCUpgradeReq mshr miss latency 473system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54047.666159 # average ReadExReq mshr miss latency 474system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84701.467778 # average ReadExReq mshr miss latency 475system.l2c.ReadExReq_avg_mshr_miss_latency::total 55986.446652 # average ReadExReq mshr miss latency 476system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency 477system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency 478system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency 479system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency 480system.l2c.demand_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency 481system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency 482system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency 483system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency 484system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency 485system.l2c.overall_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency |
| 501system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 502system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 503system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 504system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 505system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 506system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 507system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 508system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 509system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 510system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 486system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 487system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 488system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 489system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 490system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 491system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 492system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 493system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 494system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 495system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 511system.iocache.replacements 41698 # number of replacements 512system.iocache.tagsinuse 0.398700 # Cycle average of tags in use | 496system.iocache.replacements 41697 # number of replacements 497system.iocache.tagsinuse 0.501565 # Cycle average of tags in use |
| 513system.iocache.total_refs 0 # Total number of references to valid blocks. | 498system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 514system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. | 499system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. |
| 515system.iocache.avg_refs 0 # Average number of references to valid blocks. | 500system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 516system.iocache.warmup_cycle 1706437655000 # Cycle when the warmup percentage was hit. 517system.iocache.occ_blocks::tsunami.ide 0.398700 # Average occupied blocks per requestor 518system.iocache.occ_percent::tsunami.ide 0.024919 # Average percentage of cache occupancy 519system.iocache.occ_percent::total 0.024919 # Average percentage of cache occupancy 520system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 521system.iocache.ReadReq_misses::total 176 # number of ReadReq misses | 501system.iocache.warmup_cycle 1705456155000 # Cycle when the warmup percentage was hit. 502system.iocache.occ_blocks::tsunami.ide 0.501565 # Average occupied blocks per requestor 503system.iocache.occ_percent::tsunami.ide 0.031348 # Average percentage of cache occupancy 504system.iocache.occ_percent::total 0.031348 # Average percentage of cache occupancy 505system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses 506system.iocache.ReadReq_misses::total 177 # number of ReadReq misses |
| 522system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 523system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses | 507system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 508system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses |
| 524system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 525system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 526system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 527system.iocache.overall_misses::total 41728 # number of overall misses 528system.iocache.ReadReq_miss_latency::tsunami.ide 21267998 # number of ReadReq miss cycles 529system.iocache.ReadReq_miss_latency::total 21267998 # number of ReadReq miss cycles 530system.iocache.WriteReq_miss_latency::tsunami.ide 10658856806 # number of WriteReq miss cycles 531system.iocache.WriteReq_miss_latency::total 10658856806 # number of WriteReq miss cycles 532system.iocache.demand_miss_latency::tsunami.ide 10680124804 # number of demand (read+write) miss cycles 533system.iocache.demand_miss_latency::total 10680124804 # number of demand (read+write) miss cycles 534system.iocache.overall_miss_latency::tsunami.ide 10680124804 # number of overall miss cycles 535system.iocache.overall_miss_latency::total 10680124804 # number of overall miss cycles 536system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 537system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) | 509system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses 510system.iocache.demand_misses::total 41729 # number of demand (read+write) misses 511system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses 512system.iocache.overall_misses::total 41729 # number of overall misses 513system.iocache.ReadReq_miss_latency::tsunami.ide 21380998 # number of ReadReq miss cycles 514system.iocache.ReadReq_miss_latency::total 21380998 # number of ReadReq miss cycles 515system.iocache.WriteReq_miss_latency::tsunami.ide 10589255806 # number of WriteReq miss cycles 516system.iocache.WriteReq_miss_latency::total 10589255806 # number of WriteReq miss cycles 517system.iocache.demand_miss_latency::tsunami.ide 10610636804 # number of demand (read+write) miss cycles 518system.iocache.demand_miss_latency::total 10610636804 # number of demand (read+write) miss cycles 519system.iocache.overall_miss_latency::tsunami.ide 10610636804 # number of overall miss cycles 520system.iocache.overall_miss_latency::total 10610636804 # number of overall miss cycles 521system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) 522system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) |
| 538system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 539system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) | 523system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 524system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) |
| 540system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 541system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 542system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 543system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses | 525system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses 526system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses 527system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses 528system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses |
| 544system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 545system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 546system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 547system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 548system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 549system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 550system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 551system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 529system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 530system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 531system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 532system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 533system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 534system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 535system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 536system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 552system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727 # average ReadReq miss latency 553system.iocache.ReadReq_avg_miss_latency::total 120840.897727 # average ReadReq miss latency 554system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262 # average WriteReq miss latency 555system.iocache.WriteReq_avg_miss_latency::total 256518.502262 # average WriteReq miss latency 556system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency 557system.iocache.demand_avg_miss_latency::total 255946.242427 # average overall miss latency 558system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency 559system.iocache.overall_avg_miss_latency::total 255946.242427 # average overall miss latency 560system.iocache.blocked_cycles::no_mshrs 284980 # number of cycles access was blocked | 537system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency 538system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency 539system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency 540system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency 541system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency 542system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency 543system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency 544system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency 545system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked |
| 561system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 546system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 562system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked | 547system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked |
| 563system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 548system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 564system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked | 549system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked |
| 565system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 566system.iocache.fast_writes 0 # number of fast writes performed 567system.iocache.cache_copies 0 # number of cache copies performed | 550system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.iocache.fast_writes 0 # number of fast writes performed 552system.iocache.cache_copies 0 # number of cache copies performed |
| 568system.iocache.writebacks::writebacks 41522 # number of writebacks 569system.iocache.writebacks::total 41522 # number of writebacks 570system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 571system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses | 553system.iocache.writebacks::writebacks 41520 # number of writebacks 554system.iocache.writebacks::total 41520 # number of writebacks 555system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 556system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses |
| 572system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 573system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses | 557system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 558system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses |
| 574system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 575system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 576system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 577system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 578system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles 579system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles 580system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles 581system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles 582system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles 583system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles 584system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles 585system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles | 559system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses 560system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses 561system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses 562system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses 563system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles 564system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles 565system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles 566system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles 567system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles 568system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles 569system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles 570system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles |
| 586system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 587system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 588system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 589system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 590system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 591system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 592system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 593system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 571system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 572system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 573system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 574system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 575system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 576system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 577system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 578system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 594system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency 595system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency 596system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency 597system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency 598system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency 599system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency 600system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency 601system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency | 579system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency 580system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency 581system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency 582system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency 583system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency 584system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency 585system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency 586system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency |
| 602system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 605system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 606system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 607system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 608system.disk0.dma_write_txs 395 # Number of DMA write transactions. 609system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 610system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 611system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 612system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 613system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 614system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 587system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 589system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 590system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 591system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 592system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 593system.disk0.dma_write_txs 395 # Number of DMA write transactions. 594system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 595system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 596system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 597system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 598system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 599system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 615system.cpu0.branchPred.lookups 10581841 # Number of BP lookups 616system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted 617system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect 618system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups 619system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits | 600system.cpu0.branchPred.lookups 12335027 # Number of BP lookups 601system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted 602system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect 603system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups 604system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits |
| 620system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 605system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 621system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage 622system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. 623system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. | 606system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage 607system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. 608system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. |
| 624system.cpu0.dtb.fetch_hits 0 # ITB hits 625system.cpu0.dtb.fetch_misses 0 # ITB misses 626system.cpu0.dtb.fetch_acv 0 # ITB acv 627system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 628system.cpu0.dtb.read_hits 7560815 # DTB read hits 629system.cpu0.dtb.read_misses 30461 # DTB read misses 630system.cpu0.dtb.read_acv 538 # DTB read access violations 631system.cpu0.dtb.read_accesses 623625 # DTB read accesses 632system.cpu0.dtb.write_hits 5040625 # DTB write hits 633system.cpu0.dtb.write_misses 7520 # DTB write misses 634system.cpu0.dtb.write_acv 334 # DTB write access violations 635system.cpu0.dtb.write_accesses 206551 # DTB write accesses 636system.cpu0.dtb.data_hits 12601440 # DTB hits 637system.cpu0.dtb.data_misses 37981 # DTB misses 638system.cpu0.dtb.data_acv 872 # DTB access violations 639system.cpu0.dtb.data_accesses 830176 # DTB accesses 640system.cpu0.itb.fetch_hits 911527 # ITB hits 641system.cpu0.itb.fetch_misses 30644 # ITB misses 642system.cpu0.itb.fetch_acv 921 # ITB acv 643system.cpu0.itb.fetch_accesses 942171 # ITB accesses | 613system.cpu0.dtb.read_hits 8753494 # DTB read hits 614system.cpu0.dtb.read_misses 29787 # DTB read misses 615system.cpu0.dtb.read_acv 536 # DTB read access violations 616system.cpu0.dtb.read_accesses 623801 # DTB read accesses 617system.cpu0.dtb.write_hits 5745053 # DTB write hits 618system.cpu0.dtb.write_misses 8131 # DTB write misses 619system.cpu0.dtb.write_acv 346 # DTB write access violations 620system.cpu0.dtb.write_accesses 207769 # DTB write accesses 621system.cpu0.dtb.data_hits 14498547 # DTB hits 622system.cpu0.dtb.data_misses 37918 # DTB misses 623system.cpu0.dtb.data_acv 882 # DTB access violations 624system.cpu0.dtb.data_accesses 831570 # DTB accesses 625system.cpu0.itb.fetch_hits 986254 # ITB hits 626system.cpu0.itb.fetch_misses 27996 # ITB misses 627system.cpu0.itb.fetch_acv 985 # ITB acv 628system.cpu0.itb.fetch_accesses 1014250 # ITB accesses |
| 644system.cpu0.itb.read_hits 0 # DTB read hits 645system.cpu0.itb.read_misses 0 # DTB read misses 646system.cpu0.itb.read_acv 0 # DTB read access violations 647system.cpu0.itb.read_accesses 0 # DTB read accesses 648system.cpu0.itb.write_hits 0 # DTB write hits 649system.cpu0.itb.write_misses 0 # DTB write misses 650system.cpu0.itb.write_acv 0 # DTB write access violations 651system.cpu0.itb.write_accesses 0 # DTB write accesses 652system.cpu0.itb.data_hits 0 # DTB hits 653system.cpu0.itb.data_misses 0 # DTB misses 654system.cpu0.itb.data_acv 0 # DTB access violations 655system.cpu0.itb.data_accesses 0 # DTB accesses | 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses |
| 656system.cpu0.numCycles 89753559 # number of cpu cycles simulated | 641system.cpu0.numCycles 101860002 # number of cpu cycles simulated |
| 657system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 658system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 659system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss 660system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed 661system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered 662system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken 663system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked 664system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing 665system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked 666system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 667system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps 668system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions 669system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR 670system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched 671system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed 672system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) 673system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) | 644system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss 645system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed 646system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered 647system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken 648system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked 649system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing 650system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked 651system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 652system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps 653system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions 654system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR 655system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched 656system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed 657system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) 658system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) 659system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) |
| 675system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 660system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 676system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) 677system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) 678system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) 679system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) 680system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) 681system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) 682system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) 683system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) 684system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) | 661system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) 662system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) 663system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) 664system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) 665system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) 666system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) 667system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) 668system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) 669system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) |
| 685system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 686system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 687system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 670system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 671system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 688system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) 689system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle 690system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle 691system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle 692system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked 693system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running 694system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking 695system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing 696system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch 697system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction 698system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode 699system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode 700system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing 701system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle 702system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking 703system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst 704system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running 705system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking 706system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename 707system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full 708system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full 709system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full 710system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed 711system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made 712system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups 713system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups 714system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed 715system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing 716system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed 717system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed 718system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer 719system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. 720system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. 721system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. 722system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. 723system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) 724system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ 725system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued 726system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued 727system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling 728system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph 729system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed 730system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle 731system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle 732system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle | 673system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) 674system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle 675system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle 676system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle 677system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked 678system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running 679system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking 680system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing 681system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch 682system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction 683system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode 684system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode 685system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing 686system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle 687system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking 688system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst 689system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running 690system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking 691system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename 692system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full 693system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full 694system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full 695system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed 696system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made 697system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups 698system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups 699system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed 700system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing 701system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed 702system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed 703system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer 704system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. 705system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. 706system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. 707system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. 708system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) 709system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ 710system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued 711system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued 712system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling 713system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph 714system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed 715system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle 716system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle 717system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle |
| 733system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 718system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 734system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle 735system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle 736system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle 737system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle 738system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle 739system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle 740system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle 741system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle 742system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle | 719system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle 720system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle 721system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle 722system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle 723system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle 724system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle 725system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle 726system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle 727system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle |
| 743system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 744system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 745system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 728system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 729system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 746system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle | 731system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle |
| 747system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 732system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 748system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available 749system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available 750system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available 751system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available 752system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available 753system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available 754system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available 755system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available 756system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available 762system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available 763system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available 764system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available 765system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available 766system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available 767system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available 768system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available 769system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available 770system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available 771system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available 772system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available 773system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available 774system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available 775system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available 776system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available 777system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available 778system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available | 733system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available 734system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available 736system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available 737system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available 738system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available 741system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available 742system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available 743system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available 744system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available 745system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available 746system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available 747system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available 748system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available 749system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available 750system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available 751system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available 752system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available 753system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available 754system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available 755system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available 762system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available 763system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available |
| 779system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 780system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 764system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 765system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 781system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued 782system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued 783system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued 784system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued 785system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued 786system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued 787system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued 788system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued 789system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued 790system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued 796system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued 797system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued 798system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued 799system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued 800system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued 801system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued 802system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued 803system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued 804system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued 805system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued 806system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued 807system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued 808system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued 809system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued 810system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued 811system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued 812system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued 813system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued | 766system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued 767system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued 768system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued 769system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued 770system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued 771system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued 772system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.14% # Type of FU issued 773system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.14% # Type of FU issued 774system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.14% # Type of FU issued 775system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.14% # Type of FU issued 776system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.14% # Type of FU issued 777system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.14% # Type of FU issued 778system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.14% # Type of FU issued 779system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.14% # Type of FU issued 780system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.14% # Type of FU issued 781system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.14% # Type of FU issued 782system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.14% # Type of FU issued 783system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.14% # Type of FU issued 784system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.14% # Type of FU issued 785system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.14% # Type of FU issued 786system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.14% # Type of FU issued 787system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.14% # Type of FU issued 788system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.14% # Type of FU issued 789system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.14% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.14% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.14% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued 796system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued 797system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued 798system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued |
| 814system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 799system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 815system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued 816system.cpu0.iq.rate 0.488941 # Inst issue rate 817system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested 818system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) 819system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads 820system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes 821system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses 822system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads 823system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes 824system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses 825system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses 826system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses 827system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores | 800system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued 801system.cpu0.iq.rate 0.500378 # Inst issue rate 802system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested 803system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) 804system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads 805system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes 806system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses 807system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads 808system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes 809system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses 810system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses 811system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses 812system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores |
| 828system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 813system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 829system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed 830system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed 831system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations 832system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed | 814system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed 815system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed 816system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations 817system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed |
| 833system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 834system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 818system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 819system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 835system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled 836system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked | 820system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled 821system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked |
| 837system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 822system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 838system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing 839system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking 840system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking 841system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ 842system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch 843system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions 844system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions 845system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions 846system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall 847system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall 848system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations 849system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly 850system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly 851system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute 852system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions 853system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed 854system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute | 823system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing 824system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking 825system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking 826system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ 827system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch 828system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions 829system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions 830system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions 831system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall 832system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall 833system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations 834system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly 835system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly 836system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute 837system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions 838system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed 839system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute |
| 855system.cpu0.iew.exec_swp 0 # number of swp insts executed | 840system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 856system.cpu0.iew.exec_nop 2697587 # number of nop insts executed 857system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed 858system.cpu0.iew.exec_branches 6879787 # Number of branches executed 859system.cpu0.iew.exec_stores 5059363 # Number of stores executed 860system.cpu0.iew.exec_rate 0.485294 # Inst execution rate 861system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit 862system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back 863system.cpu0.iew.wb_producers 21537449 # num instructions producing a value 864system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value | 841system.cpu0.iew.exec_nop 3200571 # number of nop insts executed 842system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed 843system.cpu0.iew.exec_branches 8058196 # Number of branches executed 844system.cpu0.iew.exec_stores 5766685 # Number of stores executed 845system.cpu0.iew.exec_rate 0.496575 # Inst execution rate 846system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit 847system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back 848system.cpu0.iew.wb_producers 25063994 # num instructions producing a value 849system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value |
| 865system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 850system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 866system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle 867system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back | 851system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle 852system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back |
| 868system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 853system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 869system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit 870system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards 871system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted 872system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle 873system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle 874system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle | 854system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit 855system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards 856system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted 857system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle 858system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle 859system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle |
| 875system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 860system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 876system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle 877system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle 878system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle 879system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle 880system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle 881system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle 882system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle 883system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle 884system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle | 861system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle 862system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle 863system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle 864system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle 865system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle 866system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle 867system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle 868system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle 869system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle |
| 885system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 886system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 887system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 870system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 871system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 888system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle 889system.cpu0.commit.committedInsts 43662606 # Number of instructions committed 890system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed | 873system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle 874system.cpu0.commit.committedInsts 50693798 # Number of instructions committed 875system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed |
| 891system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 876system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 892system.cpu0.commit.refs 11854981 # Number of memory references committed 893system.cpu0.commit.loads 6964106 # Number of loads committed 894system.cpu0.commit.membars 168172 # Number of memory barriers committed 895system.cpu0.commit.branches 6551324 # Number of branches committed 896system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. 897system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. 898system.cpu0.commit.function_calls 540020 # Number of function calls committed. 899system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached | 877system.cpu0.commit.refs 13627446 # Number of memory references committed 878system.cpu0.commit.loads 8065517 # Number of loads committed 879system.cpu0.commit.membars 196376 # Number of memory barriers committed 880system.cpu0.commit.branches 7658577 # Number of branches committed 881system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. 882system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. 883system.cpu0.commit.function_calls 646517 # Number of function calls committed. 884system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached |
| 900system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 885system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 901system.cpu0.rob.rob_reads 110111593 # The number of ROB reads 902system.cpu0.rob.rob_writes 98948174 # The number of ROB writes 903system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself 904system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling 905system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 906system.cpu0.committedInsts 41199881 # Number of Instructions Simulated 907system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated 908system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated 909system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction 910system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads 911system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle 912system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads 913system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads 914system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes 915system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads 916system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes 917system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads 918system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes | 886system.cpu0.rob.rob_reads 129054613 # The number of ROB reads 887system.cpu0.rob.rob_writes 115056832 # The number of ROB writes 888system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself 889system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling 890system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 891system.cpu0.committedInsts 47774945 # Number of Instructions Simulated 892system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated 893system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated 894system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction 895system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads 896system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle 897system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads 898system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads 899system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes 900system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads 901system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes 902system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads 903system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes |
| 919system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 920system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 921system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 922system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 923system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 924system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 925system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 926system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 942system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 943system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 944system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 945system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 946system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 947system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 948system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 949system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 904system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 905system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 906system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 907system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 908system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 909system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 910system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 911system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 927system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 928system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 929system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 930system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 931system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 932system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 933system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 934system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 950system.cpu0.icache.replacements 728874 # number of replacements 951system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use 952system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. 953system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. 954system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. 955system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. 956system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor 957system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy 958system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy 959system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits 960system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits 961system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits 962system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits 963system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits 964system.cpu0.icache.overall_hits::total 5890439 # number of overall hits 965system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses 966system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses 967system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses 968system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses 969system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses 970system.cpu0.icache.overall_misses::total 766860 # number of overall misses 971system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles 972system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles 973system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles 974system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles 975system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles 976system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles 977system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) 978system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) 979system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses 980system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses 981system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses 982system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses 983system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses 984system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses 985system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses 986system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses 987system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses 988system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses 989system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency 990system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency 991system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency 992system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency 993system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency 994system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency 995system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked 996system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked 997system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked 998system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 999system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked 1000system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked | 935system.cpu0.icache.replacements 863258 # number of replacements 936system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use 937system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. 938system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. 939system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. 940system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. 941system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor 942system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy 943system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy 944system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits 945system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits 946system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits 947system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits 948system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits 949system.cpu0.icache.overall_hits::total 6729374 # number of overall hits 950system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses 951system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses 952system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses 953system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses 954system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses 955system.cpu0.icache.overall_misses::total 907848 # number of overall misses 956system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles 957system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles 958system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles 959system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles 960system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles 961system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles 962system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) 963system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) 964system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses 965system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses 966system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses 967system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses 968system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses 969system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses 970system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses 971system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses 972system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses 973system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses 974system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency 975system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency 976system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency 977system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency 978system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency 979system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency 980system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked 981system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 982system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked 983system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 984system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked 985system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1001system.cpu0.icache.fast_writes 0 # number of fast writes performed 1002system.cpu0.icache.cache_copies 0 # number of cache copies performed | 986system.cpu0.icache.fast_writes 0 # number of fast writes performed 987system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1003system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits 1004system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits 1005system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits 1006system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits 1007system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits 1008system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits 1009system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # number of ReadReq MSHR misses 1010system.cpu0.icache.ReadReq_mshr_misses::total 729542 # number of ReadReq MSHR misses 1011system.cpu0.icache.demand_mshr_misses::cpu0.inst 729542 # number of demand (read+write) MSHR misses 1012system.cpu0.icache.demand_mshr_misses::total 729542 # number of demand (read+write) MSHR misses 1013system.cpu0.icache.overall_mshr_misses::cpu0.inst 729542 # number of overall MSHR misses 1014system.cpu0.icache.overall_mshr_misses::total 729542 # number of overall MSHR misses 1015system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8901782997 # number of ReadReq MSHR miss cycles 1016system.cpu0.icache.ReadReq_mshr_miss_latency::total 8901782997 # number of ReadReq MSHR miss cycles 1017system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8901782997 # number of demand (read+write) MSHR miss cycles 1018system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles 1019system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8901782997 # number of overall MSHR miss cycles 1020system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles 1021system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses 1022system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses 1023system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses 1024system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses 1025system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses 1026system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses 1027system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency 1028system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency 1029system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency 1030system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency 1031system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency 1032system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency | 988system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits 989system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits 990system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits 991system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits 992system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits 993system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits 994system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses 995system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses 996system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses 997system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses 998system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses 999system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses 1000system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles 1001system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles 1002system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles 1003system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles 1004system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles 1005system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles 1006system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses 1007system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses 1008system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses 1009system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses 1010system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses 1011system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses 1012system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency 1013system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency 1014system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency 1015system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency 1016system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency 1017system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency |
| 1033system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1018system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1034system.cpu0.dcache.replacements 1051655 # number of replacements 1035system.cpu0.dcache.tagsinuse 479.291529 # Cycle average of tags in use 1036system.cpu0.dcache.total_refs 8945957 # Total number of references to valid blocks. 1037system.cpu0.dcache.sampled_refs 1052167 # Sample count of references to valid blocks. 1038system.cpu0.dcache.avg_refs 8.502412 # Average number of references to valid blocks. | 1019system.cpu0.dcache.replacements 1272639 # number of replacements 1020system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use 1021system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. 1022system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. 1023system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. |
| 1039system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. | 1024system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. |
| 1040system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor 1041system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy 1042system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy 1043system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits 1044system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits 1045system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits 1046system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits 1047system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits 1048system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits 1049system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits 1050system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits 1051system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits 1052system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits 1053system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits 1054system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits 1055system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses 1056system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses 1057system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses 1058system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses 1059system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses 1060system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses 1061system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses 1062system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses 1063system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses 1064system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses 1065system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses 1066system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses 1067system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles 1068system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles 1069system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles 1070system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles 1071system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles 1072system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles 1073system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles 1074system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles 1075system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles 1076system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles 1077system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles 1078system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles 1079system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) 1080system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) 1081system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) 1082system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) 1083system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) 1084system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) 1085system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) 1086system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) 1087system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses 1088system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses 1089system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses 1090system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses 1091system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses 1092system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses 1093system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses 1094system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses 1095system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses 1096system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses 1097system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses 1098system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses 1099system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses 1100system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses 1101system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses 1102system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses 1103system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency 1104system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency 1105system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency 1106system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency 1108system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency 1109system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency 1110system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency 1111system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency 1112system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency 1113system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency 1114system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency 1115system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked 1116system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked 1117system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked | 1025system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor 1026system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy 1027system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy 1028system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits 1029system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits 1030system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits 1031system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits 1032system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits 1033system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits 1034system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits 1035system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits 1036system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits 1037system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits 1038system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits 1039system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits 1040system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses 1041system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses 1042system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses 1043system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses 1044system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses 1045system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses 1046system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses 1047system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses 1048system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses 1049system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses 1050system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses 1051system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses 1052system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles 1053system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles 1054system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles 1055system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles 1056system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles 1057system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles 1058system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles 1059system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles 1060system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles 1061system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles 1062system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles 1063system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles 1064system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) 1065system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) 1066system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) 1067system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) 1068system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) 1069system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) 1070system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) 1071system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) 1072system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses 1073system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses 1074system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses 1075system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses 1076system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses 1077system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses 1078system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses 1079system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses 1080system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses 1081system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses 1082system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses 1083system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses 1084system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses 1085system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses 1086system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses 1087system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses 1088system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency 1089system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency 1090system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency 1091system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency 1092system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency 1093system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency 1094system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency 1095system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency 1096system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency 1097system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency 1098system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency 1099system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency 1100system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked 1101system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked 1102system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked |
| 1118system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked | 1103system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 1119system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked 1120system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked | 1104system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked 1105system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked |
| 1121system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1122system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1106system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1107system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1123system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks 1124system.cpu0.dcache.writebacks::total 554167 # number of writebacks 1125system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits 1126system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits 1127system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits 1128system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits 1129system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits 1130system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits 1131system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits 1132system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits 1133system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits 1134system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits 1135system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses 1136system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses 1137system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses 1138system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses 1139system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses 1140system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses 1141system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses 1142system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses 1143system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses 1144system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses 1145system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses 1146system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses 1147system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles 1148system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles 1149system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles 1150system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles 1151system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles 1152system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles 1153system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles 1154system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles 1155system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles 1157system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles 1158system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles 1159system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles 1161system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles 1163system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles 1164system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles 1165system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses 1166system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses 1167system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses 1168system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses 1169system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses 1170system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses 1171system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses 1172system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses 1173system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses 1174system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses 1175system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses 1176system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses 1177system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency 1178system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency 1179system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency 1180system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency 1181system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency 1182system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency 1183system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency 1184system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency 1185system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency 1186system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency 1187system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency 1188system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency | 1108system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks 1109system.cpu0.dcache.writebacks::total 748565 # number of writebacks 1110system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits 1111system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits 1112system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits 1113system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits 1114system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits 1115system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits 1116system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits 1117system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits 1118system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits 1119system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits 1120system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses 1121system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses 1122system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses 1123system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses 1124system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses 1125system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses 1126system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses 1127system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses 1128system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses 1129system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses 1130system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses 1131system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses 1132system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles 1133system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles 1134system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles 1135system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles 1136system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles 1137system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles 1138system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles 1139system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles 1140system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles 1143system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles 1144system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles 1145system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles 1146system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles 1147system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles 1148system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles 1149system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles 1150system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses 1151system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses 1152system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses 1153system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses 1154system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses 1155system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses 1156system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses 1157system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses 1158system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses 1159system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses 1160system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses 1161system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses 1162system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency 1163system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency 1164system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency 1165system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency 1166system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency 1167system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency 1168system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency 1169system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency 1170system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency 1171system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency 1172system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency 1173system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency |
| 1189system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1190system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1191system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1192system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1193system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1194system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1195system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1174system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1175system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1176system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1177system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1178system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1179system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1180system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1196system.cpu1.branchPred.lookups 4327546 # Number of BP lookups 1197system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted 1198system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect 1199system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups 1200system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits | 1181system.cpu1.branchPred.lookups 2650086 # Number of BP lookups 1182system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted 1183system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect 1184system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups 1185system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits |
| 1201system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1186system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1202system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage 1203system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. 1204system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. | 1187system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage 1188system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. 1189system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. |
| 1205system.cpu1.dtb.fetch_hits 0 # ITB hits 1206system.cpu1.dtb.fetch_misses 0 # ITB misses 1207system.cpu1.dtb.fetch_acv 0 # ITB acv 1208system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1190system.cpu1.dtb.fetch_hits 0 # ITB hits 1191system.cpu1.dtb.fetch_misses 0 # ITB misses 1192system.cpu1.dtb.fetch_acv 0 # ITB acv 1193system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1209system.cpu1.dtb.read_hits 3068448 # DTB read hits 1210system.cpu1.dtb.read_misses 13337 # DTB read misses 1211system.cpu1.dtb.read_acv 21 # DTB read access violations 1212system.cpu1.dtb.read_accesses 325420 # DTB read accesses 1213system.cpu1.dtb.write_hits 1915630 # DTB write hits 1214system.cpu1.dtb.write_misses 2521 # DTB write misses 1215system.cpu1.dtb.write_acv 68 # DTB write access violations 1216system.cpu1.dtb.write_accesses 132592 # DTB write accesses 1217system.cpu1.dtb.data_hits 4984078 # DTB hits 1218system.cpu1.dtb.data_misses 15858 # DTB misses 1219system.cpu1.dtb.data_acv 89 # DTB access violations 1220system.cpu1.dtb.data_accesses 458012 # DTB accesses 1221system.cpu1.itb.fetch_hits 498592 # ITB hits 1222system.cpu1.itb.fetch_misses 6957 # ITB misses 1223system.cpu1.itb.fetch_acv 210 # ITB acv 1224system.cpu1.itb.fetch_accesses 505549 # ITB accesses | 1194system.cpu1.dtb.read_hits 1963408 # DTB read hits 1195system.cpu1.dtb.read_misses 10761 # DTB read misses 1196system.cpu1.dtb.read_acv 27 # DTB read access violations 1197system.cpu1.dtb.read_accesses 325022 # DTB read accesses 1198system.cpu1.dtb.write_hits 1266270 # DTB write hits 1199system.cpu1.dtb.write_misses 2185 # DTB write misses 1200system.cpu1.dtb.write_acv 66 # DTB write access violations 1201system.cpu1.dtb.write_accesses 133146 # DTB write accesses 1202system.cpu1.dtb.data_hits 3229678 # DTB hits 1203system.cpu1.dtb.data_misses 12946 # DTB misses 1204system.cpu1.dtb.data_acv 93 # DTB access violations 1205system.cpu1.dtb.data_accesses 458168 # DTB accesses 1206system.cpu1.itb.fetch_hits 437746 # ITB hits 1207system.cpu1.itb.fetch_misses 6892 # ITB misses 1208system.cpu1.itb.fetch_acv 236 # ITB acv 1209system.cpu1.itb.fetch_accesses 444638 # ITB accesses |
| 1225system.cpu1.itb.read_hits 0 # DTB read hits 1226system.cpu1.itb.read_misses 0 # DTB read misses 1227system.cpu1.itb.read_acv 0 # DTB read access violations 1228system.cpu1.itb.read_accesses 0 # DTB read accesses 1229system.cpu1.itb.write_hits 0 # DTB write hits 1230system.cpu1.itb.write_misses 0 # DTB write misses 1231system.cpu1.itb.write_acv 0 # DTB write access violations 1232system.cpu1.itb.write_accesses 0 # DTB write accesses 1233system.cpu1.itb.data_hits 0 # DTB hits 1234system.cpu1.itb.data_misses 0 # DTB misses 1235system.cpu1.itb.data_acv 0 # DTB access violations 1236system.cpu1.itb.data_accesses 0 # DTB accesses | 1210system.cpu1.itb.read_hits 0 # DTB read hits 1211system.cpu1.itb.read_misses 0 # DTB read misses 1212system.cpu1.itb.read_acv 0 # DTB read access violations 1213system.cpu1.itb.read_accesses 0 # DTB read accesses 1214system.cpu1.itb.write_hits 0 # DTB write hits 1215system.cpu1.itb.write_misses 0 # DTB write misses 1216system.cpu1.itb.write_acv 0 # DTB write access violations 1217system.cpu1.itb.write_accesses 0 # DTB write accesses 1218system.cpu1.itb.data_hits 0 # DTB hits 1219system.cpu1.itb.data_misses 0 # DTB misses 1220system.cpu1.itb.data_acv 0 # DTB access violations 1221system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1237system.cpu1.numCycles 28341850 # number of cpu cycles simulated | 1222system.cpu1.numCycles 16144974 # number of cpu cycles simulated |
| 1238system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1239system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1223system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1224system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1240system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss 1241system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed 1242system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered 1243system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken 1244system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked 1245system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing 1246system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked 1247system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1248system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps 1249system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions 1250system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR 1251system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched 1252system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed 1253system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) | 1225system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss 1226system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed 1227system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered 1228system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken 1229system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked 1230system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing 1231system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked 1232system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1233system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps 1234system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions 1235system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 1236system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched 1237system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed 1238system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) 1239system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) 1240system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) |
| 1256system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1241system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1257system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) 1259system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) 1260system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) 1264system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) | 1242system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) 1243system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) 1244system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) 1245system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) 1246system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) 1247system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) 1248system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) 1249system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) 1250system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) |
| 1266system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1267system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1268system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1251system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1269system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) 1270system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle 1271system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle 1272system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle 1273system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked 1274system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running 1275system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking 1276system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing 1277system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch 1278system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction 1279system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode 1280system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode 1281system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing 1282system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle 1283system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking 1284system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst 1285system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running 1286system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking 1287system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename 1288system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full 1289system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full 1290system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full 1291system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed 1292system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made 1293system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups 1294system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups 1295system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed 1296system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing 1297system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed 1298system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed 1299system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer 1300system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. 1301system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. 1302system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. 1303system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. 1304system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) 1305system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ 1306system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued 1307system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued 1308system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling 1309system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph 1310system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed 1311system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle 1312system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle 1313system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle | 1254system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) 1255system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle 1256system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle 1257system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle 1258system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked 1259system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running 1260system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking 1261system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing 1262system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch 1263system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction 1264system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode 1265system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode 1266system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing 1267system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle 1268system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking 1269system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst 1270system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running 1271system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking 1272system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename 1273system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full 1274system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full 1275system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full 1276system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed 1277system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made 1278system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups 1279system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups 1280system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed 1281system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing 1282system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed 1283system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed 1284system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer 1285system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. 1286system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. 1287system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. 1288system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. 1289system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) 1290system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ 1291system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued 1292system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued 1293system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling 1294system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph 1295system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed 1296system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle 1297system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle 1298system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle |
| 1314system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1299system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1315system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle 1316system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle 1317system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle 1318system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle 1319system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle 1320system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle 1321system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle 1322system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle 1323system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle | 1300system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle 1301system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle 1302system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle 1303system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle 1304system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle 1305system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle 1306system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle 1307system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle 1308system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle |
| 1324system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1325system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1326system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1309system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1327system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle | 1312system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle |
| 1328system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1313system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1329system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available 1347system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available 1348system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available 1349system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available 1350system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available 1351system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available 1352system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available 1353system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available 1354system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available 1358system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available | 1314system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available 1315system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available 1316system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available 1317system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available 1318system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available 1319system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available 1320system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available 1321system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available 1322system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 1323system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available 1324system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available 1325system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available 1326system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available 1327system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available |
| 1360system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1361system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1345system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1362system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued 1363system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued 1364system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued 1365system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued 1366system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued 1367system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued 1368system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued 1369system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued 1370system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued 1371system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued 1377system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued 1378system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued 1379system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued 1380system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued 1381system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued 1382system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued 1383system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued 1384system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued 1385system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued 1386system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued 1387system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued 1388system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued 1389system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued 1390system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued 1391system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued 1392system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued 1393system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued 1394system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued | 1347system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued 1348system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued 1349system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued 1350system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued 1351system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued 1352system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued 1353system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued 1354system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued 1355system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued 1356system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued 1357system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued 1358system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued 1359system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued 1360system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued 1361system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued 1362system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued 1363system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued 1364system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued 1365system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued 1366system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued 1367system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued 1368system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued 1369system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued 1377system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued 1378system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued 1379system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued |
| 1395system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1380system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1396system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued 1397system.cpu1.iq.rate 0.572889 # Inst issue rate 1398system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested 1399system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) 1400system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads 1401system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes 1402system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses 1403system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads 1404system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes 1405system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses 1406system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses 1407system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses 1408system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores | 1381system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued 1382system.cpu1.iq.rate 0.600865 # Inst issue rate 1383system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested 1384system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) 1385system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads 1386system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes 1387system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses 1388system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads 1389system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes 1390system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses 1391system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses 1392system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses 1393system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores |
| 1409system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1394system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1410system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed 1411system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed 1412system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations 1413system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed | 1395system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed 1396system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed 1397system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations 1398system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed |
| 1414system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1415system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1399system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1400system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1416system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled 1417system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked | 1401system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled 1402system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked |
| 1418system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1403system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1419system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing 1420system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking 1421system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking 1422system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ 1423system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch 1424system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions 1425system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions 1426system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions 1427system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall 1428system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall 1429system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations 1430system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly 1431system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly 1432system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute 1433system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions 1434system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed 1435system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute | 1404system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing 1405system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking 1406system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking 1407system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ 1408system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch 1409system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions 1410system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions 1411system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions 1412system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall 1413system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall 1414system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations 1415system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly 1416system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly 1417system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute 1418system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions 1419system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed 1420system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute |
| 1436system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1421system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1437system.cpu1.iew.exec_nop 989430 # number of nop insts executed 1438system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed 1439system.cpu1.iew.exec_branches 2535241 # Number of branches executed 1440system.cpu1.iew.exec_stores 1924592 # Number of stores executed 1441system.cpu1.iew.exec_rate 0.567378 # Inst execution rate 1442system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit 1443system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back 1444system.cpu1.iew.wb_producers 7724743 # num instructions producing a value 1445system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value | 1422system.cpu1.iew.exec_nop 515192 # number of nop insts executed 1423system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed 1424system.cpu1.iew.exec_branches 1435370 # Number of branches executed 1425system.cpu1.iew.exec_stores 1274468 # Number of stores executed 1426system.cpu1.iew.exec_rate 0.595272 # Inst execution rate 1427system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit 1428system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back 1429system.cpu1.iew.wb_producers 4461159 # num instructions producing a value 1430system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value |
| 1446system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1431system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1447system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle 1448system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back | 1432system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle 1433system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back |
| 1449system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1434system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1450system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit 1451system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards 1452system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted 1453system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle 1454system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle 1455system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle | 1435system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit 1436system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards 1437system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted 1438system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle 1439system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle 1440system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle |
| 1456system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1441system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1457system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle 1458system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle 1459system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle 1460system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle 1461system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle 1462system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle 1463system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle 1464system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle 1465system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle | 1442system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle 1443system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle 1444system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle 1445system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle 1446system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle 1447system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle 1448system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle 1449system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle 1450system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle |
| 1466system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1467system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1468system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1451system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1469system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle 1470system.cpu1.commit.committedInsts 15801951 # Number of instructions committed 1471system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed | 1454system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle 1455system.cpu1.commit.committedInsts 9413351 # Number of instructions committed 1456system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed |
| 1472system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1457system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1473system.cpu1.commit.refs 4623326 # Number of memory references committed 1474system.cpu1.commit.loads 2789628 # Number of loads committed 1475system.cpu1.commit.membars 68640 # Number of memory barriers committed 1476system.cpu1.commit.branches 2366242 # Number of branches committed 1477system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. 1478system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. 1479system.cpu1.commit.function_calls 250839 # Number of function calls committed. 1480system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached | 1458system.cpu1.commit.refs 3003807 # Number of memory references committed 1459system.cpu1.commit.loads 1788957 # Number of loads committed 1460system.cpu1.commit.membars 45075 # Number of memory barriers committed 1461system.cpu1.commit.branches 1347256 # Number of branches committed 1462system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. 1463system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. 1464system.cpu1.commit.function_calls 150668 # Number of function calls committed. 1465system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached |
| 1481system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1466system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1482system.cpu1.rob.rob_reads 42991260 # The number of ROB reads 1483system.cpu1.rob.rob_writes 37176651 # The number of ROB writes 1484system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself 1485system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling 1486system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1487system.cpu1.committedInsts 14927555 # Number of Instructions Simulated 1488system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated 1489system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated 1490system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction 1491system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads 1492system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle 1493system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads 1494system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads 1495system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes 1496system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads 1497system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes 1498system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads 1499system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes 1500system.cpu1.icache.replacements 359909 # number of replacements 1501system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use 1502system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. 1503system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. 1504system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. 1505system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. 1506system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor 1507system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy 1508system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy 1509system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits 1510system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits 1511system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits 1512system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits 1513system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits 1514system.cpu1.icache.overall_hits::total 2054105 # number of overall hits 1515system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses 1516system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses 1517system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses 1518system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses 1519system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses 1520system.cpu1.icache.overall_misses::total 376623 # number of overall misses 1521system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles 1522system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles 1523system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles 1524system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles 1525system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles 1526system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles 1527system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) 1528system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) 1529system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses 1530system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses 1531system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses 1532system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses 1533system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses 1534system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses 1535system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses 1536system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses 1537system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses 1538system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses 1539system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency 1540system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency 1541system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency 1542system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency 1543system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency 1544system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency 1545system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked 1546system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked 1547system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked 1548system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 1549system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked 1550system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked | 1467system.cpu1.rob.rob_reads 25388124 # The number of ROB reads 1468system.cpu1.rob.rob_writes 22088528 # The number of ROB writes 1469system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself 1470system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling 1471system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1472system.cpu1.committedInsts 8958605 # Number of Instructions Simulated 1473system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated 1474system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated 1475system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction 1476system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads 1477system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle 1478system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads 1479system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads 1480system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes 1481system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads 1482system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes 1483system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads 1484system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes 1485system.cpu1.icache.replacements 226821 # number of replacements 1486system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use 1487system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. 1488system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. 1489system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. 1490system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. 1491system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor 1492system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy 1493system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy 1494system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits 1495system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits 1496system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits 1497system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits 1498system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits 1499system.cpu1.icache.overall_hits::total 1277714 # number of overall hits 1500system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses 1501system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses 1502system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses 1503system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses 1504system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses 1505system.cpu1.icache.overall_misses::total 235963 # number of overall misses 1506system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles 1507system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles 1508system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles 1509system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles 1510system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles 1511system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles 1512system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) 1513system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) 1514system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses 1515system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses 1516system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses 1517system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses 1518system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses 1519system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses 1520system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses 1521system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses 1522system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses 1523system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses 1524system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency 1525system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency 1526system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency 1527system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency 1528system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency 1529system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency 1530system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked 1531system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1532system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked 1533system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1534system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked 1535system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1551system.cpu1.icache.fast_writes 0 # number of fast writes performed 1552system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1536system.cpu1.icache.fast_writes 0 # number of fast writes performed 1537system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1553system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits 1554system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits 1555system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits 1556system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits 1557system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits 1558system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits 1559system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses 1560system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses 1561system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses 1562system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses 1563system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses 1564system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses 1565system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles 1566system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles 1567system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles 1568system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles 1569system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles 1570system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles 1571system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses 1572system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses 1573system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses 1574system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses 1575system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses 1576system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses 1577system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency 1578system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency 1579system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency 1580system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency 1581system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency 1582system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency | 1538system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits 1539system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits 1540system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits 1541system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits 1542system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits 1543system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits 1544system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227395 # number of ReadReq MSHR misses 1545system.cpu1.icache.ReadReq_mshr_misses::total 227395 # number of ReadReq MSHR misses 1546system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses 1547system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses 1548system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses 1549system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses 1550system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles 1551system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles 1552system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles 1553system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles 1554system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles 1555system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles 1556system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses 1558system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses 1559system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses 1560system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses 1561system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency 1563system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency 1564system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency 1565system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency 1566system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency 1567system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency |
| 1583system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1568system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1584system.cpu1.dcache.replacements 377681 # number of replacements 1585system.cpu1.dcache.tagsinuse 497.778191 # Cycle average of tags in use 1586system.cpu1.dcache.total_refs 3769592 # Total number of references to valid blocks. 1587system.cpu1.dcache.sampled_refs 378084 # Sample count of references to valid blocks. 1588system.cpu1.dcache.avg_refs 9.970250 # Average number of references to valid blocks. 1589system.cpu1.dcache.warmup_cycle 35370260000 # Cycle when the warmup percentage was hit. 1590system.cpu1.dcache.occ_blocks::cpu1.data 497.778191 # Average occupied blocks per requestor 1591system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy 1592system.cpu1.dcache.occ_percent::total 0.972223 # Average percentage of cache occupancy 1593system.cpu1.dcache.ReadReq_hits::cpu1.data 2307913 # number of ReadReq hits 1594system.cpu1.dcache.ReadReq_hits::total 2307913 # number of ReadReq hits 1595system.cpu1.dcache.WriteReq_hits::cpu1.data 1365825 # number of WriteReq hits 1596system.cpu1.dcache.WriteReq_hits::total 1365825 # number of WriteReq hits 1597system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47088 # number of LoadLockedReq hits 1598system.cpu1.dcache.LoadLockedReq_hits::total 47088 # number of LoadLockedReq hits 1599system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50932 # number of StoreCondReq hits 1600system.cpu1.dcache.StoreCondReq_hits::total 50932 # number of StoreCondReq hits 1601system.cpu1.dcache.demand_hits::cpu1.data 3673738 # number of demand (read+write) hits 1602system.cpu1.dcache.demand_hits::total 3673738 # number of demand (read+write) hits 1603system.cpu1.dcache.overall_hits::cpu1.data 3673738 # number of overall hits 1604system.cpu1.dcache.overall_hits::total 3673738 # number of overall hits 1605system.cpu1.dcache.ReadReq_misses::cpu1.data 542018 # number of ReadReq misses 1606system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses 1607system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses 1608system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses 1609system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses 1610system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses 1611system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses 1612system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses 1613system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses 1614system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses 1615system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses 1616system.cpu1.dcache.overall_misses::total 950793 # number of overall misses 1617system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # number of ReadReq miss cycles 1618system.cpu1.dcache.ReadReq_miss_latency::total 8456828000 # number of ReadReq miss cycles 1619system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13523509258 # number of WriteReq miss cycles 1620system.cpu1.dcache.WriteReq_miss_latency::total 13523509258 # number of WriteReq miss cycles 1621system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132387000 # number of LoadLockedReq miss cycles 1622system.cpu1.dcache.LoadLockedReq_miss_latency::total 132387000 # number of LoadLockedReq miss cycles 1623system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5554000 # number of StoreCondReq miss cycles 1624system.cpu1.dcache.StoreCondReq_miss_latency::total 5554000 # number of StoreCondReq miss cycles 1625system.cpu1.dcache.demand_miss_latency::cpu1.data 21980337258 # number of demand (read+write) miss cycles 1626system.cpu1.dcache.demand_miss_latency::total 21980337258 # number of demand (read+write) miss cycles 1627system.cpu1.dcache.overall_miss_latency::cpu1.data 21980337258 # number of overall miss cycles 1628system.cpu1.dcache.overall_miss_latency::total 21980337258 # number of overall miss cycles 1629system.cpu1.dcache.ReadReq_accesses::cpu1.data 2849931 # number of ReadReq accesses(hits+misses) 1630system.cpu1.dcache.ReadReq_accesses::total 2849931 # number of ReadReq accesses(hits+misses) 1631system.cpu1.dcache.WriteReq_accesses::cpu1.data 1774600 # number of WriteReq accesses(hits+misses) 1632system.cpu1.dcache.WriteReq_accesses::total 1774600 # number of WriteReq accesses(hits+misses) 1633system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56190 # number of LoadLockedReq accesses(hits+misses) 1634system.cpu1.dcache.LoadLockedReq_accesses::total 56190 # number of LoadLockedReq accesses(hits+misses) 1635system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 51712 # number of StoreCondReq accesses(hits+misses) 1636system.cpu1.dcache.StoreCondReq_accesses::total 51712 # number of StoreCondReq accesses(hits+misses) 1637system.cpu1.dcache.demand_accesses::cpu1.data 4624531 # number of demand (read+write) accesses 1638system.cpu1.dcache.demand_accesses::total 4624531 # number of demand (read+write) accesses 1639system.cpu1.dcache.overall_accesses::cpu1.data 4624531 # number of overall (read+write) accesses 1640system.cpu1.dcache.overall_accesses::total 4624531 # number of overall (read+write) accesses 1641system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.190186 # miss rate for ReadReq accesses 1642system.cpu1.dcache.ReadReq_miss_rate::total 0.190186 # miss rate for ReadReq accesses 1643system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.230348 # miss rate for WriteReq accesses 1644system.cpu1.dcache.WriteReq_miss_rate::total 0.230348 # miss rate for WriteReq accesses 1645system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.161986 # miss rate for LoadLockedReq accesses 1646system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.161986 # miss rate for LoadLockedReq accesses 1647system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015084 # miss rate for StoreCondReq accesses 1648system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015084 # miss rate for StoreCondReq accesses 1649system.cpu1.dcache.demand_miss_rate::cpu1.data 0.205598 # miss rate for demand accesses 1650system.cpu1.dcache.demand_miss_rate::total 0.205598 # miss rate for demand accesses 1651system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses 1652system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses 1653system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency 1654system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency 1655system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency 1656system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency 1657system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency 1658system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency 1659system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency 1660system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # average StoreCondReq miss latency 1661system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency 1662system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751 # average overall miss latency 1663system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency 1664system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751 # average overall miss latency 1665system.cpu1.dcache.blocked_cycles::no_mshrs 393760 # number of cycles access was blocked | 1569system.cpu1.dcache.replacements 108831 # number of replacements 1570system.cpu1.dcache.tagsinuse 491.507176 # Cycle average of tags in use 1571system.cpu1.dcache.total_refs 2642897 # Total number of references to valid blocks. 1572system.cpu1.dcache.sampled_refs 109233 # Sample count of references to valid blocks. 1573system.cpu1.dcache.avg_refs 24.195042 # Average number of references to valid blocks. 1574system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. 1575system.cpu1.dcache.occ_blocks::cpu1.data 491.507176 # Average occupied blocks per requestor 1576system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # Average percentage of cache occupancy 1577system.cpu1.dcache.occ_percent::total 0.959975 # Average percentage of cache occupancy 1578system.cpu1.dcache.ReadReq_hits::cpu1.data 1619180 # number of ReadReq hits 1579system.cpu1.dcache.ReadReq_hits::total 1619180 # number of ReadReq hits 1580system.cpu1.dcache.WriteReq_hits::cpu1.data 952866 # number of WriteReq hits 1581system.cpu1.dcache.WriteReq_hits::total 952866 # number of WriteReq hits 1582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33989 # number of LoadLockedReq hits 1583system.cpu1.dcache.LoadLockedReq_hits::total 33989 # number of LoadLockedReq hits 1584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32614 # number of StoreCondReq hits 1585system.cpu1.dcache.StoreCondReq_hits::total 32614 # number of StoreCondReq hits 1586system.cpu1.dcache.demand_hits::cpu1.data 2572046 # number of demand (read+write) hits 1587system.cpu1.dcache.demand_hits::total 2572046 # number of demand (read+write) hits 1588system.cpu1.dcache.overall_hits::cpu1.data 2572046 # number of overall hits 1589system.cpu1.dcache.overall_hits::total 2572046 # number of overall hits 1590system.cpu1.dcache.ReadReq_misses::cpu1.data 209251 # number of ReadReq misses 1591system.cpu1.dcache.ReadReq_misses::total 209251 # number of ReadReq misses 1592system.cpu1.dcache.WriteReq_misses::cpu1.data 220110 # number of WriteReq misses 1593system.cpu1.dcache.WriteReq_misses::total 220110 # number of WriteReq misses 1594system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5396 # number of LoadLockedReq misses 1595system.cpu1.dcache.LoadLockedReq_misses::total 5396 # number of LoadLockedReq misses 1596system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3146 # number of StoreCondReq misses 1597system.cpu1.dcache.StoreCondReq_misses::total 3146 # number of StoreCondReq misses 1598system.cpu1.dcache.demand_misses::cpu1.data 429361 # number of demand (read+write) misses 1599system.cpu1.dcache.demand_misses::total 429361 # number of demand (read+write) misses 1600system.cpu1.dcache.overall_misses::cpu1.data 429361 # number of overall misses 1601system.cpu1.dcache.overall_misses::total 429361 # number of overall misses 1602system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3173212000 # number of ReadReq miss cycles 1603system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles 1604system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles 1605system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles 1606system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles 1607system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles 1608system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles 1609system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles 1610system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles 1611system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles 1612system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles 1613system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles 1614system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) 1615system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) 1616system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) 1617system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) 1618system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) 1619system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) 1620system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) 1621system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) 1622system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses 1623system.cpu1.dcache.demand_accesses::total 3001407 # number of demand (read+write) accesses 1624system.cpu1.dcache.overall_accesses::cpu1.data 3001407 # number of overall (read+write) accesses 1625system.cpu1.dcache.overall_accesses::total 3001407 # number of overall (read+write) accesses 1626system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114443 # miss rate for ReadReq accesses 1627system.cpu1.dcache.ReadReq_miss_rate::total 0.114443 # miss rate for ReadReq accesses 1628system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187651 # miss rate for WriteReq accesses 1629system.cpu1.dcache.WriteReq_miss_rate::total 0.187651 # miss rate for WriteReq accesses 1630system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137006 # miss rate for LoadLockedReq accesses 1631system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137006 # miss rate for LoadLockedReq accesses 1632system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087975 # miss rate for StoreCondReq accesses 1633system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087975 # miss rate for StoreCondReq accesses 1634system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143053 # miss rate for demand accesses 1635system.cpu1.dcache.demand_miss_rate::total 0.143053 # miss rate for demand accesses 1636system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses 1637system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses 1638system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency 1639system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency 1640system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency 1641system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency 1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency 1643system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency 1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency 1645system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency 1646system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency 1647system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency 1648system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency 1649system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency 1650system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked |
| 1666system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1651system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1667system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked | 1652system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked |
| 1668system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1653system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1669system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked | 1654system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked |
| 1670system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1671system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1672system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1655system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1656system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1657system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1673system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks 1674system.cpu1.dcache.writebacks::total 289966 # number of writebacks 1675system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits 1676system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits 1677system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits 1678system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits 1679system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits 1680system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits 1681system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits 1682system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits 1683system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits 1684system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits 1685system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses 1686system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses 1687system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses 1688system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses 1689system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses 1690system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses 1691system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses 1692system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses 1693system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses 1694system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses 1695system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses 1696system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses 1697system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles 1698system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles 1699system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles 1700system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles 1701system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles 1702system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles 1703system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles 1704system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles 1705system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles 1706system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles 1707system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles 1708system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles 1709system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles 1710system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles 1711system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles 1712system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles 1713system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles 1714system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles 1715system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses 1716system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses 1717system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses 1718system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses 1719system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses 1720system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses 1721system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses 1722system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses 1723system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses 1724system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses 1725system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses 1726system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses 1727system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency 1728system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency 1729system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency 1730system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency 1731system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency 1732system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency 1733system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency 1734system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency 1735system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency 1736system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency 1737system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency 1738system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency | 1658system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks 1659system.cpu1.dcache.writebacks::total 72108 # number of writebacks 1660system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits 1661system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits 1662system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits 1663system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits 1664system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits 1665system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits 1666system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits 1667system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits 1668system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits 1669system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits 1670system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses 1672system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses 1673system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses 1674system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses 1675system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses 1676system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses 1677system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses 1678system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses 1679system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses 1680system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses 1681system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles 1684system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles 1685system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles 1691system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles 1692system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles 1693system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles 1694system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles 1695system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles 1696system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles 1697system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles 1698system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles 1699system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles 1700system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses 1701system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses 1702system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses 1703system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses 1704system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses 1705system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses 1707system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses 1708system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses 1709system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses 1710system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses 1711system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses 1712system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency 1713system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency 1714system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency 1715system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency 1716system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency 1717system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency 1718system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency 1719system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency 1720system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency 1721system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency 1722system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency 1723system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency |
| 1739system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1740system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1741system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1742system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1743system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1744system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1745system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1746system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1724system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1725system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1727system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1729system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1731system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1747system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed 1748system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed 1749system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl 1750system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl 1751system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl 1752system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl 1753system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl 1754system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl 1755system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl 1756system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl 1757system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl 1758system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl 1759system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl 1760system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl 1761system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl 1762system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl 1763system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl 1764system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl 1765system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl 1766system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl 1767system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl | 1732system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed 1733system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed 1734system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl 1735system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl 1736system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl 1737system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl 1738system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl 1739system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl 1740system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl 1741system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl 1742system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl 1743system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl 1744system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl 1745system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl 1746system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl 1747system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl 1748system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl 1749system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl 1750system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl 1751system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl 1752system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl |
| 1768system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1769system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1770system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1753system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1754system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1755system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1771system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl 1772system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl | 1756system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl 1757system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl |
| 1773system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 1774system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 1775system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 1776system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 1777system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 1778system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 1779system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 1780system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 1796system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed 1797system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed 1798system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed 1799system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed 1800system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 1801system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 1802system.cpu0.kern.syscall::total 202 # number of syscalls executed 1803system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1758system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 1759system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 1760system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 1761system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 1762system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 1763system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 1764system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 1765system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 1781system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed 1782system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed 1783system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed 1784system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed 1785system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 1786system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 1787system.cpu0.kern.syscall::total 202 # number of syscalls executed 1788system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1804system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed 1805system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed 1806system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed 1807system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed 1808system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed 1809system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed 1810system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed 1811system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed 1812system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed 1813system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed 1814system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed 1815system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed 1816system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed 1817system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed 1818system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed 1819system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed 1820system.cpu0.kern.callpal::total 144957 # number of callpals executed 1821system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches | 1789system.cpu0.kern.callpal::wripir 297 0.18% 0.18% # number of callpals executed 1790system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed 1791system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 1792system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 1793system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed 1794system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed 1795system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed 1796system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed 1797system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed 1798system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed 1799system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed 1800system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed 1801system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed 1802system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed 1803system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed 1804system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed 1805system.cpu0.kern.callpal::total 166884 # number of callpals executed 1806system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches |
| 1822system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches 1823system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1824system.cpu0.kern.mode_good::kernel 1257 1825system.cpu0.kern.mode_good::user 1258 1826system.cpu0.kern.mode_good::idle 0 | 1807system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches 1808system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1809system.cpu0.kern.mode_good::kernel 1257 1810system.cpu0.kern.mode_good::user 1258 1811system.cpu0.kern.mode_good::idle 0 |
| 1827system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches | 1812system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches |
| 1828system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1829system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 1813system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1814system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 1830system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches 1831system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode 1832system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode | 1815system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches 1816system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode 1817system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode |
| 1833system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 1818system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 1834system.cpu0.kern.swap_context 2839 # number of times the context was actually changed | 1819system.cpu0.kern.swap_context 3470 # number of times the context was actually changed |
| 1835system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1820system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1836system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed 1837system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed 1838system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl 1839system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl 1840system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl 1841system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl 1842system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl 1843system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl 1844system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl 1845system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl 1846system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl 1847system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl 1848system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl 1849system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl 1850system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl 1851system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl 1852system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl 1853system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl | 1821system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed 1822system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed 1823system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl 1824system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl 1825system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl 1826system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl 1827system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl 1828system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl 1829system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl 1830system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl 1831system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl 1832system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl 1833system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl 1834system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl 1835system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl 1836system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl 1837system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl 1838system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl |
| 1854system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1855system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1839system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1840system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1856system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl 1857system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl | 1841system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl 1842system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl |
| 1858system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 1859system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 1860system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed 1861system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed 1862system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed 1863system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed 1864system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed 1865system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed --- 7 unchanged lines hidden (view full) --- 1873system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed 1874system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed 1875system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed 1876system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed 1877system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed 1878system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed 1879system.cpu1.kern.syscall::total 124 # number of syscalls executed 1880system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1843system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 1844system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 1845system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed 1846system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed 1847system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed 1848system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed 1849system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed 1850system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed --- 7 unchanged lines hidden (view full) --- 1858system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed 1859system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed 1860system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed 1861system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed 1862system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed 1863system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed 1864system.cpu1.kern.syscall::total 124 # number of syscalls executed 1865system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1881system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed 1882system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1883system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 1884system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed 1885system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed 1886system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed 1887system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed 1888system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed 1889system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed 1890system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed 1891system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed 1892system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed 1893system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed 1894system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed 1895system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed | 1866system.cpu1.kern.callpal::wripir 194 0.38% 0.38% # number of callpals executed 1867system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed 1868system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed 1869system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed 1870system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed 1871system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed 1872system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed 1873system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed 1874system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed 1875system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed 1876system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed 1877system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed 1878system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed 1879system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed 1880system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed |
| 1896system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1881system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1897system.cpu1.kern.callpal::total 71331 # number of callpals executed 1898system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches | 1882system.cpu1.kern.callpal::total 51275 # number of callpals executed 1883system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches |
| 1899system.cpu1.kern.mode_switch::user 488 # number of protection mode switches | 1884system.cpu1.kern.mode_switch::user 488 # number of protection mode switches |
| 1900system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches 1901system.cpu1.kern.mode_good::kernel 557 | 1885system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches 1886system.cpu1.kern.mode_good::kernel 709 |
| 1902system.cpu1.kern.mode_good::user 488 | 1887system.cpu1.kern.mode_good::user 488 |
| 1903system.cpu1.kern.mode_good::idle 69 1904system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches | 1888system.cpu1.kern.mode_good::idle 221 1889system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches |
| 1905system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1906system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches 1907system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches 1908system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode 1909system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode 1910system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode 1911system.cpu1.kern.swap_context 1408 # number of times the context was actually changed | 1891system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches 1892system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches 1893system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode 1894system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode 1895system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode 1896system.cpu1.kern.swap_context 1141 # number of times the context was actually changed |
| 1912 1913---------- End Simulation Statistics ---------- | 1897 1898---------- End Simulation Statistics ---------- |