| stats.txt (9449:56610ab73040) | stats.txt (9459:8ca90cef0183) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.897858 # Number of seconds simulated 4sim_ticks 1897857556000 # Number of ticks simulated 5final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.901720 # Number of seconds simulated 4sim_ticks 1901719660500 # Number of ticks simulated 5final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 54087 # Simulator instruction rate (inst/s) 8host_op_rate 54087 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1829896991 # Simulator tick rate (ticks/s) 10host_mem_usage 335972 # Number of bytes of host memory used 11host_seconds 1037.14 # Real time elapsed on the host 12sim_insts 56096024 # Number of instructions simulated 13sim_ops 56096024 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 450802 # Total number of read requests seen 52system.physmem.writeReqs 121968 # Total number of write requests seen 53system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28851328 # Total number of bytes read from memory 55system.physmem.bytesWritten 7805952 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis | 7host_inst_rate 128809 # Simulator instruction rate (inst/s) 8host_op_rate 128809 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4317556960 # Simulator tick rate (ticks/s) 10host_mem_usage 340604 # Number of bytes of host memory used 11host_seconds 440.46 # Real time elapsed on the host 12sim_insts 56735321 # Number of instructions simulated 13sim_ops 56735321 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 449354 # Total number of read requests seen 52system.physmem.writeReqs 120733 # Total number of write requests seen 53system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28758656 # Total number of bytes read from memory 55system.physmem.bytesWritten 7726912 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis |
| 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 93system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1897852967000 # Total gap between requests | 93system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1901668058000 # Total gap between requests |
| 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 101system.physmem.readPktSize::6 450802 # Categorize read packet sizes | 101system.physmem.readPktSize::6 449354 # Categorize read packet sizes |
| 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes | 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes |
| 110system.physmem.writePktSize::6 122493 # categorize write packet sizes | 110system.physmem.writePktSize::6 121126 # categorize write packet sizes |
| 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| 119system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes | 119system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes |
| 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 122system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see | 122system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see |
| 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 188system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests 190system.physmem.totBusLat 1803000000 # Total cycles spent in databus access 191system.physmem.totBankLat 5519080000 # Total cycles spent in bank access 192system.physmem.avgQLat 14764.02 # Average queueing delay per request 193system.physmem.avgBankLat 12244.22 # Average bank access latency per request | 188system.physmem.totQLat 6361514382 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 13649024382 # Sum of mem lat for all requests 190system.physmem.totBusLat 1797116000 # Total cycles spent in databus access 191system.physmem.totBankLat 5490394000 # Total cycles spent in bank access 192system.physmem.avgQLat 14159.39 # Average queueing delay per request 193system.physmem.avgBankLat 12220.46 # Average bank access latency per request |
| 194system.physmem.avgBusLat 4000.00 # Average bus latency per request | 194system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 195system.physmem.avgMemAccLat 31008.23 # Average memory access latency 196system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s | 195system.physmem.avgMemAccLat 30379.84 # Average memory access latency 196system.physmem.avgRdBW 15.12 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 4.06 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 15.12 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 4.06 # Average consumed write bandwidth in MB/s |
| 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time | 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 203system.physmem.avgWrQLen 7.39 # Average write queue length over time 204system.physmem.readRowHits 429728 # Number of row buffer hits during reads 205system.physmem.writeRowHits 77127 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes 208system.physmem.avgGap 3313464.33 # Average gap between requests 209system.l2c.replacements 343886 # number of replacements 210system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use 211system.l2c.total_refs 2612992 # Total number of references to valid blocks. 212system.l2c.sampled_refs 408910 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.390140 # Average number of references to valid blocks. | 203system.physmem.avgWrQLen 13.85 # Average write queue length over time 204system.physmem.readRowHits 429052 # Number of row buffer hits during reads 205system.physmem.writeRowHits 77896 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.50 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 64.52 # Row buffer hit rate for writes 208system.physmem.avgGap 3335750.61 # Average gap between requests 209system.l2c.replacements 342488 # number of replacements 210system.l2c.tagsinuse 65273.985795 # Cycle average of tags in use 211system.l2c.total_refs 2579319 # Total number of references to valid blocks. 212system.l2c.sampled_refs 407454 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.330332 # Average number of references to valid blocks. |
| 214system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. | 214system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. |
| 215system.l2c.occ_blocks::writebacks 53692.952391 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4245.749457 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 5529.153379 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 1310.829137 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 551.764862 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.819289 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.064785 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.084368 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.020002 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.008419 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.996864 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 779502 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 594261 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 294591 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 226328 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1894682 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 840085 # number of Writeback hits 232system.l2c.Writeback_hits::total 840085 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 34 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 147131 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 42889 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 190020 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 779502 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 741392 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 294591 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 269217 # number of demand (read+write) hits 246system.l2c.demand_hits::total 2084702 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 779502 # number of overall hits 248system.l2c.overall_hits::cpu0.data 741392 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 294591 # number of overall hits 250system.l2c.overall_hits::cpu1.data 269217 # number of overall hits 251system.l2c.overall_hits::total 2084702 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 11921 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 272257 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 3421 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 1751 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 289350 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2525 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 517 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 3042 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 47 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 137 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 107281 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 13452 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 120733 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 11921 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 379538 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 3421 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 15203 # number of demand (read+write) misses 270system.l2c.demand_misses::total 410083 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 11921 # number of overall misses 272system.l2c.overall_misses::cpu0.data 379538 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 3421 # number of overall misses 274system.l2c.overall_misses::cpu1.data 15203 # number of overall misses 275system.l2c.overall_misses::total 410083 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 712478500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11719521500 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 222220000 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 113744499 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12767964499 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 468000 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 936000 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 1404000 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 313000 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 113500 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 426500 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 7724029500 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 1451007500 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 9175037000 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 712478500 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 19443551000 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 222220000 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 1564751999 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 21943001499 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 712478500 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 19443551000 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 222220000 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 1564751999 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 21943001499 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 791423 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 866518 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 298012 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 228079 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2184032 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 840085 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 840085 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 2668 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 597 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 3265 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 119 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 200 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 254412 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 56341 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 310753 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 791423 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1120930 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 298012 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 284420 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2494785 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 791423 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1120930 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 298012 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 284420 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2494785 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.015063 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.314197 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.011479 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.007677 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.132484 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946402 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865997 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.931700 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.580247 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756303 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.685000 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.421682 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.238760 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.388518 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.015063 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.338592 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.011479 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.053453 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.164376 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.015063 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.338592 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.011479 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.053453 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.164376 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59766.672259 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 43045.804148 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64957.614733 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 64959.736722 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 44126.367717 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 185.346535 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1810.444874 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 461.538462 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6659.574468 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1261.111111 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 3113.138686 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71998.112434 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 107865.559025 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 75994.442282 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 53508.683606 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 53508.683606 # average overall miss latency | 215system.l2c.occ_blocks::writebacks 53688.105683 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 5378.814643 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 5989.071273 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 150.579784 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 67.414412 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.819215 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.082074 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.091386 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.002298 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.996002 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 855139 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 732341 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 222061 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 70684 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1880225 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 820780 # number of Writeback hits 232system.l2c.Writeback_hits::total 820780 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 155166 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 26038 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 181204 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 855139 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 887507 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 222061 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 96722 # number of demand (read+write) hits 246system.l2c.demand_hits::total 2061429 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 855139 # number of overall hits 248system.l2c.overall_hits::cpu0.data 887507 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 222061 # number of overall hits 250system.l2c.overall_hits::cpu1.data 96722 # number of overall hits 251system.l2c.overall_hits::total 2061429 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 13402 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 273000 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 1871 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 879 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2698 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1127 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 3825 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 423 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 448 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 871 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 111862 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 7571 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 119433 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 13402 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 384862 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 1871 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 8450 # number of demand (read+write) misses 270system.l2c.demand_misses::total 408585 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 13402 # number of overall misses 272system.l2c.overall_misses::cpu0.data 384862 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 1871 # number of overall misses 274system.l2c.overall_misses::cpu1.data 8450 # number of overall misses 275system.l2c.overall_misses::total 408585 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 813261500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11720735498 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 126107500 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 66824498 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12726928996 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 1011000 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 4739996 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 5750996 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1139500 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 1253500 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 7926259499 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 948720500 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 8874979999 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 813261500 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 19646994997 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 126107500 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 1015544998 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 21601908995 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 813261500 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 19646994997 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 126107500 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 1015544998 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 21601908995 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 868541 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 1005341 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 223932 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 71563 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2169377 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 820780 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 820780 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 2861 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 1401 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 4262 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 945 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 267028 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 33609 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 300637 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 868541 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1272369 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 223932 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 105172 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2470014 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 868541 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1272369 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 223932 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 105172 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2470014 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.015430 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.271550 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.008355 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.012283 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.133288 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943027 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.804425 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.897466 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.898089 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945148 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.921693 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.418915 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.225267 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.397266 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.015430 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.302477 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.008355 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.080345 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.165418 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.015430 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.302477 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.008355 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.080345 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.165418 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 60682.099687 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 42933.097062 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 67401.122394 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 76023.319681 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 44014.667013 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 374.722016 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4205.852706 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 1503.528366 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2693.853428 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 254.464286 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 1439.150402 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70857.480637 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125309.800555 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 74309.277997 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 52870.049060 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 60682.099687 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 51049.454082 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 67401.122394 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 120182.840000 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 52870.049060 # average overall miss latency |
| 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed | 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed |
| 382system.l2c.writebacks::writebacks 80445 # number of writebacks 383system.l2c.writebacks::total 80445 # number of writebacks | 382system.l2c.writebacks::writebacks 79213 # number of writebacks 383system.l2c.writebacks::total 79213 # number of writebacks |
| 384system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 386system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 387system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 388system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 389system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 390system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 391system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 392system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 393system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 394system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 395system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits | 384system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits 386system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 387system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 388system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 389system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits 390system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 391system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 392system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 393system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits 394system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 395system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits |
| 396system.l2c.ReadReq_mshr_misses::cpu0.inst 11920 # number of ReadReq MSHR misses 397system.l2c.ReadReq_mshr_misses::cpu0.data 272257 # number of ReadReq MSHR misses 398system.l2c.ReadReq_mshr_misses::cpu1.inst 3405 # number of ReadReq MSHR misses 399system.l2c.ReadReq_mshr_misses::cpu1.data 1750 # number of ReadReq MSHR misses 400system.l2c.ReadReq_mshr_misses::total 289332 # number of ReadReq MSHR misses 401system.l2c.UpgradeReq_mshr_misses::cpu0.data 2525 # number of UpgradeReq MSHR misses 402system.l2c.UpgradeReq_mshr_misses::cpu1.data 517 # number of UpgradeReq MSHR misses 403system.l2c.UpgradeReq_mshr_misses::total 3042 # number of UpgradeReq MSHR misses 404system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 47 # number of SCUpgradeReq MSHR misses 405system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90 # number of SCUpgradeReq MSHR misses 406system.l2c.SCUpgradeReq_mshr_misses::total 137 # number of SCUpgradeReq MSHR misses 407system.l2c.ReadExReq_mshr_misses::cpu0.data 107281 # number of ReadExReq MSHR misses 408system.l2c.ReadExReq_mshr_misses::cpu1.data 13452 # number of ReadExReq MSHR misses 409system.l2c.ReadExReq_mshr_misses::total 120733 # number of ReadExReq MSHR misses 410system.l2c.demand_mshr_misses::cpu0.inst 11920 # number of demand (read+write) MSHR misses 411system.l2c.demand_mshr_misses::cpu0.data 379538 # number of demand (read+write) MSHR misses 412system.l2c.demand_mshr_misses::cpu1.inst 3405 # number of demand (read+write) MSHR misses 413system.l2c.demand_mshr_misses::cpu1.data 15202 # number of demand (read+write) MSHR misses 414system.l2c.demand_mshr_misses::total 410065 # number of demand (read+write) MSHR misses 415system.l2c.overall_mshr_misses::cpu0.inst 11920 # number of overall MSHR misses 416system.l2c.overall_mshr_misses::cpu0.data 379538 # number of overall MSHR misses 417system.l2c.overall_mshr_misses::cpu1.inst 3405 # number of overall MSHR misses 418system.l2c.overall_mshr_misses::cpu1.data 15202 # number of overall MSHR misses 419system.l2c.overall_mshr_misses::total 410065 # number of overall MSHR misses 420system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561911095 # number of ReadReq MSHR miss cycles 421system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8192955588 # number of ReadReq MSHR miss cycles 422system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 178565558 # number of ReadReq MSHR miss cycles 423system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113324293 # number of ReadReq MSHR miss cycles 424system.l2c.ReadReq_mshr_miss_latency::total 9046756534 # number of ReadReq MSHR miss cycles 425system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25301493 # number of UpgradeReq MSHR miss cycles 426system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5294512 # number of UpgradeReq MSHR miss cycles 427system.l2c.UpgradeReq_mshr_miss_latency::total 30596005 # number of UpgradeReq MSHR miss cycles 428system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 516543 # number of SCUpgradeReq MSHR miss cycles 429system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 904088 # number of SCUpgradeReq MSHR miss cycles 430system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420631 # number of SCUpgradeReq MSHR miss cycles 431system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6410159669 # number of ReadExReq MSHR miss cycles 432system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1283732505 # number of ReadExReq MSHR miss cycles 433system.l2c.ReadExReq_mshr_miss_latency::total 7693892174 # number of ReadExReq MSHR miss cycles 434system.l2c.demand_mshr_miss_latency::cpu0.inst 561911095 # number of demand (read+write) MSHR miss cycles 435system.l2c.demand_mshr_miss_latency::cpu0.data 14603115257 # number of demand (read+write) MSHR miss cycles 436system.l2c.demand_mshr_miss_latency::cpu1.inst 178565558 # number of demand (read+write) MSHR miss cycles 437system.l2c.demand_mshr_miss_latency::cpu1.data 1397056798 # number of demand (read+write) MSHR miss cycles 438system.l2c.demand_mshr_miss_latency::total 16740648708 # number of demand (read+write) MSHR miss cycles 439system.l2c.overall_mshr_miss_latency::cpu0.inst 561911095 # number of overall MSHR miss cycles 440system.l2c.overall_mshr_miss_latency::cpu0.data 14603115257 # number of overall MSHR miss cycles 441system.l2c.overall_mshr_miss_latency::cpu1.inst 178565558 # number of overall MSHR miss cycles 442system.l2c.overall_mshr_miss_latency::cpu1.data 1397056798 # number of overall MSHR miss cycles 443system.l2c.overall_mshr_miss_latency::total 16740648708 # number of overall MSHR miss cycles 444system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936053000 # number of ReadReq MSHR uncacheable cycles 445system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 455620500 # number of ReadReq MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_uncacheable_latency::total 1391673500 # number of ReadReq MSHR uncacheable cycles 447system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1587348000 # number of WriteReq MSHR uncacheable cycles 448system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 874199500 # number of WriteReq MSHR uncacheable cycles 449system.l2c.WriteReq_mshr_uncacheable_latency::total 2461547500 # number of WriteReq MSHR uncacheable cycles 450system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2523401000 # number of overall MSHR uncacheable cycles 451system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1329820000 # number of overall MSHR uncacheable cycles 452system.l2c.overall_mshr_uncacheable_latency::total 3853221000 # number of overall MSHR uncacheable cycles 453system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.314197 # mshr miss rate for ReadReq accesses 455system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for ReadReq accesses 456system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007673 # mshr miss rate for ReadReq accesses 457system.l2c.ReadReq_mshr_miss_rate::total 0.132476 # mshr miss rate for ReadReq accesses 458system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.946402 # mshr miss rate for UpgradeReq accesses 459system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865997 # mshr miss rate for UpgradeReq accesses 460system.l2c.UpgradeReq_mshr_miss_rate::total 0.931700 # mshr miss rate for UpgradeReq accesses 461system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.580247 # mshr miss rate for SCUpgradeReq accesses 462system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756303 # mshr miss rate for SCUpgradeReq accesses 463system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.685000 # mshr miss rate for SCUpgradeReq accesses 464system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421682 # mshr miss rate for ReadExReq accesses 465system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.238760 # mshr miss rate for ReadExReq accesses 466system.l2c.ReadExReq_mshr_miss_rate::total 0.388518 # mshr miss rate for ReadExReq accesses 467system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses 472system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses 473system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.727048 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64756.738857 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 31267.735798 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.393267 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10240.835590 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10057.858317 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10990.276596 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.422222 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10369.569343 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59751.117803 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95430.605486 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 63726.505380 # average ReadExReq mshr miss latency 491system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency 493system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency 495system.l2c.demand_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency 496system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency 497system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency 498system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency 499system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency 500system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency | 396system.l2c.ReadReq_mshr_misses::cpu0.inst 13401 # number of ReadReq MSHR misses 397system.l2c.ReadReq_mshr_misses::cpu0.data 273000 # number of ReadReq MSHR misses 398system.l2c.ReadReq_mshr_misses::cpu1.inst 1855 # number of ReadReq MSHR misses 399system.l2c.ReadReq_mshr_misses::cpu1.data 878 # number of ReadReq MSHR misses 400system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses 401system.l2c.UpgradeReq_mshr_misses::cpu0.data 2698 # number of UpgradeReq MSHR misses 402system.l2c.UpgradeReq_mshr_misses::cpu1.data 1127 # number of UpgradeReq MSHR misses 403system.l2c.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses 404system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 423 # number of SCUpgradeReq MSHR misses 405system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 448 # number of SCUpgradeReq MSHR misses 406system.l2c.SCUpgradeReq_mshr_misses::total 871 # number of SCUpgradeReq MSHR misses 407system.l2c.ReadExReq_mshr_misses::cpu0.data 111862 # number of ReadExReq MSHR misses 408system.l2c.ReadExReq_mshr_misses::cpu1.data 7571 # number of ReadExReq MSHR misses 409system.l2c.ReadExReq_mshr_misses::total 119433 # number of ReadExReq MSHR misses 410system.l2c.demand_mshr_misses::cpu0.inst 13401 # number of demand (read+write) MSHR misses 411system.l2c.demand_mshr_misses::cpu0.data 384862 # number of demand (read+write) MSHR misses 412system.l2c.demand_mshr_misses::cpu1.inst 1855 # number of demand (read+write) MSHR misses 413system.l2c.demand_mshr_misses::cpu1.data 8449 # number of demand (read+write) MSHR misses 414system.l2c.demand_mshr_misses::total 408567 # number of demand (read+write) MSHR misses 415system.l2c.overall_mshr_misses::cpu0.inst 13401 # number of overall MSHR misses 416system.l2c.overall_mshr_misses::cpu0.data 384862 # number of overall MSHR misses 417system.l2c.overall_mshr_misses::cpu1.inst 1855 # number of overall MSHR misses 418system.l2c.overall_mshr_misses::cpu1.data 8449 # number of overall MSHR misses 419system.l2c.overall_mshr_misses::total 408567 # number of overall MSHR misses 420system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644081442 # number of ReadReq MSHR miss cycles 421system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8187744767 # number of ReadReq MSHR miss cycles 422system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 101989522 # number of ReadReq MSHR miss cycles 423system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55676772 # number of ReadReq MSHR miss cycles 424system.l2c.ReadReq_mshr_miss_latency::total 8989492503 # number of ReadReq MSHR miss cycles 425system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27208158 # number of UpgradeReq MSHR miss cycles 426system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11300121 # number of UpgradeReq MSHR miss cycles 427system.l2c.UpgradeReq_mshr_miss_latency::total 38508279 # number of UpgradeReq MSHR miss cycles 428system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4442418 # number of SCUpgradeReq MSHR miss cycles 429system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4488947 # number of SCUpgradeReq MSHR miss cycles 430system.l2c.SCUpgradeReq_mshr_miss_latency::total 8931365 # number of SCUpgradeReq MSHR miss cycles 431system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6555553694 # number of ReadExReq MSHR miss cycles 432system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 854426889 # number of ReadExReq MSHR miss cycles 433system.l2c.ReadExReq_mshr_miss_latency::total 7409980583 # number of ReadExReq MSHR miss cycles 434system.l2c.demand_mshr_miss_latency::cpu0.inst 644081442 # number of demand (read+write) MSHR miss cycles 435system.l2c.demand_mshr_miss_latency::cpu0.data 14743298461 # number of demand (read+write) MSHR miss cycles 436system.l2c.demand_mshr_miss_latency::cpu1.inst 101989522 # number of demand (read+write) MSHR miss cycles 437system.l2c.demand_mshr_miss_latency::cpu1.data 910103661 # number of demand (read+write) MSHR miss cycles 438system.l2c.demand_mshr_miss_latency::total 16399473086 # number of demand (read+write) MSHR miss cycles 439system.l2c.overall_mshr_miss_latency::cpu0.inst 644081442 # number of overall MSHR miss cycles 440system.l2c.overall_mshr_miss_latency::cpu0.data 14743298461 # number of overall MSHR miss cycles 441system.l2c.overall_mshr_miss_latency::cpu1.inst 101989522 # number of overall MSHR miss cycles 442system.l2c.overall_mshr_miss_latency::cpu1.data 910103661 # number of overall MSHR miss cycles 443system.l2c.overall_mshr_miss_latency::total 16399473086 # number of overall MSHR miss cycles 444system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1363910000 # number of ReadReq MSHR uncacheable cycles 445system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28770000 # number of ReadReq MSHR uncacheable cycles 446system.l2c.ReadReq_mshr_uncacheable_latency::total 1392680000 # number of ReadReq MSHR uncacheable cycles 447system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2007132500 # number of WriteReq MSHR uncacheable cycles 448system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 609318500 # number of WriteReq MSHR uncacheable cycles 449system.l2c.WriteReq_mshr_uncacheable_latency::total 2616451000 # number of WriteReq MSHR uncacheable cycles 450system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3371042500 # number of overall MSHR uncacheable cycles 451system.l2c.overall_mshr_uncacheable_latency::cpu1.data 638088500 # number of overall MSHR uncacheable cycles 452system.l2c.overall_mshr_uncacheable_latency::total 4009131000 # number of overall MSHR uncacheable cycles 453system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for ReadReq accesses 454system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271550 # mshr miss rate for ReadReq accesses 455system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for ReadReq accesses 456system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012269 # mshr miss rate for ReadReq accesses 457system.l2c.ReadReq_mshr_miss_rate::total 0.133280 # mshr miss rate for ReadReq accesses 458system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943027 # mshr miss rate for UpgradeReq accesses 459system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.804425 # mshr miss rate for UpgradeReq accesses 460system.l2c.UpgradeReq_mshr_miss_rate::total 0.897466 # mshr miss rate for UpgradeReq accesses 461system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.898089 # mshr miss rate for SCUpgradeReq accesses 462system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945148 # mshr miss rate for SCUpgradeReq accesses 463system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.921693 # mshr miss rate for SCUpgradeReq accesses 464system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418915 # mshr miss rate for ReadExReq accesses 465system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.225267 # mshr miss rate for ReadExReq accesses 466system.l2c.ReadExReq_mshr_miss_rate::total 0.397266 # mshr miss rate for ReadExReq accesses 467system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for demand accesses 468system.l2c.demand_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for demand accesses 469system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for demand accesses 470system.l2c.demand_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for demand accesses 471system.l2c.demand_mshr_miss_rate::total 0.165411 # mshr miss rate for demand accesses 472system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015429 # mshr miss rate for overall accesses 473system.l2c.overall_mshr_miss_rate::cpu0.data 0.302477 # mshr miss rate for overall accesses 474system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008284 # mshr miss rate for overall accesses 475system.l2c.overall_mshr_miss_rate::cpu1.data 0.080335 # mshr miss rate for overall accesses 476system.l2c.overall_mshr_miss_rate::total 0.165411 # mshr miss rate for overall accesses 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29991.739073 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63413.179954 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 31091.094451 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10084.565604 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10026.726708 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.523922 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10502.170213 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.970982 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10254.150402 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58603.937834 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 112855.222428 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 62042.991326 # average ReadExReq mshr miss latency 491system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency 493system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency 495system.l2c.demand_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency 496system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 48062.192523 # average overall mshr miss latency 497system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38308.012901 # average overall mshr miss latency 498system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 54980.874394 # average overall mshr miss latency 499system.l2c.overall_avg_mshr_miss_latency::cpu1.data 107717.322878 # average overall mshr miss latency 500system.l2c.overall_avg_mshr_miss_latency::total 40139.005563 # average overall mshr miss latency |
| 501system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 502system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 503system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 504system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 505system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 506system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 507system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 508system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 509system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 510system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 501system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 502system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 503system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 504system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 505system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 506system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 507system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 508system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 509system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 510system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 511system.iocache.replacements 41695 # number of replacements 512system.iocache.tagsinuse 0.486173 # Cycle average of tags in use | 511system.iocache.replacements 41699 # number of replacements 512system.iocache.tagsinuse 0.510808 # Cycle average of tags in use |
| 513system.iocache.total_refs 0 # Total number of references to valid blocks. | 513system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 514system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. | 514system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. |
| 515system.iocache.avg_refs 0 # Average number of references to valid blocks. | 515system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 516system.iocache.warmup_cycle 1705465376000 # Cycle when the warmup percentage was hit. 517system.iocache.occ_blocks::tsunami.ide 0.486173 # Average occupied blocks per requestor 518system.iocache.occ_percent::tsunami.ide 0.030386 # Average percentage of cache occupancy 519system.iocache.occ_percent::total 0.030386 # Average percentage of cache occupancy 520system.iocache.ReadReq_misses::tsunami.ide 172 # number of ReadReq misses 521system.iocache.ReadReq_misses::total 172 # number of ReadReq misses | 516system.iocache.warmup_cycle 1705448726000 # Cycle when the warmup percentage was hit. 517system.iocache.occ_blocks::tsunami.ide 0.510808 # Average occupied blocks per requestor 518system.iocache.occ_percent::tsunami.ide 0.031925 # Average percentage of cache occupancy 519system.iocache.occ_percent::total 0.031925 # Average percentage of cache occupancy 520system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 521system.iocache.ReadReq_misses::total 179 # number of ReadReq misses |
| 522system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 523system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses | 522system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 523system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses |
| 524system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses 525system.iocache.demand_misses::total 41724 # number of demand (read+write) misses 526system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses 527system.iocache.overall_misses::total 41724 # number of overall misses 528system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles 529system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles 530system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles 531system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles 532system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles 533system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles 534system.iocache.overall_miss_latency::tsunami.ide 9561121804 # number of overall miss cycles 535system.iocache.overall_miss_latency::total 9561121804 # number of overall miss cycles 536system.iocache.ReadReq_accesses::tsunami.ide 172 # number of ReadReq accesses(hits+misses) 537system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) | 524system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 525system.iocache.demand_misses::total 41731 # number of demand (read+write) misses 526system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 527system.iocache.overall_misses::total 41731 # number of overall misses 528system.iocache.ReadReq_miss_latency::tsunami.ide 21606998 # number of ReadReq miss cycles 529system.iocache.ReadReq_miss_latency::total 21606998 # number of ReadReq miss cycles 530system.iocache.WriteReq_miss_latency::tsunami.ide 9515470806 # number of WriteReq miss cycles 531system.iocache.WriteReq_miss_latency::total 9515470806 # number of WriteReq miss cycles 532system.iocache.demand_miss_latency::tsunami.ide 9537077804 # number of demand (read+write) miss cycles 533system.iocache.demand_miss_latency::total 9537077804 # number of demand (read+write) miss cycles 534system.iocache.overall_miss_latency::tsunami.ide 9537077804 # number of overall miss cycles 535system.iocache.overall_miss_latency::total 9537077804 # number of overall miss cycles 536system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 537system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) |
| 538system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 539system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) | 538system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 539system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) |
| 540system.iocache.demand_accesses::tsunami.ide 41724 # number of demand (read+write) accesses 541system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses 542system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses 543system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses | 540system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 541system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 542system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 543system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses |
| 544system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 545system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 546system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 547system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 548system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 549system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 550system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 551system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 544system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 545system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 546system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 547system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 548system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 549system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 550system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 551system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 552system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency 553system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency 554system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency 555system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency 556system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency 557system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency 558system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency 559system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency 560system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked | 552system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120709.486034 # average ReadReq miss latency 553system.iocache.ReadReq_avg_miss_latency::total 120709.486034 # average ReadReq miss latency 554system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229001.511504 # average WriteReq miss latency 555system.iocache.WriteReq_avg_miss_latency::total 229001.511504 # average WriteReq miss latency 556system.iocache.demand_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency 557system.iocache.demand_avg_miss_latency::total 228537.006158 # average overall miss latency 558system.iocache.overall_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency 559system.iocache.overall_avg_miss_latency::total 228537.006158 # average overall miss latency 560system.iocache.blocked_cycles::no_mshrs 190616 # number of cycles access was blocked |
| 561system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 561system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 562system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked | 562system.iocache.blocked::no_mshrs 22877 # number of cycles access was blocked |
| 563system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 563system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 564system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked | 564system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked |
| 565system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 566system.iocache.fast_writes 0 # number of fast writes performed 567system.iocache.cache_copies 0 # number of cache copies performed | 565system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 566system.iocache.fast_writes 0 # number of fast writes performed 567system.iocache.cache_copies 0 # number of cache copies performed |
| 568system.iocache.writebacks::writebacks 41523 # number of writebacks 569system.iocache.writebacks::total 41523 # number of writebacks 570system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses 571system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses | 568system.iocache.writebacks::writebacks 41520 # number of writebacks 569system.iocache.writebacks::total 41520 # number of writebacks 570system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 571system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses |
| 572system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 573system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses | 572system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 573system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses |
| 574system.iocache.demand_mshr_misses::tsunami.ide 41724 # number of demand (read+write) MSHR misses 575system.iocache.demand_mshr_misses::total 41724 # number of demand (read+write) MSHR misses 576system.iocache.overall_mshr_misses::tsunami.ide 41724 # number of overall MSHR misses 577system.iocache.overall_mshr_misses::total 41724 # number of overall MSHR misses 578system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11872000 # number of ReadReq MSHR miss cycles 579system.iocache.ReadReq_mshr_miss_latency::total 11872000 # number of ReadReq MSHR miss cycles 580system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7377518046 # number of WriteReq MSHR miss cycles 581system.iocache.WriteReq_mshr_miss_latency::total 7377518046 # number of WriteReq MSHR miss cycles 582system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles 583system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles 584system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles 585system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles | 574system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 575system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 576system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 577system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 578system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles 579system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles 580system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles 581system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles 582system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles 583system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles 584system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles 585system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles |
| 586system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 587system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 588system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 589system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 590system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 591system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 592system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 593system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 586system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 587system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 588system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 589system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 590system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 591system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 592system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 593system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 594system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency 595system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency 596system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency 597system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency 598system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency 599system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency 600system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency 601system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency | 594system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency 595system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency 596system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency 597system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency 598system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency 599system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency 600system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency 601system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency |
| 602system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 605system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 606system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 607system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 608system.disk0.dma_write_txs 395 # Number of DMA write transactions. 609system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 610system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 611system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 612system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 613system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 614system.disk2.dma_write_txs 1 # Number of DMA write transactions. 615system.cpu0.dtb.fetch_hits 0 # ITB hits 616system.cpu0.dtb.fetch_misses 0 # ITB misses 617system.cpu0.dtb.fetch_acv 0 # ITB acv 618system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 602system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 603system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 605system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 606system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 607system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 608system.disk0.dma_write_txs 395 # Number of DMA write transactions. 609system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 610system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 611system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 612system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 613system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 614system.disk2.dma_write_txs 1 # Number of DMA write transactions. 615system.cpu0.dtb.fetch_hits 0 # ITB hits 616system.cpu0.dtb.fetch_misses 0 # ITB misses 617system.cpu0.dtb.fetch_acv 0 # ITB acv 618system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 619system.cpu0.dtb.read_hits 7996955 # DTB read hits 620system.cpu0.dtb.read_misses 29938 # DTB read misses 621system.cpu0.dtb.read_acv 553 # DTB read access violations 622system.cpu0.dtb.read_accesses 624438 # DTB read accesses 623system.cpu0.dtb.write_hits 5309744 # DTB write hits 624system.cpu0.dtb.write_misses 7955 # DTB write misses 625system.cpu0.dtb.write_acv 319 # DTB write access violations 626system.cpu0.dtb.write_accesses 207916 # DTB write accesses 627system.cpu0.dtb.data_hits 13306699 # DTB hits 628system.cpu0.dtb.data_misses 37893 # DTB misses 629system.cpu0.dtb.data_acv 872 # DTB access violations 630system.cpu0.dtb.data_accesses 832354 # DTB accesses 631system.cpu0.itb.fetch_hits 944692 # ITB hits 632system.cpu0.itb.fetch_misses 28693 # ITB misses 633system.cpu0.itb.fetch_acv 988 # ITB acv 634system.cpu0.itb.fetch_accesses 973385 # ITB accesses | 619system.cpu0.dtb.read_hits 8796431 # DTB read hits 620system.cpu0.dtb.read_misses 31428 # DTB read misses 621system.cpu0.dtb.read_acv 541 # DTB read access violations 622system.cpu0.dtb.read_accesses 625134 # DTB read accesses 623system.cpu0.dtb.write_hits 5759616 # DTB write hits 624system.cpu0.dtb.write_misses 8293 # DTB write misses 625system.cpu0.dtb.write_acv 340 # DTB write access violations 626system.cpu0.dtb.write_accesses 208056 # DTB write accesses 627system.cpu0.dtb.data_hits 14556047 # DTB hits 628system.cpu0.dtb.data_misses 39721 # DTB misses 629system.cpu0.dtb.data_acv 881 # DTB access violations 630system.cpu0.dtb.data_accesses 833190 # DTB accesses 631system.cpu0.itb.fetch_hits 984271 # ITB hits 632system.cpu0.itb.fetch_misses 30098 # ITB misses 633system.cpu0.itb.fetch_acv 957 # ITB acv 634system.cpu0.itb.fetch_accesses 1014369 # ITB accesses |
| 635system.cpu0.itb.read_hits 0 # DTB read hits 636system.cpu0.itb.read_misses 0 # DTB read misses 637system.cpu0.itb.read_acv 0 # DTB read access violations 638system.cpu0.itb.read_accesses 0 # DTB read accesses 639system.cpu0.itb.write_hits 0 # DTB write hits 640system.cpu0.itb.write_misses 0 # DTB write misses 641system.cpu0.itb.write_acv 0 # DTB write access violations 642system.cpu0.itb.write_accesses 0 # DTB write accesses 643system.cpu0.itb.data_hits 0 # DTB hits 644system.cpu0.itb.data_misses 0 # DTB misses 645system.cpu0.itb.data_acv 0 # DTB access violations 646system.cpu0.itb.data_accesses 0 # DTB accesses | 635system.cpu0.itb.read_hits 0 # DTB read hits 636system.cpu0.itb.read_misses 0 # DTB read misses 637system.cpu0.itb.read_acv 0 # DTB read access violations 638system.cpu0.itb.read_accesses 0 # DTB read accesses 639system.cpu0.itb.write_hits 0 # DTB write hits 640system.cpu0.itb.write_misses 0 # DTB write misses 641system.cpu0.itb.write_acv 0 # DTB write access violations 642system.cpu0.itb.write_accesses 0 # DTB write accesses 643system.cpu0.itb.data_hits 0 # DTB hits 644system.cpu0.itb.data_misses 0 # DTB misses 645system.cpu0.itb.data_acv 0 # DTB access violations 646system.cpu0.itb.data_accesses 0 # DTB accesses |
| 647system.cpu0.numCycles 92901317 # number of cpu cycles simulated | 647system.cpu0.numCycles 101814962 # number of cpu cycles simulated |
| 648system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 649system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 648system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 649system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 650system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups 651system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted 652system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect 653system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups 654system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits | 650system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups 651system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted 652system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect 653system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups 654system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits |
| 655system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 655system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 656system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. 657system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. 658system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss 659system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed 660system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered 661system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken 662system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked 663system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing 664system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked 665system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 666system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps 667system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions 668system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR 669system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched 670system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed 671system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) 673system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) | 656system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target. 657system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions. 658system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss 659system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed 660system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered 661system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken 662system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked 663system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing 664system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked 665system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 666system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps 667system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions 668system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR 669system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched 670system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed 671system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) 672system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) 673system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) |
| 674system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 674system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 675system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) 676system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) 677system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) 678system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) 679system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) 680system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) 681system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) 682system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) 683system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) | 675system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) 676system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) 677system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) 678system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) 679system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) 680system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) 681system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) 682system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) 683system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) |
| 684system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 685system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 686system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 684system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 685system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 686system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 687system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) 688system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle 689system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle 690system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle 691system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked 692system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running 693system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking 694system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing 695system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch 696system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction 697system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode 698system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode 699system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing 700system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle 701system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking 702system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst 703system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running 704system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking 705system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename 706system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full 707system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full 708system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full 709system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed 710system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made 711system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups 712system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups 713system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed 714system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing 715system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed 716system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed 717system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer 718system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. 719system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. 720system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. 721system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. 722system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) 723system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ 724system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued 725system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued 726system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling 727system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph 728system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed 729system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle 731system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle | 687system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) 688system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle 689system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle 690system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle 691system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked 692system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running 693system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking 694system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing 695system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch 696system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction 697system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode 698system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode 699system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing 700system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle 701system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking 702system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst 703system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running 704system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking 705system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename 706system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full 707system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full 708system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full 709system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed 710system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made 711system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups 712system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups 713system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed 714system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing 715system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed 716system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed 717system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer 718system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. 719system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. 720system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. 721system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. 722system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) 723system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ 724system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued 725system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued 726system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling 727system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph 728system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed 729system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle 730system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle 731system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle |
| 732system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 732system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 733system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle 734system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle 735system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle 736system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle 737system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle 738system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle 739system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle 740system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle 741system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle | 733system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle 734system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle 735system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle 736system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle 737system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle 738system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle 739system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle 740system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle 741system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle |
| 742system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 743system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 744system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 742system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 743system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 744system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 745system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle | 745system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle |
| 746system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 746system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 747system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available 748system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available 749system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available 750system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available 751system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available 752system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available 753system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available 754system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available 755system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available 762system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available 763system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available 764system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available 765system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available 766system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available 767system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available 768system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available 769system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available 770system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available 771system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available 772system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available 773system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available 774system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available 775system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available 776system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available 777system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available | 747system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available 748system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available 749system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available 750system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available 751system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available 752system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available 753system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available 754system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available 755system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available 756system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available 757system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available 758system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available 759system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available 760system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available 761system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available 762system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available 763system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available 764system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available 765system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available 766system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available 767system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available 768system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available 769system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available 770system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available 771system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available 772system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available 773system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available 774system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available 775system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available 776system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available 777system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available |
| 778system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 779system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 778system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 779system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 780system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued 781system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued 782system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued 783system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued 784system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued 785system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued 786system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued 787system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued 788system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued 789system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued 796system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued 797system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued 798system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued 799system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued 800system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued 801system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued 802system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued 803system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued 804system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued 805system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued 806system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued 807system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued 808system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued 809system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued 810system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued 811system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued 812system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued | 780system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued 781system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued 782system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued 783system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued 784system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued 785system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued 786system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued 787system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued 788system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued 789system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued 790system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued 791system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued 792system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued 793system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued 794system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued 795system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued 796system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued 797system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued 798system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued 799system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued 800system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued 801system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued 802system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued 803system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued 804system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued 805system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued 806system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued 807system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued 808system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued 809system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued 810system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued 811system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued 812system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued |
| 813system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 813system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 814system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued 815system.cpu0.iq.rate 0.496715 # Inst issue rate 816system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested 817system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) 818system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads 819system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes 820system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses 821system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads 822system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes 823system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses 824system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses 825system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses 826system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores | 814system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued 815system.cpu0.iq.rate 0.501619 # Inst issue rate 816system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested 817system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) 818system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads 819system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes 820system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses 821system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads 822system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes 823system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses 824system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses 825system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses 826system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores |
| 827system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 827system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 828system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed 829system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed 830system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations 831system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed | 828system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed 829system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed 830system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations 831system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed |
| 832system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 833system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 832system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 833system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 834system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled 835system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked | 834system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled 835system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked |
| 836system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 836system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 837system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing 838system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking 839system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking 840system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ 841system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch 842system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions 843system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions 844system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions 845system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall 846system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall 847system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations 848system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly 849system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly 850system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute 851system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions 852system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed 853system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute | 837system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing 838system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking 839system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking 840system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ 841system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch 842system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions 843system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions 844system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions 845system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall 846system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall 847system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations 848system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly 849system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly 850system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute 851system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions 852system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed 853system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute |
| 854system.cpu0.iew.exec_swp 0 # number of swp insts executed | 854system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 855system.cpu0.iew.exec_nop 2855336 # number of nop insts executed 856system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed 857system.cpu0.iew.exec_branches 7249094 # Number of branches executed 858system.cpu0.iew.exec_stores 5329658 # Number of stores executed 859system.cpu0.iew.exec_rate 0.492967 # Inst execution rate 860system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit 861system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back 862system.cpu0.iew.wb_producers 22555336 # num instructions producing a value 863system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value | 855system.cpu0.iew.exec_nop 3208712 # number of nop insts executed 856system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed 857system.cpu0.iew.exec_branches 8068479 # Number of branches executed 858system.cpu0.iew.exec_stores 5781453 # Number of stores executed 859system.cpu0.iew.exec_rate 0.497833 # Inst execution rate 860system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit 861system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back 862system.cpu0.iew.wb_producers 25094352 # num instructions producing a value 863system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value |
| 864system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 864system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 865system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle 866system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back | 865system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle 866system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back |
| 867system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 867system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 868system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit 869system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards 870system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted 871system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle 873system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle | 868system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit 869system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards 870system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted 871system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle 872system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle 873system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle |
| 874system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 874system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 875system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle 876system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle 877system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle 878system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle 879system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle 880system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle 881system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle 882system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle 883system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle | 875system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle 876system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle 877system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle 878system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle 879system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle 880system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle 881system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle 882system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle 883system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle |
| 884system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 885system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 886system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 884system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 885system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 886system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 887system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle 888system.cpu0.commit.committedInsts 45914377 # Number of instructions committed 889system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed | 887system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle 888system.cpu0.commit.committedInsts 50792559 # Number of instructions committed 889system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed |
| 890system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 890system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 891system.cpu0.commit.refs 12498719 # Number of memory references committed 892system.cpu0.commit.loads 7343270 # Number of loads committed 893system.cpu0.commit.membars 179286 # Number of memory barriers committed 894system.cpu0.commit.branches 6902899 # Number of branches committed 895system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. 896system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. 897system.cpu0.commit.function_calls 573621 # Number of function calls committed. 898system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached | 891system.cpu0.commit.refs 13661699 # Number of memory references committed 892system.cpu0.commit.loads 8084046 # Number of loads committed 893system.cpu0.commit.membars 197074 # Number of memory barriers committed 894system.cpu0.commit.branches 7671683 # Number of branches committed 895system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. 896system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. 897system.cpu0.commit.function_calls 648346 # Number of function calls committed. 898system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached |
| 899system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 899system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 900system.cpu0.rob.rob_reads 116563585 # The number of ROB reads 901system.cpu0.rob.rob_writes 104266102 # The number of ROB writes 902system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself 903system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling 904system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 905system.cpu0.committedInsts 43304295 # Number of Instructions Simulated 906system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated 907system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated 908system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction 909system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads 910system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle 911system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads 912system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads 913system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes 914system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads 915system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes 916system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads 917system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes | 900system.cpu0.rob.rob_reads 129398549 # The number of ROB reads 901system.cpu0.rob.rob_writes 115399767 # The number of ROB writes 902system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself 903system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling 904system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 905system.cpu0.committedInsts 47867129 # Number of Instructions Simulated 906system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated 907system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated 908system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction 909system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads 910system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle 911system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads 912system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads 913system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes 914system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads 915system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes 916system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads 917system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes |
| 918system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 919system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 920system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 921system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 922system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 923system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 924system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 925system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 941system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 942system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 943system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 944system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 945system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 946system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 947system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 948system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 918system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 919system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 920system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 921system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 922system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 923system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 924system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 925system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 941system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 942system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 943system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 944system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 945system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 946system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 947system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 948system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 949system.cpu0.icache.replacements 790851 # number of replacements 950system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use 951system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. 952system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. 953system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. 954system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. 955system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor | 949system.cpu0.icache.replacements 867960 # number of replacements 950system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use 951system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. 952system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. 953system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. 954system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. 955system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor |
| 956system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy 957system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy | 956system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy 957system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy |
| 958system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits 959system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits 960system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits 961system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits 962system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits 963system.cpu0.icache.overall_hits::total 6144778 # number of overall hits 964system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses 965system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses 966system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses 967system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses 968system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses 969system.cpu0.icache.overall_misses::total 831804 # number of overall misses 970system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles 971system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles 972system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles 973system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles 974system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles 975system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles 976system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) 977system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) 978system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses 979system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses 980system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses 981system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses 982system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses 983system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses 984system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses 985system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses 986system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses 987system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses 988system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency 989system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency 990system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency 991system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency 992system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency 993system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency 994system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked 995system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked 996system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked 997system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked 998system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked 999system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked | 958system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits 959system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits 960system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits 961system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits 962system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits 963system.cpu0.icache.overall_hits::total 6737923 # number of overall hits 964system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses 965system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses 966system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses 967system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses 968system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses 969system.cpu0.icache.overall_misses::total 912101 # number of overall misses 970system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles 971system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles 972system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles 973system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles 974system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles 975system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles 976system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) 977system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) 978system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses 979system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses 980system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses 981system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses 982system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses 983system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses 984system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses 985system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses 986system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses 987system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses 988system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency 989system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency 990system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency 991system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency 992system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency 993system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency 994system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked 995system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked 996system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked 997system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked 998system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked 999system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked |
| 1000system.cpu0.icache.fast_writes 0 # number of fast writes performed 1001system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1000system.cpu0.icache.fast_writes 0 # number of fast writes performed 1001system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1002system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits 1003system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits 1004system.cpu0.icache.demand_mshr_hits::cpu0.inst 40285 # number of demand (read+write) MSHR hits 1005system.cpu0.icache.demand_mshr_hits::total 40285 # number of demand (read+write) MSHR hits 1006system.cpu0.icache.overall_mshr_hits::cpu0.inst 40285 # number of overall MSHR hits 1007system.cpu0.icache.overall_mshr_hits::total 40285 # number of overall MSHR hits 1008system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791519 # number of ReadReq MSHR misses 1009system.cpu0.icache.ReadReq_mshr_misses::total 791519 # number of ReadReq MSHR misses 1010system.cpu0.icache.demand_mshr_misses::cpu0.inst 791519 # number of demand (read+write) MSHR misses 1011system.cpu0.icache.demand_mshr_misses::total 791519 # number of demand (read+write) MSHR misses 1012system.cpu0.icache.overall_mshr_misses::cpu0.inst 791519 # number of overall MSHR misses 1013system.cpu0.icache.overall_mshr_misses::total 791519 # number of overall MSHR misses 1014system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9521125993 # number of ReadReq MSHR miss cycles 1015system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles 1016system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles 1017system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles 1018system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles 1019system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles 1020system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses 1021system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses 1022system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses 1023system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses 1024system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses 1025system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses 1026system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency 1027system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency 1028system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency 1029system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency 1030system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency 1031system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency | 1002system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits 1003system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits 1004system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits 1005system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits 1006system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits 1007system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits 1008system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses 1009system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses 1010system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses 1011system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses 1012system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses 1013system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses 1014system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles 1015system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles 1016system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles 1017system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles 1018system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles 1019system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles 1020system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses 1021system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses 1022system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses 1023system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses 1024system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses 1025system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses 1026system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency 1027system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency 1028system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency 1029system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency 1030system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency 1031system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency |
| 1032system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1032system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1033system.cpu0.dcache.replacements 1122816 # number of replacements 1034system.cpu0.dcache.tagsinuse 467.302243 # Cycle average of tags in use 1035system.cpu0.dcache.total_refs 9451134 # Total number of references to valid blocks. 1036system.cpu0.dcache.sampled_refs 1123328 # Sample count of references to valid blocks. 1037system.cpu0.dcache.avg_refs 8.413512 # Average number of references to valid blocks. | 1033system.cpu0.dcache.replacements 1274576 # number of replacements 1034system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use 1035system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. 1036system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. 1037system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. |
| 1038system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. | 1038system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. |
| 1039system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor 1040system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy 1041system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy 1042system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits 1043system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits 1044system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits 1045system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits 1046system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits 1047system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits 1048system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits 1049system.cpu0.dcache.StoreCondReq_hits::total 180603 # number of StoreCondReq hits 1050system.cpu0.dcache.demand_hits::cpu0.data 9107578 # number of demand (read+write) hits 1051system.cpu0.dcache.demand_hits::total 9107578 # number of demand (read+write) hits 1052system.cpu0.dcache.overall_hits::cpu0.data 9107578 # number of overall hits 1053system.cpu0.dcache.overall_hits::total 9107578 # number of overall hits 1054system.cpu0.dcache.ReadReq_misses::cpu0.data 1395487 # number of ReadReq misses 1055system.cpu0.dcache.ReadReq_misses::total 1395487 # number of ReadReq misses 1056system.cpu0.dcache.WriteReq_misses::cpu0.data 1670757 # number of WriteReq misses 1057system.cpu0.dcache.WriteReq_misses::total 1670757 # number of WriteReq misses 1058system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17192 # number of LoadLockedReq misses 1059system.cpu0.dcache.LoadLockedReq_misses::total 17192 # number of LoadLockedReq misses 1060system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses 1061system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses 1062system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses 1063system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses 1064system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses 1065system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses 1066system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles 1067system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles 1068system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles 1069system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles 1070system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles 1071system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles 1072system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles 1073system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles 1074system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles 1075system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles 1076system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles 1077system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles 1078system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) 1079system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) 1080system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) 1081system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) 1082system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) 1083system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) 1084system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) 1085system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) 1086system.cpu0.dcache.demand_accesses::cpu0.data 12173822 # number of demand (read+write) accesses 1087system.cpu0.dcache.demand_accesses::total 12173822 # number of demand (read+write) accesses 1088system.cpu0.dcache.overall_accesses::cpu0.data 12173822 # number of overall (read+write) accesses 1089system.cpu0.dcache.overall_accesses::total 12173822 # number of overall (read+write) accesses 1090system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193493 # miss rate for ReadReq accesses 1091system.cpu0.dcache.ReadReq_miss_rate::total 0.193493 # miss rate for ReadReq accesses 1092system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.336727 # miss rate for WriteReq accesses 1093system.cpu0.dcache.WriteReq_miss_rate::total 0.336727 # miss rate for WriteReq accesses 1094system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098877 # miss rate for LoadLockedReq accesses 1095system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098877 # miss rate for LoadLockedReq accesses 1096system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses 1097system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses 1098system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses 1099system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses 1100system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses 1101system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses 1102system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency 1103system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency 1104system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency 1105system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency 1106system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency 1108system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency 1109system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency 1110system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency 1111system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency 1112system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency 1113system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency 1114system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked 1115system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked 1116system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked | 1039system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor 1040system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy 1041system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy 1042system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits 1043system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits 1044system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits 1045system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits 1046system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits 1047system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits 1048system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits 1049system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits 1050system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits 1051system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits 1052system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits 1053system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits 1054system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses 1055system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses 1056system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses 1057system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses 1058system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses 1059system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses 1060system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses 1061system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses 1062system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses 1063system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses 1064system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses 1065system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses 1066system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # number of ReadReq miss cycles 1067system.cpu0.dcache.ReadReq_miss_latency::total 34092049500 # number of ReadReq miss cycles 1068system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69554473067 # number of WriteReq miss cycles 1069system.cpu0.dcache.WriteReq_miss_latency::total 69554473067 # number of WriteReq miss cycles 1070system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288471000 # number of LoadLockedReq miss cycles 1071system.cpu0.dcache.LoadLockedReq_miss_latency::total 288471000 # number of LoadLockedReq miss cycles 1072system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21390500 # number of StoreCondReq miss cycles 1073system.cpu0.dcache.StoreCondReq_miss_latency::total 21390500 # number of StoreCondReq miss cycles 1074system.cpu0.dcache.demand_miss_latency::cpu0.data 103646522567 # number of demand (read+write) miss cycles 1075system.cpu0.dcache.demand_miss_latency::total 103646522567 # number of demand (read+write) miss cycles 1076system.cpu0.dcache.overall_miss_latency::cpu0.data 103646522567 # number of overall miss cycles 1077system.cpu0.dcache.overall_miss_latency::total 103646522567 # number of overall miss cycles 1078system.cpu0.dcache.ReadReq_accesses::cpu0.data 7956400 # number of ReadReq accesses(hits+misses) 1079system.cpu0.dcache.ReadReq_accesses::total 7956400 # number of ReadReq accesses(hits+misses) 1080system.cpu0.dcache.WriteReq_accesses::cpu0.data 5375043 # number of WriteReq accesses(hits+misses) 1081system.cpu0.dcache.WriteReq_accesses::total 5375043 # number of WriteReq accesses(hits+misses) 1082system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181027 # number of LoadLockedReq accesses(hits+misses) 1083system.cpu0.dcache.LoadLockedReq_accesses::total 181027 # number of LoadLockedReq accesses(hits+misses) 1084system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188032 # number of StoreCondReq accesses(hits+misses) 1085system.cpu0.dcache.StoreCondReq_accesses::total 188032 # number of StoreCondReq accesses(hits+misses) 1086system.cpu0.dcache.demand_accesses::cpu0.data 13331443 # number of demand (read+write) accesses 1087system.cpu0.dcache.demand_accesses::total 13331443 # number of demand (read+write) accesses 1088system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses 1089system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses 1090system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses 1091system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses 1092system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses 1093system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses 1094system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses 1095system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses 1096system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses 1097system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses 1098system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses 1099system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses 1100system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses 1101system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses 1102system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency 1103system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency 1104system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency 1105system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency 1106system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency 1108system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency 1109system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # average StoreCondReq miss latency 1110system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency 1111system.cpu0.dcache.demand_avg_miss_latency::total 31131.401620 # average overall miss latency 1112system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency 1113system.cpu0.dcache.overall_avg_miss_latency::total 31131.401620 # average overall miss latency 1114system.cpu0.dcache.blocked_cycles::no_mshrs 2393556 # number of cycles access was blocked 1115system.cpu0.dcache.blocked_cycles::no_targets 1763 # number of cycles access was blocked 1116system.cpu0.dcache.blocked::no_mshrs 48538 # number of cycles access was blocked |
| 1117system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked | 1117system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 1118system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked 1119system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked | 1118system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked 1119system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked |
| 1120system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1121system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1120system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1121system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1122system.cpu0.dcache.writebacks::writebacks 614637 # number of writebacks 1123system.cpu0.dcache.writebacks::total 614637 # number of writebacks 1124system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 536909 # number of ReadReq MSHR hits 1125system.cpu0.dcache.ReadReq_mshr_hits::total 536909 # number of ReadReq MSHR hits 1126system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1412908 # number of WriteReq MSHR hits 1127system.cpu0.dcache.WriteReq_mshr_hits::total 1412908 # number of WriteReq MSHR hits 1128system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3986 # number of LoadLockedReq MSHR hits 1129system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3986 # number of LoadLockedReq MSHR hits 1130system.cpu0.dcache.demand_mshr_hits::cpu0.data 1949817 # number of demand (read+write) MSHR hits 1131system.cpu0.dcache.demand_mshr_hits::total 1949817 # number of demand (read+write) MSHR hits 1132system.cpu0.dcache.overall_mshr_hits::cpu0.data 1949817 # number of overall MSHR hits 1133system.cpu0.dcache.overall_mshr_hits::total 1949817 # number of overall MSHR hits 1134system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 858578 # number of ReadReq MSHR misses 1135system.cpu0.dcache.ReadReq_mshr_misses::total 858578 # number of ReadReq MSHR misses 1136system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257849 # number of WriteReq MSHR misses 1137system.cpu0.dcache.WriteReq_mshr_misses::total 257849 # number of WriteReq MSHR misses 1138system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13206 # number of LoadLockedReq MSHR misses 1139system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13206 # number of LoadLockedReq MSHR misses 1140system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses 1141system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses 1142system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses 1143system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses 1144system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses 1145system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses 1146system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles 1147system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles 1148system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles 1149system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles 1150system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles 1151system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles 1152system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles 1153system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles 1154system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles 1157system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles 1158system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles 1161system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles 1163system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles 1164system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses 1165system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses 1166system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses 1167system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses 1168system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses 1169system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses 1170system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses 1171system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses 1172system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses 1173system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses 1174system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses 1175system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses 1176system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency 1177system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency 1178system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency 1179system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency 1180system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency 1181system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency 1182system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency 1183system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency 1184system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency 1185system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency 1186system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency 1187system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency | 1122system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks 1123system.cpu0.dcache.writebacks::total 749955 # number of writebacks 1124system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits 1125system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits 1126system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits 1127system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits 1128system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits 1129system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits 1130system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits 1131system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits 1132system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits 1133system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits 1134system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses 1135system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses 1136system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses 1137system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses 1138system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses 1139system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses 1140system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses 1141system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses 1142system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses 1143system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses 1144system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses 1145system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses 1146system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles 1147system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles 1148system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles 1149system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles 1150system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles 1151system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles 1152system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles 1153system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles 1154system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles 1157system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles 1158system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles 1161system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles 1163system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles 1164system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses 1165system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses 1166system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses 1167system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses 1168system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses 1169system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses 1170system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses 1171system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses 1172system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses 1173system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses 1174system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses 1175system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses 1176system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency 1177system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency 1178system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency 1179system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency 1180system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency 1181system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency 1182system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency 1183system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency 1184system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency 1185system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency 1186system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency 1187system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency |
| 1188system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1189system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1190system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1191system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1192system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1193system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1194system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1195system.cpu1.dtb.fetch_hits 0 # ITB hits 1196system.cpu1.dtb.fetch_misses 0 # ITB misses 1197system.cpu1.dtb.fetch_acv 0 # ITB acv 1198system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1188system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1189system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1190system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1191system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1192system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1193system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1194system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1195system.cpu1.dtb.fetch_hits 0 # ITB hits 1196system.cpu1.dtb.fetch_misses 0 # ITB misses 1197system.cpu1.dtb.fetch_acv 0 # ITB acv 1198system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1199system.cpu1.dtb.read_hits 2657978 # DTB read hits 1200system.cpu1.dtb.read_misses 12789 # DTB read misses 1201system.cpu1.dtb.read_acv 27 # DTB read access violations 1202system.cpu1.dtb.read_accesses 325192 # DTB read accesses 1203system.cpu1.dtb.write_hits 1642917 # DTB write hits 1204system.cpu1.dtb.write_misses 2443 # DTB write misses | 1199system.cpu1.dtb.read_hits 1943067 # DTB read hits 1200system.cpu1.dtb.read_misses 10795 # DTB read misses 1201system.cpu1.dtb.read_acv 23 # DTB read access violations 1202system.cpu1.dtb.read_accesses 324453 # DTB read accesses 1203system.cpu1.dtb.write_hits 1254400 # DTB write hits 1204system.cpu1.dtb.write_misses 2201 # DTB write misses |
| 1205system.cpu1.dtb.write_acv 63 # DTB write access violations | 1205system.cpu1.dtb.write_acv 63 # DTB write access violations |
| 1206system.cpu1.dtb.write_accesses 132832 # DTB write accesses 1207system.cpu1.dtb.data_hits 4300895 # DTB hits 1208system.cpu1.dtb.data_misses 15232 # DTB misses 1209system.cpu1.dtb.data_acv 90 # DTB access violations 1210system.cpu1.dtb.data_accesses 458024 # DTB accesses 1211system.cpu1.itb.fetch_hits 468004 # ITB hits 1212system.cpu1.itb.fetch_misses 6860 # ITB misses 1213system.cpu1.itb.fetch_acv 223 # ITB acv 1214system.cpu1.itb.fetch_accesses 474864 # ITB accesses | 1206system.cpu1.dtb.write_accesses 132933 # DTB write accesses 1207system.cpu1.dtb.data_hits 3197467 # DTB hits 1208system.cpu1.dtb.data_misses 12996 # DTB misses 1209system.cpu1.dtb.data_acv 86 # DTB access violations 1210system.cpu1.dtb.data_accesses 457386 # DTB accesses 1211system.cpu1.itb.fetch_hits 434450 # ITB hits 1212system.cpu1.itb.fetch_misses 7705 # ITB misses 1213system.cpu1.itb.fetch_acv 232 # ITB acv 1214system.cpu1.itb.fetch_accesses 442155 # ITB accesses |
| 1215system.cpu1.itb.read_hits 0 # DTB read hits 1216system.cpu1.itb.read_misses 0 # DTB read misses 1217system.cpu1.itb.read_acv 0 # DTB read access violations 1218system.cpu1.itb.read_accesses 0 # DTB read accesses 1219system.cpu1.itb.write_hits 0 # DTB write hits 1220system.cpu1.itb.write_misses 0 # DTB write misses 1221system.cpu1.itb.write_acv 0 # DTB write access violations 1222system.cpu1.itb.write_accesses 0 # DTB write accesses 1223system.cpu1.itb.data_hits 0 # DTB hits 1224system.cpu1.itb.data_misses 0 # DTB misses 1225system.cpu1.itb.data_acv 0 # DTB access violations 1226system.cpu1.itb.data_accesses 0 # DTB accesses | 1215system.cpu1.itb.read_hits 0 # DTB read hits 1216system.cpu1.itb.read_misses 0 # DTB read misses 1217system.cpu1.itb.read_acv 0 # DTB read access violations 1218system.cpu1.itb.read_accesses 0 # DTB read accesses 1219system.cpu1.itb.write_hits 0 # DTB write hits 1220system.cpu1.itb.write_misses 0 # DTB write misses 1221system.cpu1.itb.write_acv 0 # DTB write access violations 1222system.cpu1.itb.write_accesses 0 # DTB write accesses 1223system.cpu1.itb.data_hits 0 # DTB hits 1224system.cpu1.itb.data_misses 0 # DTB misses 1225system.cpu1.itb.data_acv 0 # DTB access violations 1226system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1227system.cpu1.numCycles 24425153 # number of cpu cycles simulated | 1227system.cpu1.numCycles 16039611 # number of cpu cycles simulated |
| 1228system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1229system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1228system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1229system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1230system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups 1231system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted 1232system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect 1233system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups 1234system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits | 1230system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups 1231system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted 1232system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect 1233system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups 1234system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits |
| 1235system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1235system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1236system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. 1237system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. 1238system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss 1239system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed 1240system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered 1241system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken 1242system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked 1243system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing 1244system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked 1245system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1246system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps 1247system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions 1248system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR 1249system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched 1250system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed 1251system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) | 1236system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target. 1237system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions. 1238system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss 1239system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed 1240system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered 1241system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken 1242system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked 1243system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing 1244system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked 1245system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1246system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps 1247system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions 1248system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 1249system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched 1250system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed 1251system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) |
| 1254system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1254system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1255system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total) 1256system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) 1259system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total) 1260system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) | 1255system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) 1256system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) 1259system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) 1260system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) |
| 1264system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1266system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1264system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1266system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1267system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) 1268system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle 1269system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle 1270system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle 1271system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked 1272system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running 1273system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking 1274system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing 1275system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch 1276system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction 1277system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode 1278system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode 1279system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing 1280system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle 1281system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking 1282system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst 1283system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running 1284system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking 1285system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename 1286system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full 1287system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full 1288system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full 1289system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed 1290system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made 1291system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups 1292system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups 1293system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed 1294system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing 1295system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed 1296system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed 1297system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer 1298system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. 1299system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. 1300system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. 1301system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. 1302system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) 1303system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ 1304system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued 1305system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued 1306system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling 1307system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph 1308system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed 1309system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle | 1267system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) 1268system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle 1269system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle 1270system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle 1271system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked 1272system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running 1273system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking 1274system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing 1275system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch 1276system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction 1277system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode 1278system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode 1279system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing 1280system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle 1281system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking 1282system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst 1283system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running 1284system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking 1285system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename 1286system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full 1287system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full 1288system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full 1289system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed 1290system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made 1291system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups 1292system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups 1293system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed 1294system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing 1295system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed 1296system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed 1297system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer 1298system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. 1299system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. 1300system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. 1301system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. 1302system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) 1303system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ 1304system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued 1305system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued 1306system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling 1307system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph 1308system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed 1309system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle 1310system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle 1311system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle |
| 1312system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1312system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1313system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle 1314system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle 1315system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle 1316system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle 1317system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle 1318system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle 1319system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle 1320system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle 1321system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle | 1313system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle 1314system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle 1315system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle 1316system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle 1317system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle 1318system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle 1319system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle 1320system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle 1321system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle |
| 1322system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1323system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1324system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1322system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1323system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1324system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1325system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle | 1325system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle |
| 1326system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1326system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1327system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available 1347system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available 1348system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available 1349system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available 1350system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available 1351system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available 1352system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available 1353system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available 1354system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available | 1327system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available 1328system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available 1329system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available 1330system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available 1331system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available 1332system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available 1333system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available 1334system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available 1335system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available 1336system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available 1337system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available 1338system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available 1339system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available 1340system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available 1341system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available 1342system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available 1343system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available 1344system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available 1345system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available 1346system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available 1347system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available 1348system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available 1349system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available 1350system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available 1351system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available 1352system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available 1353system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available 1354system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available 1355system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available 1356system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available 1357system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available |
| 1358system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1358system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1359system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1360system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued 1361system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued 1362system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued 1363system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued 1364system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued 1365system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued 1366system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued 1367system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued 1368system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued 1369system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued 1377system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued 1378system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued 1379system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued 1380system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued 1381system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued 1382system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued 1383system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued 1384system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued 1385system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued 1386system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued 1387system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued 1388system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued 1389system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued 1390system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued 1391system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued 1392system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued | 1360system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued 1361system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued 1362system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued 1363system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued 1364system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued 1365system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued 1366system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued 1367system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued 1368system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued 1369system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued 1370system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued 1371system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued 1372system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued 1373system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued 1374system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued 1375system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued 1376system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued 1377system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued 1378system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued 1379system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued 1380system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued 1381system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued 1382system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued 1383system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued 1384system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued 1385system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued 1386system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued 1387system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued 1388system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued 1389system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued 1390system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued 1391system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued 1392system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued |
| 1393system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1393system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1394system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued 1395system.cpu1.iq.rate 0.571646 # Inst issue rate 1396system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested 1397system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) 1398system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads 1399system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes 1400system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses 1401system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads 1402system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes 1403system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses 1404system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses 1405system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses 1406system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores | 1394system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued 1395system.cpu1.iq.rate 0.599231 # Inst issue rate 1396system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested 1397system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) 1398system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads 1399system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes 1400system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses 1401system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads 1402system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes 1403system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses 1404system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses 1405system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses 1406system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores |
| 1407system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1407system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1408system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed 1409system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed 1410system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations 1411system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed | 1408system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed 1409system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed 1410system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations 1411system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed |
| 1412system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1413system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1412system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1413system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1414system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled 1415system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked | 1414system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled 1415system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked |
| 1416system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1416system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1417system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing 1418system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking 1419system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking 1420system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ 1421system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch 1422system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions 1423system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions 1424system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions 1425system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall 1426system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall 1427system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations 1428system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly 1429system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly 1430system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute 1431system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions 1432system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed 1433system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute | 1417system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing 1418system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking 1419system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking 1420system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ 1421system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch 1422system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions 1423system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions 1424system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions 1425system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall 1426system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall 1427system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations 1428system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly 1429system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly 1430system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute 1431system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions 1432system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed 1433system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute |
| 1434system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1434system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1435system.cpu1.iew.exec_nop 825136 # number of nop insts executed 1436system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed 1437system.cpu1.iew.exec_branches 2168898 # Number of branches executed 1438system.cpu1.iew.exec_stores 1651079 # Number of stores executed 1439system.cpu1.iew.exec_rate 0.566055 # Inst execution rate 1440system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit 1441system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back 1442system.cpu1.iew.wb_producers 6651311 # num instructions producing a value 1443system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value | 1435system.cpu1.iew.exec_nop 509280 # number of nop insts executed 1436system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed 1437system.cpu1.iew.exec_branches 1421889 # Number of branches executed 1438system.cpu1.iew.exec_stores 1262534 # Number of stores executed 1439system.cpu1.iew.exec_rate 0.593631 # Inst execution rate 1440system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit 1441system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back 1442system.cpu1.iew.wb_producers 4419848 # num instructions producing a value 1443system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value |
| 1444system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1444system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1445system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle 1446system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back | 1445system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle 1446system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back |
| 1447system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1447system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1448system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit 1449system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards 1450system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted 1451system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle | 1448system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit 1449system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards 1450system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted 1451system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle 1452system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle 1453system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle |
| 1454system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1454system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1455system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle 1456system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle 1457system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle 1458system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle 1459system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle 1460system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle 1461system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle 1462system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle 1463system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle | 1455system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle 1456system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle 1457system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle 1458system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle 1459system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle 1460system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle 1461system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle 1462system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle 1463system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle |
| 1464system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1465system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1466system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1464system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1465system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1466system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1467system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle 1468system.cpu1.commit.committedInsts 13515996 # Number of instructions committed 1469system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed | 1467system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle 1468system.cpu1.commit.committedInsts 9315763 # Number of instructions committed 1469system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed |
| 1470system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1470system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1471system.cpu1.commit.refs 3973553 # Number of memory references committed 1472system.cpu1.commit.loads 2406453 # Number of loads committed 1473system.cpu1.commit.membars 57533 # Number of memory barriers committed 1474system.cpu1.commit.branches 2017672 # Number of branches committed 1475system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. 1476system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. 1477system.cpu1.commit.function_calls 216490 # Number of function calls committed. 1478system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached | 1471system.cpu1.commit.refs 2968800 # Number of memory references committed 1472system.cpu1.commit.loads 1769624 # Number of loads committed 1473system.cpu1.commit.membars 44277 # Number of memory barriers committed 1474system.cpu1.commit.branches 1334383 # Number of branches committed 1475system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. 1476system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. 1477system.cpu1.commit.function_calls 148923 # Number of function calls committed. 1478system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached |
| 1479system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1479system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1480system.cpu1.rob.rob_reads 36803153 # The number of ROB reads 1481system.cpu1.rob.rob_writes 31994561 # The number of ROB writes 1482system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself 1483system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling 1484system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1485system.cpu1.committedInsts 12791729 # Number of Instructions Simulated 1486system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated 1487system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated 1488system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction 1489system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads 1490system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle 1491system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads 1492system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads 1493system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes 1494system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads 1495system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes 1496system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads 1497system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes 1498system.cpu1.icache.replacements 297472 # number of replacements 1499system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use 1500system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks. 1501system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. 1502system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks. 1503system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. 1504system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor 1505system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy 1506system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy 1507system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits 1508system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits 1509system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits 1510system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits 1511system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits 1512system.cpu1.icache.overall_hits::total 1814153 # number of overall hits 1513system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses 1514system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses 1515system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses 1516system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses 1517system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses 1518system.cpu1.icache.overall_misses::total 311692 # number of overall misses 1519system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles 1520system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles 1521system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles 1522system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles 1523system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles 1524system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles 1525system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses) 1526system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses) 1527system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses 1528system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses 1529system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses 1530system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses 1531system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses 1532system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses 1533system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses 1534system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses 1535system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses 1536system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses 1537system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency 1538system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency 1539system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency 1540system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency 1541system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency 1542system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency 1543system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked 1544system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked 1545system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked 1546system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked 1547system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked 1548system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked | 1480system.cpu1.rob.rob_reads 25106022 # The number of ROB reads 1481system.cpu1.rob.rob_writes 21862282 # The number of ROB writes 1482system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself 1483system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling 1484system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1485system.cpu1.committedInsts 8868192 # Number of Instructions Simulated 1486system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated 1487system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated 1488system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction 1489system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads 1490system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle 1491system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads 1492system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads 1493system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes 1494system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads 1495system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes 1496system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads 1497system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes 1498system.cpu1.icache.replacements 223384 # number of replacements 1499system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use 1500system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. 1501system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. 1502system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. 1503system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. 1504system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor 1505system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy 1506system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy 1507system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits 1508system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits 1509system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits 1510system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits 1511system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits 1512system.cpu1.icache.overall_hits::total 1268764 # number of overall hits 1513system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses 1514system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses 1515system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses 1516system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses 1517system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses 1518system.cpu1.icache.overall_misses::total 232532 # number of overall misses 1519system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles 1520system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles 1521system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles 1522system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles 1523system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles 1524system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles 1525system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) 1526system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) 1527system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses 1528system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses 1529system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses 1530system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses 1531system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses 1532system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses 1533system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses 1534system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses 1535system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses 1536system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses 1537system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency 1538system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency 1539system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency 1540system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency 1541system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency 1542system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency 1543system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked 1544system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1545system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked 1546system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1547system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked 1548system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1549system.cpu1.icache.fast_writes 0 # number of fast writes performed 1550system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1549system.cpu1.icache.fast_writes 0 # number of fast writes performed 1550system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1551system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits 1552system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits 1553system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits 1554system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits 1555system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits 1556system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits 1557system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses 1558system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses 1559system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses 1560system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses 1561system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses 1562system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses 1563system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles 1564system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles 1565system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles 1566system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles 1567system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles 1568system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles 1569system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses 1570system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses 1571system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses 1572system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses 1573system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses 1574system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses 1575system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency 1576system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency 1577system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency 1578system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency 1579system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency 1580system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency | 1551system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits 1552system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits 1553system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits 1554system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits 1555system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits 1556system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits 1557system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses 1558system.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses 1559system.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses 1560system.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses 1561system.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses 1562system.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses 1563system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles 1564system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles 1565system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles 1566system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles 1567system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles 1568system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles 1569system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses 1570system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses 1571system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses 1572system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses 1573system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses 1574system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses 1575system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency 1576system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency 1577system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency 1578system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency 1579system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency 1580system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency |
| 1581system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1581system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1582system.cpu1.dcache.replacements 296647 # number of replacements 1583system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use 1584system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks. 1585system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks. 1586system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks. 1587system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit. 1588system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor 1589system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy 1590system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy 1591system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits 1592system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits 1593system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits 1594system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits 1595system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits 1596system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits 1597system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits 1598system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits 1599system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits 1600system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits 1601system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits 1602system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits 1603system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses 1604system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses 1605system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses 1606system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses 1607system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses 1608system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses 1609system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses 1610system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses 1611system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses 1612system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses 1613system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses 1614system.cpu1.dcache.overall_misses::total 774607 # number of overall misses 1615system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles 1616system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles 1617system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles 1618system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles 1619system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles 1620system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles 1621system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles 1622system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles 1623system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles 1624system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles 1625system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles 1626system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles 1627system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) 1628system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) 1629system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) 1630system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) 1631system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) 1632system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) 1633system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses) 1634system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses) 1635system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses 1636system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses 1637system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses 1638system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses 1639system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses 1640system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses 1641system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses 1642system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency 1659system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency 1660system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency 1661system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency 1662system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency 1663system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked 1664system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked 1665system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked 1666system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked 1667system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked 1668system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked | 1582system.cpu1.dcache.replacements 107089 # number of replacements 1583system.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use 1584system.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks. 1585system.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks. 1586system.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks. 1587system.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit. 1588system.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor 1589system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy 1590system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy 1591system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits 1592system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits 1593system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits 1594system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits 1595system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits 1596system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits 1597system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits 1598system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits 1599system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits 1600system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits 1601system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits 1602system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits 1603system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses 1604system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses 1605system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses 1606system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses 1607system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses 1608system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses 1609system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses 1610system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses 1611system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses 1612system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses 1613system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses 1614system.cpu1.dcache.overall_misses::total 423319 # number of overall misses 1615system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # number of ReadReq miss cycles 1616system.cpu1.dcache.ReadReq_miss_latency::total 3148302000 # number of ReadReq miss cycles 1617system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8860772084 # number of WriteReq miss cycles 1618system.cpu1.dcache.WriteReq_miss_latency::total 8860772084 # number of WriteReq miss cycles 1619system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54690000 # number of LoadLockedReq miss cycles 1620system.cpu1.dcache.LoadLockedReq_miss_latency::total 54690000 # number of LoadLockedReq miss cycles 1621system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22134000 # number of StoreCondReq miss cycles 1622system.cpu1.dcache.StoreCondReq_miss_latency::total 22134000 # number of StoreCondReq miss cycles 1623system.cpu1.dcache.demand_miss_latency::cpu1.data 12009074084 # number of demand (read+write) miss cycles 1624system.cpu1.dcache.demand_miss_latency::total 12009074084 # number of demand (read+write) miss cycles 1625system.cpu1.dcache.overall_miss_latency::cpu1.data 12009074084 # number of overall miss cycles 1626system.cpu1.dcache.overall_miss_latency::total 12009074084 # number of overall miss cycles 1627system.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses) 1628system.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses) 1629system.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses) 1630system.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses) 1631system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses) 1632system.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses) 1633system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses) 1634system.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses) 1635system.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses 1636system.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses 1637system.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses 1638system.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses 1639system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses 1640system.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses 1641system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses 1642system.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # average StoreCondReq miss latency 1659system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency 1660system.cpu1.dcache.demand_avg_miss_latency::total 28368.852057 # average overall miss latency 1661system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency 1662system.cpu1.dcache.overall_avg_miss_latency::total 28368.852057 # average overall miss latency 1663system.cpu1.dcache.blocked_cycles::no_mshrs 339060 # number of cycles access was blocked 1664system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1665system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked 1666system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1667system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked 1668system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1669system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1670system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1669system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1670system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1671system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks 1672system.cpu1.dcache.writebacks::total 225448 # number of writebacks 1673system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits 1674system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits 1675system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits 1676system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits 1677system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits 1678system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits 1679system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits 1680system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits 1681system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits 1682system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits 1683system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses 1684system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses 1685system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses 1686system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses 1695system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles 1696system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles 1697system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles 1698system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles 1699system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles 1700system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles 1701system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles 1702system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles 1703system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles 1704system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles 1705system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles 1706system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles 1707system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles 1708system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles 1709system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles 1710system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles 1711system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles 1712system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses 1714system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses 1715system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses 1716system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses 1717system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses 1719system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses 1720system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses 1721system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses 1722system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses 1723system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses 1724system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses 1725system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency 1726system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency 1727system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency 1728system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency 1729system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency 1731system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency 1732system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency | 1671system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks 1672system.cpu1.dcache.writebacks::total 70825 # number of writebacks 1673system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits 1674system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits 1675system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits 1676system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits 1677system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits 1678system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits 1679system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits 1680system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits 1681system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits 1682system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits 1683system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses 1684system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses 1685system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses 1686system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses 1695system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles 1696system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles 1697system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles 1698system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles 1699system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles 1700system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles 1701system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles 1702system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles 1703system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles 1704system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles 1705system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles 1706system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles 1707system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles 1708system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles 1709system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles 1710system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles 1711system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles 1712system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses 1714system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses 1715system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses 1716system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses 1717system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses 1719system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses 1720system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses 1721system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses 1722system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses 1723system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses 1724system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses 1725system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency 1726system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency 1727system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency 1728system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency 1729system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency 1731system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency 1732system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency |
| 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1745system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed 1746system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed 1747system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl 1748system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl 1749system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl 1750system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl 1751system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl 1752system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl 1753system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl 1754system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl 1755system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl 1756system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl 1757system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl 1758system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl 1759system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl 1760system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl 1761system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl 1762system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl 1763system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl 1764system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl 1765system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl | 1745system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed 1746system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed 1747system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl 1748system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl 1749system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl 1750system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl 1751system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl 1752system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl 1753system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl 1754system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl 1755system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl 1756system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl 1757system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl 1758system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl 1759system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl 1760system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl 1761system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl 1762system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl 1763system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl 1764system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl 1765system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl |
| 1766system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1767system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1768system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1766system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1767system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1768system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1769system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl 1770system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl 1771system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed 1772system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed 1773system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed 1774system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed 1775system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed 1776system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed 1777system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed 1778system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed 1779system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed 1780system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed 1781system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed 1782system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed 1783system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed 1784system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed 1785system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed 1786system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed 1787system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed 1788system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed 1789system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed 1790system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed 1791system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed 1792system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed 1793system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed 1794system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed 1795system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed 1796system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed 1797system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed 1798system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed 1799system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed 1800system.cpu0.kern.syscall::total 209 # number of syscalls executed | 1769system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl 1770system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl 1771system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed 1772system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed 1773system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed 1774system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed 1775system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed 1776system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed 1777system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed 1778system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed 1779system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed 1780system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed 1781system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed 1782system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed 1783system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed 1784system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed 1785system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed 1786system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed 1787system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed 1788system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed 1789system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed 1790system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed 1791system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed 1792system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed 1793system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed 1794system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed 1795system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed 1796system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed 1797system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed 1798system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed 1799system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed 1800system.cpu0.kern.syscall::total 202 # number of syscalls executed |
| 1801system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1801system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1802system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed 1803system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 1804system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 1805system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 1806system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed 1807system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed 1808system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed 1809system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed 1810system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed 1811system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed 1812system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed 1813system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed 1814system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed 1815system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed 1816system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed 1817system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed 1818system.cpu0.kern.callpal::total 154704 # number of callpals executed 1819system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches 1820system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches | 1802system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed 1803system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed 1804system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed 1805system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed 1806system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed 1807system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed 1808system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed 1809system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed 1810system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed 1811system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed 1812system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed 1813system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed 1814system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed 1815system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed 1816system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed 1817system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed 1818system.cpu0.kern.callpal::total 167505 # number of callpals executed 1819system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches 1820system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches |
| 1821system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 1821system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 1822system.cpu0.kern.mode_good::kernel 1271 1823system.cpu0.kern.mode_good::user 1272 | 1822system.cpu0.kern.mode_good::kernel 1255 1823system.cpu0.kern.mode_good::user 1256 |
| 1824system.cpu0.kern.mode_good::idle 0 | 1824system.cpu0.kern.mode_good::idle 0 |
| 1825system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches | 1825system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches |
| 1826system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1827system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 1826system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1827system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 1828system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches 1829system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode 1830system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode | 1828system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches 1829system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode 1830system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode |
| 1831system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 1831system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 1832system.cpu0.kern.swap_context 3083 # number of times the context was actually changed | 1832system.cpu0.kern.swap_context 3483 # number of times the context was actually changed |
| 1833system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1833system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1834system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed 1835system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed 1836system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl 1837system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl 1838system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl 1839system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl 1840system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl 1841system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl 1842system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl 1843system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl 1844system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl 1845system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl 1846system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl 1847system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl 1848system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl 1849system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl 1850system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl 1851system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl | 1834system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed 1835system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed 1836system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl 1837system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl 1838system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl 1839system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl 1840system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl 1841system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl 1842system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl 1843system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl 1844system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl 1845system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl 1846system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl 1847system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl 1848system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl 1849system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl 1850system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl 1851system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl |
| 1852system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1853system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1852system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1853system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1854system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl 1855system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl 1856system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed 1857system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed 1858system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed 1859system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed 1860system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed 1861system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed 1862system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed 1863system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed 1864system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed 1865system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed 1866system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed 1867system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed 1868system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed 1869system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed 1870system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed 1871system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed 1872system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed 1873system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed 1874system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed 1875system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed 1876system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed 1877system.cpu1.kern.syscall::total 117 # number of syscalls executed | 1854system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl 1855system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl 1856system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed 1857system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed 1858system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed 1859system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed 1860system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed 1861system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed 1862system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed 1863system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed 1864system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed 1865system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed 1866system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed 1867system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed 1868system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed 1869system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed 1870system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed 1871system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed 1872system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed 1873system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed 1874system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed 1875system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed 1876system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed 1877system.cpu1.kern.syscall::total 124 # number of syscalls executed |
| 1878system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1878system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1879system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed 1880system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1881system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 1882system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed 1883system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed 1884system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed 1885system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed 1886system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed 1887system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed 1888system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed 1889system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed 1890system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed 1891system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed 1892system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed 1893system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed | 1879system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed 1880system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed 1881system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed 1882system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed 1883system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed 1884system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed 1885system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed 1886system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed 1887system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed 1888system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed 1889system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed 1890system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed 1891system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed 1892system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed 1893system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed |
| 1894system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1894system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1895system.cpu1.kern.callpal::total 61585 # number of callpals executed 1896system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches 1897system.cpu1.kern.mode_switch::user 476 # number of protection mode switches 1898system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 1899system.cpu1.kern.mode_good::kernel 537 1900system.cpu1.kern.mode_good::user 476 1901system.cpu1.kern.mode_good::idle 61 1902system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches | 1895system.cpu1.kern.callpal::total 50665 # number of callpals executed 1896system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches 1897system.cpu1.kern.mode_switch::user 488 # number of protection mode switches 1898system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches 1899system.cpu1.kern.mode_good::kernel 704 1900system.cpu1.kern.mode_good::user 488 1901system.cpu1.kern.mode_good::idle 216 1902system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches |
| 1903system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1903system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1904system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches 1905system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches 1906system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode 1907system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode 1908system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode 1909system.cpu1.kern.swap_context 1166 # number of times the context was actually changed | 1904system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches 1905system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches 1906system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode 1907system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode 1908system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode 1909system.cpu1.kern.swap_context 1119 # number of times the context was actually changed |
| 1910 1911---------- End Simulation Statistics ---------- | 1910 1911---------- End Simulation Statistics ---------- |