| stats.txt (9348:44d31345e360) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.897858 # Number of seconds simulated 4sim_ticks 1897857556000 # Number of ticks simulated 5final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.897858 # Number of seconds simulated 4sim_ticks 1897857556000 # Number of ticks simulated 5final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 131170 # Simulator instruction rate (inst/s) 8host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4437782045 # Simulator tick rate (ticks/s) 10host_mem_usage 332328 # Number of bytes of host memory used 11host_seconds 427.66 # Real time elapsed on the host | 7host_inst_rate 54087 # Simulator instruction rate (inst/s) 8host_op_rate 54087 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1829896991 # Simulator tick rate (ticks/s) 10host_mem_usage 335972 # Number of bytes of host memory used 11host_seconds 1037.14 # Real time elapsed on the host |
| 12sim_insts 56096024 # Number of instructions simulated 13sim_ops 56096024 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory --- 888 unchanged lines hidden (view full) --- 908system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction 909system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads 910system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle 911system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads 912system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads 913system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes 914system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads 915system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes | 12sim_insts 56096024 # Number of instructions simulated 13sim_ops 56096024 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory --- 888 unchanged lines hidden (view full) --- 908system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction 909system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads 910system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle 911system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads 912system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads 913system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes 914system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads 915system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes |
| 916system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads 917system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes | 916system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads 917system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes |
| 918system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 919system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 920system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 921system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 922system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 923system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 924system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 925system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 134 unchanged lines hidden (view full) --- 1060system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses 1061system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses 1062system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses 1063system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses 1064system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses 1065system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses 1066system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles 1067system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles | 918system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 919system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 920system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 921system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 922system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 923system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 924system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 925system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 134 unchanged lines hidden (view full) --- 1060system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses 1061system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses 1062system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses 1063system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses 1064system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses 1065system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses 1066system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles 1067system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles |
| 1068system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles 1069system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles | 1068system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles 1069system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles |
| 1070system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles 1071system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles | 1070system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles 1071system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles |
| 1072system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles 1073system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles 1074system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles 1075system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles 1076system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles 1077system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles | 1072system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles 1073system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles 1074system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles 1075system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles 1076system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles 1077system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles |
| 1078system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) 1079system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) 1080system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) 1081system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) 1082system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) 1083system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) 1084system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) 1085system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1096system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses 1097system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses 1098system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses 1099system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses 1100system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses 1101system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses 1102system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency 1103system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency | 1078system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) 1079system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) 1080system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) 1081system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) 1082system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) 1083system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) 1084system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) 1085system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1096system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses 1097system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses 1098system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses 1099system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses 1100system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses 1101system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses 1102system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency 1103system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency |
| 1104system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency 1105system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency | 1104system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency 1105system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency |
| 1106system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency | 1106system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency 1107system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency |
| 1108system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency 1109system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency 1110system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency 1111system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency 1112system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency 1113system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency | 1108system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency 1109system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency 1110system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency 1111system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency 1112system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency 1113system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency |
| 1114system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked 1115system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked 1116system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked 1117system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1118system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked 1119system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked 1120system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1121system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 1140system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses 1141system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses 1142system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses 1143system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses 1144system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses 1145system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses 1146system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles 1147system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles | 1114system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked 1115system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked 1116system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked 1117system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked 1118system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked 1119system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked 1120system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1121system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 1140system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses 1141system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses 1142system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses 1143system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses 1144system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses 1145system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses 1146system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles 1147system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles |
| 1148system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles 1149system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles | 1148system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles 1149system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles |
| 1150system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles 1151system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles | 1150system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles 1151system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles |
| 1152system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles 1153system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles 1154system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles 1157system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles | 1152system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles 1153system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles 1154system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles 1155system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles 1156system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles 1157system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles |
| 1158system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles 1161system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles 1163system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles 1164system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses 1165system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses --- 4 unchanged lines hidden (view full) --- 1170system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses 1171system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses 1172system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses 1173system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses 1174system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses 1175system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses 1176system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency 1177system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency | 1158system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles 1161system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles 1163system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles 1164system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses 1165system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses --- 4 unchanged lines hidden (view full) --- 1170system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses 1171system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses 1172system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses 1173system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses 1174system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses 1175system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses 1176system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency 1177system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency |
| 1178system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency 1179system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency | 1178system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency 1179system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency |
| 1180system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency 1181system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency | 1180system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency 1181system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency |
| 1182system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency 1183system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency 1184system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency 1185system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency 1186system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency 1187system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency | 1182system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency 1183system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency 1184system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency 1185system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency 1186system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency 1187system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency |
| 1188system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1189system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1190system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1191system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1192system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1193system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1194system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1195system.cpu1.dtb.fetch_hits 0 # ITB hits --- 35 unchanged lines hidden (view full) --- 1231system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted 1232system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect 1233system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups 1234system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits 1235system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1236system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. 1237system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. 1238system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss | 1188system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1189system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1190system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1191system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1192system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1193system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1194system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1195system.cpu1.dtb.fetch_hits 0 # ITB hits --- 35 unchanged lines hidden (view full) --- 1231system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted 1232system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect 1233system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups 1234system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits 1235system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1236system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. 1237system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. 1238system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss |
| 1239system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed | 1239system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed |
| 1240system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered 1241system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken | 1240system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered 1241system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken |
| 1242system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked | 1242system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked |
| 1243system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing | 1243system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing |
| 1244system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked | 1244system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked |
| 1245system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1246system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps 1247system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions 1248system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR | 1245system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1246system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps 1247system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions 1248system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR |
| 1249system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched 1250system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed | 1249system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched 1250system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed |
| 1251system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1251system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) 1252system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) 1253system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) 1254system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1255system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) | 1255system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total) |
| 1256system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) | 1256system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) 1257system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) 1258system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) |
| 1259system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) | 1259system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total) |
| 1260system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) 1264system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1266system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1267system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) --- 4 unchanged lines hidden (view full) --- 1272system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running 1273system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking 1274system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing 1275system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch 1276system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction 1277system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode 1278system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode 1279system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing | 1260system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) 1261system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) 1262system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) 1263system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) 1264system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1265system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1266system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1267system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) --- 4 unchanged lines hidden (view full) --- 1272system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running 1273system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking 1274system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing 1275system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch 1276system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction 1277system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode 1278system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode 1279system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing |
| 1280system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle 1281system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking 1282system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst 1283system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running | 1280system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle 1281system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking 1282system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst 1283system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running |
| 1284system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking | 1284system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking |
| 1285system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename | 1285system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename |
| 1286system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full 1287system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full 1288system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full | 1286system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full 1287system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full 1288system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full |
| 1289system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed 1290system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made 1291system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups | 1289system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed 1290system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made 1291system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups |
| 1292system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups 1293system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed | 1292system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups 1293system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed |
| 1294system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing | 1294system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing |
| 1295system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed 1296system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed 1297system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer 1298system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. 1299system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. 1300system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. 1301system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. 1302system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) --- 107 unchanged lines hidden (view full) --- 1410system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations 1411system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed 1412system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1413system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1414system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled 1415system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked 1416system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1417system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing | 1295system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed 1296system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed 1297system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer 1298system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. 1299system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. 1300system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. 1301system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. 1302system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) --- 107 unchanged lines hidden (view full) --- 1410system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations 1411system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed 1412system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1413system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1414system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled 1415system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked 1416system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1417system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing |
| 1418system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking | 1418system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking |
| 1419system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking 1420system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ | 1419system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking 1420system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ |
| 1421system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch | 1421system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch |
| 1422system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions 1423system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions 1424system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions 1425system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall 1426system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall 1427system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations 1428system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly 1429system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly --- 58 unchanged lines hidden (view full) --- 1488system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction 1489system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads 1490system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle 1491system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads 1492system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads 1493system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes 1494system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads 1495system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes | 1422system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions 1423system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions 1424system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions 1425system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall 1426system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall 1427system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations 1428system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly 1429system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly --- 58 unchanged lines hidden (view full) --- 1488system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction 1489system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads 1490system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle 1491system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads 1492system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads 1493system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes 1494system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads 1495system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes |
| 1496system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads 1497system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes | 1496system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads 1497system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes |
| 1498system.cpu1.icache.replacements 297472 # number of replacements 1499system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use | 1498system.cpu1.icache.replacements 297472 # number of replacements 1499system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use |
| 1500system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. | 1500system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks. |
| 1501system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. | 1501system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. |
| 1502system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. | 1502system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks. |
| 1503system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. 1504system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor 1505system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy 1506system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy | 1503system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. 1504system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor 1505system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy 1506system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy |
| 1507system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits 1508system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits 1509system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits 1510system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits 1511system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits 1512system.cpu1.icache.overall_hits::total 1814154 # number of overall hits | 1507system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits 1508system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits 1509system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits 1510system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits 1511system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits 1512system.cpu1.icache.overall_hits::total 1814153 # number of overall hits |
| 1513system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses 1514system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses 1515system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses 1516system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses 1517system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses 1518system.cpu1.icache.overall_misses::total 311692 # number of overall misses 1519system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles 1520system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles 1521system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles 1522system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles 1523system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles 1524system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles | 1513system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses 1514system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses 1515system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses 1516system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses 1517system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses 1518system.cpu1.icache.overall_misses::total 311692 # number of overall misses 1519system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles 1520system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles 1521system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles 1522system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles 1523system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles 1524system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles |
| 1525system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) 1526system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) 1527system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses 1528system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses 1529system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses 1530system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses | 1525system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses) 1526system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses) 1527system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses 1528system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses 1529system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses 1530system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses |
| 1531system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses 1532system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses 1533system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses 1534system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses 1535system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses 1536system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses 1537system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency 1538system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency --- 62 unchanged lines hidden (view full) --- 1601system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits 1602system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits 1603system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses 1604system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses 1605system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses 1606system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses 1607system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses 1608system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses | 1531system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses 1532system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses 1533system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses 1534system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses 1535system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses 1536system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses 1537system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency 1538system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency --- 62 unchanged lines hidden (view full) --- 1601system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits 1602system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits 1603system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses 1604system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses 1605system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses 1606system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses 1607system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses 1608system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses |
| 1609system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses 1610system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses | 1609system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses 1610system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses |
| 1611system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses 1612system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses 1613system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses 1614system.cpu1.dcache.overall_misses::total 774607 # number of overall misses | 1611system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses 1612system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses 1613system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses 1614system.cpu1.dcache.overall_misses::total 774607 # number of overall misses |
| 1615system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles 1616system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles | 1615system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles 1616system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles |
| 1617system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles 1618system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles 1619system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles 1620system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles 1621system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles 1622system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles | 1617system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles 1618system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles 1619system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles 1620system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles 1621system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles 1622system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles |
| 1623system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles 1624system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles 1625system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles 1626system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles | 1623system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles 1624system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles 1625system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles 1626system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles |
| 1627system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) 1628system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) 1629system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) 1630system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) 1631system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) 1632system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) | 1627system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) 1628system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) 1629system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) 1630system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) 1631system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) 1632system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) |
| 1633system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses) 1634system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses) | 1633system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses) 1634system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses) |
| 1635system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses 1636system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses 1637system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses 1638system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses 1639system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses 1640system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses 1641system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses 1642system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses | 1635system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses 1636system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses 1637system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses 1638system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses 1639system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses 1640system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses 1641system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses 1642system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses |
| 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses | 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses |
| 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses | 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses |
| 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency | 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency |
| 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency | 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency |
| 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency 1659system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency 1660system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency 1661system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency 1662system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency | 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency 1659system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency 1660system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency 1661system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency 1662system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency |
| 1663system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked 1664system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked 1665system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked 1666system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked 1667system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked 1668system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked 1669system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1670system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses | 1663system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked 1664system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked 1665system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked 1666system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked 1667system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked 1668system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked 1669system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1670system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses |
| 1695system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles 1696system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles | 1695system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles 1696system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles |
| 1697system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles 1698system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles 1699system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles 1700system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles 1701system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles 1702system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles | 1697system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles 1698system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles 1699system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles 1700system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles 1701system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles 1702system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles |
| 1703system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles 1704system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles 1705system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles 1706system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles | 1703system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles 1704system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles 1705system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles 1706system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles |
| 1707system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles 1708system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles 1709system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles 1710system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles 1711system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles 1712system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses 1714system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses 1715system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses 1716system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses 1717system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses | 1707system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles 1708system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles 1709system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles 1710system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles 1711system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles 1712system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles 1713system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses 1714system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses 1715system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses 1716system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses 1717system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses |
| 1719system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses 1720system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses | 1719system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses 1720system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses |
| 1721system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses 1722system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses 1723system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses 1724system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses | 1721system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses 1722system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses 1723system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses 1724system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses |
| 1725system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency 1726system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency | 1725system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency 1726system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency |
| 1727system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency 1728system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency 1729system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency 1731system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency 1732system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency | 1727system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency 1728system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency 1729system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency 1731system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency 1732system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency |
| 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency | 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency |
| 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu0.kern.inst.arm 0 # number of arm instructions executed --- 167 unchanged lines hidden --- | 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1744system.cpu0.kern.inst.arm 0 # number of arm instructions executed --- 167 unchanged lines hidden --- |