| stats.txt (9096:8971a998190a) | stats.txt (9134:275232ad377d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.900531 # Number of seconds simulated 4sim_ticks 1900530800500 # Number of ticks simulated 5final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.900530 # Number of seconds simulated 4sim_ticks 1900530295500 # Number of ticks simulated 5final_tick 1900530295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 119697 # Simulator instruction rate (inst/s) 8host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3968630665 # Simulator tick rate (ticks/s) 10host_mem_usage 303044 # Number of bytes of host memory used 11host_seconds 478.89 # Real time elapsed on the host 12sim_insts 57321719 # Number of instructions simulated 13sim_ops 57321719 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory | 7host_inst_rate 128893 # Simulator instruction rate (inst/s) 8host_op_rate 128893 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4273489918 # Simulator tick rate (ticks/s) 10host_mem_usage 307500 # Number of bytes of host memory used 11host_seconds 444.73 # Real time elapsed on the host 12sim_insts 57321882 # Number of instructions simulated 13sim_ops 57321882 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 875200 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24658176 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu1.inst 108032 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 692736 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28984960 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 875200 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 108032 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 983232 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7922432 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7922432 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13675 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 385284 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_reads::cpu1.inst 1688 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10824 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 452890 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 123788 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 123788 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 460503 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12974366 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_read::cpu1.inst 56843 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 364496 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15250986 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 460503 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 56843 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 517346 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4168538 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4168538 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4168538 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 460503 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12974366 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 345959 # number of replacements 52system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use 53system.l2c.total_refs 2564962 # Total number of references to valid blocks. 54system.l2c.sampled_refs 411131 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.238795 # Average number of references to valid blocks. | 48system.physmem.bw_total::cpu1.inst 56843 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 364496 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19419523 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 345965 # number of replacements 52system.l2c.tagsinuse 65264.028554 # Cycle average of tags in use 53system.l2c.total_refs 2565305 # Total number of references to valid blocks. 54system.l2c.sampled_refs 411137 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.239538 # Average number of references to valid blocks. |
| 56system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. | 56system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. |
| 57system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy | 57system.l2c.occ_blocks::writebacks 53566.065326 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 5313.128544 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 6099.641645 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 209.824884 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 75.368156 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.817353 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.081072 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.093073 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.003202 # Average percentage of cache occupancy |
| 66system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy | 66system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy |
| 68system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits 74system.l2c.Writeback_hits::total 806312 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits 90system.l2c.overall_hits::cpu0.data 817538 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits 92system.l2c.overall_hits::cpu1.data 145338 # number of overall hits 93system.l2c.overall_hits::total 2054695 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses | 68system.l2c.ReadReq_hits::cpu0.inst 778193 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 689575 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 314248 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 100958 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1882974 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 806039 # number of Writeback hits 74system.l2c.Writeback_hits::total 806039 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 439 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 613 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 128167 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 44386 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 172553 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 778193 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 817742 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 314248 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 145344 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2055527 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 778193 # number of overall hits 90system.l2c.overall_hits::cpu0.data 817742 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 314248 # number of overall hits 92system.l2c.overall_hits::cpu1.data 145344 # number of overall hits 93system.l2c.overall_hits::total 2055527 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13677 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 272973 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1705 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 853 # number of ReadReq misses |
| 98system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses | 98system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses |
| 99system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses | 99system.l2c.UpgradeReq_misses::cpu0.data 2871 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 1574 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 4445 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 724 # number of SCUpgradeReq misses |
| 103system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses | 103system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses |
| 104system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses 112system.l2c.demand_misses::total 412362 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses 114system.l2c.overall_misses::cpu0.data 386058 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10924 # number of overall misses 117system.l2c.overall_misses::total 412362 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles | 104system.l2c.SCUpgradeReq_misses::total 1471 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 113108 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 10072 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 123180 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13677 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 386081 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1705 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 10925 # number of demand (read+write) misses 112system.l2c.demand_misses::total 412388 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13677 # number of overall misses 114system.l2c.overall_misses::cpu0.data 386081 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1705 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10925 # number of overall misses 117system.l2c.overall_misses::total 412388 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 728382998 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14214430499 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 91270500 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 46668499 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 15080752496 # number of ReadReq miss cycles |
| 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles | 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles |
| 124system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles | 124system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 22402914 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500 # number of SCUpgradeReq miss cycles |
| 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles | 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles |
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miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency | 155system.l2c.ReadExReq_accesses::cpu0.data 241275 # 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miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.184950 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.416524 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.017272 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.320712 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.005396 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.069911 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.167100 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.017272 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.320712 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.005396 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.069911 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.167100 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52145.004620 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 900.034831 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 5040.025647 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3857.044199 # average SCUpgradeReq miss latency |
| 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency | 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency |
| 202system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency | 202system.l2c.SCUpgradeReq_avg_miss_latency::total 2111.828688 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 53674.391102 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52601.831266 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52601.831266 # average overall miss latency |
| 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed | 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed |
| 224system.l2c.writebacks::writebacks 82258 # number of writebacks 225system.l2c.writebacks::total 82258 # number of writebacks | 224system.l2c.writebacks::writebacks 82268 # number of writebacks 225system.l2c.writebacks::total 82268 # number of writebacks |
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| 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses | 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13676 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 272973 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 1688 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 853 # number of ReadReq MSHR misses |
| 239system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses | 239system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses |
| 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses | 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2871 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 1574 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 4445 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 724 # number of SCUpgradeReq MSHR misses |
| 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses | 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses |
| 245system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles | 245system.l2c.SCUpgradeReq_mshr_misses::total 1471 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 113108 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 10072 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 123180 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13676 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 386081 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 1688 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 10925 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 412370 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13676 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 386081 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 1688 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 10925 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 412370 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561190998 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939303500 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69880000 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36325000 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 11606699498 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114956000 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62989500 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 177945500 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29007500 # number of SCUpgradeReq MSHR miss cycles |
| 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles | 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles |
| 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles | 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 58887500 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4696029997 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427574999 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 5123604996 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 561190998 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15635333497 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 69880000 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 463899999 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 16730304494 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 561190998 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15635333497 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 69880000 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 463899999 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 16730304494 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820944530 # number of ReadReq MSHR uncacheable cycles |
| 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles | 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles |
| 285system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles | 285system.l2c.ReadReq_mshr_uncacheable_latency::total 837594530 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194274500 # number of WriteReq MSHR uncacheable cycles |
| 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles | 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles |
| 288system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles | 288system.l2c.WriteReq_mshr_uncacheable_latency::total 1553694500 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015219030 # number of overall MSHR uncacheable cycles |
| 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles | 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles |
| 291system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency | 291system.l2c.overall_mshr_uncacheable_latency::total 2391289030 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283594 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008378 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.133133 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942857 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781918 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.878806 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.932990 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960154 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.946589 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.468793 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184950 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.416524 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.167092 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.167092 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735 # average SCUpgradeReq mshr miss latency |
| 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency | 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency |
| 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency | 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency |
| 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 350system.iocache.replacements 41698 # number of replacements | 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 350system.iocache.replacements 41698 # number of replacements |
| 351system.iocache.tagsinuse 0.465240 # Cycle average of tags in use | 351system.iocache.tagsinuse 0.465235 # Cycle average of tags in use |
| 352system.iocache.total_refs 0 # Total number of references to valid blocks. 353system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. 354system.iocache.avg_refs 0 # Average number of references to valid blocks. 355system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. | 352system.iocache.total_refs 0 # Total number of references to valid blocks. 353system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. 354system.iocache.avg_refs 0 # Average number of references to valid blocks. 355system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. |
| 356system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor | 356system.iocache.occ_blocks::tsunami.ide 0.465235 # Average occupied blocks per requestor |
| 357system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 178 # number of ReadReq misses 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 363system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 366system.iocache.overall_misses::total 41730 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles | 357system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 178 # number of ReadReq misses 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 363system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 366system.iocache.overall_misses::total 41730 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles |
| 369system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles | 369system.iocache.WriteReq_miss_latency::tsunami.ide 7637828806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 7637828806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 7659067804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 7659067804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 7659067804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 7659067804 # number of overall miss cycles |
| 375system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 379system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency | 375system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 379system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency |
| 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked | 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 183813.746775 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 183538.648550 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 183538.648550 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 7685000 # number of cycles access was blocked |
| 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 401system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked | 401system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked |
| 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 403system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked | 403system.iocache.avg_blocked_cycles::no_mshrs 1074.524609 # average number of cycles each access was blocked |
| 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks 409system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 413system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles | 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks 409system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 413system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles |
| 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles | 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476969000 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 5476969000 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 5488951000 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 5488951000 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 5488951000 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 5488951000 # number of overall MSHR miss cycles |
| 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency | 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency |
| 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency | 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency |
| 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 458system.cpu0.dtb.read_hits 8334313 # DTB read hits 459system.cpu0.dtb.read_misses 29661 # DTB read misses 460system.cpu0.dtb.read_acv 416 # DTB read access violations 461system.cpu0.dtb.read_accesses 650050 # DTB read accesses 462system.cpu0.dtb.write_hits 5360515 # DTB write hits 463system.cpu0.dtb.write_misses 6017 # DTB write misses 464system.cpu0.dtb.write_acv 275 # DTB write access violations 465system.cpu0.dtb.write_accesses 211537 # DTB write accesses 466system.cpu0.dtb.data_hits 13694828 # DTB hits 467system.cpu0.dtb.data_misses 35678 # DTB misses 468system.cpu0.dtb.data_acv 691 # DTB access violations 469system.cpu0.dtb.data_accesses 861587 # DTB accesses 470system.cpu0.itb.fetch_hits 972456 # ITB hits 471system.cpu0.itb.fetch_misses 29747 # ITB misses 472system.cpu0.itb.fetch_acv 802 # ITB acv 473system.cpu0.itb.fetch_accesses 1002203 # ITB accesses | 458system.cpu0.dtb.read_hits 8334041 # DTB read hits 459system.cpu0.dtb.read_misses 29708 # DTB read misses 460system.cpu0.dtb.read_acv 432 # DTB read access violations 461system.cpu0.dtb.read_accesses 650283 # DTB read accesses 462system.cpu0.dtb.write_hits 5360343 # DTB write hits 463system.cpu0.dtb.write_misses 6029 # DTB write misses 464system.cpu0.dtb.write_acv 281 # DTB write access violations 465system.cpu0.dtb.write_accesses 211361 # DTB write accesses 466system.cpu0.dtb.data_hits 13694384 # DTB hits 467system.cpu0.dtb.data_misses 35737 # DTB misses 468system.cpu0.dtb.data_acv 713 # DTB access violations 469system.cpu0.dtb.data_accesses 861644 # DTB accesses 470system.cpu0.itb.fetch_hits 975254 # ITB hits 471system.cpu0.itb.fetch_misses 26821 # ITB misses 472system.cpu0.itb.fetch_acv 801 # ITB acv 473system.cpu0.itb.fetch_accesses 1002075 # ITB accesses |
| 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses | 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses |
| 486system.cpu0.numCycles 107494535 # number of cpu cycles simulated | 486system.cpu0.numCycles 107505653 # number of cpu cycles simulated |
| 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 489system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits | 489system.cpu0.BPredUnit.lookups 11783453 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 9875598 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 345606 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 8356965 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5072042 # Number of BTB hits |
| 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 495system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) | 495system.cpu0.BPredUnit.usedRAS 768478 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 29315 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 25158431 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 60438649 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 11783453 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 5840520 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 11478099 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1678793 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 36446213 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 35059 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 187963 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 310129 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 7506544 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 232672 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 74721559 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.808852 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.135528 # Number of instructions fetched each cycle (Total) |
| 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 514system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) | 514system.cpu0.fetch.rateDist::0 63243460 84.64% 84.64% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 740935 0.99% 85.63% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1559450 2.09% 87.72% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 686263 0.92% 88.64% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2492339 3.34% 91.97% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 528695 0.71% 92.68% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 568727 0.76% 93.44% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 718688 0.96% 94.40% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4183002 5.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 526system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle | 526system.cpu0.fetch.rateDist::total 74721559 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.109608 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.562190 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 26241114 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 36078495 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 10432905 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 895868 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1073176 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 504459 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 32663 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 59394337 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 93513 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1073176 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 27177088 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 15322085 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 17293060 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 9793199 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 4062949 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 56409108 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 7164 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 656382 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1492215 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 37953965 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 68862069 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 68509500 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 352569 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 33051447 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 4902518 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1333146 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 200213 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 10586539 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 8773665 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 5638420 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1132750 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 738704 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 50116530 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 1671338 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 48856724 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 108345 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 5942974 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3041199 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1133867 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 74721559 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.653850 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.297886 # Number of insts issued each cycle |
| 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 572system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle | 572system.cpu0.iq.issued_per_cycle::0 52677257 70.50% 70.50% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 10184833 13.63% 84.13% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 4563049 6.11% 90.24% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 2984127 3.99% 94.23% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2257312 3.02% 97.25% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1142410 1.53% 98.78% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 582471 0.78% 99.56% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 283512 0.38% 99.94% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 46588 0.06% 100.00% # Number of insts issued each cycle |
| 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 584system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle | 584system.cpu0.iq.issued_per_cycle::total 74721559 # Number of insts issued each cycle |
| 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 586system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available | 586system.cpu0.iq.fu_full::IntAlu 73394 11.97% 11.97% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 287556 46.90% 58.87% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 252163 41.13% 100.00% # attempts to use FU when none available |
| 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 619system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued | 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 619system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued |
| 620system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued | 620system.cpu0.iq.FU_type_0::IntAlu 33933939 69.46% 69.47% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 53607 0.11% 69.57% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.57% # Type of FU issued |
| 623system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued | 623system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued --- 10 unchanged lines hidden (view full) --- 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued |
| 649system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued | 649system.cpu0.iq.FU_type_0::MemRead 8676123 17.76% 87.37% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 5426873 11.11% 98.48% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 742938 1.52% 100.00% # Type of FU issued |
| 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 653system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued 654system.cpu0.iq.rate 0.454505 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores | 653system.cpu0.iq.FU_type_0::total 48856724 # Type of FU issued 654system.cpu0.iq.rate 0.454457 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 613113 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.012549 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 172655307 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 57499462 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 47860573 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 501158 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 243682 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 236026 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 49203092 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 262278 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 518007 # Number of loads that had data forwarded from stores |
| 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 667system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed | 667system.cpu0.iew.lsq.thread0.squashedLoads 1116542 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 2532 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 12656 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 476196 # Number of stores squashed |
| 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 673system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked | 673system.cpu0.iew.lsq.thread0.rescheduledLoads 18844 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 94055 # Number of times an access to memory failed due to the cache being blocked |
| 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 676system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute | 676system.cpu0.iew.iewSquashCycles 1073176 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 10803844 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 780020 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 54838073 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 560128 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 8773665 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 5638420 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1470903 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 544426 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 8361 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 12656 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 186168 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 328100 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 514268 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 48431034 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 8384906 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 425690 # Number of squashed instructions skipped in execute |
| 693system.cpu0.iew.exec_swp 0 # number of swp insts executed | 693system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 694system.cpu0.iew.exec_nop 3050834 # number of nop insts executed 695system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 7758760 # Number of branches executed 697system.cpu0.iew.exec_stores 5379143 # Number of stores executed 698system.cpu0.iew.exec_rate 0.450548 # Inst execution rate 699system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 24100280 # num instructions producing a value 702system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value | 694system.cpu0.iew.exec_nop 3050205 # number of nop insts executed 695system.cpu0.iew.exec_refs 13763900 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 7759085 # Number of branches executed 697system.cpu0.iew.exec_stores 5378994 # Number of stores executed 698system.cpu0.iew.exec_rate 0.450498 # Inst execution rate 699system.cpu0.iew.wb_sent 48183963 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 48096599 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 24100955 # num instructions producing a value 702system.cpu0.iew.wb_consumers 32404442 # num instructions consuming a value |
| 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 704system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back | 704system.cpu0.iew.wb_rate 0.447387 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.743755 # average fanout of values written-back |
| 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 707system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions 708system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions 709system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit 710system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards 711system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted 712system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle | 707system.cpu0.commit.commitCommittedInsts 48294855 # The number of committed instructions 708system.cpu0.commit.commitCommittedOps 48294855 # The number of committed instructions 709system.cpu0.commit.commitSquashedInsts 6449755 # The number of squashed insts skipped by commit 710system.cpu0.commit.commitNonSpecStalls 537471 # The number of times commit has been forced to stall to communicate backwards 711system.cpu0.commit.branchMispredicts 480800 # The number of times a branch was mispredicted 712system.cpu0.commit.committed_per_cycle::samples 73648383 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::mean 0.655749 # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::stdev 1.560255 # Number of insts commited each cycle |
| 715system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 715system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 716system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle | 716system.cpu0.commit.committed_per_cycle::0 55233499 75.00% 75.00% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::1 7733418 10.50% 85.50% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::2 4278651 5.81% 91.31% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::3 2283988 3.10% 94.41% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::4 1242605 1.69% 96.09% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::5 524240 0.71% 96.81% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::6 434900 0.59% 97.40% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::7 385505 0.52% 97.92% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::8 1531577 2.08% 100.00% # Number of insts commited each cycle |
| 725system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 725system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 728system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle 729system.cpu0.commit.committedInsts 48294177 # Number of instructions committed 730system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed | 728system.cpu0.commit.committed_per_cycle::total 73648383 # Number of insts commited each cycle 729system.cpu0.commit.committedInsts 48294855 # Number of instructions committed 730system.cpu0.commit.committedOps 48294855 # Number of ops (including micro ops) committed |
| 731system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 731system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 732system.cpu0.commit.refs 12819276 # Number of memory references committed 733system.cpu0.commit.loads 7657070 # Number of loads committed | 732system.cpu0.commit.refs 12819347 # Number of memory references committed 733system.cpu0.commit.loads 7657123 # Number of loads committed |
| 734system.cpu0.commit.membars 181890 # Number of memory barriers committed | 734system.cpu0.commit.membars 181890 # Number of memory barriers committed |
| 735system.cpu0.commit.branches 7325526 # Number of branches committed | 735system.cpu0.commit.branches 7325688 # Number of branches committed |
| 736system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. | 736system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. |
| 737system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. 738system.cpu0.commit.function_calls 610965 # Number of function calls committed. 739system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached | 737system.cpu0.commit.int_insts 44748779 # Number of committed integer instructions. 738system.cpu0.commit.function_calls 610967 # Number of function calls committed. 739system.cpu0.commit.bw_lim_events 1531577 # number cycles where commit BW limit reached |
| 740system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 740system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 741system.cpu0.rob.rob_reads 126666255 # The number of ROB reads 742system.cpu0.rob.rob_writes 110560293 # The number of ROB writes 743system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself 744system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling 745system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 746system.cpu0.committedInsts 45532520 # Number of Instructions Simulated 747system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated 748system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated 749system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction 750system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads 751system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle 752system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads 753system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads 754system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes 755system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads 756system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes 757system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads 758system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes | 741system.cpu0.rob.rob_reads 126676900 # The number of ROB reads 742system.cpu0.rob.rob_writes 110562172 # The number of ROB writes 743system.cpu0.timesIdled 1222053 # Number of times that the entire CPU went into an idle state and unscheduled itself 744system.cpu0.idleCycles 32784094 # Total number of cycles that the CPU has spent unscheduled due to idling 745system.cpu0.quiesceCycles 3693280483 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 746system.cpu0.committedInsts 45533193 # Number of Instructions Simulated 747system.cpu0.committedOps 45533193 # Number of Ops (including micro ops) Simulated 748system.cpu0.committedInsts_total 45533193 # Number of Instructions Simulated 749system.cpu0.cpi 2.361039 # CPI: Cycles Per Instruction 750system.cpu0.cpi_total 2.361039 # CPI: Total CPI of All Threads 751system.cpu0.ipc 0.423542 # IPC: Instructions Per Cycle 752system.cpu0.ipc_total 0.423542 # IPC: Total IPC of All Threads 753system.cpu0.int_regfile_reads 63859411 # number of integer regfile reads 754system.cpu0.int_regfile_writes 34945756 # number of integer regfile writes 755system.cpu0.fp_regfile_reads 117042 # number of floating regfile reads 756system.cpu0.fp_regfile_writes 117632 # number of floating regfile writes 757system.cpu0.misc_regfile_reads 1550181 # number of misc regfile reads 758system.cpu0.misc_regfile_writes 750158 # number of misc regfile writes |
| 759system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 760system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 761system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 762system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 763system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 764system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 765system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 766system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 782system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 783system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 784system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 785system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 786system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 787system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 788system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 789system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 759system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 760system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 761system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 762system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 763system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 764system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 765system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 766system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 782system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 783system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 784system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 785system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 786system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 787system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 788system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 789system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 790system.cpu0.icache.replacements 790628 # number of replacements 791system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use 792system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. 793system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. 794system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. | 790system.cpu0.icache.replacements 791282 # number of replacements 791system.cpu0.icache.tagsinuse 510.000823 # Cycle average of tags in use 792system.cpu0.icache.total_refs 6671308 # Total number of references to valid blocks. 793system.cpu0.icache.sampled_refs 791794 # Sample count of references to valid blocks. 794system.cpu0.icache.avg_refs 8.425560 # Average number of references to valid blocks. |
| 795system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. | 795system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. |
| 796system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor | 796system.cpu0.icache.occ_blocks::cpu0.inst 510.000823 # Average occupied blocks per requestor |
| 797system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy 798system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy | 797system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy 798system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy |
| 799system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits 804system.cpu0.icache.overall_hits::total 6669453 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses 810system.cpu0.icache.overall_misses::total 834673 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked | 799system.cpu0.icache.ReadReq_hits::cpu0.inst 6671308 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 6671308 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 6671308 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 6671308 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 6671308 # number of overall hits 804system.cpu0.icache.overall_hits::total 6671308 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 835236 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 835236 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 835236 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 835236 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 835236 # number of overall misses 810system.cpu0.icache.overall_misses::total 835236 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13775160993 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 13775160993 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 13775160993 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 13775160993 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 13775160993 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 13775160993 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 7506544 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 7506544 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 7506544 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 7506544 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 7506544 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 7506544 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111268 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.111268 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111268 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.111268 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111268 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.111268 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 16492.537430 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 16492.537430 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 1463996 # number of cycles access was blocked |
| 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 837system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked | 837system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked |
| 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 839system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked | 839system.cpu0.icache.avg_blocked_cycles::no_mshrs 9265.797468 # average number of cycles each access was blocked |
| 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed | 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 843system.cpu0.icache.writebacks::writebacks 247 # number of writebacks 844system.cpu0.icache.writebacks::total 247 # number of writebacks 845system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits 846system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits 847system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits 848system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits 849system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits 850system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits 851system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses 852system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses 853system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses 854system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses 855system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses 856system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses 857system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles 859system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles 860system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles 861system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles 862system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles 863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses 865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses 866system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses 867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses 868system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency 870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency | 843system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits 844system.cpu0.icache.ReadReq_mshr_hits::total 43249 # number of ReadReq MSHR hits 845system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits 846system.cpu0.icache.demand_mshr_hits::total 43249 # number of demand (read+write) MSHR hits 847system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits 848system.cpu0.icache.overall_mshr_hits::total 43249 # number of overall MSHR hits 849system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791987 # number of ReadReq MSHR misses 850system.cpu0.icache.ReadReq_mshr_misses::total 791987 # number of ReadReq MSHR misses 851system.cpu0.icache.demand_mshr_misses::cpu0.inst 791987 # number of demand (read+write) MSHR misses 852system.cpu0.icache.demand_mshr_misses::total 791987 # number of demand (read+write) MSHR misses 853system.cpu0.icache.overall_mshr_misses::cpu0.inst 791987 # number of overall MSHR misses 854system.cpu0.icache.overall_mshr_misses::total 791987 # number of overall MSHR misses 855system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10696262996 # number of ReadReq MSHR miss cycles 856system.cpu0.icache.ReadReq_mshr_miss_latency::total 10696262996 # number of ReadReq MSHR miss cycles 857system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10696262996 # number of demand (read+write) MSHR miss cycles 858system.cpu0.icache.demand_mshr_miss_latency::total 10696262996 # number of demand (read+write) MSHR miss cycles 859system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10696262996 # number of overall MSHR miss cycles 860system.cpu0.icache.overall_mshr_miss_latency::total 10696262996 # number of overall MSHR miss cycles 861system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for ReadReq accesses 862system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105506 # mshr miss rate for ReadReq accesses 863system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for demand accesses 864system.cpu0.icache.demand_mshr_miss_rate::total 0.105506 # mshr miss rate for demand accesses 865system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for overall accesses 866system.cpu0.icache.overall_mshr_miss_rate::total 0.105506 # mshr miss rate for overall accesses 867system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average ReadReq mshr miss latency 868system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254 # average ReadReq mshr miss latency 869system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency 870system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency 871system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency 872system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency |
| 875system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 873system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 876system.cpu0.dcache.replacements 1206208 # number of replacements 877system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use 878system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. 879system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. 880system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. | 874system.cpu0.dcache.replacements 1206262 # number of replacements 875system.cpu0.dcache.tagsinuse 505.874752 # Cycle average of tags in use 876system.cpu0.dcache.total_refs 9821312 # Total number of references to valid blocks. 877system.cpu0.dcache.sampled_refs 1206702 # Sample count of references to valid blocks. 878system.cpu0.dcache.avg_refs 8.138971 # Average number of references to valid blocks. |
| 881system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. | 879system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. |
| 882system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor 883system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy 884system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy 885system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits 886system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits 887system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits 888system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits 889system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits 890system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits 891system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits 892system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits 893system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits 894system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits 895system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits 896system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits 897system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses 898system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses 899system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses 900system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses 901system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses 902system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses 903system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses 904system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses 905system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses 906system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses 907system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses 908system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses 909system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles 910system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles 911system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles 912system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles 913system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles 914system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles 915system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles 916system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles 917system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles 918system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles 919system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles 920system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles 921system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses) 922system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses) 923system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses) 924system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses) 925system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses) 926system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) 927system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) 928system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) 929system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses 930system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses 931system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses 932system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses 933system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses 934system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses 935system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses 936system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses 937system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses 938system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses 939system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses 940system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses 941system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses 942system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses 943system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses 944system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses 945system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency 946system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency 947system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency 948system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency 949system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency 950system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency 951system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency 952system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency 953system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency 954system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency 955system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency 956system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency 957system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked | 880system.cpu0.dcache.occ_blocks::cpu0.data 505.874752 # Average occupied blocks per requestor 881system.cpu0.dcache.occ_percent::cpu0.data 0.988037 # Average percentage of cache occupancy 882system.cpu0.dcache.occ_percent::total 0.988037 # Average percentage of cache occupancy 883system.cpu0.dcache.ReadReq_hits::cpu0.data 6113380 # number of ReadReq hits 884system.cpu0.dcache.ReadReq_hits::total 6113380 # number of ReadReq hits 885system.cpu0.dcache.WriteReq_hits::cpu0.data 3377082 # number of WriteReq hits 886system.cpu0.dcache.WriteReq_hits::total 3377082 # number of WriteReq hits 887system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150588 # number of LoadLockedReq hits 888system.cpu0.dcache.LoadLockedReq_hits::total 150588 # number of LoadLockedReq hits 889system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171660 # number of StoreCondReq hits 890system.cpu0.dcache.StoreCondReq_hits::total 171660 # number of StoreCondReq hits 891system.cpu0.dcache.demand_hits::cpu0.data 9490462 # number of demand (read+write) hits 892system.cpu0.dcache.demand_hits::total 9490462 # number of demand (read+write) hits 893system.cpu0.dcache.overall_hits::cpu0.data 9490462 # number of overall hits 894system.cpu0.dcache.overall_hits::total 9490462 # number of overall hits 895system.cpu0.dcache.ReadReq_misses::cpu0.data 1478592 # number of ReadReq misses 896system.cpu0.dcache.ReadReq_misses::total 1478592 # number of ReadReq misses 897system.cpu0.dcache.WriteReq_misses::cpu0.data 1593723 # number of WriteReq misses 898system.cpu0.dcache.WriteReq_misses::total 1593723 # number of WriteReq misses 899system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18660 # number of LoadLockedReq misses 900system.cpu0.dcache.LoadLockedReq_misses::total 18660 # number of LoadLockedReq misses 901system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4698 # number of StoreCondReq misses 902system.cpu0.dcache.StoreCondReq_misses::total 4698 # number of StoreCondReq misses 903system.cpu0.dcache.demand_misses::cpu0.data 3072315 # number of demand (read+write) misses 904system.cpu0.dcache.demand_misses::total 3072315 # number of demand (read+write) misses 905system.cpu0.dcache.overall_misses::cpu0.data 3072315 # number of overall misses 906system.cpu0.dcache.overall_misses::total 3072315 # number of overall misses 907system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41280324500 # number of ReadReq miss cycles 908system.cpu0.dcache.ReadReq_miss_latency::total 41280324500 # number of ReadReq miss cycles 909system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65318664554 # number of WriteReq miss cycles 910system.cpu0.dcache.WriteReq_miss_latency::total 65318664554 # number of WriteReq miss cycles 911system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315332000 # number of LoadLockedReq miss cycles 912system.cpu0.dcache.LoadLockedReq_miss_latency::total 315332000 # number of LoadLockedReq miss cycles 913system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68573000 # number of StoreCondReq miss cycles 914system.cpu0.dcache.StoreCondReq_miss_latency::total 68573000 # number of StoreCondReq miss cycles 915system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054 # number of demand (read+write) miss cycles 916system.cpu0.dcache.demand_miss_latency::total 106598989054 # number of demand (read+write) miss cycles 917system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054 # number of overall miss cycles 918system.cpu0.dcache.overall_miss_latency::total 106598989054 # number of overall miss cycles 919system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591972 # number of ReadReq accesses(hits+misses) 920system.cpu0.dcache.ReadReq_accesses::total 7591972 # number of ReadReq accesses(hits+misses) 921system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970805 # number of WriteReq accesses(hits+misses) 922system.cpu0.dcache.WriteReq_accesses::total 4970805 # number of WriteReq accesses(hits+misses) 923system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169248 # number of LoadLockedReq accesses(hits+misses) 924system.cpu0.dcache.LoadLockedReq_accesses::total 169248 # number of LoadLockedReq accesses(hits+misses) 925system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176358 # number of StoreCondReq accesses(hits+misses) 926system.cpu0.dcache.StoreCondReq_accesses::total 176358 # number of StoreCondReq accesses(hits+misses) 927system.cpu0.dcache.demand_accesses::cpu0.data 12562777 # number of demand (read+write) accesses 928system.cpu0.dcache.demand_accesses::total 12562777 # number of demand (read+write) accesses 929system.cpu0.dcache.overall_accesses::cpu0.data 12562777 # number of overall (read+write) accesses 930system.cpu0.dcache.overall_accesses::total 12562777 # number of overall (read+write) accesses 931system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194757 # miss rate for ReadReq accesses 932system.cpu0.dcache.ReadReq_miss_rate::total 0.194757 # miss rate for ReadReq accesses 933system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses 934system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses 935system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110252 # miss rate for LoadLockedReq accesses 936system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110252 # miss rate for LoadLockedReq accesses 937system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026639 # miss rate for StoreCondReq accesses 938system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026639 # miss rate for StoreCondReq accesses 939system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244557 # miss rate for demand accesses 940system.cpu0.dcache.demand_miss_rate::total 0.244557 # miss rate for demand accesses 941system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244557 # miss rate for overall accesses 942system.cpu0.dcache.overall_miss_rate::total 0.244557 # miss rate for overall accesses 943system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615 # average ReadReq miss latency 944system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615 # average ReadReq miss latency 945system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446 # average WriteReq miss latency 946system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446 # average WriteReq miss latency 947system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008 # average LoadLockedReq miss latency 948system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008 # average LoadLockedReq miss latency 949system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154 # average StoreCondReq miss latency 950system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154 # average StoreCondReq miss latency 951system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency 952system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989 # average overall miss latency 953system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency 954system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989 # average overall miss latency 955system.cpu0.dcache.blocked_cycles::no_mshrs 716919646 # number of cycles access was blocked |
| 958system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked | 956system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked |
| 959system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked | 957system.cpu0.dcache.blocked::no_mshrs 65391 # number of cycles access was blocked |
| 960system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked | 958system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 961system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked | 959system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848 # average number of cycles each access was blocked |
| 962system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked 963system.cpu0.dcache.fast_writes 0 # number of fast writes performed 964system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 960system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked 961system.cpu0.dcache.fast_writes 0 # number of fast writes performed 962system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 965system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks 966system.cpu0.dcache.writebacks::total 693284 # number of writebacks 967system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits 968system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits 969system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits 970system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits 971system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits 972system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits 973system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits 974system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits 975system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits 976system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits 977system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses 978system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses 979system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses 980system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses 981system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses 982system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses 983system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses 984system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses 985system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses 986system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses 987system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses 988system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses 989system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles 990system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles 991system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles 992system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles 993system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles 994system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles 995system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles 996system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles 997system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles 998system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles 999system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles 1000system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles 1001system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles 1002system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles 1003system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles 1004system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles 1005system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles 1006system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles 1007system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses 1016system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses 1017system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses 1018system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency 1020system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency 1021system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency 1022system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency 1025system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency 1026system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency 1027system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency 1028system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency 1029system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency 1030system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency | 963system.cpu0.dcache.writebacks::writebacks 693314 # number of writebacks 964system.cpu0.dcache.writebacks::total 693314 # number of writebacks 965system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515793 # number of ReadReq MSHR hits 966system.cpu0.dcache.ReadReq_mshr_hits::total 515793 # number of ReadReq MSHR hits 967system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344404 # number of WriteReq MSHR hits 968system.cpu0.dcache.WriteReq_mshr_hits::total 1344404 # number of WriteReq MSHR hits 969system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3762 # number of LoadLockedReq MSHR hits 970system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3762 # number of LoadLockedReq MSHR hits 971system.cpu0.dcache.demand_mshr_hits::cpu0.data 1860197 # number of demand (read+write) MSHR hits 972system.cpu0.dcache.demand_mshr_hits::total 1860197 # number of demand (read+write) MSHR hits 973system.cpu0.dcache.overall_mshr_hits::cpu0.data 1860197 # number of overall MSHR hits 974system.cpu0.dcache.overall_mshr_hits::total 1860197 # number of overall MSHR hits 975system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962799 # number of ReadReq MSHR misses 976system.cpu0.dcache.ReadReq_mshr_misses::total 962799 # number of ReadReq MSHR misses 977system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249319 # number of WriteReq MSHR misses 978system.cpu0.dcache.WriteReq_mshr_misses::total 249319 # number of WriteReq MSHR misses 979system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14898 # number of LoadLockedReq MSHR misses 980system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14898 # number of LoadLockedReq MSHR misses 981system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4698 # number of StoreCondReq MSHR misses 982system.cpu0.dcache.StoreCondReq_mshr_misses::total 4698 # number of StoreCondReq MSHR misses 983system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212118 # number of demand (read+write) MSHR misses 984system.cpu0.dcache.demand_mshr_misses::total 1212118 # number of demand (read+write) MSHR misses 985system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212118 # number of overall MSHR misses 986system.cpu0.dcache.overall_mshr_misses::total 1212118 # number of overall MSHR misses 987system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25944695097 # number of ReadReq MSHR miss cycles 988system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25944695097 # number of ReadReq MSHR miss cycles 989system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8701407966 # number of WriteReq MSHR miss cycles 990system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8701407966 # number of WriteReq MSHR miss cycles 991system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186837501 # number of LoadLockedReq MSHR miss cycles 992system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186837501 # number of LoadLockedReq MSHR miss cycles 993system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 53961001 # number of StoreCondReq MSHR miss cycles 994system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 53961001 # number of StoreCondReq MSHR miss cycles 995system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34646103063 # number of demand (read+write) MSHR miss cycles 996system.cpu0.dcache.demand_mshr_miss_latency::total 34646103063 # number of demand (read+write) MSHR miss cycles 997system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34646103063 # number of overall MSHR miss cycles 998system.cpu0.dcache.overall_mshr_miss_latency::total 34646103063 # number of overall MSHR miss cycles 999system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918480000 # number of ReadReq MSHR uncacheable cycles 1000system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918480000 # number of ReadReq MSHR uncacheable cycles 1001system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327721998 # number of WriteReq MSHR uncacheable cycles 1002system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327721998 # number of WriteReq MSHR uncacheable cycles 1003system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246201998 # number of overall MSHR uncacheable cycles 1004system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246201998 # number of overall MSHR uncacheable cycles 1005system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126818 # mshr miss rate for ReadReq accesses 1006system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126818 # mshr miss rate for ReadReq accesses 1007system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050157 # mshr miss rate for WriteReq accesses 1008system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050157 # mshr miss rate for WriteReq accesses 1009system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088025 # mshr miss rate for LoadLockedReq accesses 1010system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088025 # mshr miss rate for LoadLockedReq accesses 1011system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026639 # mshr miss rate for StoreCondReq accesses 1012system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026639 # mshr miss rate for StoreCondReq accesses 1013system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for demand accesses 1014system.cpu0.dcache.demand_mshr_miss_rate::total 0.096485 # mshr miss rate for demand accesses 1015system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for overall accesses 1016system.cpu0.dcache.overall_mshr_miss_rate::total 0.096485 # mshr miss rate for overall accesses 1017system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257 # average ReadReq mshr miss latency 1018system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257 # average ReadReq mshr miss latency 1019system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375 # average WriteReq mshr miss latency 1020system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375 # average WriteReq mshr miss latency 1021system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968 # average LoadLockedReq mshr miss latency 1022system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968 # average LoadLockedReq mshr miss latency 1023system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682 # average StoreCondReq mshr miss latency 1024system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682 # average StoreCondReq mshr miss latency 1025system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency 1026system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency 1027system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency 1028system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency |
| 1031system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1032system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1033system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1034system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1035system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1036system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1037system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu1.dtb.fetch_hits 0 # ITB hits 1039system.cpu1.dtb.fetch_misses 0 # ITB misses 1040system.cpu1.dtb.fetch_acv 0 # ITB acv 1041system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1029system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1030system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1031system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1032system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1033system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1034system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1035system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1036system.cpu1.dtb.fetch_hits 0 # ITB hits 1037system.cpu1.dtb.fetch_misses 0 # ITB misses 1038system.cpu1.dtb.fetch_acv 0 # ITB acv 1039system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1042system.cpu1.dtb.read_hits 2499316 # DTB read hits 1043system.cpu1.dtb.read_misses 12569 # DTB read misses | 1040system.cpu1.dtb.read_hits 2497958 # DTB read hits 1041system.cpu1.dtb.read_misses 12385 # DTB read misses |
| 1044system.cpu1.dtb.read_acv 105 # DTB read access violations | 1042system.cpu1.dtb.read_acv 105 # DTB read access violations |
| 1045system.cpu1.dtb.read_accesses 313735 # DTB read accesses 1046system.cpu1.dtb.write_hits 1734639 # DTB write hits 1047system.cpu1.dtb.write_misses 3525 # DTB write misses 1048system.cpu1.dtb.write_acv 140 # DTB write access violations 1049system.cpu1.dtb.write_accesses 132367 # DTB write accesses 1050system.cpu1.dtb.data_hits 4233955 # DTB hits 1051system.cpu1.dtb.data_misses 16094 # DTB misses 1052system.cpu1.dtb.data_acv 245 # DTB access violations 1053system.cpu1.dtb.data_accesses 446102 # DTB accesses 1054system.cpu1.itb.fetch_hits 489806 # ITB hits 1055system.cpu1.itb.fetch_misses 8851 # ITB misses 1056system.cpu1.itb.fetch_acv 360 # ITB acv 1057system.cpu1.itb.fetch_accesses 498657 # ITB accesses | 1043system.cpu1.dtb.read_accesses 312687 # DTB read accesses 1044system.cpu1.dtb.write_hits 1734137 # DTB write hits 1045system.cpu1.dtb.write_misses 3404 # DTB write misses 1046system.cpu1.dtb.write_acv 137 # DTB write access violations 1047system.cpu1.dtb.write_accesses 131810 # DTB write accesses 1048system.cpu1.dtb.data_hits 4232095 # DTB hits 1049system.cpu1.dtb.data_misses 15789 # DTB misses 1050system.cpu1.dtb.data_acv 242 # DTB access violations 1051system.cpu1.dtb.data_accesses 444497 # DTB accesses 1052system.cpu1.itb.fetch_hits 488697 # ITB hits 1053system.cpu1.itb.fetch_misses 8773 # ITB misses 1054system.cpu1.itb.fetch_acv 366 # ITB acv 1055system.cpu1.itb.fetch_accesses 497470 # ITB accesses |
| 1058system.cpu1.itb.read_hits 0 # DTB read hits 1059system.cpu1.itb.read_misses 0 # DTB read misses 1060system.cpu1.itb.read_acv 0 # DTB read access violations 1061system.cpu1.itb.read_accesses 0 # DTB read accesses 1062system.cpu1.itb.write_hits 0 # DTB write hits 1063system.cpu1.itb.write_misses 0 # DTB write misses 1064system.cpu1.itb.write_acv 0 # DTB write access violations 1065system.cpu1.itb.write_accesses 0 # DTB write accesses 1066system.cpu1.itb.data_hits 0 # DTB hits 1067system.cpu1.itb.data_misses 0 # DTB misses 1068system.cpu1.itb.data_acv 0 # DTB access violations 1069system.cpu1.itb.data_accesses 0 # DTB accesses | 1056system.cpu1.itb.read_hits 0 # DTB read hits 1057system.cpu1.itb.read_misses 0 # DTB read misses 1058system.cpu1.itb.read_acv 0 # DTB read access violations 1059system.cpu1.itb.read_accesses 0 # DTB read accesses 1060system.cpu1.itb.write_hits 0 # DTB write hits 1061system.cpu1.itb.write_misses 0 # DTB write misses 1062system.cpu1.itb.write_acv 0 # DTB write access violations 1063system.cpu1.itb.write_accesses 0 # DTB write accesses 1064system.cpu1.itb.data_hits 0 # DTB hits 1065system.cpu1.itb.data_misses 0 # DTB misses 1066system.cpu1.itb.data_acv 0 # DTB access violations 1067system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1070system.cpu1.numCycles 22717311 # number of cpu cycles simulated | 1068system.cpu1.numCycles 22715640 # number of cpu cycles simulated |
| 1071system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1072system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1069system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1070system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1073system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups 1074system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted 1075system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect 1076system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups 1077system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits | 1071system.cpu1.BPredUnit.lookups 3441563 # Number of BP lookups 1072system.cpu1.BPredUnit.condPredicted 2848590 # Number of conditional branches predicted 1073system.cpu1.BPredUnit.condIncorrect 108508 # Number of conditional branches incorrect 1074system.cpu1.BPredUnit.BTBLookups 2344214 # Number of BTB lookups 1075system.cpu1.BPredUnit.BTBHits 1191088 # Number of BTB hits |
| 1078system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1076system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1079system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. 1080system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. 1081system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss 1082system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed 1083system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered 1084system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken 1085system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked 1086system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing 1087system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked 1088system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1089system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps 1090system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions 1091system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR 1092system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched 1093system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed 1094system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) 1095system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) 1096system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) | 1077system.cpu1.BPredUnit.usedRAS 236176 # Number of times the RAS was used to get a target. 1078system.cpu1.BPredUnit.RASInCorrect 10617 # Number of incorrect RAS predictions. 1079system.cpu1.fetch.icacheStallCycles 9035553 # Number of cycles fetch is stalled on an Icache miss 1080system.cpu1.fetch.Insts 16314409 # Number of instructions fetch has processed 1081system.cpu1.fetch.Branches 3441563 # Number of branches that fetch encountered 1082system.cpu1.fetch.predictedBranches 1427264 # Number of branches that fetch has predicted taken 1083system.cpu1.fetch.Cycles 2922038 # Number of cycles fetch has run and was not squashing or blocked 1084system.cpu1.fetch.SquashCycles 525528 # Number of cycles fetch has spent squashing 1085system.cpu1.fetch.BlockedCycles 8308395 # Number of cycles fetch has spent blocked 1086system.cpu1.fetch.MiscStallCycles 28029 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1087system.cpu1.fetch.PendingTrapStallCycles 86548 # Number of stall cycles due to pending traps 1088system.cpu1.fetch.PendingQuiesceStallCycles 64086 # Number of stall cycles due to pending quiesce instructions 1089system.cpu1.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 1090system.cpu1.fetch.CacheLines 1962045 # Number of cache lines fetched 1091system.cpu1.fetch.IcacheSquashes 75286 # Number of outstanding Icache misses that were squashed 1092system.cpu1.fetch.rateDist::samples 20775175 # Number of instructions fetched each cycle (Total) 1093system.cpu1.fetch.rateDist::mean 0.785284 # Number of instructions fetched each cycle (Total) 1094system.cpu1.fetch.rateDist::stdev 2.154306 # Number of instructions fetched each cycle (Total) |
| 1097system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1095system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1098system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) 1105system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) | 1096system.cpu1.fetch.rateDist::0 17853137 85.93% 85.93% # Number of instructions fetched each cycle (Total) 1097system.cpu1.fetch.rateDist::1 203247 0.98% 86.91% # Number of instructions fetched each cycle (Total) 1098system.cpu1.fetch.rateDist::2 300737 1.45% 88.36% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::3 225181 1.08% 89.44% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::4 403762 1.94% 91.39% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::5 151742 0.73% 92.12% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::6 164996 0.79% 92.91% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::7 308573 1.49% 94.40% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::8 1163800 5.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 1107system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1108system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1109system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1105system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1107system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1110system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) 1111system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle 1112system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle 1113system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle 1114system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked 1115system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running 1116system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking 1117system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing 1118system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch 1119system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction 1120system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode 1121system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode 1122system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing 1123system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle 1124system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking 1125system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst 1126system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running 1127system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking 1128system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename 1129system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full 1130system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full 1131system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full 1132system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed 1133system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made 1134system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups 1135system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups 1136system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed 1137system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing 1138system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed 1139system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed 1140system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer 1141system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. 1142system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. 1143system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. 1144system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. 1145system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) 1146system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ 1147system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued 1148system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued 1149system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling 1150system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph 1151system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed 1152system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle 1153system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle 1154system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle | 1108system.cpu1.fetch.rateDist::total 20775175 # Number of instructions fetched each cycle (Total) 1109system.cpu1.fetch.branchRate 0.151506 # Number of branch fetches per cycle 1110system.cpu1.fetch.rate 0.718202 # Number of inst fetches per cycle 1111system.cpu1.decode.IdleCycles 8809071 # Number of cycles decode is idle 1112system.cpu1.decode.BlockedCycles 8765539 # Number of cycles decode is blocked 1113system.cpu1.decode.RunCycles 2707216 # Number of cycles decode is running 1114system.cpu1.decode.UnblockCycles 172890 # Number of cycles decode is unblocking 1115system.cpu1.decode.SquashCycles 320458 # Number of cycles decode is squashing 1116system.cpu1.decode.BranchResolved 151147 # Number of times decode resolved a branch 1117system.cpu1.decode.BranchMispred 10158 # Number of times decode detected a branch misprediction 1118system.cpu1.decode.DecodedInsts 16014026 # Number of instructions handled by decode 1119system.cpu1.decode.SquashedInsts 29482 # Number of squashed instructions handled by decode 1120system.cpu1.rename.SquashCycles 320458 # Number of cycles rename is squashing 1121system.cpu1.rename.IdleCycles 9091295 # Number of cycles rename is idle 1122system.cpu1.rename.BlockCycles 884150 # Number of cycles rename is blocking 1123system.cpu1.rename.serializeStallCycles 6951341 # count of cycles rename stalled for serializing inst 1124system.cpu1.rename.RunCycles 2592964 # Number of cycles rename is running 1125system.cpu1.rename.UnblockCycles 934965 # Number of cycles rename is unblocking 1126system.cpu1.rename.RenamedInsts 14837454 # Number of instructions processed by rename 1127system.cpu1.rename.ROBFullEvents 127 # Number of times rename has blocked due to ROB full 1128system.cpu1.rename.IQFullEvents 84091 # Number of times rename has blocked due to IQ full 1129system.cpu1.rename.LSQFullEvents 280482 # Number of times rename has blocked due to LSQ full 1130system.cpu1.rename.RenamedOperands 9656446 # Number of destination operands rename has renamed 1131system.cpu1.rename.RenameLookups 17623003 # Number of register rename lookups that rename has made 1132system.cpu1.rename.int_rename_lookups 17415204 # Number of integer rename lookups 1133system.cpu1.rename.fp_rename_lookups 207799 # Number of floating rename lookups 1134system.cpu1.rename.CommittedMaps 8330618 # Number of HB maps that are committed 1135system.cpu1.rename.UndoneMaps 1325820 # Number of HB maps that are undone due to squashing 1136system.cpu1.rename.serializingInsts 594023 # count of serializing insts renamed 1137system.cpu1.rename.tempSerializingInsts 64559 # count of temporary serializing insts renamed 1138system.cpu1.rename.skidInsts 2775443 # count of insts added to the skid buffer 1139system.cpu1.memDep0.insertedLoads 2639269 # Number of loads inserted to the mem dependence unit. 1140system.cpu1.memDep0.insertedStores 1825014 # Number of stores inserted to the mem dependence unit. 1141system.cpu1.memDep0.conflictingLoads 248716 # Number of conflicting loads. 1142system.cpu1.memDep0.conflictingStores 160479 # Number of conflicting stores. 1143system.cpu1.iq.iqInstsAdded 12970444 # Number of instructions added to the IQ (excludes non-spec) 1144system.cpu1.iq.iqNonSpecInstsAdded 664664 # Number of non-speculative instructions added to the IQ 1145system.cpu1.iq.iqInstsIssued 12696455 # Number of instructions issued 1146system.cpu1.iq.iqSquashedInstsIssued 35550 # Number of squashed instructions issued 1147system.cpu1.iq.iqSquashedInstsExamined 1743951 # Number of squashed instructions iterated over during squash; mainly for profiling 1148system.cpu1.iq.iqSquashedOperandsExamined 828101 # Number of squashed operands that are examined and possibly removed from graph 1149system.cpu1.iq.iqSquashedNonSpecRemoved 468923 # Number of squashed non-spec instructions that were removed 1150system.cpu1.iq.issued_per_cycle::samples 20775175 # Number of insts issued each cycle 1151system.cpu1.iq.issued_per_cycle::mean 0.611136 # Number of insts issued each cycle 1152system.cpu1.iq.issued_per_cycle::stdev 1.284217 # Number of insts issued each cycle |
| 1155system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1153system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1156system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle 1163system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle | 1154system.cpu1.iq.issued_per_cycle::0 15113498 72.75% 72.75% # Number of insts issued each cycle 1155system.cpu1.iq.issued_per_cycle::1 2653136 12.77% 85.52% # Number of insts issued each cycle 1156system.cpu1.iq.issued_per_cycle::2 1113601 5.36% 90.88% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::3 723121 3.48% 94.36% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::4 602829 2.90% 97.26% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::5 288191 1.39% 98.65% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::6 181892 0.88% 99.52% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::7 88125 0.42% 99.95% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::8 10782 0.05% 100.00% # Number of insts issued each cycle |
| 1165system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1166system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1167system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1163system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1165system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1168system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle | 1166system.cpu1.iq.issued_per_cycle::total 20775175 # Number of insts issued each cycle |
| 1169system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1167system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1170system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 1199system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available 1200system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available | 1168system.cpu1.iq.fu_full::IntAlu 3857 1.52% 1.52% # attempts to use FU when none available 1169system.cpu1.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available 1170system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::MemRead 134714 53.16% 54.69% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::MemWrite 114823 45.31% 100.00% # attempts to use FU when none available |
| 1201system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1202system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1203system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued | 1199system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1200system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1201system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued |
| 1204system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued 1205system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued 1206system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued | 1202system.cpu1.iq.FU_type_0::IntAlu 7925481 62.42% 62.45% # Type of FU issued 1203system.cpu1.iq.FU_type_0::IntMult 20760 0.16% 62.61% # Type of FU issued 1204system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued 1205system.cpu1.iq.FU_type_0::FloatAdd 10544 0.08% 62.69% # Type of FU issued |
| 1208system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued 1209system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued 1210system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued 1211system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued 1212system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued 1214system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued 1215system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 1225system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued 1229system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued 1230system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued 1231system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued 1232system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued | 1206system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued 1208system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued 1209system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued 1210system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued 1211system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued 1212system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 1223system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued 1224system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued 1225system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued 1229system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued 1230system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued |
| 1233system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued 1234system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued 1235system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued | 1231system.cpu1.iq.FU_type_0::MemRead 2621698 20.65% 83.35% # Type of FU issued 1232system.cpu1.iq.FU_type_0::MemWrite 1764339 13.90% 97.25% # Type of FU issued 1233system.cpu1.iq.FU_type_0::IprAccess 349399 2.75% 100.00% # Type of FU issued |
| 1236system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1234system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1237system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued 1238system.cpu1.iq.rate 0.559079 # Inst issue rate 1239system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested 1240system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) 1241system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads 1242system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes 1243system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses 1244system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads 1245system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes 1246system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses 1247system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses 1248system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses 1249system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores | 1235system.cpu1.iq.FU_type_0::total 12696455 # Type of FU issued 1236system.cpu1.iq.rate 0.558930 # Inst issue rate 1237system.cpu1.iq.fu_busy_cnt 253394 # FU busy when requested 1238system.cpu1.iq.fu_busy_rate 0.019958 # FU busy rate (busy events/executed inst) 1239system.cpu1.iq.int_inst_queue_reads 46157750 # Number of integer instruction queue reads 1240system.cpu1.iq.int_inst_queue_writes 15236198 # Number of integer instruction queue writes 1241system.cpu1.iq.int_inst_queue_wakeup_accesses 12337265 # Number of integer instruction queue wakeup accesses 1242system.cpu1.iq.fp_inst_queue_reads 299278 # Number of floating instruction queue reads 1243system.cpu1.iq.fp_inst_queue_writes 145041 # Number of floating instruction queue writes 1244system.cpu1.iq.fp_inst_queue_wakeup_accesses 140795 # Number of floating instruction queue wakeup accesses 1245system.cpu1.iq.int_alu_accesses 12790304 # Number of integer alu accesses 1246system.cpu1.iq.fp_alu_accesses 156722 # Number of floating point alu accesses 1247system.cpu1.iew.lsq.thread0.forwLoads 115188 # Number of loads that had data forwarded from stores |
| 1250system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1248system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1251system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed 1252system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed 1253system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations 1254system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed | 1249system.cpu1.iew.lsq.thread0.squashedLoads 346106 # Number of loads squashed 1250system.cpu1.iew.lsq.thread0.ignoredResponses 806 # Number of memory responses ignored because the instruction is squashed 1251system.cpu1.iew.lsq.thread0.memOrderViolation 2268 # Number of memory ordering violations 1252system.cpu1.iew.lsq.thread0.squashedStores 152574 # Number of stores squashed |
| 1255system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1256system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1253system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1254system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1257system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled 1258system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked | 1255system.cpu1.iew.lsq.thread0.rescheduledLoads 376 # Number of loads that were rescheduled 1256system.cpu1.iew.lsq.thread0.cacheBlocked 11381 # Number of times an access to memory failed due to the cache being blocked |
| 1259system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1257system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1260system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing 1261system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking 1262system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking 1263system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ 1264system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch 1265system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions 1266system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions 1267system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions 1268system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall 1269system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall 1270system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations 1271system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly 1272system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly 1273system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute 1274system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions 1275system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed 1276system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute | 1258system.cpu1.iew.iewSquashCycles 320458 # Number of cycles IEW is squashing 1259system.cpu1.iew.iewBlockCycles 536973 # Number of cycles IEW is blocking 1260system.cpu1.iew.iewUnblockCycles 73252 # Number of cycles IEW is unblocking 1261system.cpu1.iew.iewDispatchedInsts 14361364 # Number of instructions dispatched to IQ 1262system.cpu1.iew.iewDispSquashedInsts 205800 # Number of squashed instructions skipped by dispatch 1263system.cpu1.iew.iewDispLoadInsts 2639269 # Number of dispatched load instructions 1264system.cpu1.iew.iewDispStoreInsts 1825014 # Number of dispatched store instructions 1265system.cpu1.iew.iewDispNonSpecInsts 596393 # Number of dispatched non-speculative instructions 1266system.cpu1.iew.iewIQFullEvents 55379 # Number of times the IQ has become full, causing a stall 1267system.cpu1.iew.iewLSQFullEvents 5710 # Number of times the LSQ has become full, causing a stall 1268system.cpu1.iew.memOrderViolationEvents 2268 # Number of memory order violations 1269system.cpu1.iew.predictedTakenIncorrect 53644 # Number of branches that were predicted taken incorrectly 1270system.cpu1.iew.predictedNotTakenIncorrect 129908 # Number of branches that were predicted not taken incorrectly 1271system.cpu1.iew.branchMispredicts 183552 # Number of branch mispredicts detected at execute 1272system.cpu1.iew.iewExecutedInsts 12575424 # Number of executed instructions 1273system.cpu1.iew.iewExecLoadInsts 2521777 # Number of load instructions executed 1274system.cpu1.iew.iewExecSquashedInsts 121030 # Number of squashed instructions skipped in execute |
| 1277system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1275system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1278system.cpu1.iew.exec_nop 726447 # number of nop insts executed 1279system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed 1280system.cpu1.iew.exec_branches 1887172 # Number of branches executed 1281system.cpu1.iew.exec_stores 1746592 # Number of stores executed 1282system.cpu1.iew.exec_rate 0.553740 # Inst execution rate 1283system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit 1284system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back 1285system.cpu1.iew.wb_producers 5700900 # num instructions producing a value 1286system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value | 1276system.cpu1.iew.exec_nop 726256 # number of nop insts executed 1277system.cpu1.iew.exec_refs 4267761 # number of memory reference insts executed 1278system.cpu1.iew.exec_branches 1886646 # Number of branches executed 1279system.cpu1.iew.exec_stores 1745984 # Number of stores executed 1280system.cpu1.iew.exec_rate 0.553602 # Inst execution rate 1281system.cpu1.iew.wb_sent 12512047 # cumulative count of insts sent to commit 1282system.cpu1.iew.wb_count 12478060 # cumulative count of insts written-back 1283system.cpu1.iew.wb_producers 5698826 # num instructions producing a value 1284system.cpu1.iew.wb_consumers 8037620 # num instructions consuming a value |
| 1287system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1285system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1288system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle 1289system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back | 1286system.cpu1.iew.wb_rate 0.549316 # insts written-back per cycle 1287system.cpu1.iew.wb_fanout 0.709019 # average fanout of values written-back |
| 1290system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1288system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1291system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions 1292system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions 1293system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit 1294system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards 1295system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted 1296system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle 1297system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle 1298system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle | 1289system.cpu1.commit.commitCommittedInsts 12432644 # The number of committed instructions 1290system.cpu1.commit.commitCommittedOps 12432644 # The number of committed instructions 1291system.cpu1.commit.commitSquashedInsts 1853978 # The number of squashed insts skipped by commit 1292system.cpu1.commit.commitNonSpecStalls 195741 # The number of times commit has been forced to stall to communicate backwards 1293system.cpu1.commit.branchMispredicts 172939 # The number of times a branch was mispredicted 1294system.cpu1.commit.committed_per_cycle::samples 20454717 # Number of insts commited each cycle 1295system.cpu1.commit.committed_per_cycle::mean 0.607813 # Number of insts commited each cycle 1296system.cpu1.commit.committed_per_cycle::stdev 1.554325 # Number of insts commited each cycle |
| 1299system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1297system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1300system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle 1307system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle 1308system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle | 1298system.cpu1.commit.committed_per_cycle::0 15840554 77.44% 77.44% # Number of insts commited each cycle 1299system.cpu1.commit.committed_per_cycle::1 2123906 10.38% 87.83% # Number of insts commited each cycle 1300system.cpu1.commit.committed_per_cycle::2 810748 3.96% 91.79% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::3 497113 2.43% 94.22% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::4 362163 1.77% 95.99% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::5 133438 0.65% 96.64% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::6 130960 0.64% 97.28% # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::7 152379 0.74% 98.03% # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::8 403456 1.97% 100.00% # Number of insts commited each cycle |
| 1309system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1310system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1311system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1307system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1308system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1309system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1312system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle 1313system.cpu1.commit.committedInsts 12433159 # Number of instructions committed 1314system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed | 1310system.cpu1.commit.committed_per_cycle::total 20454717 # Number of insts commited each cycle 1311system.cpu1.commit.committedInsts 12432644 # Number of instructions committed 1312system.cpu1.commit.committedOps 12432644 # Number of ops (including micro ops) committed |
| 1315system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1313system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1316system.cpu1.commit.refs 3965647 # Number of memory references committed 1317system.cpu1.commit.loads 2293191 # Number of loads committed 1318system.cpu1.commit.membars 64658 # Number of memory barriers committed 1319system.cpu1.commit.branches 1777478 # Number of branches committed | 1314system.cpu1.commit.refs 3965603 # Number of memory references committed 1315system.cpu1.commit.loads 2293163 # Number of loads committed 1316system.cpu1.commit.membars 64660 # Number of memory barriers committed 1317system.cpu1.commit.branches 1777364 # Number of branches committed |
| 1320system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. | 1318system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. |
| 1321system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. | 1319system.cpu1.commit.int_insts 11487490 # Number of committed integer instructions. |
| 1322system.cpu1.commit.function_calls 194670 # Number of function calls committed. | 1320system.cpu1.commit.function_calls 194670 # Number of function calls committed. |
| 1323system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached | 1321system.cpu1.commit.bw_lim_events 403456 # number cycles where commit BW limit reached |
| 1324system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1322system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1325system.cpu1.rob.rob_reads 34238592 # The number of ROB reads 1326system.cpu1.rob.rob_writes 28901418 # The number of ROB writes 1327system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself 1328system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling 1329system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1330system.cpu1.committedInsts 11789199 # Number of Instructions Simulated 1331system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated 1332system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated 1333system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction 1334system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads 1335system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle 1336system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads 1337system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads 1338system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes 1339system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads 1340system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes 1341system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads 1342system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes 1343system.cpu1.icache.replacements 315447 # number of replacements 1344system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use 1345system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. 1346system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. 1347system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. | 1323system.cpu1.rob.rob_reads 34231845 # The number of ROB reads 1324system.cpu1.rob.rob_writes 28892260 # The number of ROB writes 1325system.cpu1.timesIdled 230897 # Number of times that the entire CPU went into an idle state and unscheduled itself 1326system.cpu1.idleCycles 1940465 # Total number of cycles that the CPU has spent unscheduled due to idling 1327system.cpu1.quiesceCycles 3778342351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1328system.cpu1.committedInsts 11788689 # Number of Instructions Simulated 1329system.cpu1.committedOps 11788689 # Number of Ops (including micro ops) Simulated 1330system.cpu1.committedInsts_total 11788689 # Number of Instructions Simulated 1331system.cpu1.cpi 1.926901 # CPI: Cycles Per Instruction 1332system.cpu1.cpi_total 1.926901 # CPI: Total CPI of All Threads 1333system.cpu1.ipc 0.518968 # IPC: Instructions Per Cycle 1334system.cpu1.ipc_total 0.518968 # IPC: Total IPC of All Threads 1335system.cpu1.int_regfile_reads 16191128 # number of integer regfile reads 1336system.cpu1.int_regfile_writes 8793643 # number of integer regfile writes 1337system.cpu1.fp_regfile_reads 73550 # number of floating regfile reads 1338system.cpu1.fp_regfile_writes 74224 # number of floating regfile writes 1339system.cpu1.misc_regfile_reads 699686 # number of misc regfile reads 1340system.cpu1.misc_regfile_writes 299450 # number of misc regfile writes 1341system.cpu1.icache.replacements 315418 # number of replacements 1342system.cpu1.icache.tagsinuse 471.006638 # Cycle average of tags in use 1343system.cpu1.icache.total_refs 1633897 # Total number of references to valid blocks. 1344system.cpu1.icache.sampled_refs 315930 # Sample count of references to valid blocks. 1345system.cpu1.icache.avg_refs 5.171706 # Average number of references to valid blocks. |
| 1348system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. | 1346system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. |
| 1349system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor 1350system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy 1351system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy 1352system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits 1353system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits 1354system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits 1355system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits 1356system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits 1357system.cpu1.icache.overall_hits::total 1635327 # number of overall hits 1358system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses 1359system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses 1360system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses 1361system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses 1362system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses 1363system.cpu1.icache.overall_misses::total 328187 # number of overall misses 1364system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles 1365system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles 1366system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles 1367system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles 1368system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles 1369system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles 1370system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) 1371system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) 1372system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses 1373system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses 1374system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses 1375system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses 1376system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses 1377system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses 1378system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses 1379system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses 1380system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses 1381system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses 1382system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency 1383system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency 1384system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency 1385system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency 1386system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency 1387system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency 1388system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked | 1347system.cpu1.icache.occ_blocks::cpu1.inst 471.006638 # Average occupied blocks per requestor 1348system.cpu1.icache.occ_percent::cpu1.inst 0.919935 # Average percentage of cache occupancy 1349system.cpu1.icache.occ_percent::total 0.919935 # Average percentage of cache occupancy 1350system.cpu1.icache.ReadReq_hits::cpu1.inst 1633897 # number of ReadReq hits 1351system.cpu1.icache.ReadReq_hits::total 1633897 # number of ReadReq hits 1352system.cpu1.icache.demand_hits::cpu1.inst 1633897 # number of demand (read+write) hits 1353system.cpu1.icache.demand_hits::total 1633897 # number of demand (read+write) hits 1354system.cpu1.icache.overall_hits::cpu1.inst 1633897 # number of overall hits 1355system.cpu1.icache.overall_hits::total 1633897 # number of overall hits 1356system.cpu1.icache.ReadReq_misses::cpu1.inst 328148 # number of ReadReq misses 1357system.cpu1.icache.ReadReq_misses::total 328148 # number of ReadReq misses 1358system.cpu1.icache.demand_misses::cpu1.inst 328148 # number of demand (read+write) misses 1359system.cpu1.icache.demand_misses::total 328148 # number of demand (read+write) misses 1360system.cpu1.icache.overall_misses::cpu1.inst 328148 # number of overall misses 1361system.cpu1.icache.overall_misses::total 328148 # number of overall misses 1362system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323185498 # number of ReadReq miss cycles 1363system.cpu1.icache.ReadReq_miss_latency::total 5323185498 # number of ReadReq miss cycles 1364system.cpu1.icache.demand_miss_latency::cpu1.inst 5323185498 # number of demand (read+write) miss cycles 1365system.cpu1.icache.demand_miss_latency::total 5323185498 # number of demand (read+write) miss cycles 1366system.cpu1.icache.overall_miss_latency::cpu1.inst 5323185498 # number of overall miss cycles 1367system.cpu1.icache.overall_miss_latency::total 5323185498 # number of overall miss cycles 1368system.cpu1.icache.ReadReq_accesses::cpu1.inst 1962045 # number of ReadReq accesses(hits+misses) 1369system.cpu1.icache.ReadReq_accesses::total 1962045 # number of ReadReq accesses(hits+misses) 1370system.cpu1.icache.demand_accesses::cpu1.inst 1962045 # number of demand (read+write) accesses 1371system.cpu1.icache.demand_accesses::total 1962045 # number of demand (read+write) accesses 1372system.cpu1.icache.overall_accesses::cpu1.inst 1962045 # number of overall (read+write) accesses 1373system.cpu1.icache.overall_accesses::total 1962045 # number of overall (read+write) accesses 1374system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167248 # miss rate for ReadReq accesses 1375system.cpu1.icache.ReadReq_miss_rate::total 0.167248 # miss rate for ReadReq accesses 1376system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167248 # miss rate for demand accesses 1377system.cpu1.icache.demand_miss_rate::total 0.167248 # miss rate for demand accesses 1378system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167248 # miss rate for overall accesses 1379system.cpu1.icache.overall_miss_rate::total 0.167248 # miss rate for overall accesses 1380system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439 # average ReadReq miss latency 1381system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439 # average ReadReq miss latency 1382system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency 1383system.cpu1.icache.demand_avg_miss_latency::total 16221.904439 # average overall miss latency 1384system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency 1385system.cpu1.icache.overall_avg_miss_latency::total 16221.904439 # average overall miss latency 1386system.cpu1.icache.blocked_cycles::no_mshrs 248998 # number of cycles access was blocked |
| 1389system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1387system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1390system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked | 1388system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked |
| 1391system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1389system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1392system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked | 1390system.cpu1.icache.avg_blocked_cycles::no_mshrs 5928.523810 # average number of cycles each access was blocked |
| 1393system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1394system.cpu1.icache.fast_writes 0 # number of fast writes performed 1395system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1391system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1392system.cpu1.icache.fast_writes 0 # number of fast writes performed 1393system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1396system.cpu1.icache.writebacks::writebacks 38 # number of writebacks 1397system.cpu1.icache.writebacks::total 38 # number of writebacks 1398system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits 1399system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits 1400system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits 1401system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits 1402system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits 1403system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits 1404system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses 1405system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses 1406system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses 1407system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses 1408system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses 1409system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses 1410system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles 1411system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles 1412system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles 1413system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles 1414system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles 1415system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles 1416system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses 1417system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses 1418system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses 1419system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses 1420system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses 1421system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses 1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency 1423system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency 1424system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency 1425system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency 1426system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency 1427system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency | 1394system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12162 # number of ReadReq MSHR hits 1395system.cpu1.icache.ReadReq_mshr_hits::total 12162 # number of ReadReq MSHR hits 1396system.cpu1.icache.demand_mshr_hits::cpu1.inst 12162 # number of demand (read+write) MSHR hits 1397system.cpu1.icache.demand_mshr_hits::total 12162 # number of demand (read+write) MSHR hits 1398system.cpu1.icache.overall_mshr_hits::cpu1.inst 12162 # number of overall MSHR hits 1399system.cpu1.icache.overall_mshr_hits::total 12162 # number of overall MSHR hits 1400system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315986 # number of ReadReq MSHR misses 1401system.cpu1.icache.ReadReq_mshr_misses::total 315986 # number of ReadReq MSHR misses 1402system.cpu1.icache.demand_mshr_misses::cpu1.inst 315986 # number of demand (read+write) MSHR misses 1403system.cpu1.icache.demand_mshr_misses::total 315986 # number of demand (read+write) MSHR misses 1404system.cpu1.icache.overall_mshr_misses::cpu1.inst 315986 # number of overall MSHR misses 1405system.cpu1.icache.overall_mshr_misses::total 315986 # number of overall MSHR misses 1406system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183764998 # number of ReadReq MSHR miss cycles 1407system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183764998 # number of ReadReq MSHR miss cycles 1408system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183764998 # number of demand (read+write) MSHR miss cycles 1409system.cpu1.icache.demand_mshr_miss_latency::total 4183764998 # number of demand (read+write) MSHR miss cycles 1410system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183764998 # number of overall MSHR miss cycles 1411system.cpu1.icache.overall_mshr_miss_latency::total 4183764998 # number of overall MSHR miss cycles 1412system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for ReadReq accesses 1413system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.161049 # mshr miss rate for ReadReq accesses 1414system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for demand accesses 1415system.cpu1.icache.demand_mshr_miss_rate::total 0.161049 # mshr miss rate for demand accesses 1416system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for overall accesses 1417system.cpu1.icache.overall_mshr_miss_rate::total 0.161049 # mshr miss rate for overall accesses 1418system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average ReadReq mshr miss latency 1419system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250 # average ReadReq mshr miss latency 1420system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency 1421system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency 1422system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency 1423system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency |
| 1428system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1424system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1429system.cpu1.dcache.replacements 159076 # number of replacements 1430system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use 1431system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks. 1432system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks. 1433system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks. | 1425system.cpu1.dcache.replacements 159031 # number of replacements 1426system.cpu1.dcache.tagsinuse 488.853384 # Cycle average of tags in use 1427system.cpu1.dcache.total_refs 3387429 # Total number of references to valid blocks. 1428system.cpu1.dcache.sampled_refs 159543 # Sample count of references to valid blocks. 1429system.cpu1.dcache.avg_refs 21.232075 # Average number of references to valid blocks. |
| 1434system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. | 1430system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. |
| 1435system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor 1436system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy 1437system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy 1438system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits 1439system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits 1440system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits 1441system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits 1442system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits 1443system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits | 1431system.cpu1.dcache.occ_blocks::cpu1.data 488.853384 # Average occupied blocks per requestor 1432system.cpu1.dcache.occ_percent::cpu1.data 0.954792 # Average percentage of cache occupancy 1433system.cpu1.dcache.occ_percent::total 0.954792 # Average percentage of cache occupancy 1434system.cpu1.dcache.ReadReq_hits::cpu1.data 2021122 # number of ReadReq hits 1435system.cpu1.dcache.ReadReq_hits::total 2021122 # number of ReadReq hits 1436system.cpu1.dcache.WriteReq_hits::cpu1.data 1250999 # number of WriteReq hits 1437system.cpu1.dcache.WriteReq_hits::total 1250999 # number of WriteReq hits 1438system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49956 # number of LoadLockedReq hits 1439system.cpu1.dcache.LoadLockedReq_hits::total 49956 # number of LoadLockedReq hits |
| 1444system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits 1445system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits | 1440system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits 1441system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits |
| 1446system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits 1447system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits 1448system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits 1449system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits 1450system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses 1451system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses 1452system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses 1453system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses 1454system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses 1455system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses 1456system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses 1457system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses 1458system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses 1459system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses 1460system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses 1461system.cpu1.dcache.overall_misses::total 668020 # number of overall misses 1462system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles 1463system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles 1464system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles 1465system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles 1466system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles 1467system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles 1468system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles 1469system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles 1470system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles 1471system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles 1472system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles 1473system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles 1474system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses) 1475system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses) 1476system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses) 1477system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses) 1478system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses) 1479system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses) 1480system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses) 1481system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses) 1482system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses 1483system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses 1484system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses 1485system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses 1486system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses 1487system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses 1488system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses 1489system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency 1506system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency 1507system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency 1508system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency 1509system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency 1510system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked | 1442system.cpu1.dcache.demand_hits::cpu1.data 3272121 # number of demand (read+write) hits 1443system.cpu1.dcache.demand_hits::total 3272121 # number of demand (read+write) hits 1444system.cpu1.dcache.overall_hits::cpu1.data 3272121 # number of overall hits 1445system.cpu1.dcache.overall_hits::total 3272121 # number of overall hits 1446system.cpu1.dcache.ReadReq_misses::cpu1.data 307358 # number of ReadReq misses 1447system.cpu1.dcache.ReadReq_misses::total 307358 # number of ReadReq misses 1448system.cpu1.dcache.WriteReq_misses::cpu1.data 360875 # number of WriteReq misses 1449system.cpu1.dcache.WriteReq_misses::total 360875 # number of WriteReq misses 1450system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8692 # number of LoadLockedReq misses 1451system.cpu1.dcache.LoadLockedReq_misses::total 8692 # number of LoadLockedReq misses 1452system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5047 # number of StoreCondReq misses 1453system.cpu1.dcache.StoreCondReq_misses::total 5047 # number of StoreCondReq misses 1454system.cpu1.dcache.demand_misses::cpu1.data 668233 # number of demand (read+write) misses 1455system.cpu1.dcache.demand_misses::total 668233 # number of demand (read+write) misses 1456system.cpu1.dcache.overall_misses::cpu1.data 668233 # number of overall misses 1457system.cpu1.dcache.overall_misses::total 668233 # number of overall misses 1458system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6376981500 # number of ReadReq miss cycles 1459system.cpu1.dcache.ReadReq_miss_latency::total 6376981500 # number of ReadReq miss cycles 1460system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11324805298 # number of WriteReq miss cycles 1461system.cpu1.dcache.WriteReq_miss_latency::total 11324805298 # number of WriteReq miss cycles 1462system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121402000 # number of LoadLockedReq miss cycles 1463system.cpu1.dcache.LoadLockedReq_miss_latency::total 121402000 # number of LoadLockedReq miss cycles 1464system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68410000 # number of StoreCondReq miss cycles 1465system.cpu1.dcache.StoreCondReq_miss_latency::total 68410000 # number of StoreCondReq miss cycles 1466system.cpu1.dcache.demand_miss_latency::cpu1.data 17701786798 # number of demand (read+write) miss cycles 1467system.cpu1.dcache.demand_miss_latency::total 17701786798 # number of demand (read+write) miss cycles 1468system.cpu1.dcache.overall_miss_latency::cpu1.data 17701786798 # number of overall miss cycles 1469system.cpu1.dcache.overall_miss_latency::total 17701786798 # number of overall miss cycles 1470system.cpu1.dcache.ReadReq_accesses::cpu1.data 2328480 # number of ReadReq accesses(hits+misses) 1471system.cpu1.dcache.ReadReq_accesses::total 2328480 # number of ReadReq accesses(hits+misses) 1472system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611874 # number of WriteReq accesses(hits+misses) 1473system.cpu1.dcache.WriteReq_accesses::total 1611874 # number of WriteReq accesses(hits+misses) 1474system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58648 # number of LoadLockedReq accesses(hits+misses) 1475system.cpu1.dcache.LoadLockedReq_accesses::total 58648 # number of LoadLockedReq accesses(hits+misses) 1476system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53648 # number of StoreCondReq accesses(hits+misses) 1477system.cpu1.dcache.StoreCondReq_accesses::total 53648 # number of StoreCondReq accesses(hits+misses) 1478system.cpu1.dcache.demand_accesses::cpu1.data 3940354 # number of demand (read+write) accesses 1479system.cpu1.dcache.demand_accesses::total 3940354 # number of demand (read+write) accesses 1480system.cpu1.dcache.overall_accesses::cpu1.data 3940354 # number of overall (read+write) accesses 1481system.cpu1.dcache.overall_accesses::total 3940354 # number of overall (read+write) accesses 1482system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131999 # miss rate for ReadReq accesses 1483system.cpu1.dcache.ReadReq_miss_rate::total 0.131999 # miss rate for ReadReq accesses 1484system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223885 # miss rate for WriteReq accesses 1485system.cpu1.dcache.WriteReq_miss_rate::total 0.223885 # miss rate for WriteReq accesses 1486system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148206 # miss rate for LoadLockedReq accesses 1487system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148206 # miss rate for LoadLockedReq accesses 1488system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094076 # miss rate for StoreCondReq accesses 1489system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094076 # miss rate for StoreCondReq accesses 1490system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169587 # miss rate for demand accesses 1491system.cpu1.dcache.demand_miss_rate::total 0.169587 # miss rate for demand accesses 1492system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169587 # miss rate for overall accesses 1493system.cpu1.dcache.overall_miss_rate::total 0.169587 # miss rate for overall accesses 1494system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286 # average ReadReq miss latency 1495system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286 # average ReadReq miss latency 1496system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972 # average WriteReq miss latency 1497system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972 # average WriteReq miss latency 1498system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180 # average LoadLockedReq miss latency 1499system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180 # average LoadLockedReq miss latency 1500system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883 # average StoreCondReq miss latency 1501system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883 # average StoreCondReq miss latency 1502system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency 1503system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906 # average overall miss latency 1504system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency 1505system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906 # average overall miss latency 1506system.cpu1.dcache.blocked_cycles::no_mshrs 57267488 # number of cycles access was blocked |
| 1511system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1507system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1512system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked | 1508system.cpu1.dcache.blocked::no_mshrs 6761 # number of cycles access was blocked |
| 1513system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1509system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1514system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked | 1510system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8470.268895 # average number of cycles each access was blocked |
| 1515system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1516system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1517system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1511system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1512system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1513system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1518system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks 1519system.cpu1.dcache.writebacks::total 112743 # number of writebacks 1520system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits 1521system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits 1522system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits 1523system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits 1524system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits 1525system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits 1526system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits 1527system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits 1528system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits 1529system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits 1530system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses 1531system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses 1532system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses 1533system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses 1534system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses 1535system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses 1536system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses 1537system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses 1538system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses 1539system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses 1540system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses 1541system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses 1542system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles 1543system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles 1544system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles 1545system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles 1546system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles 1547system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles 1548system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles 1549system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles 1550system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles 1551system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles 1552system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles 1553system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles 1554system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles 1555system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles 1556system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles 1557system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles 1558system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles 1559system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles 1560system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses 1561system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses 1562system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses 1563system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses 1564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses 1565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses 1566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses 1567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses 1568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses 1569system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses 1570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses 1571system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses 1572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency 1573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency 1574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency 1575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency 1576system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency 1577system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency 1578system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency 1579system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency 1580system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency 1581system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency 1582system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency 1583system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency | 1514system.cpu1.dcache.writebacks::writebacks 112725 # number of writebacks 1515system.cpu1.dcache.writebacks::total 112725 # number of writebacks 1516system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 197085 # number of ReadReq MSHR hits 1517system.cpu1.dcache.ReadReq_mshr_hits::total 197085 # number of ReadReq MSHR hits 1518system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298748 # number of WriteReq MSHR hits 1519system.cpu1.dcache.WriteReq_mshr_hits::total 298748 # number of WriteReq MSHR hits 1520system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1016 # number of LoadLockedReq MSHR hits 1521system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1016 # number of LoadLockedReq MSHR hits 1522system.cpu1.dcache.demand_mshr_hits::cpu1.data 495833 # number of demand (read+write) MSHR hits 1523system.cpu1.dcache.demand_mshr_hits::total 495833 # number of demand (read+write) MSHR hits 1524system.cpu1.dcache.overall_mshr_hits::cpu1.data 495833 # number of overall MSHR hits 1525system.cpu1.dcache.overall_mshr_hits::total 495833 # number of overall MSHR hits 1526system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110273 # number of ReadReq MSHR misses 1527system.cpu1.dcache.ReadReq_mshr_misses::total 110273 # number of ReadReq MSHR misses 1528system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62127 # number of WriteReq MSHR misses 1529system.cpu1.dcache.WriteReq_mshr_misses::total 62127 # number of WriteReq MSHR misses 1530system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7676 # number of LoadLockedReq MSHR misses 1531system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7676 # number of LoadLockedReq MSHR misses 1532system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5047 # number of StoreCondReq MSHR misses 1533system.cpu1.dcache.StoreCondReq_mshr_misses::total 5047 # number of StoreCondReq MSHR misses 1534system.cpu1.dcache.demand_mshr_misses::cpu1.data 172400 # number of demand (read+write) MSHR misses 1535system.cpu1.dcache.demand_mshr_misses::total 172400 # number of demand (read+write) MSHR misses 1536system.cpu1.dcache.overall_mshr_misses::cpu1.data 172400 # number of overall MSHR misses 1537system.cpu1.dcache.overall_mshr_misses::total 172400 # number of overall MSHR misses 1538system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1761266064 # number of ReadReq MSHR miss cycles 1539system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1761266064 # number of ReadReq MSHR miss cycles 1540system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471935334 # number of WriteReq MSHR miss cycles 1541system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471935334 # number of WriteReq MSHR miss cycles 1542system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78208000 # number of LoadLockedReq MSHR miss cycles 1543system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78208000 # number of LoadLockedReq MSHR miss cycles 1544system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52884501 # number of StoreCondReq MSHR miss cycles 1545system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52884501 # number of StoreCondReq MSHR miss cycles 1546system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3233201398 # number of demand (read+write) MSHR miss cycles 1547system.cpu1.dcache.demand_mshr_miss_latency::total 3233201398 # number of demand (read+write) MSHR miss cycles 1548system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3233201398 # number of overall MSHR miss cycles 1549system.cpu1.dcache.overall_mshr_miss_latency::total 3233201398 # number of overall MSHR miss cycles 1550system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18624000 # number of ReadReq MSHR uncacheable cycles 1551system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18624000 # number of ReadReq MSHR uncacheable cycles 1552system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400633000 # number of WriteReq MSHR uncacheable cycles 1553system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400633000 # number of WriteReq MSHR uncacheable cycles 1554system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419257000 # number of overall MSHR uncacheable cycles 1555system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419257000 # number of overall MSHR uncacheable cycles 1556system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047358 # mshr miss rate for ReadReq accesses 1557system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047358 # mshr miss rate for ReadReq accesses 1558system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038543 # mshr miss rate for WriteReq accesses 1559system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038543 # mshr miss rate for WriteReq accesses 1560system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130883 # mshr miss rate for LoadLockedReq accesses 1561system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130883 # mshr miss rate for LoadLockedReq accesses 1562system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094076 # mshr miss rate for StoreCondReq accesses 1563system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094076 # mshr miss rate for StoreCondReq accesses 1564system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for demand accesses 1565system.cpu1.dcache.demand_mshr_miss_rate::total 0.043752 # mshr miss rate for demand accesses 1566system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for overall accesses 1567system.cpu1.dcache.overall_mshr_miss_rate::total 0.043752 # mshr miss rate for overall accesses 1568system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394 # average ReadReq mshr miss latency 1569system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394 # average ReadReq mshr miss latency 1570system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357 # average WriteReq mshr miss latency 1571system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357 # average WriteReq mshr miss latency 1572system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917 # average LoadLockedReq mshr miss latency 1573system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917 # average LoadLockedReq mshr miss latency 1574system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210 # average StoreCondReq mshr miss latency 1575system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210 # average StoreCondReq mshr miss latency 1576system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency 1577system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency 1578system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency 1579system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency |
| 1584system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1585system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1587system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1589system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1592system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed | 1580system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1581system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1582system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1583system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1584system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1585system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1586system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1587system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1588system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed |
| 1593system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed | 1589system.cpu0.kern.inst.hwrei 167511 # number of hwrei instructions executed |
| 1594system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl 1595system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl 1596system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl 1597system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl | 1590system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl 1591system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl 1592system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl 1593system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl |
| 1598system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl 1599system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl | 1594system.cpu0.kern.ipl_count::31 84510 58.04% 100.00% # number of times we switched to this ipl 1595system.cpu0.kern.ipl_count::total 145602 # number of times we switched to this ipl |
| 1600system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl 1601system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl 1602system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl 1603system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl 1604system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl 1605system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl | 1596system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl 1597system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl 1598system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl 1599system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl 1600system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl 1601system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl |
| 1606system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl 1607system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl 1608system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl 1609system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl 1610system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl 1611system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl | 1602system.cpu0.kern.ipl_ticks::0 1862592154000 98.01% 98.01% # number of cycles we spent at this ipl 1603system.cpu0.kern.ipl_ticks::21 96215500 0.01% 98.02% # number of cycles we spent at this ipl 1604system.cpu0.kern.ipl_ticks::22 394866000 0.02% 98.04% # number of cycles we spent at this ipl 1605system.cpu0.kern.ipl_ticks::30 155183500 0.01% 98.04% # number of cycles we spent at this ipl 1606system.cpu0.kern.ipl_ticks::31 37157983500 1.96% 100.00% # number of cycles we spent at this ipl 1607system.cpu0.kern.ipl_ticks::total 1900396402500 # number of cycles we spent at this ipl |
| 1612system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl 1613system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1614system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1615system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1608system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl 1609system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1610system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1611system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1616system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl 1617system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl | 1612system.cpu0.kern.ipl_used::31 0.681008 # fraction of swpipl calls that actually changed the ipl 1613system.cpu0.kern.ipl_used::total 0.810058 # fraction of swpipl calls that actually changed the ipl |
| 1618system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed 1619system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed 1620system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed 1621system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed 1622system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed 1623system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed 1624system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed 1625system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed --- 23 unchanged lines hidden (view full) --- 1649system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1650system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed 1651system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed 1652system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed 1653system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed 1654system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed 1655system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed 1656system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed | 1614system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed 1615system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed 1616system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed 1617system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed 1618system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed 1619system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed 1620system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed 1621system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed --- 23 unchanged lines hidden (view full) --- 1645system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1646system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed 1647system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed 1648system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed 1649system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed 1650system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed 1651system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed 1652system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed |
| 1657system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed | 1653system.cpu0.kern.callpal::swpipl 138811 90.43% 92.75% # number of callpals executed |
| 1658system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed 1659system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed 1660system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed 1661system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed 1662system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed 1663system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed 1664system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed 1665system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed | 1654system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed 1655system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed 1656system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed 1657system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed 1658system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed 1659system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed 1660system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed 1661system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed |
| 1666system.cpu0.kern.callpal::total 153507 # number of callpals executed | 1662system.cpu0.kern.callpal::total 153508 # number of callpals executed |
| 1667system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches | 1663system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches |
| 1668system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches | 1664system.cpu0.kern.mode_switch::user 1099 # number of protection mode switches |
| 1669system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 1665system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 1670system.cpu0.kern.mode_good::kernel 1098 1671system.cpu0.kern.mode_good::user 1098 | 1666system.cpu0.kern.mode_good::kernel 1099 1667system.cpu0.kern.mode_good::user 1099 |
| 1672system.cpu0.kern.mode_good::idle 0 | 1668system.cpu0.kern.mode_good::idle 0 |
| 1673system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches | 1669system.cpu0.kern.mode_switch_good::kernel 0.164275 # fraction of useful protection mode switches |
| 1674system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1675system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 1670system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1671system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 1676system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches 1677system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode 1678system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode | 1672system.cpu0.kern.mode_switch_good::total 0.282193 # fraction of useful protection mode switches 1673system.cpu0.kern.mode_ticks::kernel 1897960603000 99.90% 99.90% # number of ticks spent at the given mode 1674system.cpu0.kern.mode_ticks::user 1864923000 0.10% 100.00% # number of ticks spent at the given mode |
| 1679system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1680system.cpu0.kern.swap_context 3077 # number of times the context was actually changed 1681system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1682system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed | 1675system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1676system.cpu0.kern.swap_context 3077 # number of times the context was actually changed 1677system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1678system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed |
| 1683system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed 1684system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl 1685system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl | 1679system.cpu1.kern.inst.hwrei 74469 # number of hwrei instructions executed 1680system.cpu1.kern.ipl_count::0 24566 38.36% 38.36% # number of times we switched to this ipl 1681system.cpu1.kern.ipl_count::22 1923 3.00% 41.37% # number of times we switched to this ipl |
| 1686system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl | 1682system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl |
| 1687system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl 1688system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl 1689system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl | 1683system.cpu1.kern.ipl_count::31 37109 57.95% 100.00% # number of times we switched to this ipl 1684system.cpu1.kern.ipl_count::total 64037 # number of times we switched to this ipl 1685system.cpu1.kern.ipl_good::0 23887 48.07% 48.07% # number of times we switched to this ipl from a different ipl |
| 1690system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl 1691system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl | 1686system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl 1687system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl |
| 1692system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl 1693system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl 1694system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl 1695system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl 1696system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl 1697system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl 1698system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl 1699system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl | 1688system.cpu1.kern.ipl_good::31 23448 47.18% 100.00% # number of times we switched to this ipl from a different ipl 1689system.cpu1.kern.ipl_good::total 49697 # number of times we switched to this ipl from a different ipl 1690system.cpu1.kern.ipl_ticks::0 1870827131500 98.44% 98.44% # number of cycles we spent at this ipl 1691system.cpu1.kern.ipl_ticks::22 343570500 0.02% 98.46% # number of cycles we spent at this ipl 1692system.cpu1.kern.ipl_ticks::30 182754500 0.01% 98.46% # number of cycles we spent at this ipl 1693system.cpu1.kern.ipl_ticks::31 29175936000 1.54% 100.00% # number of cycles we spent at this ipl 1694system.cpu1.kern.ipl_ticks::total 1900529392500 # number of cycles we spent at this ipl 1695system.cpu1.kern.ipl_used::0 0.972360 # fraction of swpipl calls that actually changed the ipl |
| 1700system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1701system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1696system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1697system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1702system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl 1703system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl | 1698system.cpu1.kern.ipl_used::31 0.631868 # fraction of swpipl calls that actually changed the ipl 1699system.cpu1.kern.ipl_used::total 0.776067 # fraction of swpipl calls that actually changed the ipl |
| 1704system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed 1705system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed 1706system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed 1707system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed 1708system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed 1709system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed 1710system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed 1711system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed --- 13 unchanged lines hidden (view full) --- 1725system.cpu1.kern.syscall::total 116 # number of syscalls executed 1726system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1727system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed 1728system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed 1729system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed 1730system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed 1731system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed 1732system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed | 1700system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed 1701system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed 1702system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed 1703system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed 1704system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed 1705system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed 1706system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed 1707system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed --- 13 unchanged lines hidden (view full) --- 1721system.cpu1.kern.syscall::total 116 # number of syscalls executed 1722system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1723system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed 1724system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed 1725system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed 1726system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed 1727system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed 1728system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed |
| 1733system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed | 1729system.cpu1.kern.callpal::swpipl 57994 87.22% 90.51% # number of callpals executed |
| 1734system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed | 1730system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed |
| 1735system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed | 1731system.cpu1.kern.callpal::wrkgp 1 0.00% 94.12% # number of callpals executed |
| 1736system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed 1737system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed 1738system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed 1739system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed 1740system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed 1741system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed 1742system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1732system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed 1733system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed 1734system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed 1735system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed 1736system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed 1737system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed 1738system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1743system.cpu1.kern.callpal::total 66490 # number of callpals executed | 1739system.cpu1.kern.callpal::total 66492 # number of callpals executed |
| 1744system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches 1745system.cpu1.kern.mode_switch::user 641 # number of protection mode switches 1746system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches 1747system.cpu1.kern.mode_good::kernel 1003 1748system.cpu1.kern.mode_good::user 641 1749system.cpu1.kern.mode_good::idle 362 1750system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches 1751system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1752system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches 1753system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches | 1740system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches 1741system.cpu1.kern.mode_switch::user 641 # number of protection mode switches 1742system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches 1743system.cpu1.kern.mode_good::kernel 1003 1744system.cpu1.kern.mode_good::user 641 1745system.cpu1.kern.mode_good::idle 362 1746system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches 1747system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1748system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches 1749system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches |
| 1754system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode 1755system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode 1756system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode | 1750system.cpu1.kern.mode_ticks::kernel 7877089500 0.41% 0.41% # number of ticks spent at the given mode 1751system.cpu1.kern.mode_ticks::user 911545000 0.05% 0.46% # number of ticks spent at the given mode 1752system.cpu1.kern.mode_ticks::idle 1891740750000 99.54% 100.00% # number of ticks spent at the given mode |
| 1757system.cpu1.kern.swap_context 1825 # number of times the context was actually changed 1758 1759---------- End Simulation Statistics ---------- | 1753system.cpu1.kern.swap_context 1825 # number of times the context was actually changed 1754 1755---------- End Simulation Statistics ---------- |