| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.896396 # Number of seconds simulated 4sim_ticks 1896395899500 # Number of ticks simulated 5final_tick 1896395899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.900531 # Number of seconds simulated 4sim_ticks 1900530800500 # Number of ticks simulated 5final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 196112 # Simulator instruction rate (inst/s) 8host_op_rate 196112 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6628227410 # Simulator tick rate (ticks/s) 10host_mem_usage 302056 # Number of bytes of host memory used 11host_seconds 286.11 # Real time elapsed on the host 12sim_insts 56109524 # Number of instructions simulated 13sim_ops 56109524 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 881728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24808704 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 99648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 472640 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28913408 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 881728 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 99648 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 981376 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7865856 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7865856 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13777 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 387636 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1557 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 7385 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 451772 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122904 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122904 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 464949 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 13082028 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1397750 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 52546 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 249231 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15246504 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 464949 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 52546 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 517495 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4147792 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4147792 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4147792 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 464949 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 13082028 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1397750 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 52546 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 249231 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19394296 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 344859 # number of replacements 52system.l2c.tagsinuse 65321.127934 # Cycle average of tags in use 53system.l2c.total_refs 2609636 # Total number of references to valid blocks. 54system.l2c.sampled_refs 410035 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.364423 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 6312493000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 53767.491128 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 5338.607060 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 6047.920982 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 140.590955 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 26.517809 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.820427 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.081461 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.092284 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.002145 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000405 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.996721 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 978177 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 784326 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 102747 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 33274 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1898524 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 832872 # number of Writeback hits 74system.l2c.Writeback_hits::total 832872 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 159 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 200 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 175658 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 7994 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 183652 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 978177 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 959984 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 102747 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 41268 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2082176 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 978177 # number of overall hits 90system.l2c.overall_hits::cpu0.data 959984 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 102747 # number of overall hits 92system.l2c.overall_hits::cpu1.data 41268 # number of overall hits 93system.l2c.overall_hits::total 2082176 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13779 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 273160 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1574 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 765 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 289278 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2448 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 557 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3005 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 42 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 122 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 114897 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 6716 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 121613 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13779 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 388057 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1574 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 7481 # number of demand (read+write) misses 112system.l2c.demand_misses::total 410891 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13779 # number of overall misses 114system.l2c.overall_misses::cpu0.data 388057 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1574 # number of overall misses 116system.l2c.overall_misses::cpu1.data 7481 # number of overall misses 117system.l2c.overall_misses::total 410891 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 720793500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14208419500 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 82364000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 41213000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 15052790000 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2256000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 1409000 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 3665000 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 419000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 157000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 576000 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6027292500 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 352112000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6379404500 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 720793500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20235712000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 82364000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 393325000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21432194500 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 720793500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20235712000 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 82364000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 393325000 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21432194500 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 991956 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 1057486 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 104321 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 34039 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2187802 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 832872 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 832872 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 2607 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 598 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3205 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 71 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 102 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 173 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 290555 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 14710 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 305265 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 991956 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1348041 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 104321 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 48749 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2493067 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 991956 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1348041 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 104321 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 48749 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2493067 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.013891 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.258311 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.015088 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.022474 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.132223 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939010 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.931438 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.937598 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591549 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.784314 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.705202 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.395440 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.456560 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.398385 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.013891 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.287867 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.015088 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.153460 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.164813 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.013891 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.287867 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.015088 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.153460 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.164813 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52035.723422 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 921.568627 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2529.622980 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 1219.633943 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9976.190476 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1962.500000 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 4721.311475 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52456.600035 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52160.291902 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52160.291902 # average overall miss latency | 7host_inst_rate 119697 # Simulator instruction rate (inst/s) 8host_op_rate 119697 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3968630665 # Simulator tick rate (ticks/s) 10host_mem_usage 303044 # Number of bytes of host memory used 11host_seconds 478.89 # Real time elapsed on the host 12sim_insts 57321719 # Number of instructions simulated 13sim_ops 57321719 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 345959 # number of replacements 52system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use 53system.l2c.total_refs 2564962 # Total number of references to valid blocks. 54system.l2c.sampled_refs 411131 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.238795 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits 74system.l2c.Writeback_hits::total 806312 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits 90system.l2c.overall_hits::cpu0.data 817538 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits 92system.l2c.overall_hits::cpu1.data 145338 # number of overall hits 93system.l2c.overall_hits::total 2054695 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses 112system.l2c.demand_misses::total 412362 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses 114system.l2c.overall_misses::cpu0.data 386058 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10924 # number of overall misses 117system.l2c.overall_misses::total 412362 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 3107000 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 549004499 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6610096496 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 728665998 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20275260996 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 90803000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 596081998 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21690811992 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 728665998 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20275260996 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 90803000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 596081998 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21690811992 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 791216 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 962482 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 315983 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 101848 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2171529 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 806312 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 806312 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 3043 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 2008 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 5051 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 777 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 1554 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 241114 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 54414 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 791216 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1203596 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 315983 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 156262 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2467057 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 791216 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1203596 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 315983 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 156262 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2467057 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.017295 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.283607 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.005367 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.008454 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.133182 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942162 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780876 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.878044 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934363 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.961390 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.947876 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.469035 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.184934 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.416725 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.017295 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.320754 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.005367 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.069908 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.167147 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.017295 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.320754 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.005367 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.069908 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency |
| 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed | 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed |
| 224system.l2c.writebacks::writebacks 81384 # number of writebacks 225system.l2c.writebacks::total 81384 # number of writebacks | 224system.l2c.writebacks::writebacks 82258 # number of writebacks 225system.l2c.writebacks::total 82258 # number of writebacks |
| 226system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 228system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 229system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 230system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 231system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 232system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 233system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 234system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits | 226system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 228system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 229system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 230system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 231system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 232system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 233system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 234system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits |
| 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13778 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 273160 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 1557 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 765 # number of ReadReq MSHR misses 239system.l2c.ReadReq_mshr_misses::total 289260 # number of ReadReq MSHR misses 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2448 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 557 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 3005 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 42 # number of SCUpgradeReq MSHR misses 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses 245system.l2c.SCUpgradeReq_mshr_misses::total 122 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 114897 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 6716 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 121613 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13778 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 388057 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 1557 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 7481 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 410873 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13778 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 388057 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 1557 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 7481 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 410873 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 552060500 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10929358000 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62432500 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 31914000 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 11575765000 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97983500 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22281000 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 120264500 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1681500 # number of SCUpgradeReq MSHR miss cycles 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3200000 # number of SCUpgradeReq MSHR miss cycles 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 4881500 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4629799500 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270393000 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 4900192500 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 552060500 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15559157500 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 62432500 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 302307000 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 16475957500 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 552060500 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15559157500 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 62432500 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 302307000 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 16475957500 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 821481000 # number of ReadReq MSHR uncacheable cycles 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16663000 # number of ReadReq MSHR uncacheable cycles 285system.l2c.ReadReq_mshr_uncacheable_latency::total 838144000 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1131946998 # number of WriteReq MSHR uncacheable cycles 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 287746500 # number of WriteReq MSHR uncacheable cycles 288system.l2c.WriteReq_mshr_uncacheable_latency::total 1419693498 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1953427998 # number of overall MSHR uncacheable cycles 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 304409500 # number of overall MSHR uncacheable cycles 291system.l2c.overall_mshr_uncacheable_latency::total 2257837498 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.258311 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022474 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.132215 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939010 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.931438 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.937598 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591549 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784314 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.705202 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.395440 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.456560 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.398385 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.164806 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013890 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.287867 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014925 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.153460 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.164806 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40010.828818 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41717.647059 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.547328 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.939542 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.795332 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40021.464226 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.714286 # average SCUpgradeReq mshr miss latency | 235system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses 237system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses 238system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses 239system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses 240system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses 241system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses 242system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses 243system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses 244system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses 245system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses 246system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses 247system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses 248system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses 249system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses 251system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses 252system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses 253system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses 254system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses 256system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses 257system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses 258system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses 259system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles 261system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles 262system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles 263system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles 264system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles 265system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles 266system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles 267system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles 268system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles 269system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles 270system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles 271system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles 272system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles 275system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles 276system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles 277system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles 280system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles 281system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles 282system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles 283system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles 284system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles 285system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles 286system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles 287system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles 288system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles 289system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles 290system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles 291system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles 292system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses 294system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses 295system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses 296system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses 297system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses 298system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses 299system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses 300system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses 301system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses 302system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses 303system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses 304system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses 305system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses 306system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses 308system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses 309system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses 310system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses 311system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses 313system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses 314system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses 315system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency 318system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency 319system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency 320system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency 321system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency 322system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency 323system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency 324system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency |
| 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency | 325system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency |
| 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40012.295082 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40295.216585 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40261.018463 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.328016 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40068.260996 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40095.031142 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40097.944766 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40409.971929 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40099.878795 # average overall mshr miss latency | 326system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency 327system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency 328system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency 329system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency 332system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency 333system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency 334system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency 337system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency 338system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency 339system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency |
| 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 340system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 341system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 342system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 343system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 344system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 345system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 346system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 347system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 348system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 349system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 350system.iocache.replacements 41697 # number of replacements 351system.iocache.tagsinuse 0.462803 # Cycle average of tags in use | 350system.iocache.replacements 41698 # number of replacements 351system.iocache.tagsinuse 0.465240 # Cycle average of tags in use |
| 352system.iocache.total_refs 0 # Total number of references to valid blocks. | 352system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 353system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. | 353system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. |
| 354system.iocache.avg_refs 0 # Average number of references to valid blocks. | 354system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 355system.iocache.warmup_cycle 1708345741000 # Cycle when the warmup percentage was hit. 356system.iocache.occ_blocks::tsunami.ide 0.462803 # Average occupied blocks per requestor 357system.iocache.occ_percent::tsunami.ide 0.028925 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.028925 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 177 # number of ReadReq misses | 355system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit. 356system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor 357system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy 358system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy 359system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 178 # number of ReadReq misses |
| 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses | 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses |
| 363system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41729 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses 366system.iocache.overall_misses::total 41729 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 20390998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 20390998 # number of ReadReq miss cycles 369system.iocache.WriteReq_miss_latency::tsunami.ide 5719191806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 5719191806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 5739582804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 5739582804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 5739582804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 5739582804 # number of overall miss cycles 375system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) | 363system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 366system.iocache.overall_misses::total 41730 # number of overall misses 367system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles 369system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles 375system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) |
| 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) | 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) |
| 379system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses | 379system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses |
| 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 115203.378531 # average ReadReq miss latency 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 137639.386937 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 137544.221141 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 137544.221141 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 64663068 # number of cycles access was blocked | 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked |
| 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 401system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked | 401system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked |
| 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 403system.iocache.avg_blocked_cycles::no_mshrs 6183.711198 # average number of cycles each access was blocked | 403system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked |
| 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks | 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41520 # number of writebacks 408system.iocache.writebacks::total 41520 # number of writebacks |
| 409system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses | 409system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses |
| 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses | 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses |
| 413system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11186998 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11186998 # number of ReadReq MSHR miss cycles 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3558333000 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 3558333000 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 3569519998 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 3569519998 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 3569519998 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 3569519998 # number of overall MSHR miss cycles | 413system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles |
| 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531 # average ReadReq mshr miss latency 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 85540.511347 # average overall mshr miss latency | 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency |
| 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu0.dtb.fetch_hits 0 # ITB hits 455system.cpu0.dtb.fetch_misses 0 # ITB misses 456system.cpu0.dtb.fetch_acv 0 # ITB acv 457system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 458system.cpu0.dtb.read_hits 9453856 # DTB read hits 459system.cpu0.dtb.read_misses 36184 # DTB read misses 460system.cpu0.dtb.read_acv 571 # DTB read access violations 461system.cpu0.dtb.read_accesses 675976 # DTB read accesses 462system.cpu0.dtb.write_hits 6300368 # DTB write hits 463system.cpu0.dtb.write_misses 8347 # DTB write misses 464system.cpu0.dtb.write_acv 346 # DTB write access violations 465system.cpu0.dtb.write_accesses 234133 # DTB write accesses 466system.cpu0.dtb.data_hits 15754224 # DTB hits 467system.cpu0.dtb.data_misses 44531 # DTB misses 468system.cpu0.dtb.data_acv 917 # DTB access violations 469system.cpu0.dtb.data_accesses 910109 # DTB accesses 470system.cpu0.itb.fetch_hits 1108660 # ITB hits 471system.cpu0.itb.fetch_misses 28136 # ITB misses 472system.cpu0.itb.fetch_acv 1047 # ITB acv 473system.cpu0.itb.fetch_accesses 1136796 # ITB accesses | 458system.cpu0.dtb.read_hits 8334313 # DTB read hits 459system.cpu0.dtb.read_misses 29661 # DTB read misses 460system.cpu0.dtb.read_acv 416 # DTB read access violations 461system.cpu0.dtb.read_accesses 650050 # DTB read accesses 462system.cpu0.dtb.write_hits 5360515 # DTB write hits 463system.cpu0.dtb.write_misses 6017 # DTB write misses 464system.cpu0.dtb.write_acv 275 # DTB write access violations 465system.cpu0.dtb.write_accesses 211537 # DTB write accesses 466system.cpu0.dtb.data_hits 13694828 # DTB hits 467system.cpu0.dtb.data_misses 35678 # DTB misses 468system.cpu0.dtb.data_acv 691 # DTB access violations 469system.cpu0.dtb.data_accesses 861587 # DTB accesses 470system.cpu0.itb.fetch_hits 972456 # ITB hits 471system.cpu0.itb.fetch_misses 29747 # ITB misses 472system.cpu0.itb.fetch_acv 802 # ITB acv 473system.cpu0.itb.fetch_accesses 1002203 # ITB accesses |
| 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses | 474system.cpu0.itb.read_hits 0 # DTB read hits 475system.cpu0.itb.read_misses 0 # DTB read misses 476system.cpu0.itb.read_acv 0 # DTB read access violations 477system.cpu0.itb.read_accesses 0 # DTB read accesses 478system.cpu0.itb.write_hits 0 # DTB write hits 479system.cpu0.itb.write_misses 0 # DTB write misses 480system.cpu0.itb.write_acv 0 # DTB write access violations 481system.cpu0.itb.write_accesses 0 # DTB write accesses 482system.cpu0.itb.data_hits 0 # DTB hits 483system.cpu0.itb.data_misses 0 # DTB misses 484system.cpu0.itb.data_acv 0 # DTB access violations 485system.cpu0.itb.data_accesses 0 # DTB accesses |
| 486system.cpu0.numCycles 111705884 # number of cpu cycles simulated | 486system.cpu0.numCycles 107494535 # number of cpu cycles simulated |
| 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 489system.cpu0.BPredUnit.lookups 13423445 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 11229595 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 405618 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 9732141 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5644182 # Number of BTB hits | 489system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups 490system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted 491system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect 492system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups 493system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits |
| 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 494system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 495system.cpu0.BPredUnit.usedRAS 889528 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 35792 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 28347650 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 67883922 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 13423445 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 6533710 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 12779049 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1882893 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 34959873 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 30735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 200156 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 304542 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 145 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 8317299 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 264993 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 77847394 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.872013 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.211541 # Number of instructions fetched each cycle (Total) | 495system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target. 496system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions. 497system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss 498system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed 499system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered 500system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken 501system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked 502system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing 503system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked 504system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 505system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps 506system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions 507system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR 508system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched 509system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed 510system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total) 511system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total) 512system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total) |
| 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 513system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 514system.cpu0.fetch.rateDist::0 65068345 83.58% 83.58% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 840291 1.08% 84.66% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1663244 2.14% 86.80% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 773630 0.99% 87.79% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2654406 3.41% 91.20% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 587924 0.76% 91.96% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 633021 0.81% 92.77% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 971381 1.25% 94.02% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4655152 5.98% 100.00% # Number of instructions fetched each cycle (Total) | 514system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total) 515system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total) 516system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total) 517system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total) 518system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total) 519system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total) 520system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total) 521system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total) 522system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total) |
| 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 523system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 524system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 525system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 526system.cpu0.fetch.rateDist::total 77847394 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.120168 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.607702 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 29292805 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 34750406 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 11695757 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 922620 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1185805 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 575553 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 39816 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 66717094 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 118720 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1185805 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 30365496 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 12492089 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 18756431 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 10933791 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 4113780 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 63191653 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 6630 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 474971 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1473898 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 42180100 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 76536527 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 76096983 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 439544 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 36808161 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 5371931 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1596682 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 238140 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 11595704 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 9967009 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 6589337 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1245862 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 818929 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 55970736 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 2008418 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 54697537 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 108647 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 6579388 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3235320 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1364468 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 77847394 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.702625 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.358580 # Number of insts issued each cycle | 526system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total) 527system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle 528system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle 529system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle 530system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked 531system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running 532system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking 533system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing 534system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch 535system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction 536system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode 537system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode 538system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing 539system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle 540system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking 541system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst 542system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running 543system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking 544system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename 545system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full 546system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full 547system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full 548system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed 549system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made 550system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups 551system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups 552system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed 553system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing 554system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed 555system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed 556system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer 557system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit. 558system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit. 559system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads. 560system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores. 561system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec) 562system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ 563system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued 564system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued 565system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling 566system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph 567system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed 568system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle 569system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle 570system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle |
| 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 571system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 572system.cpu0.iq.issued_per_cycle::0 53933184 69.28% 69.28% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 10617760 13.64% 82.92% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 4942911 6.35% 89.27% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 3320001 4.26% 93.53% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2532609 3.25% 96.79% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1408678 1.81% 98.60% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 686959 0.88% 99.48% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 303964 0.39% 99.87% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 101328 0.13% 100.00% # Number of insts issued each cycle | 572system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle 573system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle 574system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle 575system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle 576system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle 577system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle 578system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle 579system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle 580system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle |
| 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 581system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 582system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 583system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 584system.cpu0.iq.issued_per_cycle::total 77847394 # Number of insts issued each cycle | 584system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle |
| 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 585system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 586system.cpu0.iq.fu_full::IntAlu 87681 11.80% 11.80% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 0 0.00% 11.80% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.80% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.80% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.80% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.80% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.80% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.80% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.80% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.80% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.80% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.80% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.80% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.80% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.80% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.80% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.80% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.80% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.80% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.80% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.80% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.80% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.80% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.80% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.80% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.80% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.80% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.80% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.80% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 349168 46.97% 58.77% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 306477 41.23% 100.00% # attempts to use FU when none available | 586system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available 587system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available 588system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available 589system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available 590system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available 591system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available 592system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available 593system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available 594system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available 595system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available 596system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available 597system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available 598system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available 599system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available 600system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available 601system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available 602system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available 603system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available 604system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available 605system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available 606system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available 607system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available 608system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available 609system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available 610system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available 611system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available 612system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available 613system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available 614system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available 615system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available 616system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available |
| 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 617system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 618system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 619system.cpu0.iq.FU_type_0::No_OpClass 3778 0.01% 0.01% # Type of FU issued 620system.cpu0.iq.FU_type_0::IntAlu 37484034 68.53% 68.54% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 60241 0.11% 68.65% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued 623system.cpu0.iq.FU_type_0::FloatAdd 16826 0.03% 68.68% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.68% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued 631system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued 632system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued 633system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued 634system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued 635system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued 636system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued 637system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued 638system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued 639system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued 640system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.68% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.68% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.68% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.68% # Type of FU issued 649system.cpu0.iq.FU_type_0::MemRead 9867065 18.04% 86.72% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 6373328 11.65% 98.37% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 890382 1.63% 100.00% # Type of FU issued | 619system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued 620system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued 621system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued 622system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued 623system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued 624system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued 625system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued 626system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued 627system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued 628system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued 629system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued 630system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued 631system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.61% # Type of FU issued 632system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.61% # Type of FU issued 633system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.61% # Type of FU issued 634system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.61% # Type of FU issued 635system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.61% # Type of FU issued 636system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.61% # Type of FU issued 637system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.61% # Type of FU issued 638system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.61% # Type of FU issued 639system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.61% # Type of FU issued 640system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.61% # Type of FU issued 641system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued 642system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued 643system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued 644system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued 645system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued 646system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued 647system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued 648system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued 649system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued 650system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued 651system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued |
| 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 652system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 653system.cpu0.iq.FU_type_0::total 54697537 # Type of FU issued 654system.cpu0.iq.rate 0.489657 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 743326 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.013590 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 187461216 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 64264846 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 53535096 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 633224 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 306465 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 298013 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 55105300 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 331785 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 567631 # Number of loads that had data forwarded from stores | 653system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued 654system.cpu0.iq.rate 0.454505 # Inst issue rate 655system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested 656system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst) 657system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads 658system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes 659system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses 660system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads 661system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes 662system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses 663system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses 664system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses 665system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores |
| 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 666system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 667system.cpu0.iew.lsq.thread0.squashedLoads 1269870 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 3726 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 13071 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 496722 # Number of stores squashed | 667system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed 668system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed 669system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations 670system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed |
| 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 671system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 672system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 673system.cpu0.iew.lsq.thread0.rescheduledLoads 18808 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 143577 # Number of times an access to memory failed due to the cache being blocked | 673system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled 674system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked |
| 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 675system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 676system.cpu0.iew.iewSquashCycles 1185805 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 8725439 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 608869 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 61441844 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 619329 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 9967009 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 6589337 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1767664 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 482033 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 12133 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 13071 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 215254 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 393579 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 608833 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 54218225 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 9516523 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 479311 # Number of squashed instructions skipped in execute | 676system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing 677system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking 678system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking 679system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ 680system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch 681system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions 682system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions 683system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions 684system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall 685system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall 686system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations 687system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly 688system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly 689system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute 690system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions 691system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed 692system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute |
| 693system.cpu0.iew.exec_swp 0 # number of swp insts executed | 693system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 694system.cpu0.iew.exec_nop 3462690 # number of nop insts executed 695system.cpu0.iew.exec_refs 15839640 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 8639850 # Number of branches executed 697system.cpu0.iew.exec_stores 6323117 # Number of stores executed 698system.cpu0.iew.exec_rate 0.485366 # Inst execution rate 699system.cpu0.iew.wb_sent 53937806 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 53833109 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 26624302 # num instructions producing a value 702system.cpu0.iew.wb_consumers 35973761 # num instructions consuming a value | 694system.cpu0.iew.exec_nop 3050834 # number of nop insts executed 695system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed 696system.cpu0.iew.exec_branches 7758760 # Number of branches executed 697system.cpu0.iew.exec_stores 5379143 # Number of stores executed 698system.cpu0.iew.exec_rate 0.450548 # Inst execution rate 699system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit 700system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back 701system.cpu0.iew.wb_producers 24100280 # num instructions producing a value 702system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value |
| 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 703system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 704system.cpu0.iew.wb_rate 0.481918 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.740103 # average fanout of values written-back | 704system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle 705system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back |
| 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 706system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 707system.cpu0.commit.commitCommittedInsts 54183968 # The number of committed instructions 708system.cpu0.commit.commitCommittedOps 54183968 # The number of committed instructions 709system.cpu0.commit.commitSquashedInsts 7167159 # The number of squashed insts skipped by commit 710system.cpu0.commit.commitNonSpecStalls 643950 # The number of times commit has been forced to stall to communicate backwards 711system.cpu0.commit.branchMispredicts 567683 # The number of times a branch was mispredicted 712system.cpu0.commit.committed_per_cycle::samples 76661589 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::mean 0.706794 # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::stdev 1.627118 # Number of insts commited each cycle | 707system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions 708system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions 709system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit 710system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards 711system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted 712system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle 713system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle 714system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle |
| 715system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 715system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 716system.cpu0.commit.committed_per_cycle::0 56437400 73.62% 73.62% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::1 8432395 11.00% 84.62% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::2 4492859 5.86% 90.48% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::3 2495159 3.25% 93.73% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::4 1450592 1.89% 95.63% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::5 646072 0.84% 96.47% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::6 460772 0.60% 97.07% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::7 487702 0.64% 97.71% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::8 1758638 2.29% 100.00% # Number of insts commited each cycle | 716system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle 717system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle 718system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle 719system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle 720system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle 721system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle 722system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle 723system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle 724system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle |
| 725system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 725system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 726system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 727system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 728system.cpu0.commit.committed_per_cycle::total 76661589 # Number of insts commited each cycle 729system.cpu0.commit.committedInsts 54183968 # Number of instructions committed 730system.cpu0.commit.committedOps 54183968 # Number of ops (including micro ops) committed | 728system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle 729system.cpu0.commit.committedInsts 48294177 # Number of instructions committed 730system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed |
| 731system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 731system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 732system.cpu0.commit.refs 14789754 # Number of memory references committed 733system.cpu0.commit.loads 8697139 # Number of loads committed 734system.cpu0.commit.membars 219715 # Number of memory barriers committed 735system.cpu0.commit.branches 8176675 # Number of branches committed 736system.cpu0.commit.fp_insts 295518 # Number of committed floating point instructions. 737system.cpu0.commit.int_insts 50137398 # Number of committed integer instructions. 738system.cpu0.commit.function_calls 709743 # Number of function calls committed. 739system.cpu0.commit.bw_lim_events 1758638 # number cycles where commit BW limit reached | 732system.cpu0.commit.refs 12819276 # Number of memory references committed 733system.cpu0.commit.loads 7657070 # Number of loads committed 734system.cpu0.commit.membars 181890 # Number of memory barriers committed 735system.cpu0.commit.branches 7325526 # Number of branches committed 736system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions. 737system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions. 738system.cpu0.commit.function_calls 610965 # Number of function calls committed. 739system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached |
| 740system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 740system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 741system.cpu0.rob.rob_reads 136054419 # The number of ROB reads 742system.cpu0.rob.rob_writes 123888625 # The number of ROB writes 743system.cpu0.timesIdled 1249831 # Number of times that the entire CPU went into an idle state and unscheduled itself 744system.cpu0.idleCycles 33858490 # Total number of cycles that the CPU has spent unscheduled due to idling 745system.cpu0.quiesceCycles 3681079567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 746system.cpu0.committedInsts 51051860 # Number of Instructions Simulated 747system.cpu0.committedOps 51051860 # Number of Ops (including micro ops) Simulated 748system.cpu0.committedInsts_total 51051860 # Number of Instructions Simulated 749system.cpu0.cpi 2.188086 # CPI: Cycles Per Instruction 750system.cpu0.cpi_total 2.188086 # CPI: Total CPI of All Threads 751system.cpu0.ipc 0.457020 # IPC: Instructions Per Cycle 752system.cpu0.ipc_total 0.457020 # IPC: Total IPC of All Threads 753system.cpu0.int_regfile_reads 71111535 # number of integer regfile reads 754system.cpu0.int_regfile_writes 38857328 # number of integer regfile writes 755system.cpu0.fp_regfile_reads 146185 # number of floating regfile reads 756system.cpu0.fp_regfile_writes 148692 # number of floating regfile writes 757system.cpu0.misc_regfile_reads 1886112 # number of misc regfile reads 758system.cpu0.misc_regfile_writes 899559 # number of misc regfile writes | 741system.cpu0.rob.rob_reads 126666255 # The number of ROB reads 742system.cpu0.rob.rob_writes 110560293 # The number of ROB writes 743system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself 744system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling 745system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 746system.cpu0.committedInsts 45532520 # Number of Instructions Simulated 747system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated 748system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated 749system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction 750system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads 751system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle 752system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads 753system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads 754system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes 755system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads 756system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes 757system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads 758system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes |
| 759system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 760system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 761system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 762system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 763system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 764system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 765system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 766system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 782system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 783system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 784system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 785system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 786system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 787system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 788system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 789system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 759system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 760system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 761system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 762system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 763system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 764system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 765system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 766system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 782system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 783system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 784system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 785system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 786system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 787system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 788system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 789system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 790system.cpu0.icache.replacements 991395 # number of replacements 791system.cpu0.icache.tagsinuse 510.024196 # Cycle average of tags in use 792system.cpu0.icache.total_refs 7272203 # Total number of references to valid blocks. 793system.cpu0.icache.sampled_refs 991905 # Sample count of references to valid blocks. 794system.cpu0.icache.avg_refs 7.331552 # Average number of references to valid blocks. 795system.cpu0.icache.warmup_cycle 23165696000 # Cycle when the warmup percentage was hit. 796system.cpu0.icache.occ_blocks::cpu0.inst 510.024196 # Average occupied blocks per requestor 797system.cpu0.icache.occ_percent::cpu0.inst 0.996141 # Average percentage of cache occupancy 798system.cpu0.icache.occ_percent::total 0.996141 # Average percentage of cache occupancy 799system.cpu0.icache.ReadReq_hits::cpu0.inst 7272203 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 7272203 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 7272203 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 7272203 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 7272203 # number of overall hits 804system.cpu0.icache.overall_hits::total 7272203 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 1045096 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 1045096 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 1045096 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 1045096 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 1045096 # number of overall misses 810system.cpu0.icache.overall_misses::total 1045096 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15554108994 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 15554108994 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 15554108994 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 15554108994 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 15554108994 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 15554108994 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 8317299 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 8317299 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 8317299 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 8317299 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 8317299 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 8317299 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125653 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.125653 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125653 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.125653 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125653 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.125653 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 14882.947590 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 14882.947590 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 1419995 # number of cycles access was blocked | 790system.cpu0.icache.replacements 790628 # number of replacements 791system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use 792system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks. 793system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks. 794system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks. 795system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit. 796system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor 797system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy 798system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy 799system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits 804system.cpu0.icache.overall_hits::total 6669453 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses 810system.cpu0.icache.overall_misses::total 834673 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency 835system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked |
| 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 837system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked | 837system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked |
| 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 839system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178 # average number of cycles each access was blocked | 839system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked |
| 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed | 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 843system.cpu0.icache.writebacks::writebacks 253 # number of writebacks 844system.cpu0.icache.writebacks::total 253 # number of writebacks 845system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53062 # number of ReadReq MSHR hits 846system.cpu0.icache.ReadReq_mshr_hits::total 53062 # number of ReadReq MSHR hits 847system.cpu0.icache.demand_mshr_hits::cpu0.inst 53062 # number of demand (read+write) MSHR hits 848system.cpu0.icache.demand_mshr_hits::total 53062 # number of demand (read+write) MSHR hits 849system.cpu0.icache.overall_mshr_hits::cpu0.inst 53062 # number of overall MSHR hits 850system.cpu0.icache.overall_mshr_hits::total 53062 # number of overall MSHR hits 851system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 992034 # number of ReadReq MSHR misses 852system.cpu0.icache.ReadReq_mshr_misses::total 992034 # number of ReadReq MSHR misses 853system.cpu0.icache.demand_mshr_misses::cpu0.inst 992034 # number of demand (read+write) MSHR misses 854system.cpu0.icache.demand_mshr_misses::total 992034 # number of demand (read+write) MSHR misses 855system.cpu0.icache.overall_mshr_misses::cpu0.inst 992034 # number of overall MSHR misses 856system.cpu0.icache.overall_mshr_misses::total 992034 # number of overall MSHR misses 857system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11805368995 # number of ReadReq MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_miss_latency::total 11805368995 # number of ReadReq MSHR miss cycles 859system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11805368995 # number of demand (read+write) MSHR miss cycles 860system.cpu0.icache.demand_mshr_miss_latency::total 11805368995 # number of demand (read+write) MSHR miss cycles 861system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11805368995 # number of overall MSHR miss cycles 862system.cpu0.icache.overall_mshr_miss_latency::total 11805368995 # number of overall MSHR miss cycles 863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119274 # mshr miss rate for ReadReq accesses 865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for demand accesses 866system.cpu0.icache.demand_mshr_miss_rate::total 0.119274 # mshr miss rate for demand accesses 867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119274 # mshr miss rate for overall accesses 868system.cpu0.icache.overall_mshr_miss_rate::total 0.119274 # mshr miss rate for overall accesses 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average ReadReq mshr miss latency 870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715 # average ReadReq mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715 # average overall mshr miss latency | 843system.cpu0.icache.writebacks::writebacks 247 # number of writebacks 844system.cpu0.icache.writebacks::total 247 # number of writebacks 845system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits 846system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits 847system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits 848system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits 849system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits 850system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits 851system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses 852system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses 853system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses 854system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses 855system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses 856system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses 857system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles 859system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles 860system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles 861system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles 862system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles 863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses 865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses 866system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses 867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses 868system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency 870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency |
| 875system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 875system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 876system.cpu0.dcache.replacements 1352160 # number of replacements 877system.cpu0.dcache.tagsinuse 506.886378 # Cycle average of tags in use 878system.cpu0.dcache.total_refs 11309312 # Total number of references to valid blocks. 879system.cpu0.dcache.sampled_refs 1352672 # Sample count of references to valid blocks. 880system.cpu0.dcache.avg_refs 8.360720 # Average number of references to valid blocks. 881system.cpu0.dcache.warmup_cycle 19277000 # Cycle when the warmup percentage was hit. 882system.cpu0.dcache.occ_blocks::cpu0.data 506.886378 # Average occupied blocks per requestor 883system.cpu0.dcache.occ_percent::cpu0.data 0.990012 # Average percentage of cache occupancy 884system.cpu0.dcache.occ_percent::total 0.990012 # Average percentage of cache occupancy 885system.cpu0.dcache.ReadReq_hits::cpu0.data 6911324 # number of ReadReq hits 886system.cpu0.dcache.ReadReq_hits::total 6911324 # number of ReadReq hits 887system.cpu0.dcache.WriteReq_hits::cpu0.data 3997215 # number of WriteReq hits 888system.cpu0.dcache.WriteReq_hits::total 3997215 # number of WriteReq hits 889system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 183850 # number of LoadLockedReq hits 890system.cpu0.dcache.LoadLockedReq_hits::total 183850 # number of LoadLockedReq hits 891system.cpu0.dcache.StoreCondReq_hits::cpu0.data 210761 # number of StoreCondReq hits 892system.cpu0.dcache.StoreCondReq_hits::total 210761 # number of StoreCondReq hits 893system.cpu0.dcache.demand_hits::cpu0.data 10908539 # number of demand (read+write) hits 894system.cpu0.dcache.demand_hits::total 10908539 # number of demand (read+write) hits 895system.cpu0.dcache.overall_hits::cpu0.data 10908539 # number of overall hits 896system.cpu0.dcache.overall_hits::total 10908539 # number of overall hits 897system.cpu0.dcache.ReadReq_misses::cpu0.data 1709932 # number of ReadReq misses 898system.cpu0.dcache.ReadReq_misses::total 1709932 # number of ReadReq misses 899system.cpu0.dcache.WriteReq_misses::cpu0.data 1869031 # number of WriteReq misses 900system.cpu0.dcache.WriteReq_misses::total 1869031 # number of WriteReq misses 901system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22271 # number of LoadLockedReq misses 902system.cpu0.dcache.LoadLockedReq_misses::total 22271 # number of LoadLockedReq misses 903system.cpu0.dcache.StoreCondReq_misses::cpu0.data 641 # number of StoreCondReq misses 904system.cpu0.dcache.StoreCondReq_misses::total 641 # number of StoreCondReq misses 905system.cpu0.dcache.demand_misses::cpu0.data 3578963 # number of demand (read+write) misses 906system.cpu0.dcache.demand_misses::total 3578963 # number of demand (read+write) misses 907system.cpu0.dcache.overall_misses::cpu0.data 3578963 # number of overall misses 908system.cpu0.dcache.overall_misses::total 3578963 # number of overall misses 909system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36329127500 # number of ReadReq miss cycles 910system.cpu0.dcache.ReadReq_miss_latency::total 36329127500 # number of ReadReq miss cycles 911system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 56639435392 # number of WriteReq miss cycles 912system.cpu0.dcache.WriteReq_miss_latency::total 56639435392 # number of WriteReq miss cycles 913system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326225500 # number of LoadLockedReq miss cycles 914system.cpu0.dcache.LoadLockedReq_miss_latency::total 326225500 # number of LoadLockedReq miss cycles 915system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5918000 # number of StoreCondReq miss cycles 916system.cpu0.dcache.StoreCondReq_miss_latency::total 5918000 # number of StoreCondReq miss cycles 917system.cpu0.dcache.demand_miss_latency::cpu0.data 92968562892 # number of demand (read+write) miss cycles 918system.cpu0.dcache.demand_miss_latency::total 92968562892 # number of demand (read+write) miss cycles 919system.cpu0.dcache.overall_miss_latency::cpu0.data 92968562892 # number of overall miss cycles 920system.cpu0.dcache.overall_miss_latency::total 92968562892 # number of overall miss cycles 921system.cpu0.dcache.ReadReq_accesses::cpu0.data 8621256 # number of ReadReq accesses(hits+misses) 922system.cpu0.dcache.ReadReq_accesses::total 8621256 # number of ReadReq accesses(hits+misses) 923system.cpu0.dcache.WriteReq_accesses::cpu0.data 5866246 # number of WriteReq accesses(hits+misses) 924system.cpu0.dcache.WriteReq_accesses::total 5866246 # number of WriteReq accesses(hits+misses) 925system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 206121 # number of LoadLockedReq accesses(hits+misses) 926system.cpu0.dcache.LoadLockedReq_accesses::total 206121 # number of LoadLockedReq accesses(hits+misses) 927system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211402 # number of StoreCondReq accesses(hits+misses) 928system.cpu0.dcache.StoreCondReq_accesses::total 211402 # number of StoreCondReq accesses(hits+misses) 929system.cpu0.dcache.demand_accesses::cpu0.data 14487502 # number of demand (read+write) accesses 930system.cpu0.dcache.demand_accesses::total 14487502 # number of demand (read+write) accesses 931system.cpu0.dcache.overall_accesses::cpu0.data 14487502 # number of overall (read+write) accesses 932system.cpu0.dcache.overall_accesses::total 14487502 # number of overall (read+write) accesses 933system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198339 # miss rate for ReadReq accesses 934system.cpu0.dcache.ReadReq_miss_rate::total 0.198339 # miss rate for ReadReq accesses 935system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318608 # miss rate for WriteReq accesses 936system.cpu0.dcache.WriteReq_miss_rate::total 0.318608 # miss rate for WriteReq accesses 937system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.108048 # miss rate for LoadLockedReq accesses 938system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.108048 # miss rate for LoadLockedReq accesses 939system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003032 # miss rate for StoreCondReq accesses 940system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003032 # miss rate for StoreCondReq accesses 941system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247038 # miss rate for demand accesses 942system.cpu0.dcache.demand_miss_rate::total 0.247038 # miss rate for demand accesses 943system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247038 # miss rate for overall accesses 944system.cpu0.dcache.overall_miss_rate::total 0.247038 # miss rate for overall accesses 945system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669 # average ReadReq miss latency 946system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669 # average ReadReq miss latency 947system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195 # average WriteReq miss latency 948system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195 # average WriteReq miss latency 949system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151 # average LoadLockedReq miss latency 950system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151 # average LoadLockedReq miss latency 951system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9232.449298 # average StoreCondReq miss latency 952system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9232.449298 # average StoreCondReq miss latency 953system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency 954system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764 # average overall miss latency 955system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764 # average overall miss latency 956system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764 # average overall miss latency 957system.cpu0.dcache.blocked_cycles::no_mshrs 790531306 # number of cycles access was blocked 958system.cpu0.dcache.blocked_cycles::no_targets 168000 # number of cycles access was blocked 959system.cpu0.dcache.blocked::no_mshrs 99401 # number of cycles access was blocked | 876system.cpu0.dcache.replacements 1206208 # number of replacements 877system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use 878system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks. 879system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks. 880system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks. 881system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit. 882system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor 883system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy 884system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy 885system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits 886system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits 887system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits 888system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits 889system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits 890system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits 891system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits 892system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits 893system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits 894system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits 895system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits 896system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits 897system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses 898system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses 899system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses 900system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses 901system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses 902system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses 903system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses 904system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses 905system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses 906system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses 907system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses 908system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses 909system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles 910system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles 911system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles 912system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles 913system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles 914system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles 915system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles 916system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles 917system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles 918system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles 919system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles 920system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles 921system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses) 922system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses) 923system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses) 924system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses) 925system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses) 926system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses) 927system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses) 928system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses) 929system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses 930system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses 931system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses 932system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses 933system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses 934system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses 935system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses 936system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses 937system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses 938system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses 939system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses 940system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses 941system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses 942system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses 943system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses 944system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses 945system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency 946system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency 947system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency 948system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency 949system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency 950system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency 951system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency 952system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency 953system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency 954system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency 955system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency 956system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency 957system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked 958system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked 959system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked |
| 960system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked | 960system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked |
| 961system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7952.951238 # average number of cycles each access was blocked 962system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked | 961system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked 962system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked |
| 963system.cpu0.dcache.fast_writes 0 # number of fast writes performed 964system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 963system.cpu0.dcache.fast_writes 0 # number of fast writes performed 964system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 965system.cpu0.dcache.writebacks::writebacks 805259 # number of writebacks 966system.cpu0.dcache.writebacks::total 805259 # number of writebacks 967system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 661851 # number of ReadReq MSHR hits 968system.cpu0.dcache.ReadReq_mshr_hits::total 661851 # number of ReadReq MSHR hits 969system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1575507 # number of WriteReq MSHR hits 970system.cpu0.dcache.WriteReq_mshr_hits::total 1575507 # number of WriteReq MSHR hits 971system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5029 # number of LoadLockedReq MSHR hits 972system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5029 # number of LoadLockedReq MSHR hits 973system.cpu0.dcache.demand_mshr_hits::cpu0.data 2237358 # number of demand (read+write) MSHR hits 974system.cpu0.dcache.demand_mshr_hits::total 2237358 # number of demand (read+write) MSHR hits 975system.cpu0.dcache.overall_mshr_hits::cpu0.data 2237358 # number of overall MSHR hits 976system.cpu0.dcache.overall_mshr_hits::total 2237358 # number of overall MSHR hits 977system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1048081 # number of ReadReq MSHR misses 978system.cpu0.dcache.ReadReq_mshr_misses::total 1048081 # number of ReadReq MSHR misses 979system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 293524 # number of WriteReq MSHR misses 980system.cpu0.dcache.WriteReq_mshr_misses::total 293524 # number of WriteReq MSHR misses 981system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17242 # number of LoadLockedReq MSHR misses 982system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17242 # number of LoadLockedReq MSHR misses 983system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses 984system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses 985system.cpu0.dcache.demand_mshr_misses::cpu0.data 1341605 # number of demand (read+write) MSHR misses 986system.cpu0.dcache.demand_mshr_misses::total 1341605 # number of demand (read+write) MSHR misses 987system.cpu0.dcache.overall_mshr_misses::cpu0.data 1341605 # number of overall MSHR misses 988system.cpu0.dcache.overall_mshr_misses::total 1341605 # number of overall MSHR misses 989system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23566810500 # number of ReadReq MSHR miss cycles 990system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23566810500 # number of ReadReq MSHR miss cycles 991system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8456840306 # number of WriteReq MSHR miss cycles 992system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8456840306 # number of WriteReq MSHR miss cycles 993system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 195574000 # number of LoadLockedReq MSHR miss cycles 994system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 195574000 # number of LoadLockedReq MSHR miss cycles 995system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3991500 # number of StoreCondReq MSHR miss cycles 996system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3991500 # number of StoreCondReq MSHR miss cycles 997system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 32023650806 # number of demand (read+write) MSHR miss cycles 998system.cpu0.dcache.demand_mshr_miss_latency::total 32023650806 # number of demand (read+write) MSHR miss cycles 999system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 32023650806 # number of overall MSHR miss cycles 1000system.cpu0.dcache.overall_mshr_miss_latency::total 32023650806 # number of overall MSHR miss cycles 1001system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 917307000 # number of ReadReq MSHR uncacheable cycles 1002system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 917307000 # number of ReadReq MSHR uncacheable cycles 1003system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253595498 # number of WriteReq MSHR uncacheable cycles 1004system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253595498 # number of WriteReq MSHR uncacheable cycles 1005system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2170902498 # number of overall MSHR uncacheable cycles 1006system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2170902498 # number of overall MSHR uncacheable cycles 1007system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121569 # mshr miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121569 # mshr miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050036 # mshr miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050036 # mshr miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083650 # mshr miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083650 # mshr miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003027 # mshr miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003027 # mshr miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for demand accesses 1016system.cpu0.dcache.demand_mshr_miss_rate::total 0.092604 # mshr miss rate for demand accesses 1017system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092604 # mshr miss rate for overall accesses 1018system.cpu0.dcache.overall_mshr_miss_rate::total 0.092604 # mshr miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680 # average ReadReq mshr miss latency 1020system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680 # average ReadReq mshr miss latency 1021system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990 # average WriteReq mshr miss latency 1022system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990 # average WriteReq mshr miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656 # average LoadLockedReq mshr miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656 # average LoadLockedReq mshr miss latency 1025system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6236.718750 # average StoreCondReq mshr miss latency 1026system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6236.718750 # average StoreCondReq mshr miss latency 1027system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency 1028system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency 1029system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722 # average overall mshr miss latency 1030system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722 # average overall mshr miss latency | 965system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks 966system.cpu0.dcache.writebacks::total 693284 # number of writebacks 967system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits 968system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits 969system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits 970system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits 971system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits 972system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits 973system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits 974system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits 975system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits 976system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits 977system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses 978system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses 979system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses 980system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses 981system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses 982system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses 983system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses 984system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses 985system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses 986system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses 987system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses 988system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses 989system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles 990system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles 991system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles 992system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles 993system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles 994system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles 995system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles 996system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles 997system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles 998system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles 999system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles 1000system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles 1001system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles 1002system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles 1003system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles 1004system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles 1005system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles 1006system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles 1007system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses 1008system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses 1009system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses 1010system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses 1011system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses 1012system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses 1014system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses 1015system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses 1016system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses 1017system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses 1018system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses 1019system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency 1020system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency 1021system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency 1022system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency 1023system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency 1024system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency 1025system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency 1026system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency 1027system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency 1028system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency 1029system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency 1030system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency |
| 1031system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1032system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1033system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1034system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1035system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1036system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1037system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu1.dtb.fetch_hits 0 # ITB hits 1039system.cpu1.dtb.fetch_misses 0 # ITB misses 1040system.cpu1.dtb.fetch_acv 0 # ITB acv 1041system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1031system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1032system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1033system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1034system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1035system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1036system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1037system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu1.dtb.fetch_hits 0 # ITB hits 1039system.cpu1.dtb.fetch_misses 0 # ITB misses 1040system.cpu1.dtb.fetch_acv 0 # ITB acv 1041system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1042system.cpu1.dtb.read_hits 1211336 # DTB read hits 1043system.cpu1.dtb.read_misses 9865 # DTB read misses 1044system.cpu1.dtb.read_acv 6 # DTB read access violations 1045system.cpu1.dtb.read_accesses 283619 # DTB read accesses 1046system.cpu1.dtb.write_hits 674221 # DTB write hits 1047system.cpu1.dtb.write_misses 1908 # DTB write misses 1048system.cpu1.dtb.write_acv 40 # DTB write access violations 1049system.cpu1.dtb.write_accesses 107232 # DTB write accesses 1050system.cpu1.dtb.data_hits 1885557 # DTB hits 1051system.cpu1.dtb.data_misses 11773 # DTB misses 1052system.cpu1.dtb.data_acv 46 # DTB access violations 1053system.cpu1.dtb.data_accesses 390851 # DTB accesses 1054system.cpu1.itb.fetch_hits 332989 # ITB hits 1055system.cpu1.itb.fetch_misses 6158 # ITB misses 1056system.cpu1.itb.fetch_acv 143 # ITB acv 1057system.cpu1.itb.fetch_accesses 339147 # ITB accesses | 1042system.cpu1.dtb.read_hits 2499316 # DTB read hits 1043system.cpu1.dtb.read_misses 12569 # DTB read misses 1044system.cpu1.dtb.read_acv 105 # DTB read access violations 1045system.cpu1.dtb.read_accesses 313735 # DTB read accesses 1046system.cpu1.dtb.write_hits 1734639 # DTB write hits 1047system.cpu1.dtb.write_misses 3525 # DTB write misses 1048system.cpu1.dtb.write_acv 140 # DTB write access violations 1049system.cpu1.dtb.write_accesses 132367 # DTB write accesses 1050system.cpu1.dtb.data_hits 4233955 # DTB hits 1051system.cpu1.dtb.data_misses 16094 # DTB misses 1052system.cpu1.dtb.data_acv 245 # DTB access violations 1053system.cpu1.dtb.data_accesses 446102 # DTB accesses 1054system.cpu1.itb.fetch_hits 489806 # ITB hits 1055system.cpu1.itb.fetch_misses 8851 # ITB misses 1056system.cpu1.itb.fetch_acv 360 # ITB acv 1057system.cpu1.itb.fetch_accesses 498657 # ITB accesses |
| 1058system.cpu1.itb.read_hits 0 # DTB read hits 1059system.cpu1.itb.read_misses 0 # DTB read misses 1060system.cpu1.itb.read_acv 0 # DTB read access violations 1061system.cpu1.itb.read_accesses 0 # DTB read accesses 1062system.cpu1.itb.write_hits 0 # DTB write hits 1063system.cpu1.itb.write_misses 0 # DTB write misses 1064system.cpu1.itb.write_acv 0 # DTB write access violations 1065system.cpu1.itb.write_accesses 0 # DTB write accesses 1066system.cpu1.itb.data_hits 0 # DTB hits 1067system.cpu1.itb.data_misses 0 # DTB misses 1068system.cpu1.itb.data_acv 0 # DTB access violations 1069system.cpu1.itb.data_accesses 0 # DTB accesses | 1058system.cpu1.itb.read_hits 0 # DTB read hits 1059system.cpu1.itb.read_misses 0 # DTB read misses 1060system.cpu1.itb.read_acv 0 # DTB read access violations 1061system.cpu1.itb.read_accesses 0 # DTB read accesses 1062system.cpu1.itb.write_hits 0 # DTB write hits 1063system.cpu1.itb.write_misses 0 # DTB write misses 1064system.cpu1.itb.write_acv 0 # DTB write access violations 1065system.cpu1.itb.write_accesses 0 # DTB write accesses 1066system.cpu1.itb.data_hits 0 # DTB hits 1067system.cpu1.itb.data_misses 0 # DTB misses 1068system.cpu1.itb.data_acv 0 # DTB access violations 1069system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1070system.cpu1.numCycles 8872891 # number of cpu cycles simulated | 1070system.cpu1.numCycles 22717311 # number of cpu cycles simulated |
| 1071system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1072system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1071system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1072system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1073system.cpu1.BPredUnit.lookups 1582523 # Number of BP lookups 1074system.cpu1.BPredUnit.condPredicted 1301899 # Number of conditional branches predicted 1075system.cpu1.BPredUnit.condIncorrect 53959 # Number of conditional branches incorrect 1076system.cpu1.BPredUnit.BTBLookups 749480 # Number of BTB lookups 1077system.cpu1.BPredUnit.BTBHits 495600 # Number of BTB hits | 1073system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups 1074system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted 1075system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect 1076system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups 1077system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits |
| 1078system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1078system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1079system.cpu1.BPredUnit.usedRAS 108561 # Number of times the RAS was used to get a target. 1080system.cpu1.BPredUnit.RASInCorrect 5012 # Number of incorrect RAS predictions. 1081system.cpu1.fetch.icacheStallCycles 3100077 # Number of cycles fetch is stalled on an Icache miss 1082system.cpu1.fetch.Insts 7469135 # Number of instructions fetch has processed 1083system.cpu1.fetch.Branches 1582523 # Number of branches that fetch encountered 1084system.cpu1.fetch.predictedBranches 604161 # Number of branches that fetch has predicted taken 1085system.cpu1.fetch.Cycles 1348473 # Number of cycles fetch has run and was not squashing or blocked 1086system.cpu1.fetch.SquashCycles 293042 # Number of cycles fetch has spent squashing 1087system.cpu1.fetch.BlockedCycles 3524434 # Number of cycles fetch has spent blocked 1088system.cpu1.fetch.MiscStallCycles 23987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1089system.cpu1.fetch.PendingTrapStallCycles 56676 # Number of stall cycles due to pending traps 1090system.cpu1.fetch.PendingQuiesceStallCycles 47433 # Number of stall cycles due to pending quiesce instructions 1091system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 1092system.cpu1.fetch.CacheLines 951392 # Number of cache lines fetched 1093system.cpu1.fetch.IcacheSquashes 34043 # Number of outstanding Icache misses that were squashed 1094system.cpu1.fetch.rateDist::samples 8293149 # Number of instructions fetched each cycle (Total) 1095system.cpu1.fetch.rateDist::mean 0.900639 # Number of instructions fetched each cycle (Total) 1096system.cpu1.fetch.rateDist::stdev 2.276932 # Number of instructions fetched each cycle (Total) | 1079system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target. 1080system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions. 1081system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss 1082system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed 1083system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered 1084system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken 1085system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked 1086system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing 1087system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked 1088system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1089system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps 1090system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions 1091system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR 1092system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched 1093system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed 1094system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total) 1095system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total) 1096system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total) |
| 1097system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1097system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1098system.cpu1.fetch.rateDist::0 6944676 83.74% 83.74% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::1 71085 0.86% 84.60% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::2 161786 1.95% 86.55% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::3 117935 1.42% 87.97% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::4 195029 2.35% 90.32% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::5 79896 0.96% 91.29% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::6 91030 1.10% 92.38% # Number of instructions fetched each cycle (Total) 1105system.cpu1.fetch.rateDist::7 58799 0.71% 93.09% # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::8 572913 6.91% 100.00% # Number of instructions fetched each cycle (Total) | 1098system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total) 1099system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total) 1100system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total) 1101system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total) 1102system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total) 1103system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total) 1104system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total) 1105system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total) 1106system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total) |
| 1107system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1108system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1109system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1107system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1108system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1109system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1110system.cpu1.fetch.rateDist::total 8293149 # Number of instructions fetched each cycle (Total) 1111system.cpu1.fetch.branchRate 0.178355 # Number of branch fetches per cycle 1112system.cpu1.fetch.rate 0.841793 # Number of inst fetches per cycle 1113system.cpu1.decode.IdleCycles 3156648 # Number of cycles decode is idle 1114system.cpu1.decode.BlockedCycles 3626684 # Number of cycles decode is blocked 1115system.cpu1.decode.RunCycles 1266182 # Number of cycles decode is running 1116system.cpu1.decode.UnblockCycles 55854 # Number of cycles decode is unblocking 1117system.cpu1.decode.SquashCycles 187780 # Number of cycles decode is squashing 1118system.cpu1.decode.BranchResolved 69682 # Number of times decode resolved a branch 1119system.cpu1.decode.BranchMispred 4376 # Number of times decode detected a branch misprediction 1120system.cpu1.decode.DecodedInsts 7275177 # Number of instructions handled by decode 1121system.cpu1.decode.SquashedInsts 13096 # Number of squashed instructions handled by decode 1122system.cpu1.rename.SquashCycles 187780 # Number of cycles rename is squashing 1123system.cpu1.rename.IdleCycles 3279437 # Number of cycles rename is idle 1124system.cpu1.rename.BlockCycles 303001 # Number of cycles rename is blocking 1125system.cpu1.rename.serializeStallCycles 2955129 # count of cycles rename stalled for serializing inst 1126system.cpu1.rename.RunCycles 1188563 # Number of cycles rename is running 1127system.cpu1.rename.UnblockCycles 379237 # Number of cycles rename is unblocking 1128system.cpu1.rename.RenamedInsts 6712088 # Number of instructions processed by rename 1129system.cpu1.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full 1130system.cpu1.rename.IQFullEvents 36332 # Number of times rename has blocked due to IQ full 1131system.cpu1.rename.LSQFullEvents 73621 # Number of times rename has blocked due to LSQ full 1132system.cpu1.rename.RenamedOperands 4503320 # Number of destination operands rename has renamed 1133system.cpu1.rename.RenameLookups 8147567 # Number of register rename lookups that rename has made 1134system.cpu1.rename.int_rename_lookups 8100022 # Number of integer rename lookups 1135system.cpu1.rename.fp_rename_lookups 47545 # Number of floating rename lookups 1136system.cpu1.rename.CommittedMaps 3660294 # Number of HB maps that are committed 1137system.cpu1.rename.UndoneMaps 843026 # Number of HB maps that are undone due to squashing 1138system.cpu1.rename.serializingInsts 283944 # count of serializing insts renamed 1139system.cpu1.rename.tempSerializingInsts 19782 # count of temporary serializing insts renamed 1140system.cpu1.rename.skidInsts 1166048 # count of insts added to the skid buffer 1141system.cpu1.memDep0.insertedLoads 1294582 # Number of loads inserted to the mem dependence unit. 1142system.cpu1.memDep0.insertedStores 736122 # Number of stores inserted to the mem dependence unit. 1143system.cpu1.memDep0.conflictingLoads 125256 # Number of conflicting loads. 1144system.cpu1.memDep0.conflictingStores 86989 # Number of conflicting stores. 1145system.cpu1.iq.iqInstsAdded 5902743 # Number of instructions added to the IQ (excludes non-spec) 1146system.cpu1.iq.iqNonSpecInstsAdded 293921 # Number of non-speculative instructions added to the IQ 1147system.cpu1.iq.iqInstsIssued 5640439 # Number of instructions issued 1148system.cpu1.iq.iqSquashedInstsIssued 22605 # Number of squashed instructions issued 1149system.cpu1.iq.iqSquashedInstsExamined 1087589 # Number of squashed instructions iterated over during squash; mainly for profiling 1150system.cpu1.iq.iqSquashedOperandsExamined 606184 # Number of squashed operands that are examined and possibly removed from graph 1151system.cpu1.iq.iqSquashedNonSpecRemoved 224688 # Number of squashed non-spec instructions that were removed 1152system.cpu1.iq.issued_per_cycle::samples 8293149 # Number of insts issued each cycle 1153system.cpu1.iq.issued_per_cycle::mean 0.680132 # Number of insts issued each cycle 1154system.cpu1.iq.issued_per_cycle::stdev 1.353961 # Number of insts issued each cycle | 1110system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total) 1111system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle 1112system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle 1113system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle 1114system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked 1115system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running 1116system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking 1117system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing 1118system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch 1119system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction 1120system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode 1121system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode 1122system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing 1123system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle 1124system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking 1125system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst 1126system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running 1127system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking 1128system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename 1129system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full 1130system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full 1131system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full 1132system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed 1133system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made 1134system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups 1135system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups 1136system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed 1137system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing 1138system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed 1139system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed 1140system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer 1141system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit. 1142system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit. 1143system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads. 1144system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores. 1145system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec) 1146system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ 1147system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued 1148system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued 1149system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling 1150system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph 1151system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed 1152system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle 1153system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle 1154system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle |
| 1155system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1155system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1156system.cpu1.iq.issued_per_cycle::0 5841725 70.44% 70.44% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::1 1091278 13.16% 83.60% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::2 496152 5.98% 89.58% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::3 349787 4.22% 93.80% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::4 258149 3.11% 96.91% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::5 126242 1.52% 98.43% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::6 71640 0.86% 99.30% # Number of insts issued each cycle 1163system.cpu1.iq.issued_per_cycle::7 51558 0.62% 99.92% # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::8 6618 0.08% 100.00% # Number of insts issued each cycle | 1156system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle 1157system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle 1158system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle 1159system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle 1160system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle 1161system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle 1162system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle 1163system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle 1164system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle |
| 1165system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1166system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1167system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1165system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1166system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1167system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1168system.cpu1.iq.issued_per_cycle::total 8293149 # Number of insts issued each cycle | 1168system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle |
| 1169system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1169system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1170system.cpu1.iq.fu_full::IntAlu 3067 2.40% 2.40% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::IntMult 0 0.00% 2.40% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.40% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.40% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.40% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.40% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.40% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.40% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.40% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.40% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.40% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.40% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.40% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.40% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.40% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.40% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.40% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.40% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.40% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.40% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.40% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.40% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.40% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.40% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.40% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.40% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.40% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.40% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.40% # attempts to use FU when none available 1199system.cpu1.iq.fu_full::MemRead 73236 57.36% 59.76% # attempts to use FU when none available 1200system.cpu1.iq.fu_full::MemWrite 51382 40.24% 100.00% # attempts to use FU when none available | 1170system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available 1171system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available 1172system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available 1173system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available 1174system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available 1175system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available 1176system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available 1177system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available 1178system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 1179system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available 1180system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available 1181system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available 1182system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available 1183system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available 1184system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available 1185system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available 1186system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available 1187system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available 1188system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available 1189system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available 1190system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available 1191system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available 1192system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available 1193system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available 1194system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available 1195system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available 1196system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available 1197system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available 1198system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available 1199system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available 1200system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available |
| 1201system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1202system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1201system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1202system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1203system.cpu1.iq.FU_type_0::No_OpClass 3518 0.06% 0.06% # Type of FU issued 1204system.cpu1.iq.FU_type_0::IntAlu 3484656 61.78% 61.84% # Type of FU issued 1205system.cpu1.iq.FU_type_0::IntMult 10025 0.18% 62.02% # Type of FU issued 1206system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatAdd 8917 0.16% 62.18% # Type of FU issued 1208system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued 1209system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued 1210system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued 1211system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 62.21% # Type of FU issued 1212system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.21% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.21% # Type of FU issued 1214system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.21% # Type of FU issued 1215system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.21% # Type of FU issued 1216system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.21% # Type of FU issued 1217system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.21% # Type of FU issued 1218system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.21% # Type of FU issued 1219system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.21% # Type of FU issued 1220system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.21% # Type of FU issued 1221system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.21% # Type of FU issued 1222system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.21% # Type of FU issued 1223system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.21% # Type of FU issued 1224system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.21% # Type of FU issued 1225system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.21% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.21% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.21% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.21% # Type of FU issued 1229system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.21% # Type of FU issued 1230system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.21% # Type of FU issued 1231system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.21% # Type of FU issued 1232system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.21% # Type of FU issued 1233system.cpu1.iq.FU_type_0::MemRead 1261676 22.37% 84.58% # Type of FU issued 1234system.cpu1.iq.FU_type_0::MemWrite 692210 12.27% 96.85% # Type of FU issued 1235system.cpu1.iq.FU_type_0::IprAccess 177678 3.15% 100.00% # Type of FU issued | 1203system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued 1204system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued 1205system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued 1206system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued 1207system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued 1208system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued 1209system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued 1210system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued 1211system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued 1212system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued 1213system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued 1214system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued 1215system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued 1216system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.70% # Type of FU issued 1217system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.70% # Type of FU issued 1218system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.70% # Type of FU issued 1219system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.70% # Type of FU issued 1220system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.70% # Type of FU issued 1221system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.70% # Type of FU issued 1222system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.70% # Type of FU issued 1223system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.70% # Type of FU issued 1224system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.70% # Type of FU issued 1225system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued 1226system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued 1227system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued 1228system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued 1229system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued 1230system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued 1231system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued 1232system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued 1233system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued 1234system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued 1235system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued |
| 1236system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1236system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1237system.cpu1.iq.FU_type_0::total 5640439 # Type of FU issued 1238system.cpu1.iq.rate 0.635693 # Inst issue rate 1239system.cpu1.iq.fu_busy_cnt 127685 # FU busy when requested 1240system.cpu1.iq.fu_busy_rate 0.022637 # FU busy rate (busy events/executed inst) 1241system.cpu1.iq.int_inst_queue_reads 19654183 # Number of integer instruction queue reads 1242system.cpu1.iq.int_inst_queue_writes 7250568 # Number of integer instruction queue writes 1243system.cpu1.iq.int_inst_queue_wakeup_accesses 5466934 # Number of integer instruction queue wakeup accesses 1244system.cpu1.iq.fp_inst_queue_reads 70134 # Number of floating instruction queue reads 1245system.cpu1.iq.fp_inst_queue_writes 35039 # Number of floating instruction queue writes 1246system.cpu1.iq.fp_inst_queue_wakeup_accesses 33778 # Number of floating instruction queue wakeup accesses 1247system.cpu1.iq.int_alu_accesses 5728452 # Number of integer alu accesses 1248system.cpu1.iq.fp_alu_accesses 36154 # Number of floating point alu accesses 1249system.cpu1.iew.lsq.thread0.forwLoads 64737 # Number of loads that had data forwarded from stores | 1237system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued 1238system.cpu1.iq.rate 0.559079 # Inst issue rate 1239system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested 1240system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) 1241system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads 1242system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes 1243system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses 1244system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads 1245system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes 1246system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses 1247system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses 1248system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses 1249system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores |
| 1250system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1250system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1251system.cpu1.iew.lsq.thread0.squashedLoads 237812 # Number of loads squashed 1252system.cpu1.iew.lsq.thread0.ignoredResponses 428 # Number of memory responses ignored because the instruction is squashed 1253system.cpu1.iew.lsq.thread0.memOrderViolation 1426 # Number of memory ordering violations 1254system.cpu1.iew.lsq.thread0.squashedStores 105246 # Number of stores squashed | 1251system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed 1252system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed 1253system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations 1254system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed |
| 1255system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1256system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1255system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1256system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1257system.cpu1.iew.lsq.thread0.rescheduledLoads 373 # Number of loads that were rescheduled 1258system.cpu1.iew.lsq.thread0.cacheBlocked 23964 # Number of times an access to memory failed due to the cache being blocked | 1257system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled 1258system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked |
| 1259system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1259system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1260system.cpu1.iew.iewSquashCycles 187780 # Number of cycles IEW is squashing 1261system.cpu1.iew.iewBlockCycles 210633 # Number of cycles IEW is blocking 1262system.cpu1.iew.iewUnblockCycles 9248 # Number of cycles IEW is unblocking 1263system.cpu1.iew.iewDispatchedInsts 6437285 # Number of instructions dispatched to IQ 1264system.cpu1.iew.iewDispSquashedInsts 88203 # Number of squashed instructions skipped by dispatch 1265system.cpu1.iew.iewDispLoadInsts 1294582 # Number of dispatched load instructions 1266system.cpu1.iew.iewDispStoreInsts 736122 # Number of dispatched store instructions 1267system.cpu1.iew.iewDispNonSpecInsts 274301 # Number of dispatched non-speculative instructions 1268system.cpu1.iew.iewIQFullEvents 3887 # Number of times the IQ has become full, causing a stall 1269system.cpu1.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall 1270system.cpu1.iew.memOrderViolationEvents 1426 # Number of memory order violations 1271system.cpu1.iew.predictedTakenIncorrect 25150 # Number of branches that were predicted taken incorrectly 1272system.cpu1.iew.predictedNotTakenIncorrect 66283 # Number of branches that were predicted not taken incorrectly 1273system.cpu1.iew.branchMispredicts 91433 # Number of branch mispredicts detected at execute 1274system.cpu1.iew.iewExecutedInsts 5579037 # Number of executed instructions 1275system.cpu1.iew.iewExecLoadInsts 1224301 # Number of load instructions executed 1276system.cpu1.iew.iewExecSquashedInsts 61402 # Number of squashed instructions skipped in execute | 1260system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing 1261system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking 1262system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking 1263system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ 1264system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch 1265system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions 1266system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions 1267system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions 1268system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall 1269system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall 1270system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations 1271system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly 1272system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly 1273system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute 1274system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions 1275system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed 1276system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute |
| 1277system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1277system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1278system.cpu1.iew.exec_nop 240621 # number of nop insts executed 1279system.cpu1.iew.exec_refs 1903575 # number of memory reference insts executed 1280system.cpu1.iew.exec_branches 816845 # Number of branches executed 1281system.cpu1.iew.exec_stores 679274 # Number of stores executed 1282system.cpu1.iew.exec_rate 0.628773 # Inst execution rate 1283system.cpu1.iew.wb_sent 5526738 # cumulative count of insts sent to commit 1284system.cpu1.iew.wb_count 5500712 # cumulative count of insts written-back 1285system.cpu1.iew.wb_producers 2655801 # num instructions producing a value 1286system.cpu1.iew.wb_consumers 3693565 # num instructions consuming a value | 1278system.cpu1.iew.exec_nop 726447 # number of nop insts executed 1279system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed 1280system.cpu1.iew.exec_branches 1887172 # Number of branches executed 1281system.cpu1.iew.exec_stores 1746592 # Number of stores executed 1282system.cpu1.iew.exec_rate 0.553740 # Inst execution rate 1283system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit 1284system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back 1285system.cpu1.iew.wb_producers 5700900 # num instructions producing a value 1286system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value |
| 1287system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1287system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 1288system.cpu1.iew.wb_rate 0.619946 # insts written-back per cycle 1289system.cpu1.iew.wb_fanout 0.719035 # average fanout of values written-back | 1288system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle 1289system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back |
| 1290system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1290system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 1291system.cpu1.commit.commitCommittedInsts 5260797 # The number of committed instructions 1292system.cpu1.commit.commitCommittedOps 5260797 # The number of committed instructions 1293system.cpu1.commit.commitSquashedInsts 1110508 # The number of squashed insts skipped by commit 1294system.cpu1.commit.commitNonSpecStalls 69233 # The number of times commit has been forced to stall to communicate backwards 1295system.cpu1.commit.branchMispredicts 85933 # The number of times a branch was mispredicted 1296system.cpu1.commit.committed_per_cycle::samples 8105369 # Number of insts commited each cycle 1297system.cpu1.commit.committed_per_cycle::mean 0.649051 # Number of insts commited each cycle 1298system.cpu1.commit.committed_per_cycle::stdev 1.577854 # Number of insts commited each cycle | 1291system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions 1292system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions 1293system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit 1294system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards 1295system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted 1296system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle 1297system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle 1298system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle |
| 1299system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1299system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1300system.cpu1.commit.committed_per_cycle::0 6083727 75.06% 75.06% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::1 977563 12.06% 87.12% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::2 351716 4.34% 91.46% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::3 209459 2.58% 94.04% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::4 128681 1.59% 95.63% # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::5 67803 0.84% 96.47% # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::6 72265 0.89% 97.36% # Number of insts commited each cycle 1307system.cpu1.commit.committed_per_cycle::7 49144 0.61% 97.96% # Number of insts commited each cycle 1308system.cpu1.commit.committed_per_cycle::8 165011 2.04% 100.00% # Number of insts commited each cycle | 1300system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle 1301system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle 1302system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle 1303system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle 1304system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle 1305system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle 1306system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle 1307system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle 1308system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle |
| 1309system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1310system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1311system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1309system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1310system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1311system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1312system.cpu1.commit.committed_per_cycle::total 8105369 # Number of insts commited each cycle 1313system.cpu1.commit.committedInsts 5260797 # Number of instructions committed 1314system.cpu1.commit.committedOps 5260797 # Number of ops (including micro ops) committed | 1312system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle 1313system.cpu1.commit.committedInsts 12433159 # Number of instructions committed 1314system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed |
| 1315system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1315system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1316system.cpu1.commit.refs 1687646 # Number of memory references committed 1317system.cpu1.commit.loads 1056770 # Number of loads committed 1318system.cpu1.commit.membars 18284 # Number of memory barriers committed 1319system.cpu1.commit.branches 746127 # Number of branches committed 1320system.cpu1.commit.fp_insts 32538 # Number of committed floating point instructions. 1321system.cpu1.commit.int_insts 4917553 # Number of committed integer instructions. 1322system.cpu1.commit.function_calls 83297 # Number of function calls committed. 1323system.cpu1.commit.bw_lim_events 165011 # number cycles where commit BW limit reached | 1316system.cpu1.commit.refs 3965647 # Number of memory references committed 1317system.cpu1.commit.loads 2293191 # Number of loads committed 1318system.cpu1.commit.membars 64658 # Number of memory barriers committed 1319system.cpu1.commit.branches 1777478 # Number of branches committed 1320system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions. 1321system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions. 1322system.cpu1.commit.function_calls 194670 # Number of function calls committed. 1323system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached |
| 1324system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 1324system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 1325system.cpu1.rob.rob_reads 14229924 # The number of ROB reads 1326system.cpu1.rob.rob_writes 12929135 # The number of ROB writes 1327system.cpu1.timesIdled 74630 # Number of times that the entire CPU went into an idle state and unscheduled itself 1328system.cpu1.idleCycles 579742 # Total number of cycles that the CPU has spent unscheduled due to idling 1329system.cpu1.quiesceCycles 3783284242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1330system.cpu1.committedInsts 5057664 # Number of Instructions Simulated 1331system.cpu1.committedOps 5057664 # Number of Ops (including micro ops) Simulated 1332system.cpu1.committedInsts_total 5057664 # Number of Instructions Simulated 1333system.cpu1.cpi 1.754346 # CPI: Cycles Per Instruction 1334system.cpu1.cpi_total 1.754346 # CPI: Total CPI of All Threads 1335system.cpu1.ipc 0.570013 # IPC: Instructions Per Cycle 1336system.cpu1.ipc_total 0.570013 # IPC: Total IPC of All Threads 1337system.cpu1.int_regfile_reads 7235777 # number of integer regfile reads 1338system.cpu1.int_regfile_writes 3986410 # number of integer regfile writes 1339system.cpu1.fp_regfile_reads 21879 # number of floating regfile reads 1340system.cpu1.fp_regfile_writes 20613 # number of floating regfile writes 1341system.cpu1.misc_regfile_reads 262487 # number of misc regfile reads 1342system.cpu1.misc_regfile_writes 123180 # number of misc regfile writes 1343system.cpu1.icache.replacements 103776 # number of replacements 1344system.cpu1.icache.tagsinuse 452.422972 # Cycle average of tags in use 1345system.cpu1.icache.total_refs 841895 # Total number of references to valid blocks. 1346system.cpu1.icache.sampled_refs 104287 # Sample count of references to valid blocks. 1347system.cpu1.icache.avg_refs 8.072866 # Average number of references to valid blocks. 1348system.cpu1.icache.warmup_cycle 1873827117000 # Cycle when the warmup percentage was hit. 1349system.cpu1.icache.occ_blocks::cpu1.inst 452.422972 # Average occupied blocks per requestor 1350system.cpu1.icache.occ_percent::cpu1.inst 0.883639 # Average percentage of cache occupancy 1351system.cpu1.icache.occ_percent::total 0.883639 # Average percentage of cache occupancy 1352system.cpu1.icache.ReadReq_hits::cpu1.inst 841895 # number of ReadReq hits 1353system.cpu1.icache.ReadReq_hits::total 841895 # number of ReadReq hits 1354system.cpu1.icache.demand_hits::cpu1.inst 841895 # number of demand (read+write) hits 1355system.cpu1.icache.demand_hits::total 841895 # number of demand (read+write) hits 1356system.cpu1.icache.overall_hits::cpu1.inst 841895 # number of overall hits 1357system.cpu1.icache.overall_hits::total 841895 # number of overall hits 1358system.cpu1.icache.ReadReq_misses::cpu1.inst 109497 # number of ReadReq misses 1359system.cpu1.icache.ReadReq_misses::total 109497 # number of ReadReq misses 1360system.cpu1.icache.demand_misses::cpu1.inst 109497 # number of demand (read+write) misses 1361system.cpu1.icache.demand_misses::total 109497 # number of demand (read+write) misses 1362system.cpu1.icache.overall_misses::cpu1.inst 109497 # number of overall misses 1363system.cpu1.icache.overall_misses::total 109497 # number of overall misses 1364system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1632285999 # number of ReadReq miss cycles 1365system.cpu1.icache.ReadReq_miss_latency::total 1632285999 # number of ReadReq miss cycles 1366system.cpu1.icache.demand_miss_latency::cpu1.inst 1632285999 # number of demand (read+write) miss cycles 1367system.cpu1.icache.demand_miss_latency::total 1632285999 # number of demand (read+write) miss cycles 1368system.cpu1.icache.overall_miss_latency::cpu1.inst 1632285999 # number of overall miss cycles 1369system.cpu1.icache.overall_miss_latency::total 1632285999 # number of overall miss cycles 1370system.cpu1.icache.ReadReq_accesses::cpu1.inst 951392 # number of ReadReq accesses(hits+misses) 1371system.cpu1.icache.ReadReq_accesses::total 951392 # number of ReadReq accesses(hits+misses) 1372system.cpu1.icache.demand_accesses::cpu1.inst 951392 # number of demand (read+write) accesses 1373system.cpu1.icache.demand_accesses::total 951392 # number of demand (read+write) accesses 1374system.cpu1.icache.overall_accesses::cpu1.inst 951392 # number of overall (read+write) accesses 1375system.cpu1.icache.overall_accesses::total 951392 # number of overall (read+write) accesses 1376system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115091 # miss rate for ReadReq accesses 1377system.cpu1.icache.ReadReq_miss_rate::total 0.115091 # miss rate for ReadReq accesses 1378system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115091 # miss rate for demand accesses 1379system.cpu1.icache.demand_miss_rate::total 0.115091 # miss rate for demand accesses 1380system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115091 # miss rate for overall accesses 1381system.cpu1.icache.overall_miss_rate::total 0.115091 # miss rate for overall accesses 1382system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867 # average ReadReq miss latency 1383system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867 # average ReadReq miss latency 1384system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency 1385system.cpu1.icache.demand_avg_miss_latency::total 14907.129867 # average overall miss latency 1386system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867 # average overall miss latency 1387system.cpu1.icache.overall_avg_miss_latency::total 14907.129867 # average overall miss latency 1388system.cpu1.icache.blocked_cycles::no_mshrs 108999 # number of cycles access was blocked | 1325system.cpu1.rob.rob_reads 34238592 # The number of ROB reads 1326system.cpu1.rob.rob_writes 28901418 # The number of ROB writes 1327system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself 1328system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling 1329system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1330system.cpu1.committedInsts 11789199 # Number of Instructions Simulated 1331system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated 1332system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated 1333system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction 1334system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads 1335system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle 1336system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads 1337system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads 1338system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes 1339system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads 1340system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes 1341system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads 1342system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes 1343system.cpu1.icache.replacements 315447 # number of replacements 1344system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use 1345system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks. 1346system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks. 1347system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks. 1348system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit. 1349system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor 1350system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy 1351system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy 1352system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits 1353system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits 1354system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits 1355system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits 1356system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits 1357system.cpu1.icache.overall_hits::total 1635327 # number of overall hits 1358system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses 1359system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses 1360system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses 1361system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses 1362system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses 1363system.cpu1.icache.overall_misses::total 328187 # number of overall misses 1364system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles 1365system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles 1366system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles 1367system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles 1368system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles 1369system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles 1370system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses) 1371system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses) 1372system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses 1373system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses 1374system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses 1375system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses 1376system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses 1377system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses 1378system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses 1379system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses 1380system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses 1381system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses 1382system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency 1383system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency 1384system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency 1385system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency 1386system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency 1387system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency 1388system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked |
| 1389system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1389system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1390system.cpu1.icache.blocked::no_mshrs 15 # number of cycles access was blocked | 1390system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked |
| 1391system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1391system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1392system.cpu1.icache.avg_blocked_cycles::no_mshrs 7266.600000 # average number of cycles each access was blocked | 1392system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked |
| 1393system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1394system.cpu1.icache.fast_writes 0 # number of fast writes performed 1395system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1393system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1394system.cpu1.icache.fast_writes 0 # number of fast writes performed 1395system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1396system.cpu1.icache.writebacks::writebacks 39 # number of writebacks 1397system.cpu1.icache.writebacks::total 39 # number of writebacks 1398system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 5150 # number of ReadReq MSHR hits 1399system.cpu1.icache.ReadReq_mshr_hits::total 5150 # number of ReadReq MSHR hits 1400system.cpu1.icache.demand_mshr_hits::cpu1.inst 5150 # number of demand (read+write) MSHR hits 1401system.cpu1.icache.demand_mshr_hits::total 5150 # number of demand (read+write) MSHR hits 1402system.cpu1.icache.overall_mshr_hits::cpu1.inst 5150 # number of overall MSHR hits 1403system.cpu1.icache.overall_mshr_hits::total 5150 # number of overall MSHR hits 1404system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 104347 # number of ReadReq MSHR misses 1405system.cpu1.icache.ReadReq_mshr_misses::total 104347 # number of ReadReq MSHR misses 1406system.cpu1.icache.demand_mshr_misses::cpu1.inst 104347 # number of demand (read+write) MSHR misses 1407system.cpu1.icache.demand_mshr_misses::total 104347 # number of demand (read+write) MSHR misses 1408system.cpu1.icache.overall_mshr_misses::cpu1.inst 104347 # number of overall MSHR misses 1409system.cpu1.icache.overall_mshr_misses::total 104347 # number of overall MSHR misses 1410system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1240890499 # number of ReadReq MSHR miss cycles 1411system.cpu1.icache.ReadReq_mshr_miss_latency::total 1240890499 # number of ReadReq MSHR miss cycles 1412system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1240890499 # number of demand (read+write) MSHR miss cycles 1413system.cpu1.icache.demand_mshr_miss_latency::total 1240890499 # number of demand (read+write) MSHR miss cycles 1414system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1240890499 # number of overall MSHR miss cycles 1415system.cpu1.icache.overall_mshr_miss_latency::total 1240890499 # number of overall MSHR miss cycles 1416system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for ReadReq accesses 1417system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.109678 # mshr miss rate for ReadReq accesses 1418system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for demand accesses 1419system.cpu1.icache.demand_mshr_miss_rate::total 0.109678 # mshr miss rate for demand accesses 1420system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.109678 # mshr miss rate for overall accesses 1421system.cpu1.icache.overall_mshr_miss_rate::total 0.109678 # mshr miss rate for overall accesses 1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average ReadReq mshr miss latency 1423system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427 # average ReadReq mshr miss latency 1424system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency 1425system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency 1426system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427 # average overall mshr miss latency 1427system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427 # average overall mshr miss latency | 1396system.cpu1.icache.writebacks::writebacks 38 # number of writebacks 1397system.cpu1.icache.writebacks::total 38 # number of writebacks 1398system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits 1399system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits 1400system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits 1401system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits 1402system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits 1403system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits 1404system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses 1405system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses 1406system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses 1407system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses 1408system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses 1409system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses 1410system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles 1411system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles 1412system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles 1413system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles 1414system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles 1415system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles 1416system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses 1417system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses 1418system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses 1419system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses 1420system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses 1421system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses 1422system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency 1423system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency 1424system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency 1425system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency 1426system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency 1427system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency |
| 1428system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1428system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1429system.cpu1.dcache.replacements 49122 # number of replacements 1430system.cpu1.dcache.tagsinuse 427.490507 # Cycle average of tags in use 1431system.cpu1.dcache.total_refs 1549420 # Total number of references to valid blocks. 1432system.cpu1.dcache.sampled_refs 49435 # Sample count of references to valid blocks. 1433system.cpu1.dcache.avg_refs 31.342571 # Average number of references to valid blocks. 1434system.cpu1.dcache.warmup_cycle 1873347092000 # Cycle when the warmup percentage was hit. 1435system.cpu1.dcache.occ_blocks::cpu1.data 427.490507 # Average occupied blocks per requestor 1436system.cpu1.dcache.occ_percent::cpu1.data 0.834942 # Average percentage of cache occupancy 1437system.cpu1.dcache.occ_percent::total 0.834942 # Average percentage of cache occupancy 1438system.cpu1.dcache.ReadReq_hits::cpu1.data 1023689 # number of ReadReq hits 1439system.cpu1.dcache.ReadReq_hits::total 1023689 # number of ReadReq hits 1440system.cpu1.dcache.WriteReq_hits::cpu1.data 507974 # number of WriteReq hits 1441system.cpu1.dcache.WriteReq_hits::total 507974 # number of WriteReq hits 1442system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 14665 # number of LoadLockedReq hits 1443system.cpu1.dcache.LoadLockedReq_hits::total 14665 # number of LoadLockedReq hits 1444system.cpu1.dcache.StoreCondReq_hits::cpu1.data 12767 # number of StoreCondReq hits 1445system.cpu1.dcache.StoreCondReq_hits::total 12767 # number of StoreCondReq hits 1446system.cpu1.dcache.demand_hits::cpu1.data 1531663 # number of demand (read+write) hits 1447system.cpu1.dcache.demand_hits::total 1531663 # number of demand (read+write) hits 1448system.cpu1.dcache.overall_hits::cpu1.data 1531663 # number of overall hits 1449system.cpu1.dcache.overall_hits::total 1531663 # number of overall hits 1450system.cpu1.dcache.ReadReq_misses::cpu1.data 89035 # number of ReadReq misses 1451system.cpu1.dcache.ReadReq_misses::total 89035 # number of ReadReq misses 1452system.cpu1.dcache.WriteReq_misses::cpu1.data 104470 # number of WriteReq misses 1453system.cpu1.dcache.WriteReq_misses::total 104470 # number of WriteReq misses 1454system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1314 # number of LoadLockedReq misses 1455system.cpu1.dcache.LoadLockedReq_misses::total 1314 # number of LoadLockedReq misses 1456system.cpu1.dcache.StoreCondReq_misses::cpu1.data 680 # number of StoreCondReq misses 1457system.cpu1.dcache.StoreCondReq_misses::total 680 # number of StoreCondReq misses 1458system.cpu1.dcache.demand_misses::cpu1.data 193505 # number of demand (read+write) misses 1459system.cpu1.dcache.demand_misses::total 193505 # number of demand (read+write) misses 1460system.cpu1.dcache.overall_misses::cpu1.data 193505 # number of overall misses 1461system.cpu1.dcache.overall_misses::total 193505 # number of overall misses 1462system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1323211000 # number of ReadReq miss cycles 1463system.cpu1.dcache.ReadReq_miss_latency::total 1323211000 # number of ReadReq miss cycles 1464system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3353600320 # number of WriteReq miss cycles 1465system.cpu1.dcache.WriteReq_miss_latency::total 3353600320 # number of WriteReq miss cycles 1466system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 16083500 # number of LoadLockedReq miss cycles 1467system.cpu1.dcache.LoadLockedReq_miss_latency::total 16083500 # number of LoadLockedReq miss cycles 1468system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7995500 # number of StoreCondReq miss cycles 1469system.cpu1.dcache.StoreCondReq_miss_latency::total 7995500 # number of StoreCondReq miss cycles 1470system.cpu1.dcache.demand_miss_latency::cpu1.data 4676811320 # number of demand (read+write) miss cycles 1471system.cpu1.dcache.demand_miss_latency::total 4676811320 # number of demand (read+write) miss cycles 1472system.cpu1.dcache.overall_miss_latency::cpu1.data 4676811320 # number of overall miss cycles 1473system.cpu1.dcache.overall_miss_latency::total 4676811320 # number of overall miss cycles 1474system.cpu1.dcache.ReadReq_accesses::cpu1.data 1112724 # number of ReadReq accesses(hits+misses) 1475system.cpu1.dcache.ReadReq_accesses::total 1112724 # number of ReadReq accesses(hits+misses) 1476system.cpu1.dcache.WriteReq_accesses::cpu1.data 612444 # number of WriteReq accesses(hits+misses) 1477system.cpu1.dcache.WriteReq_accesses::total 612444 # number of WriteReq accesses(hits+misses) 1478system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 15979 # number of LoadLockedReq accesses(hits+misses) 1479system.cpu1.dcache.LoadLockedReq_accesses::total 15979 # number of LoadLockedReq accesses(hits+misses) 1480system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 13447 # number of StoreCondReq accesses(hits+misses) 1481system.cpu1.dcache.StoreCondReq_accesses::total 13447 # number of StoreCondReq accesses(hits+misses) 1482system.cpu1.dcache.demand_accesses::cpu1.data 1725168 # number of demand (read+write) accesses 1483system.cpu1.dcache.demand_accesses::total 1725168 # number of demand (read+write) accesses 1484system.cpu1.dcache.overall_accesses::cpu1.data 1725168 # number of overall (read+write) accesses 1485system.cpu1.dcache.overall_accesses::total 1725168 # number of overall (read+write) accesses 1486system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.080015 # miss rate for ReadReq accesses 1487system.cpu1.dcache.ReadReq_miss_rate::total 0.080015 # miss rate for ReadReq accesses 1488system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.170579 # miss rate for WriteReq accesses 1489system.cpu1.dcache.WriteReq_miss_rate::total 0.170579 # miss rate for WriteReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082233 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082233 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050569 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050569 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.112166 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.112166 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.112166 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.112166 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235 # average StoreCondReq miss latency 1506system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency 1507system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025 # average overall miss latency 1508system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025 # average overall miss latency 1509system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025 # average overall miss latency 1510system.cpu1.dcache.blocked_cycles::no_mshrs 52059498 # number of cycles access was blocked | 1429system.cpu1.dcache.replacements 159076 # number of replacements 1430system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use 1431system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks. 1432system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks. 1433system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks. 1434system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit. 1435system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor 1436system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy 1437system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy 1438system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits 1439system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits 1440system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits 1441system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits 1442system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits 1443system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits 1444system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits 1445system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits 1446system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits 1447system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits 1448system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits 1449system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits 1450system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses 1451system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses 1452system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses 1453system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses 1454system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses 1455system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses 1456system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses 1457system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses 1458system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses 1459system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses 1460system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses 1461system.cpu1.dcache.overall_misses::total 668020 # number of overall misses 1462system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles 1463system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles 1464system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles 1465system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles 1466system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles 1467system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles 1468system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles 1469system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles 1470system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles 1471system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles 1472system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles 1473system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles 1474system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses) 1475system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses) 1476system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses) 1477system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses) 1478system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses) 1479system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses) 1480system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses) 1481system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses) 1482system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses 1483system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses 1484system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses 1485system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses 1486system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses 1487system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses 1488system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses 1489system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses 1490system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses 1491system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses 1492system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses 1493system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses 1494system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses 1495system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses 1496system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses 1497system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses 1498system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency 1499system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency 1500system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency 1501system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency 1502system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency 1503system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency 1504system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency 1505system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency 1506system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency 1507system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency 1508system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency 1509system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency 1510system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked |
| 1511system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1511system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1512system.cpu1.dcache.blocked::no_mshrs 4983 # number of cycles access was blocked | 1512system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked |
| 1513system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1513system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1514system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831 # average number of cycles each access was blocked | 1514system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked |
| 1515system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1516system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1517system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1515system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1516system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1517system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1518system.cpu1.dcache.writebacks::writebacks 27321 # number of writebacks 1519system.cpu1.dcache.writebacks::total 27321 # number of writebacks 1520system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 51379 # number of ReadReq MSHR hits 1521system.cpu1.dcache.ReadReq_mshr_hits::total 51379 # number of ReadReq MSHR hits 1522system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 87869 # number of WriteReq MSHR hits 1523system.cpu1.dcache.WriteReq_mshr_hits::total 87869 # number of WriteReq MSHR hits 1524system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 246 # number of LoadLockedReq MSHR hits 1525system.cpu1.dcache.LoadLockedReq_mshr_hits::total 246 # number of LoadLockedReq MSHR hits 1526system.cpu1.dcache.demand_mshr_hits::cpu1.data 139248 # number of demand (read+write) MSHR hits 1527system.cpu1.dcache.demand_mshr_hits::total 139248 # number of demand (read+write) MSHR hits 1528system.cpu1.dcache.overall_mshr_hits::cpu1.data 139248 # number of overall MSHR hits 1529system.cpu1.dcache.overall_mshr_hits::total 139248 # number of overall MSHR hits 1530system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37656 # number of ReadReq MSHR misses 1531system.cpu1.dcache.ReadReq_mshr_misses::total 37656 # number of ReadReq MSHR misses 1532system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16601 # number of WriteReq MSHR misses 1533system.cpu1.dcache.WriteReq_mshr_misses::total 16601 # number of WriteReq MSHR misses 1534system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1068 # number of LoadLockedReq MSHR misses 1535system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1068 # number of LoadLockedReq MSHR misses 1536system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 674 # number of StoreCondReq MSHR misses 1537system.cpu1.dcache.StoreCondReq_mshr_misses::total 674 # number of StoreCondReq MSHR misses 1538system.cpu1.dcache.demand_mshr_misses::cpu1.data 54257 # number of demand (read+write) MSHR misses 1539system.cpu1.dcache.demand_mshr_misses::total 54257 # number of demand (read+write) MSHR misses 1540system.cpu1.dcache.overall_mshr_misses::cpu1.data 54257 # number of overall MSHR misses 1541system.cpu1.dcache.overall_mshr_misses::total 54257 # number of overall MSHR misses 1542system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 431650500 # number of ReadReq MSHR miss cycles 1543system.cpu1.dcache.ReadReq_mshr_miss_latency::total 431650500 # number of ReadReq MSHR miss cycles 1544system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 497061484 # number of WriteReq MSHR miss cycles 1545system.cpu1.dcache.WriteReq_mshr_miss_latency::total 497061484 # number of WriteReq MSHR miss cycles 1546system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9472500 # number of LoadLockedReq MSHR miss cycles 1547system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9472500 # number of LoadLockedReq MSHR miss cycles 1548system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5965000 # number of StoreCondReq MSHR miss cycles 1549system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5965000 # number of StoreCondReq MSHR miss cycles 1550system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 928711984 # number of demand (read+write) MSHR miss cycles 1551system.cpu1.dcache.demand_mshr_miss_latency::total 928711984 # number of demand (read+write) MSHR miss cycles 1552system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 928711984 # number of overall MSHR miss cycles 1553system.cpu1.dcache.overall_mshr_miss_latency::total 928711984 # number of overall MSHR miss cycles 1554system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18616500 # number of ReadReq MSHR uncacheable cycles 1555system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18616500 # number of ReadReq MSHR uncacheable cycles 1556system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 318558500 # number of WriteReq MSHR uncacheable cycles 1557system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 318558500 # number of WriteReq MSHR uncacheable cycles 1558system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 337175000 # number of overall MSHR uncacheable cycles 1559system.cpu1.dcache.overall_mshr_uncacheable_latency::total 337175000 # number of overall MSHR uncacheable cycles 1560system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033841 # mshr miss rate for ReadReq accesses 1561system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033841 # mshr miss rate for ReadReq accesses 1562system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027106 # mshr miss rate for WriteReq accesses 1563system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027106 # mshr miss rate for WriteReq accesses 1564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066838 # mshr miss rate for LoadLockedReq accesses 1565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066838 # mshr miss rate for LoadLockedReq accesses 1566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050123 # mshr miss rate for StoreCondReq accesses 1567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050123 # mshr miss rate for StoreCondReq accesses 1568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for demand accesses 1569system.cpu1.dcache.demand_mshr_miss_rate::total 0.031450 # mshr miss rate for demand accesses 1570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031450 # mshr miss rate for overall accesses 1571system.cpu1.dcache.overall_mshr_miss_rate::total 0.031450 # mshr miss rate for overall accesses 1572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945 # average ReadReq mshr miss latency 1573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945 # average ReadReq mshr miss latency 1574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177 # average WriteReq mshr miss latency 1575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177 # average WriteReq mshr miss latency 1576system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8869.382022 # average LoadLockedReq mshr miss latency 1577system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8869.382022 # average LoadLockedReq mshr miss latency 1578system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 8850.148368 # average StoreCondReq mshr miss latency 1579system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 8850.148368 # average StoreCondReq mshr miss latency 1580system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency 1581system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency 1582system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279 # average overall mshr miss latency 1583system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279 # average overall mshr miss latency | 1518system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks 1519system.cpu1.dcache.writebacks::total 112743 # number of writebacks 1520system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits 1521system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits 1522system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits 1523system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits 1524system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits 1525system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits 1526system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits 1527system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits 1528system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits 1529system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits 1530system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses 1531system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses 1532system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses 1533system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses 1534system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses 1535system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses 1536system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses 1537system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses 1538system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses 1539system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses 1540system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses 1541system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses 1542system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles 1543system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles 1544system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles 1545system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles 1546system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles 1547system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles 1548system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles 1549system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles 1550system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles 1551system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles 1552system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles 1553system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles 1554system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles 1555system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles 1556system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles 1557system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles 1558system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles 1559system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles 1560system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses 1561system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses 1562system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses 1563system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses 1564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses 1565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses 1566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses 1567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses 1568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses 1569system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses 1570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses 1571system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses 1572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency 1573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency 1574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency 1575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency 1576system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency 1577system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency 1578system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency 1579system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency 1580system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency 1581system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency 1582system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency 1583system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency |
| 1584system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1585system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1587system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1589system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1584system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1585system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1586system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1587system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1588system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1589system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1590system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1591system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1592system.cpu0.kern.inst.quiesce 6349 # number of quiesce instructions executed 1593system.cpu0.kern.inst.hwrei 201504 # number of hwrei instructions executed 1594system.cpu0.kern.ipl_count::0 72229 40.68% 40.68% # number of times we switched to this ipl 1595system.cpu0.kern.ipl_count::21 237 0.13% 40.82% # number of times we switched to this ipl 1596system.cpu0.kern.ipl_count::22 1919 1.08% 41.90% # number of times we switched to this ipl 1597system.cpu0.kern.ipl_count::30 6 0.00% 41.90% # number of times we switched to this ipl 1598system.cpu0.kern.ipl_count::31 103147 58.10% 100.00% # number of times we switched to this ipl 1599system.cpu0.kern.ipl_count::total 177538 # number of times we switched to this ipl 1600system.cpu0.kern.ipl_good::0 70862 49.25% 49.25% # number of times we switched to this ipl from a different ipl 1601system.cpu0.kern.ipl_good::21 237 0.16% 49.42% # number of times we switched to this ipl from a different ipl 1602system.cpu0.kern.ipl_good::22 1919 1.33% 50.75% # number of times we switched to this ipl from a different ipl 1603system.cpu0.kern.ipl_good::30 6 0.00% 50.75% # number of times we switched to this ipl from a different ipl 1604system.cpu0.kern.ipl_good::31 70856 49.25% 100.00% # number of times we switched to this ipl from a different ipl 1605system.cpu0.kern.ipl_good::total 143880 # number of times we switched to this ipl from a different ipl 1606system.cpu0.kern.ipl_ticks::0 1857798011000 97.96% 97.96% # number of cycles we spent at this ipl 1607system.cpu0.kern.ipl_ticks::21 91384000 0.00% 97.97% # number of cycles we spent at this ipl 1608system.cpu0.kern.ipl_ticks::22 387547000 0.02% 97.99% # number of cycles we spent at this ipl 1609system.cpu0.kern.ipl_ticks::30 3124500 0.00% 97.99% # number of cycles we spent at this ipl 1610system.cpu0.kern.ipl_ticks::31 38114922000 2.01% 100.00% # number of cycles we spent at this ipl 1611system.cpu0.kern.ipl_ticks::total 1896394988500 # number of cycles we spent at this ipl 1612system.cpu0.kern.ipl_used::0 0.981074 # fraction of swpipl calls that actually changed the ipl | 1592system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed 1593system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed 1594system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl 1595system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl 1596system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl 1597system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl 1598system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl 1599system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl 1600system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl 1601system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl 1602system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl 1603system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl 1604system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl 1605system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl 1606system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl 1607system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl 1608system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl 1609system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl 1610system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl 1611system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl 1612system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl |
| 1613system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1614system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1615system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1613system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1614system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1615system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1616system.cpu0.kern.ipl_used::31 0.686942 # fraction of swpipl calls that actually changed the ipl 1617system.cpu0.kern.ipl_used::total 0.810418 # fraction of swpipl calls that actually changed the ipl 1618system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed 1619system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed 1620system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed 1621system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed 1622system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed 1623system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed 1624system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed 1625system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed 1626system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed 1627system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed 1628system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed 1629system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed 1630system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed 1631system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed 1632system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed 1633system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed 1634system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed 1635system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed 1636system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed 1637system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed 1638system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed 1639system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed 1640system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed 1641system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed 1642system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed 1643system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed 1644system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed 1645system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed 1646system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed 1647system.cpu0.kern.syscall::total 228 # number of syscalls executed | 1616system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl 1617system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl 1618system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed 1619system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed 1620system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed 1621system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed 1622system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed 1623system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed 1624system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed 1625system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed 1626system.cpu0.kern.syscall::20 4 1.90% 35.24% # number of syscalls executed 1627system.cpu0.kern.syscall::23 2 0.95% 36.19% # number of syscalls executed 1628system.cpu0.kern.syscall::24 4 1.90% 38.10% # number of syscalls executed 1629system.cpu0.kern.syscall::33 7 3.33% 41.43% # number of syscalls executed 1630system.cpu0.kern.syscall::41 2 0.95% 42.38% # number of syscalls executed 1631system.cpu0.kern.syscall::45 35 16.67% 59.05% # number of syscalls executed 1632system.cpu0.kern.syscall::47 4 1.90% 60.95% # number of syscalls executed 1633system.cpu0.kern.syscall::48 6 2.86% 63.81% # number of syscalls executed 1634system.cpu0.kern.syscall::54 9 4.29% 68.10% # number of syscalls executed 1635system.cpu0.kern.syscall::58 1 0.48% 68.57% # number of syscalls executed 1636system.cpu0.kern.syscall::59 4 1.90% 70.48% # number of syscalls executed 1637system.cpu0.kern.syscall::71 32 15.24% 85.71% # number of syscalls executed 1638system.cpu0.kern.syscall::73 3 1.43% 87.14% # number of syscalls executed 1639system.cpu0.kern.syscall::74 9 4.29% 91.43% # number of syscalls executed 1640system.cpu0.kern.syscall::87 1 0.48% 91.90% # number of syscalls executed 1641system.cpu0.kern.syscall::90 1 0.48% 92.38% # number of syscalls executed 1642system.cpu0.kern.syscall::92 7 3.33% 95.71% # number of syscalls executed 1643system.cpu0.kern.syscall::97 2 0.95% 96.67% # number of syscalls executed 1644system.cpu0.kern.syscall::98 2 0.95% 97.62% # number of syscalls executed 1645system.cpu0.kern.syscall::132 2 0.95% 98.57% # number of syscalls executed 1646system.cpu0.kern.syscall::144 1 0.48% 99.05% # number of syscalls executed 1647system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed 1648system.cpu0.kern.syscall::total 210 # number of syscalls executed |
| 1648system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1649system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1649system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed 1650system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 1651system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 1652system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed 1653system.cpu0.kern.callpal::swpctx 3893 2.09% 2.15% # number of callpals executed 1654system.cpu0.kern.callpal::tbi 50 0.03% 2.17% # number of callpals executed 1655system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed 1656system.cpu0.kern.callpal::swpipl 170509 91.52% 93.70% # number of callpals executed 1657system.cpu0.kern.callpal::rdps 6338 3.40% 97.10% # number of callpals executed 1658system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed 1659system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed 1660system.cpu0.kern.callpal::rdusp 9 0.00% 97.11% # number of callpals executed 1661system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed 1662system.cpu0.kern.callpal::rti 4866 2.61% 99.72% # number of callpals executed 1663system.cpu0.kern.callpal::callsys 386 0.21% 99.93% # number of callpals executed 1664system.cpu0.kern.callpal::imb 138 0.07% 100.00% # number of callpals executed 1665system.cpu0.kern.callpal::total 186310 # number of callpals executed 1666system.cpu0.kern.mode_switch::kernel 7415 # number of protection mode switches 1667system.cpu0.kern.mode_switch::user 1346 # number of protection mode switches | 1650system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed 1651system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed 1652system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed 1653system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed 1654system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed 1655system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed 1656system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed 1657system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed 1658system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed 1659system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed 1660system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed 1661system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed 1662system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed 1663system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed 1664system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed 1665system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed 1666system.cpu0.kern.callpal::total 153507 # number of callpals executed 1667system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches 1668system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches |
| 1668system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 1669system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 1669system.cpu0.kern.mode_good::kernel 1345 1670system.cpu0.kern.mode_good::user 1346 | 1670system.cpu0.kern.mode_good::kernel 1098 1671system.cpu0.kern.mode_good::user 1098 |
| 1671system.cpu0.kern.mode_good::idle 0 | 1672system.cpu0.kern.mode_good::idle 0 |
| 1672system.cpu0.kern.mode_switch_good::kernel 0.181389 # fraction of useful protection mode switches | 1673system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches |
| 1673system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1674system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 1674system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1675system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 1675system.cpu0.kern.mode_switch_good::total 0.307157 # fraction of useful protection mode switches 1676system.cpu0.kern.mode_ticks::kernel 1894436238500 99.90% 99.90% # number of ticks spent at the given mode 1677system.cpu0.kern.mode_ticks::user 1958742000 0.10% 100.00% # number of ticks spent at the given mode | 1676system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches 1677system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode 1678system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode |
| 1678system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 1679system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 1679system.cpu0.kern.swap_context 3894 # number of times the context was actually changed | 1680system.cpu0.kern.swap_context 3077 # number of times the context was actually changed |
| 1680system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1681system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1681system.cpu1.kern.inst.quiesce 2266 # number of quiesce instructions executed 1682system.cpu1.kern.inst.hwrei 36241 # number of hwrei instructions executed 1683system.cpu1.kern.ipl_count::0 9521 32.62% 32.62% # number of times we switched to this ipl 1684system.cpu1.kern.ipl_count::22 1918 6.57% 39.19% # number of times we switched to this ipl 1685system.cpu1.kern.ipl_count::30 104 0.36% 39.54% # number of times we switched to this ipl 1686system.cpu1.kern.ipl_count::31 17647 60.46% 100.00% # number of times we switched to this ipl 1687system.cpu1.kern.ipl_count::total 29190 # number of times we switched to this ipl 1688system.cpu1.kern.ipl_good::0 9511 45.42% 45.42% # number of times we switched to this ipl from a different ipl 1689system.cpu1.kern.ipl_good::22 1918 9.16% 54.58% # number of times we switched to this ipl from a different ipl 1690system.cpu1.kern.ipl_good::30 104 0.50% 55.08% # number of times we switched to this ipl from a different ipl 1691system.cpu1.kern.ipl_good::31 9407 44.92% 100.00% # number of times we switched to this ipl from a different ipl 1692system.cpu1.kern.ipl_good::total 20940 # number of times we switched to this ipl from a different ipl 1693system.cpu1.kern.ipl_ticks::0 1870201149000 98.64% 98.64% # number of cycles we spent at this ipl 1694system.cpu1.kern.ipl_ticks::22 342845500 0.02% 98.65% # number of cycles we spent at this ipl 1695system.cpu1.kern.ipl_ticks::30 41642500 0.00% 98.66% # number of cycles we spent at this ipl 1696system.cpu1.kern.ipl_ticks::31 25494039500 1.34% 100.00% # number of cycles we spent at this ipl 1697system.cpu1.kern.ipl_ticks::total 1896079676500 # number of cycles we spent at this ipl 1698system.cpu1.kern.ipl_used::0 0.998950 # fraction of swpipl calls that actually changed the ipl | 1682system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed 1683system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed 1684system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl 1685system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl 1686system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl 1687system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl 1688system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl 1689system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl 1690system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl 1691system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl 1692system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl 1693system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl 1694system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl 1695system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl 1696system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl 1697system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl 1698system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl 1699system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl |
| 1699system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1700system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1700system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1701system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1701system.cpu1.kern.ipl_used::31 0.533065 # fraction of swpipl calls that actually changed the ipl 1702system.cpu1.kern.ipl_used::total 0.717369 # fraction of swpipl calls that actually changed the ipl 1703system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed 1704system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed 1705system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed 1706system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed 1707system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed 1708system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed 1709system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed 1710system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed 1711system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed 1712system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed 1713system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed 1714system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed 1715system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed 1716system.cpu1.kern.syscall::total 98 # number of syscalls executed | 1702system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl 1703system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl 1704system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed 1705system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed 1706system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed 1707system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed 1708system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed 1709system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed 1710system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed 1711system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed 1712system.cpu1.kern.syscall::24 2 1.72% 40.52% # number of syscalls executed 1713system.cpu1.kern.syscall::33 4 3.45% 43.97% # number of syscalls executed 1714system.cpu1.kern.syscall::45 19 16.38% 60.34% # number of syscalls executed 1715system.cpu1.kern.syscall::47 2 1.72% 62.07% # number of syscalls executed 1716system.cpu1.kern.syscall::48 4 3.45% 65.52% # number of syscalls executed 1717system.cpu1.kern.syscall::54 1 0.86% 66.38% # number of syscalls executed 1718system.cpu1.kern.syscall::59 3 2.59% 68.97% # number of syscalls executed 1719system.cpu1.kern.syscall::71 22 18.97% 87.93% # number of syscalls executed 1720system.cpu1.kern.syscall::74 7 6.03% 93.97% # number of syscalls executed 1721system.cpu1.kern.syscall::90 2 1.72% 95.69% # number of syscalls executed 1722system.cpu1.kern.syscall::92 2 1.72% 97.41% # number of syscalls executed 1723system.cpu1.kern.syscall::132 2 1.72% 99.14% # number of syscalls executed 1724system.cpu1.kern.syscall::144 1 0.86% 100.00% # number of syscalls executed 1725system.cpu1.kern.syscall::total 116 # number of syscalls executed |
| 1717system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1726system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1718system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed 1719system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1720system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 1721system.cpu1.kern.callpal::swpctx 334 1.11% 1.14% # number of callpals executed 1722system.cpu1.kern.callpal::tbi 3 0.01% 1.15% # number of callpals executed 1723system.cpu1.kern.callpal::wrent 7 0.02% 1.17% # number of callpals executed 1724system.cpu1.kern.callpal::swpipl 24745 82.19% 83.36% # number of callpals executed 1725system.cpu1.kern.callpal::rdps 2407 7.99% 91.36% # number of callpals executed 1726system.cpu1.kern.callpal::wrkgp 1 0.00% 91.36% # number of callpals executed 1727system.cpu1.kern.callpal::wrusp 4 0.01% 91.37% # number of callpals executed 1728system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed 1729system.cpu1.kern.callpal::rti 2422 8.04% 99.43% # number of callpals executed 1730system.cpu1.kern.callpal::callsys 129 0.43% 99.86% # number of callpals executed 1731system.cpu1.kern.callpal::imb 42 0.14% 100.00% # number of callpals executed | 1727system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed 1728system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed 1729system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed 1730system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed 1731system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed 1732system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed 1733system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed 1734system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed 1735system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed 1736system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed 1737system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed 1738system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed 1739system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed 1740system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed 1741system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed |
| 1732system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1742system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1733system.cpu1.kern.callpal::total 30107 # number of callpals executed 1734system.cpu1.kern.mode_switch::kernel 710 # number of protection mode switches 1735system.cpu1.kern.mode_switch::user 392 # number of protection mode switches 1736system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches 1737system.cpu1.kern.mode_good::kernel 420 1738system.cpu1.kern.mode_good::user 392 1739system.cpu1.kern.mode_good::idle 28 1740system.cpu1.kern.mode_switch_good::kernel 0.591549 # fraction of useful protection mode switches | 1743system.cpu1.kern.callpal::total 66490 # number of callpals executed 1744system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches 1745system.cpu1.kern.mode_switch::user 641 # number of protection mode switches 1746system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches 1747system.cpu1.kern.mode_good::kernel 1003 1748system.cpu1.kern.mode_good::user 641 1749system.cpu1.kern.mode_good::idle 362 1750system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches |
| 1741system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1751system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1742system.cpu1.kern.mode_switch_good::idle 0.013672 # fraction of useful protection mode switches 1743system.cpu1.kern.mode_switch_good::total 0.266667 # fraction of useful protection mode switches 1744system.cpu1.kern.mode_ticks::kernel 1688462500 0.09% 0.09% # number of ticks spent at the given mode 1745system.cpu1.kern.mode_ticks::user 719657500 0.04% 0.13% # number of ticks spent at the given mode 1746system.cpu1.kern.mode_ticks::idle 1893332404000 99.87% 100.00% # number of ticks spent at the given mode 1747system.cpu1.kern.swap_context 335 # number of times the context was actually changed | 1752system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches 1753system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches 1754system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode 1755system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode 1756system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode 1757system.cpu1.kern.swap_context 1825 # number of times the context was actually changed |
| 1748 1749---------- End Simulation Statistics ---------- | 1758 1759---------- End Simulation Statistics ---------- |