| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.899401 # Number of seconds simulated 4sim_ticks 1899401490000 # Number of ticks simulated 5final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.899401 # Number of seconds simulated 4sim_ticks 1899401490000 # Number of ticks simulated 5final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 189434 # Simulator instruction rate (inst/s) 8host_op_rate 189434 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6363739723 # Simulator tick rate (ticks/s) 10host_mem_usage 296196 # Number of bytes of host memory used 11host_seconds 298.47 # Real time elapsed on the host | 7host_inst_rate 69911 # Simulator instruction rate (inst/s) 8host_op_rate 69911 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2348556801 # Simulator tick rate (ticks/s) 10host_mem_usage 300512 # Number of bytes of host memory used 11host_seconds 808.75 # Real time elapsed on the host |
| 12sim_insts 56540749 # Number of instructions simulated 13sim_ops 56540749 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30421696 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10508736 # Number of bytes written to this memory 17system.physmem.num_reads 475339 # Number of read requests responded to by this memory 18system.physmem.num_writes 164199 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 153 unchanged lines hidden (view full) --- 173system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 56540749 # Number of instructions simulated 13sim_ops 56540749 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30421696 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10508736 # Number of bytes written to this memory 17system.physmem.num_reads 475339 # Number of read requests responded to by this memory 18system.physmem.num_writes 164199 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 153 unchanged lines hidden (view full) --- 173system.l2c.overall_avg_miss_latency::cpu0.inst 52306.597145 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52156.557593 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 52326.955075 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52134.303024 # average overall miss latency 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 181system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 181system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed 185system.l2c.writebacks::writebacks 122679 # number of writebacks 186system.l2c.writebacks::total 122679 # number of writebacks 187system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 188system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 189system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 190system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits --- 143 unchanged lines hidden (view full) --- 334system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency 335system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 336system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 337system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked 338system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 339system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked 340system.iocache.blocked::no_targets 0 # number of cycles access was blocked 341system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked | 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed 185system.l2c.writebacks::writebacks 122679 # number of writebacks 186system.l2c.writebacks::total 122679 # number of writebacks 187system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 188system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits 189system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits 190system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits --- 143 unchanged lines hidden (view full) --- 334system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.980121 # average WriteReq miss latency 335system.iocache.demand_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 336system.iocache.overall_avg_miss_latency::tsunami.ide 137570.352360 # average overall miss latency 337system.iocache.blocked_cycles::no_mshrs 64597068 # number of cycles access was blocked 338system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 339system.iocache.blocked::no_mshrs 10454 # number of cycles access was blocked 340system.iocache.blocked::no_targets 0 # number of cycles access was blocked 341system.iocache.avg_blocked_cycles::no_mshrs 6179.172374 # average number of cycles each access was blocked |
| 342system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 342system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 343system.iocache.fast_writes 0 # number of fast writes performed 344system.iocache.cache_copies 0 # number of cache copies performed 345system.iocache.writebacks::writebacks 41520 # number of writebacks 346system.iocache.writebacks::total 41520 # number of writebacks 347system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 348system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 349system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 350system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 335 unchanged lines hidden (view full) --- 686system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes 687system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads 688system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes 689system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 690system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 691system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 692system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 693system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 343system.iocache.fast_writes 0 # number of fast writes performed 344system.iocache.cache_copies 0 # number of cache copies performed 345system.iocache.writebacks::writebacks 41520 # number of writebacks 346system.iocache.writebacks::total 41520 # number of writebacks 347system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 348system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 349system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 350system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 335 unchanged lines hidden (view full) --- 686system.cpu0.fp_regfile_writes 143908 # number of floating regfile writes 687system.cpu0.misc_regfile_reads 1789860 # number of misc regfile reads 688system.cpu0.misc_regfile_writes 851828 # number of misc regfile writes 689system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 690system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 691system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 692system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 693system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 694system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 694system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 695system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 696system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 695system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 696system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 697system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 697system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 698system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 699system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 698system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 699system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 700system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 700system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 701system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 702system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 701system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 702system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 703system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 703system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 704system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 705system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 704system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 705system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 706system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 706system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 707system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 708system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 707system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 708system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 709system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 709system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 710system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 711system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 710system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 711system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 712system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 712system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 713system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 714system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 713system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 714system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 715system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 715system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 716system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 716system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 717system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 717system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 718system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 719system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 720system.cpu0.icache.replacements 923652 # number of replacements 721system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use 722system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. 723system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. 724system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. 725system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. --- 30 unchanged lines hidden (view full) --- 756system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency 757system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 758system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 759system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked 760system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked 762system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 763system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked | 718system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 719system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 720system.cpu0.icache.replacements 923652 # number of replacements 721system.cpu0.icache.tagsinuse 510.006511 # Cycle average of tags in use 722system.cpu0.icache.total_refs 6902433 # Total number of references to valid blocks. 723system.cpu0.icache.sampled_refs 924160 # Sample count of references to valid blocks. 724system.cpu0.icache.avg_refs 7.468872 # Average number of references to valid blocks. 725system.cpu0.icache.warmup_cycle 23370332000 # Cycle when the warmup percentage was hit. --- 30 unchanged lines hidden (view full) --- 756system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14933.529195 # average ReadReq miss latency 757system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 758system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14933.529195 # average overall miss latency 759system.cpu0.icache.blocked_cycles::no_mshrs 1135999 # number of cycles access was blocked 760system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu0.icache.blocked::no_mshrs 111 # number of cycles access was blocked 762system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 763system.cpu0.icache.avg_blocked_cycles::no_mshrs 10234.225225 # average number of cycles each access was blocked |
| 764system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 764system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 765system.cpu0.icache.fast_writes 0 # number of fast writes performed 766system.cpu0.icache.cache_copies 0 # number of cache copies performed 767system.cpu0.icache.writebacks::writebacks 196 # number of writebacks 768system.cpu0.icache.writebacks::total 196 # number of writebacks 769system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits 770system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits 771system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits 772system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits --- 497 unchanged lines hidden (view full) --- 1270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency 1271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1273system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked 1274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1275system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked 1276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1277system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked | 765system.cpu0.icache.fast_writes 0 # number of fast writes performed 766system.cpu0.icache.cache_copies 0 # number of cache copies performed 767system.cpu0.icache.writebacks::writebacks 196 # number of writebacks 768system.cpu0.icache.writebacks::total 196 # number of writebacks 769system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 49660 # number of ReadReq MSHR hits 770system.cpu0.icache.ReadReq_mshr_hits::total 49660 # number of ReadReq MSHR hits 771system.cpu0.icache.demand_mshr_hits::cpu0.inst 49660 # number of demand (read+write) MSHR hits 772system.cpu0.icache.demand_mshr_hits::total 49660 # number of demand (read+write) MSHR hits --- 497 unchanged lines hidden (view full) --- 1270system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15322.238028 # average ReadReq miss latency 1271system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1272system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15322.238028 # average overall miss latency 1273system.cpu1.icache.blocked_cycles::no_mshrs 361500 # number of cycles access was blocked 1274system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1275system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked 1276system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1277system.cpu1.icache.avg_blocked_cycles::no_mshrs 9513.157895 # average number of cycles each access was blocked |
| 1278system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1278system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1279system.cpu1.icache.fast_writes 0 # number of fast writes performed 1280system.cpu1.icache.cache_copies 0 # number of cache copies performed 1281system.cpu1.icache.writebacks::writebacks 52 # number of writebacks 1282system.cpu1.icache.writebacks::total 52 # number of writebacks 1283system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits 1284system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits 1285system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits 1286system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 1374system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency 1375system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1376system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1377system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked 1378system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1379system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked 1380system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1381system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked | 1279system.cpu1.icache.fast_writes 0 # number of fast writes performed 1280system.cpu1.icache.cache_copies 0 # number of cache copies performed 1281system.cpu1.icache.writebacks::writebacks 52 # number of writebacks 1282system.cpu1.icache.writebacks::total 52 # number of writebacks 1283system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 10580 # number of ReadReq MSHR hits 1284system.cpu1.icache.ReadReq_mshr_hits::total 10580 # number of ReadReq MSHR hits 1285system.cpu1.icache.demand_mshr_hits::cpu1.inst 10580 # number of demand (read+write) MSHR hits 1286system.cpu1.icache.demand_mshr_hits::total 10580 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 1374system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13354.471956 # average StoreCondReq miss latency 1375system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1376system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24258.512904 # average overall miss latency 1377system.cpu1.dcache.blocked_cycles::no_mshrs 113724448 # number of cycles access was blocked 1378system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1379system.cpu1.dcache.blocked::no_mshrs 8713 # number of cycles access was blocked 1380system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1381system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13052.272237 # average number of cycles each access was blocked |
| 1382system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1382system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1383system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1384system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1385system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks 1386system.cpu1.dcache.writebacks::total 116478 # number of writebacks 1387system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits 1388system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits 1389system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits 1390system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits --- 126 unchanged lines hidden (view full) --- 1517system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches 1518system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches 1519system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1520system.cpu0.kern.mode_good::kernel 1161 1521system.cpu0.kern.mode_good::user 1162 1522system.cpu0.kern.mode_good::idle 0 1523system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches 1524system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1383system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1384system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1385system.cpu1.dcache.writebacks::writebacks 116478 # number of writebacks 1386system.cpu1.dcache.writebacks::total 116478 # number of writebacks 1387system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 102135 # number of ReadReq MSHR hits 1388system.cpu1.dcache.ReadReq_mshr_hits::total 102135 # number of ReadReq MSHR hits 1389system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 194652 # number of WriteReq MSHR hits 1390system.cpu1.dcache.WriteReq_mshr_hits::total 194652 # number of WriteReq MSHR hits --- 126 unchanged lines hidden (view full) --- 1517system.cpu0.kern.mode_switch::kernel 7165 # number of protection mode switches 1518system.cpu0.kern.mode_switch::user 1162 # number of protection mode switches 1519system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 1520system.cpu0.kern.mode_good::kernel 1161 1521system.cpu0.kern.mode_good::user 1162 1522system.cpu0.kern.mode_good::idle 0 1523system.cpu0.kern.mode_switch_good::kernel 0.162038 # fraction of useful protection mode switches 1524system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1525system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 1526system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches | 1525system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 1526system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches |
| 1527system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode 1528system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode 1529system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1530system.cpu0.kern.swap_context 3714 # number of times the context was actually changed 1531system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1532system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed 1533system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed 1534system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl --- 70 unchanged lines hidden --- | 1527system.cpu0.kern.mode_ticks::kernel 1897616401500 99.91% 99.91% # number of ticks spent at the given mode 1528system.cpu0.kern.mode_ticks::user 1784230000 0.09% 100.00% # number of ticks spent at the given mode 1529system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 1530system.cpu0.kern.swap_context 3714 # number of times the context was actually changed 1531system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1532system.cpu1.kern.inst.quiesce 3932 # number of quiesce instructions executed 1533system.cpu1.kern.inst.hwrei 49813 # number of hwrei instructions executed 1534system.cpu1.kern.ipl_count::0 15022 36.83% 36.83% # number of times we switched to this ipl --- 70 unchanged lines hidden --- |