| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.907672 # Number of seconds simulated 4sim_ticks 1907672102500 # Number of ticks simulated 5final_tick 1907672102500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.906534 # Number of seconds simulated 4sim_ticks 1906533530000 # Number of ticks simulated 5final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 159928 # Simulator instruction rate (inst/s) 8host_op_rate 159928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5430263290 # Simulator tick rate (ticks/s) 10host_mem_usage 337712 # Number of bytes of host memory used 11host_seconds 351.30 # Real time elapsed on the host 12sim_insts 56183395 # Number of instructions simulated 13sim_ops 56183395 # Number of ops (including micro ops) simulated | 7host_inst_rate 134861 # Simulator instruction rate (inst/s) 8host_op_rate 134861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4533949866 # Simulator tick rate (ticks/s) 10host_mem_usage 343876 # Number of bytes of host memory used 11host_seconds 420.50 # Real time elapsed on the host 12sim_insts 56709432 # Number of instructions simulated 13sim_ops 56709432 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 861632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24651584 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 117952 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 582656 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 26214784 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 861632 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 117952 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 979584 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7845056 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7845056 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 13463 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 385181 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1843 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 9104 # Number of read requests responded to by this memory | 22system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 409606 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 122579 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 122579 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 451667 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12922338 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 61830 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 305428 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13741766 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 451667 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 61830 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 513497 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 4112371 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 4112371 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 4112371 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 451667 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12922338 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 61830 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 305428 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17854137 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 409606 # Number of read requests accepted 55system.physmem.writeReqs 122579 # Number of write requests accepted 56system.physmem.readBursts 409606 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 122579 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26206336 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7843200 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26214784 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7845056 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue | 33system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 410679 # Number of read requests accepted 55system.physmem.writeReqs 123513 # Number of write requests accepted 56system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 66system.physmem.perBankRdBursts::0 26087 # Per bank write bursts 67system.physmem.perBankRdBursts::1 25986 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25681 # Per bank write bursts 69system.physmem.perBankRdBursts::3 25351 # Per bank write bursts 70system.physmem.perBankRdBursts::4 24681 # Per bank write bursts 71system.physmem.perBankRdBursts::5 24934 # Per bank write bursts 72system.physmem.perBankRdBursts::6 25045 # Per bank write bursts 73system.physmem.perBankRdBursts::7 25140 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25540 # Per bank write bursts 75system.physmem.perBankRdBursts::9 26037 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25956 # Per bank write bursts 77system.physmem.perBankRdBursts::11 25606 # Per bank write bursts 78system.physmem.perBankRdBursts::12 26142 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25795 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25668 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25825 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8182 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8217 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8055 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7694 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7332 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7389 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7497 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6907 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7336 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7821 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7658 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7295 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7753 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7589 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7825 # Per bank write bursts 97system.physmem.perBankWrBursts::15 8000 # Per bank write bursts | 66system.physmem.perBankRdBursts::0 26110 # Per bank write bursts 67system.physmem.perBankRdBursts::1 26073 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25765 # Per bank write bursts 69system.physmem.perBankRdBursts::3 25777 # Per bank write bursts 70system.physmem.perBankRdBursts::4 25805 # Per bank write bursts 71system.physmem.perBankRdBursts::5 25558 # Per bank write bursts 72system.physmem.perBankRdBursts::6 25453 # Per bank write bursts 73system.physmem.perBankRdBursts::7 25268 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25514 # Per bank write bursts 75system.physmem.perBankRdBursts::9 25670 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25901 # Per bank write bursts 77system.physmem.perBankRdBursts::11 25385 # Per bank write bursts 78system.physmem.perBankRdBursts::12 25810 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25833 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25046 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25600 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8438 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8395 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7934 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7573 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7567 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7501 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7444 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7061 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7349 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7703 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7693 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7415 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7960 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8226 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7426 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7807 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 100system.physmem.totGap 1907667754500 # Total gap between requests | 99system.physmem.numWrRetry 24 # Number of times write queue was full causing retry 100system.physmem.totGap 1906529083500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 409606 # Read request sizes (log2) | 107system.physmem.readPktSize::6 410679 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 122579 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 317389 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 37968 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 29326 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 24690 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 123513 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see --- 23 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see --- 23 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2918 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 3481 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4567 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6159 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6901 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7938 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9224 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7563 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8289 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8928 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8280 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7498 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7852 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8073 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6026 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 294 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 134 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 129 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 97 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 168 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 181 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 204 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 187 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 146 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 173 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 78 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64695 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 526.308617 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 319.463735 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 416.737705 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 14846 22.95% 22.95% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 11278 17.43% 40.38% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5774 8.92% 49.31% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2666 4.12% 53.43% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2483 3.84% 57.26% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1468 2.27% 59.53% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1658 2.56% 62.10% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1459 2.26% 64.35% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 23063 35.65% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64695 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5527 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 74.082685 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2821.240872 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5524 99.95% 99.95% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 121 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 109 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 136 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 201 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 171 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 206 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 232system.physmem.rdPerTurnAround::total 5527 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5527 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.172969 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.909622 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 21.446069 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-23 4919 89.00% 89.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-31 36 0.65% 89.65% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-39 243 4.40% 94.05% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::40-47 19 0.34% 94.39% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::48-55 5 0.09% 94.48% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-63 15 0.27% 94.75% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::64-71 14 0.25% 95.01% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::72-79 2 0.04% 95.04% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-87 36 0.65% 95.69% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-95 13 0.24% 95.93% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-103 182 3.29% 99.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::104-111 3 0.05% 99.28% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-119 2 0.04% 99.31% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::120-127 2 0.04% 99.35% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 4 0.07% 99.42% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::152-159 3 0.05% 99.48% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::160-167 5 0.09% 99.57% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-175 4 0.07% 99.64% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::176-183 1 0.02% 99.66% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::184-191 2 0.04% 99.69% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 2 0.04% 99.73% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-231 12 0.22% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5527 # Writes before turning the bus around for reads 263system.physmem.totQLat 3957301251 # Total ticks spent queuing 264system.physmem.totMemAccLat 11634938751 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 2047370000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 9664.35 # Average queueing delay per DRAM burst | 232system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads 279system.physmem.totQLat 4047296750 # Total ticks spent queuing 280system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM 281system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers 282system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst |
| 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 283system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 268system.physmem.avgMemAccLat 28414.35 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 13.74 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 13.74 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s | 284system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst 285system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s 286system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s 287system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s 288system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s |
| 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.14 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 289system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 290system.physmem.busUtil 0.14 # Data bus utilization in percentage 291system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 292system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 277system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing 279system.physmem.readRowHits 368811 # Number of row buffer hits during reads 280system.physmem.writeRowHits 98518 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 80.37 # Row buffer hit rate for writes 283system.physmem.avgGap 3584595.12 # Average gap between requests 284system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined 285system.physmem_0.actEnergy 244392120 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 133348875 # Energy for precharge commands per rank (pJ) 287system.physmem_0.readEnergy 1582659000 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 397049040 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) 290system.physmem_0.actBackEnergy 57755737350 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 1093939329000 # Energy for precharge background per rank (pJ) 292system.physmem_0.totalEnergy 1278652258185 # Total energy per rank (pJ) 293system.physmem_0.averagePower 670.268952 # Core power per rank (mW) 294system.physmem_0.memoryStateTime::IDLE 1819699135250 # Time in different power states 295system.physmem_0.memoryStateTime::REF 63701300000 # Time in different power states | 293system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing 294system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing 295system.physmem.readRowHits 369870 # Number of row buffer hits during reads 296system.physmem.writeRowHits 99689 # Number of row buffer hits during writes 297system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads 298system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes 299system.physmem.avgGap 3568995.95 # Average gap between requests 300system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined 301system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ) 302system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ) 303system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ) 304system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ) 305system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) 306system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ) 307system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ) 308system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ) 309system.physmem_0.averagePower 670.306343 # Core power per rank (mW) 310system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states 311system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states |
| 296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 312system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 297system.physmem_0.memoryStateTime::ACT 24270006000 # Time in different power states | 313system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states |
| 298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 314system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 299system.physmem_1.actEnergy 244702080 # Energy for activate commands per rank (pJ) 300system.physmem_1.preEnergy 133518000 # Energy for precharge commands per rank (pJ) 301system.physmem_1.readEnergy 1611238200 # Energy for read commands per rank (pJ) 302system.physmem_1.writeEnergy 397074960 # Energy for write commands per rank (pJ) 303system.physmem_1.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) 304system.physmem_1.actBackEnergy 57480963435 # Energy for active background per rank (pJ) 305system.physmem_1.preBackEnergy 1094180367000 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1278647606475 # Total energy per rank (pJ) 307system.physmem_1.averagePower 670.266509 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 1820097449251 # Time in different power states 309system.physmem_1.memoryStateTime::REF 63701300000 # Time in different power states | 315system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ) 316system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ) 317system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ) 318system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ) 319system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) 320system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ) 321system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ) 322system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ) 323system.physmem_1.averagePower 670.243651 # Core power per rank (mW) 324system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states 325system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states |
| 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 326system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 311system.physmem_1.memoryStateTime::ACT 23871705749 # Time in different power states | 327system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states |
| 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 328system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 313system.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 314system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 315system.cpu0.branchPred.lookups 18486901 # Number of BP lookups 316system.cpu0.branchPred.condPredicted 15748793 # Number of conditional branches predicted 317system.cpu0.branchPred.condIncorrect 541835 # Number of conditional branches incorrect 318system.cpu0.branchPred.BTBLookups 11639433 # Number of BTB lookups 319system.cpu0.branchPred.BTBHits 5170762 # Number of BTB hits | 329system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 330system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 331system.cpu0.branchPred.lookups 16961800 # Number of BP lookups 332system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted 333system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect 334system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups 335system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits |
| 320system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 336system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 321system.cpu0.branchPred.BTBHitPct 44.424518 # BTB Hit Percentage 322system.cpu0.branchPred.usedRAS 1045004 # Number of times the RAS was used to get a target. 323system.cpu0.branchPred.RASInCorrect 41208 # Number of incorrect RAS predictions. 324system.cpu0.branchPred.indirectLookups 5538250 # Number of indirect predictor lookups. 325system.cpu0.branchPred.indirectHits 525213 # Number of indirect target hits. 326system.cpu0.branchPred.indirectMisses 5013037 # Number of indirect misses. 327system.cpu0.branchPredindirectMispredicted 248456 # Number of mispredicted indirect branches. | 337system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage 338system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target. 339system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions. 340system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups. 341system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits. 342system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses. 343system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches. |
| 328system.cpu_clk_domain.clock 500 # Clock period in ticks 329system.cpu0.dtb.fetch_hits 0 # ITB hits 330system.cpu0.dtb.fetch_misses 0 # ITB misses 331system.cpu0.dtb.fetch_acv 0 # ITB acv 332system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 344system.cpu_clk_domain.clock 500 # Clock period in ticks 345system.cpu0.dtb.fetch_hits 0 # ITB hits 346system.cpu0.dtb.fetch_misses 0 # ITB misses 347system.cpu0.dtb.fetch_acv 0 # ITB acv 348system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 333system.cpu0.dtb.read_hits 10388247 # DTB read hits 334system.cpu0.dtb.read_misses 39745 # DTB read misses | 349system.cpu0.dtb.read_hits 9542415 # DTB read hits 350system.cpu0.dtb.read_misses 34570 # DTB read misses |
| 335system.cpu0.dtb.read_acv 614 # DTB read access violations | 351system.cpu0.dtb.read_acv 614 # DTB read access violations |
| 336system.cpu0.dtb.read_accesses 666259 # DTB read accesses 337system.cpu0.dtb.write_hits 6304219 # DTB write hits 338system.cpu0.dtb.write_misses 9494 # DTB write misses 339system.cpu0.dtb.write_acv 419 # DTB write access violations 340system.cpu0.dtb.write_accesses 221498 # DTB write accesses 341system.cpu0.dtb.data_hits 16692466 # DTB hits 342system.cpu0.dtb.data_misses 49239 # DTB misses 343system.cpu0.dtb.data_acv 1033 # DTB access violations 344system.cpu0.dtb.data_accesses 887757 # DTB accesses 345system.cpu0.itb.fetch_hits 1498511 # ITB hits 346system.cpu0.itb.fetch_misses 7842 # ITB misses 347system.cpu0.itb.fetch_acv 715 # ITB acv 348system.cpu0.itb.fetch_accesses 1506353 # ITB accesses | 352system.cpu0.dtb.read_accesses 570502 # DTB read accesses 353system.cpu0.dtb.write_hits 5776455 # DTB write hits 354system.cpu0.dtb.write_misses 8473 # DTB write misses 355system.cpu0.dtb.write_acv 390 # DTB write access violations 356system.cpu0.dtb.write_accesses 186760 # DTB write accesses 357system.cpu0.dtb.data_hits 15318870 # DTB hits 358system.cpu0.dtb.data_misses 43043 # DTB misses 359system.cpu0.dtb.data_acv 1004 # DTB access violations 360system.cpu0.dtb.data_accesses 757262 # DTB accesses 361system.cpu0.itb.fetch_hits 1323023 # ITB hits 362system.cpu0.itb.fetch_misses 7096 # ITB misses 363system.cpu0.itb.fetch_acv 610 # ITB acv 364system.cpu0.itb.fetch_accesses 1330119 # ITB accesses |
| 349system.cpu0.itb.read_hits 0 # DTB read hits 350system.cpu0.itb.read_misses 0 # DTB read misses 351system.cpu0.itb.read_acv 0 # DTB read access violations 352system.cpu0.itb.read_accesses 0 # DTB read accesses 353system.cpu0.itb.write_hits 0 # DTB write hits 354system.cpu0.itb.write_misses 0 # DTB write misses 355system.cpu0.itb.write_acv 0 # DTB write access violations 356system.cpu0.itb.write_accesses 0 # DTB write accesses 357system.cpu0.itb.data_hits 0 # DTB hits 358system.cpu0.itb.data_misses 0 # DTB misses 359system.cpu0.itb.data_acv 0 # DTB access violations 360system.cpu0.itb.data_accesses 0 # DTB accesses | 365system.cpu0.itb.read_hits 0 # DTB read hits 366system.cpu0.itb.read_misses 0 # DTB read misses 367system.cpu0.itb.read_acv 0 # DTB read access violations 368system.cpu0.itb.read_accesses 0 # DTB read accesses 369system.cpu0.itb.write_hits 0 # DTB write hits 370system.cpu0.itb.write_misses 0 # DTB write misses 371system.cpu0.itb.write_acv 0 # DTB write access violations 372system.cpu0.itb.write_accesses 0 # DTB write accesses 373system.cpu0.itb.data_hits 0 # DTB hits 374system.cpu0.itb.data_misses 0 # DTB misses 375system.cpu0.itb.data_acv 0 # DTB access violations 376system.cpu0.itb.data_accesses 0 # DTB accesses |
| 361system.cpu0.numPwrStateTransitions 12731 # Number of power state transitions 362system.cpu0.pwrStateClkGateDist::samples 6366 # Distribution of time spent in the clock gated state 363system.cpu0.pwrStateClkGateDist::mean 290215354.618913 # Distribution of time spent in the clock gated state 364system.cpu0.pwrStateClkGateDist::stdev 443182270.048279 # Distribution of time spent in the clock gated state 365system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state 366system.cpu0.pwrStateClkGateDist::1000-5e+10 6362 99.94% 100.00% # Distribution of time spent in the clock gated state | 377system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions 378system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state 379system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state 380system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state 381system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 382system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state |
| 367system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 368system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state | 383system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 384system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| 369system.cpu0.pwrStateClkGateDist::total 6366 # Distribution of time spent in the clock gated state 370system.cpu0.pwrStateResidencyTicks::ON 60161154996 # Cumulative time (in ticks) in various power states 371system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504 # Cumulative time (in ticks) in various power states 372system.cpu0.numCycles 120328672 # number of cpu cycles simulated | 385system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state 386system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states 387system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states 388system.cpu0.numCycles 115029541 # number of cpu cycles simulated |
| 373system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 374system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 389system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 375system.cpu0.fetch.icacheStallCycles 28758768 # Number of cycles fetch is stalled on an Icache miss 376system.cpu0.fetch.Insts 80605672 # Number of instructions fetch has processed 377system.cpu0.fetch.Branches 18486901 # Number of branches that fetch encountered 378system.cpu0.fetch.predictedBranches 6740979 # Number of branches that fetch has predicted taken 379system.cpu0.fetch.Cycles 84470777 # Number of cycles fetch has run and was not squashing or blocked 380system.cpu0.fetch.SquashCycles 1538724 # Number of cycles fetch has spent squashing 381system.cpu0.fetch.TlbCycles 99 # Number of cycles fetch has spent waiting for tlb 382system.cpu0.fetch.MiscStallCycles 28344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 383system.cpu0.fetch.PendingTrapStallCycles 156668 # Number of stall cycles due to pending traps 384system.cpu0.fetch.PendingQuiesceStallCycles 425628 # Number of stall cycles due to pending quiesce instructions 385system.cpu0.fetch.IcacheWaitRetryStallCycles 282 # Number of stall cycles due to full MSHR 386system.cpu0.fetch.CacheLines 9251036 # Number of cache lines fetched 387system.cpu0.fetch.IcacheSquashes 365043 # Number of outstanding Icache misses that were squashed | 391system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss 392system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed 393system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered 394system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken 395system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked 396system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing 397system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb 398system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 399system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps 400system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions 401system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR 402system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched 403system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed |
| 388system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed | 404system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed |
| 389system.cpu0.fetch.rateDist::samples 114609928 # Number of instructions fetched each cycle (Total) 390system.cpu0.fetch.rateDist::mean 0.703304 # Number of instructions fetched each cycle (Total) 391system.cpu0.fetch.rateDist::stdev 2.035053 # Number of instructions fetched each cycle (Total) | 405system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total) 406system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total) 407system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total) |
| 392system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 408system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 393system.cpu0.fetch.rateDist::0 99708886 87.00% 87.00% # Number of instructions fetched each cycle (Total) 394system.cpu0.fetch.rateDist::1 974143 0.85% 87.85% # Number of instructions fetched each cycle (Total) 395system.cpu0.fetch.rateDist::2 1998972 1.74% 89.59% # Number of instructions fetched each cycle (Total) 396system.cpu0.fetch.rateDist::3 868407 0.76% 90.35% # Number of instructions fetched each cycle (Total) 397system.cpu0.fetch.rateDist::4 2758687 2.41% 92.76% # Number of instructions fetched each cycle (Total) 398system.cpu0.fetch.rateDist::5 641235 0.56% 93.32% # Number of instructions fetched each cycle (Total) 399system.cpu0.fetch.rateDist::6 755467 0.66% 93.98% # Number of instructions fetched each cycle (Total) 400system.cpu0.fetch.rateDist::7 978409 0.85% 94.83% # Number of instructions fetched each cycle (Total) 401system.cpu0.fetch.rateDist::8 5925722 5.17% 100.00% # Number of instructions fetched each cycle (Total) | 409system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total) 410system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total) 411system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total) 412system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total) 413system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total) 414system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total) 415system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total) 416system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total) 417system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total) |
| 402system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 403system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 404system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 418system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 419system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 420system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 405system.cpu0.fetch.rateDist::total 114609928 # Number of instructions fetched each cycle (Total) 406system.cpu0.fetch.branchRate 0.153637 # Number of branch fetches per cycle 407system.cpu0.fetch.rate 0.669879 # Number of inst fetches per cycle 408system.cpu0.decode.IdleCycles 23115734 # Number of cycles decode is idle 409system.cpu0.decode.BlockedCycles 79187494 # Number of cycles decode is blocked 410system.cpu0.decode.RunCycles 9649471 # Number of cycles decode is running 411system.cpu0.decode.UnblockCycles 1920435 # Number of cycles decode is unblocking 412system.cpu0.decode.SquashCycles 736793 # Number of cycles decode is squashing 413system.cpu0.decode.BranchResolved 689182 # Number of times decode resolved a branch 414system.cpu0.decode.BranchMispred 33223 # Number of times decode detected a branch misprediction 415system.cpu0.decode.DecodedInsts 69733339 # Number of instructions handled by decode 416system.cpu0.decode.SquashedInsts 101960 # Number of squashed instructions handled by decode 417system.cpu0.rename.SquashCycles 736793 # Number of cycles rename is squashing 418system.cpu0.rename.IdleCycles 24053074 # Number of cycles rename is idle 419system.cpu0.rename.BlockCycles 52045501 # Number of cycles rename is blocking 420system.cpu0.rename.serializeStallCycles 18448869 # count of cycles rename stalled for serializing inst 421system.cpu0.rename.RunCycles 10567955 # Number of cycles rename is running 422system.cpu0.rename.UnblockCycles 8757734 # Number of cycles rename is unblocking 423system.cpu0.rename.RenamedInsts 66954427 # Number of instructions processed by rename 424system.cpu0.rename.ROBFullEvents 200777 # Number of times rename has blocked due to ROB full 425system.cpu0.rename.IQFullEvents 2040075 # Number of times rename has blocked due to IQ full 426system.cpu0.rename.LQFullEvents 234878 # Number of times rename has blocked due to LQ full 427system.cpu0.rename.SQFullEvents 4698433 # Number of times rename has blocked due to SQ full 428system.cpu0.rename.RenamedOperands 45085797 # Number of destination operands rename has renamed 429system.cpu0.rename.RenameLookups 80572701 # Number of register rename lookups that rename has made 430system.cpu0.rename.int_rename_lookups 80419250 # Number of integer rename lookups 431system.cpu0.rename.fp_rename_lookups 143477 # Number of floating rename lookups 432system.cpu0.rename.CommittedMaps 36303569 # Number of HB maps that are committed 433system.cpu0.rename.UndoneMaps 8782228 # Number of HB maps that are undone due to squashing 434system.cpu0.rename.serializingInsts 1592248 # count of serializing insts renamed 435system.cpu0.rename.tempSerializingInsts 261178 # count of temporary serializing insts renamed 436system.cpu0.rename.skidInsts 13101083 # count of insts added to the skid buffer 437system.cpu0.memDep0.insertedLoads 10872978 # Number of loads inserted to the mem dependence unit. 438system.cpu0.memDep0.insertedStores 6724173 # Number of stores inserted to the mem dependence unit. 439system.cpu0.memDep0.conflictingLoads 1603556 # Number of conflicting loads. 440system.cpu0.memDep0.conflictingStores 1060240 # Number of conflicting stores. 441system.cpu0.iq.iqInstsAdded 59089633 # Number of instructions added to the IQ (excludes non-spec) 442system.cpu0.iq.iqNonSpecInstsAdded 2074933 # Number of non-speculative instructions added to the IQ 443system.cpu0.iq.iqInstsIssued 57153011 # Number of instructions issued 444system.cpu0.iq.iqSquashedInstsIssued 84826 # Number of squashed instructions issued 445system.cpu0.iq.iqSquashedInstsExamined 10861661 # Number of squashed instructions iterated over during squash; mainly for profiling 446system.cpu0.iq.iqSquashedOperandsExamined 4738821 # Number of squashed operands that are examined and possibly removed from graph 447system.cpu0.iq.iqSquashedNonSpecRemoved 1447538 # Number of squashed non-spec instructions that were removed 448system.cpu0.iq.issued_per_cycle::samples 114609928 # Number of insts issued each cycle 449system.cpu0.iq.issued_per_cycle::mean 0.498674 # Number of insts issued each cycle 450system.cpu0.iq.issued_per_cycle::stdev 1.243633 # Number of insts issued each cycle | 421system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total) 422system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle 423system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle 424system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle 425system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked 426system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running 427system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking 428system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing 429system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch 430system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction 431system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode 432system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode 433system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing 434system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle 435system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking 436system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst 437system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running 438system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking 439system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename 440system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full 441system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full 442system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full 443system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full 444system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed 445system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made 446system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups 447system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups 448system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed 449system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing 450system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed 451system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed 452system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer 453system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit. 454system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit. 455system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads. 456system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores. 457system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec) 458system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ 459system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued 460system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued 461system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling 462system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph 463system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed 464system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle 465system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle 466system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle |
| 451system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 467system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 452system.cpu0.iq.issued_per_cycle::0 91405720 79.75% 79.75% # Number of insts issued each cycle 453system.cpu0.iq.issued_per_cycle::1 9883367 8.62% 88.38% # Number of insts issued each cycle 454system.cpu0.iq.issued_per_cycle::2 4163005 3.63% 92.01% # Number of insts issued each cycle 455system.cpu0.iq.issued_per_cycle::3 2977529 2.60% 94.61% # Number of insts issued each cycle 456system.cpu0.iq.issued_per_cycle::4 3083312 2.69% 97.30% # Number of insts issued each cycle 457system.cpu0.iq.issued_per_cycle::5 1549770 1.35% 98.65% # Number of insts issued each cycle 458system.cpu0.iq.issued_per_cycle::6 1029487 0.90% 99.55% # Number of insts issued each cycle 459system.cpu0.iq.issued_per_cycle::7 389877 0.34% 99.89% # Number of insts issued each cycle 460system.cpu0.iq.issued_per_cycle::8 127861 0.11% 100.00% # Number of insts issued each cycle | 468system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle 469system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle 470system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle 471system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle 472system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle 473system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle 474system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle 475system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle 476system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle |
| 461system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 462system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 463system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 477system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 479system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 464system.cpu0.iq.issued_per_cycle::total 114609928 # Number of insts issued each cycle | 480system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle |
| 465system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 481system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 466system.cpu0.iq.fu_full::IntAlu 177461 15.95% 15.95% # attempts to use FU when none available 467system.cpu0.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available 468system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available 469system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available 470system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available 471system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available 472system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available 473system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available 474system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available 475system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available 476system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available 477system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available 478system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available 479system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available 480system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available 481system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available 482system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available 483system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available 484system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available 485system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available 486system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available 487system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available 488system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available 489system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available 490system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available 491system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available 492system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available 493system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available 494system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available 495system.cpu0.iq.fu_full::MemRead 577417 51.89% 67.83% # attempts to use FU when none available 496system.cpu0.iq.fu_full::MemWrite 357940 32.17% 100.00% # attempts to use FU when none available | 482system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available 483system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available 484system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available 485system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available 486system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available 487system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available 488system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available 489system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available 490system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available 491system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available 492system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available 493system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available 494system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available 495system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available 496system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available 497system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available 498system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available 499system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available 500system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available 501system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available 502system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available 503system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available 504system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available 505system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available 506system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available 507system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available 508system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available 509system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available 510system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available 511system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available 512system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available |
| 497system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 498system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 513system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 514system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 499system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued 500system.cpu0.iq.FU_type_0::IntAlu 38903396 68.07% 68.07% # Type of FU issued 501system.cpu0.iq.FU_type_0::IntMult 60002 0.10% 68.18% # Type of FU issued 502system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued 503system.cpu0.iq.FU_type_0::FloatAdd 28431 0.05% 68.23% # Type of FU issued 504system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued 505system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued 506system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued 507system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.23% # Type of FU issued 508system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued 509system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued 510system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued 511system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued 512system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued 513system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued 514system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued 515system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued 516system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued 517system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued 518system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued 519system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued 520system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.23% # Type of FU issued 521system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued 522system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.23% # Type of FU issued 523system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.23% # Type of FU issued 524system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued 525system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.23% # Type of FU issued 526system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued 527system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued 528system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued 529system.cpu0.iq.FU_type_0::MemRead 10881663 19.04% 87.27% # Type of FU issued 530system.cpu0.iq.FU_type_0::MemWrite 6404122 11.21% 98.48% # Type of FU issued 531system.cpu0.iq.FU_type_0::IprAccess 870425 1.52% 100.00% # Type of FU issued | 515system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued 516system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued 517system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued 518system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued 519system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued 520system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued 521system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued 522system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued 523system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued 524system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued 525system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued 526system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued 527system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued 528system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued 529system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued 530system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued 531system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued 532system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued 533system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued 534system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued 535system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued 536system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued 537system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued 538system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued 539system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued 540system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued 541system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued 542system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued 543system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued 544system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued 545system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued 546system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued 547system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued |
| 532system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 548system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 533system.cpu0.iq.FU_type_0::total 57153011 # Type of FU issued 534system.cpu0.iq.rate 0.474974 # Inst issue rate 535system.cpu0.iq.fu_busy_cnt 1112818 # FU busy when requested 536system.cpu0.iq.fu_busy_rate 0.019471 # FU busy rate (busy events/executed inst) 537system.cpu0.iq.int_inst_queue_reads 229452003 # Number of integer instruction queue reads 538system.cpu0.iq.int_inst_queue_writes 71724793 # Number of integer instruction queue writes 539system.cpu0.iq.int_inst_queue_wakeup_accesses 55161872 # Number of integer instruction queue wakeup accesses 540system.cpu0.iq.fp_inst_queue_reads 661591 # Number of floating instruction queue reads 541system.cpu0.iq.fp_inst_queue_writes 320309 # Number of floating instruction queue writes 542system.cpu0.iq.fp_inst_queue_wakeup_accesses 299753 # Number of floating instruction queue wakeup accesses 543system.cpu0.iq.int_alu_accesses 57905331 # Number of integer alu accesses 544system.cpu0.iq.fp_alu_accesses 357182 # Number of floating point alu accesses 545system.cpu0.iew.lsq.thread0.forwLoads 649944 # Number of loads that had data forwarded from stores | 549system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued 550system.cpu0.iq.rate 0.462657 # Inst issue rate 551system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested 552system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst) 553system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads 554system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes 555system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses 556system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads 557system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes 558system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses 559system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses 560system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses 561system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores |
| 546system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 562system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 547system.cpu0.iew.lsq.thread0.squashedLoads 2311061 # Number of loads squashed 548system.cpu0.iew.lsq.thread0.ignoredResponses 3974 # Number of memory responses ignored because the instruction is squashed 549system.cpu0.iew.lsq.thread0.memOrderViolation 19354 # Number of memory ordering violations 550system.cpu0.iew.lsq.thread0.squashedStores 772397 # Number of stores squashed | 563system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed 564system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed 565system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations 566system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed |
| 551system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 552system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 567system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 568system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 553system.cpu0.iew.lsq.thread0.rescheduledLoads 18463 # Number of loads that were rescheduled 554system.cpu0.iew.lsq.thread0.cacheBlocked 400325 # Number of times an access to memory failed due to the cache being blocked | 569system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled 570system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked |
| 555system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 571system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 556system.cpu0.iew.iewSquashCycles 736793 # Number of cycles IEW is squashing 557system.cpu0.iew.iewBlockCycles 48901711 # Number of cycles IEW is blocking 558system.cpu0.iew.iewUnblockCycles 778245 # Number of cycles IEW is unblocking 559system.cpu0.iew.iewDispatchedInsts 65010536 # Number of instructions dispatched to IQ 560system.cpu0.iew.iewDispSquashedInsts 175759 # Number of squashed instructions skipped by dispatch 561system.cpu0.iew.iewDispLoadInsts 10872978 # Number of dispatched load instructions 562system.cpu0.iew.iewDispStoreInsts 6724173 # Number of dispatched store instructions 563system.cpu0.iew.iewDispNonSpecInsts 1839088 # Number of dispatched non-speculative instructions 564system.cpu0.iew.iewIQFullEvents 42617 # Number of times the IQ has become full, causing a stall 565system.cpu0.iew.iewLSQFullEvents 533932 # Number of times the LSQ has become full, causing a stall 566system.cpu0.iew.memOrderViolationEvents 19354 # Number of memory order violations 567system.cpu0.iew.predictedTakenIncorrect 209386 # Number of branches that were predicted taken incorrectly 568system.cpu0.iew.predictedNotTakenIncorrect 582195 # Number of branches that were predicted not taken incorrectly 569system.cpu0.iew.branchMispredicts 791581 # Number of branch mispredicts detected at execute 570system.cpu0.iew.iewExecutedInsts 56370431 # Number of executed instructions 571system.cpu0.iew.iewExecLoadInsts 10457447 # Number of load instructions executed 572system.cpu0.iew.iewExecSquashedInsts 782580 # Number of squashed instructions skipped in execute | 572system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing 573system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking 574system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking 575system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ 576system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch 577system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions 578system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions 579system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions 580system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall 581system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall 582system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations 583system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly 584system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly 585system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute 586system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions 587system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed 588system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute |
| 573system.cpu0.iew.exec_swp 0 # number of swp insts executed | 589system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 574system.cpu0.iew.exec_nop 3845970 # number of nop insts executed 575system.cpu0.iew.exec_refs 16790279 # number of memory reference insts executed 576system.cpu0.iew.exec_branches 8937296 # Number of branches executed 577system.cpu0.iew.exec_stores 6332832 # Number of stores executed 578system.cpu0.iew.exec_rate 0.468470 # Inst execution rate 579system.cpu0.iew.wb_sent 55678100 # cumulative count of insts sent to commit 580system.cpu0.iew.wb_count 55461625 # cumulative count of insts written-back 581system.cpu0.iew.wb_producers 28192926 # num instructions producing a value 582system.cpu0.iew.wb_consumers 39039520 # num instructions consuming a value 583system.cpu0.iew.wb_rate 0.460918 # insts written-back per cycle 584system.cpu0.iew.wb_fanout 0.722164 # average fanout of values written-back 585system.cpu0.commit.commitSquashedInsts 11448425 # The number of squashed insts skipped by commit 586system.cpu0.commit.commitNonSpecStalls 627395 # The number of times commit has been forced to stall to communicate backwards 587system.cpu0.commit.branchMispredicts 706831 # The number of times a branch was mispredicted 588system.cpu0.commit.committed_per_cycle::samples 112623597 # Number of insts commited each cycle 589system.cpu0.commit.committed_per_cycle::mean 0.474128 # Number of insts commited each cycle 590system.cpu0.commit.committed_per_cycle::stdev 1.409611 # Number of insts commited each cycle | 590system.cpu0.iew.exec_nop 3577995 # number of nop insts executed 591system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed 592system.cpu0.iew.exec_branches 8349417 # Number of branches executed 593system.cpu0.iew.exec_stores 5801846 # Number of stores executed 594system.cpu0.iew.exec_rate 0.456667 # Inst execution rate 595system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit 596system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back 597system.cpu0.iew.wb_producers 26504573 # num instructions producing a value 598system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value 599system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle 600system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back 601system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit 602system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards 603system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted 604system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle 605system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle 606system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle |
| 591system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 607system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 592system.cpu0.commit.committed_per_cycle::0 93749029 83.24% 83.24% # Number of insts commited each cycle 593system.cpu0.commit.committed_per_cycle::1 7554104 6.71% 89.95% # Number of insts commited each cycle 594system.cpu0.commit.committed_per_cycle::2 4011836 3.56% 93.51% # Number of insts commited each cycle 595system.cpu0.commit.committed_per_cycle::3 2145505 1.91% 95.42% # Number of insts commited each cycle 596system.cpu0.commit.committed_per_cycle::4 1663134 1.48% 96.89% # Number of insts commited each cycle 597system.cpu0.commit.committed_per_cycle::5 616876 0.55% 97.44% # Number of insts commited each cycle 598system.cpu0.commit.committed_per_cycle::6 455080 0.40% 97.84% # Number of insts commited each cycle 599system.cpu0.commit.committed_per_cycle::7 507934 0.45% 98.30% # Number of insts commited each cycle 600system.cpu0.commit.committed_per_cycle::8 1920099 1.70% 100.00% # Number of insts commited each cycle | 608system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle 609system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle 610system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle 611system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle 612system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle 613system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle 614system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle 615system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle 616system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle |
| 601system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 602system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 603system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 617system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 604system.cpu0.commit.committed_per_cycle::total 112623597 # Number of insts commited each cycle 605system.cpu0.commit.committedInsts 53398017 # Number of instructions committed 606system.cpu0.commit.committedOps 53398017 # Number of ops (including micro ops) committed | 620system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle 621system.cpu0.commit.committedInsts 50072886 # Number of instructions committed 622system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed |
| 607system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 623system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 608system.cpu0.commit.refs 14513693 # Number of memory references committed 609system.cpu0.commit.loads 8561917 # Number of loads committed 610system.cpu0.commit.membars 214579 # Number of memory barriers committed 611system.cpu0.commit.branches 8068022 # Number of branches committed 612system.cpu0.commit.fp_insts 288973 # Number of committed floating point instructions. 613system.cpu0.commit.int_insts 49410509 # Number of committed integer instructions. 614system.cpu0.commit.function_calls 696168 # Number of function calls committed. 615system.cpu0.commit.op_class_0::No_OpClass 3098426 5.80% 5.80% # Class of committed instruction 616system.cpu0.commit.op_class_0::IntAlu 34606705 64.81% 70.61% # Class of committed instruction 617system.cpu0.commit.op_class_0::IntMult 58588 0.11% 70.72% # Class of committed instruction 618system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.72% # Class of committed instruction 619system.cpu0.commit.op_class_0::FloatAdd 27960 0.05% 70.77% # Class of committed instruction 620system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.77% # Class of committed instruction 621system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.77% # Class of committed instruction 622system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.77% # Class of committed instruction 623system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.78% # Class of committed instruction 624system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.78% # Class of committed instruction 625system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.78% # Class of committed instruction 626system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.78% # Class of committed instruction 627system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.78% # Class of committed instruction 628system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.78% # Class of committed instruction 629system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.78% # Class of committed instruction 630system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.78% # Class of committed instruction 631system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.78% # Class of committed instruction 632system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.78% # Class of committed instruction 633system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.78% # Class of committed instruction 634system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.78% # Class of committed instruction 635system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.78% # Class of committed instruction 636system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.78% # Class of committed instruction 637system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.78% # Class of committed instruction 638system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.78% # Class of committed instruction 639system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.78% # Class of committed instruction 640system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.78% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.78% # Class of committed instruction 642system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.78% # Class of committed instruction 643system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.78% # Class of committed instruction 644system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.78% # Class of committed instruction 645system.cpu0.commit.op_class_0::MemRead 8776496 16.44% 87.21% # Class of committed instruction 646system.cpu0.commit.op_class_0::MemWrite 5957761 11.16% 98.37% # Class of committed instruction 647system.cpu0.commit.op_class_0::IprAccess 870425 1.63% 100.00% # Class of committed instruction | 624system.cpu0.commit.refs 13411786 # Number of memory references committed 625system.cpu0.commit.loads 7949546 # Number of loads committed 626system.cpu0.commit.membars 194670 # Number of memory barriers committed 627system.cpu0.commit.branches 7579863 # Number of branches committed 628system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions. 629system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions. 630system.cpu0.commit.function_calls 640938 # Number of function calls committed. 631system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction 632system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction 633system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction 634system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction 635system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction 636system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction 637system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction 638system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction 639system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction 640system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction 642system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction 643system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction 644system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction 645system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction 646system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction 647system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction 648system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction 649system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction 650system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction 651system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction 652system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction 653system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction 654system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction 655system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction 656system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction 657system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction 658system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction 659system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction 660system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction 661system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction 662system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction 663system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction |
| 648system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 664system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 649system.cpu0.commit.op_class_0::total 53398017 # Class of committed instruction 650system.cpu0.commit.bw_lim_events 1920099 # number cycles where commit BW limit reached 651system.cpu0.rob.rob_reads 175358628 # The number of ROB reads 652system.cpu0.rob.rob_writes 131681344 # The number of ROB writes 653system.cpu0.timesIdled 541437 # Number of times that the entire CPU went into an idle state and unscheduled itself 654system.cpu0.idleCycles 5718744 # Total number of cycles that the CPU has spent unscheduled due to idling 655system.cpu0.quiesceCycles 3694399415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 656system.cpu0.committedInsts 50302904 # Number of Instructions Simulated 657system.cpu0.committedOps 50302904 # Number of Ops (including micro ops) Simulated 658system.cpu0.cpi 2.392082 # CPI: Cycles Per Instruction 659system.cpu0.cpi_total 2.392082 # CPI: Total CPI of All Threads 660system.cpu0.ipc 0.418046 # IPC: Instructions Per Cycle 661system.cpu0.ipc_total 0.418046 # IPC: Total IPC of All Threads 662system.cpu0.int_regfile_reads 73576817 # number of integer regfile reads 663system.cpu0.int_regfile_writes 40321383 # number of integer regfile writes 664system.cpu0.fp_regfile_reads 142542 # number of floating regfile reads 665system.cpu0.fp_regfile_writes 152983 # number of floating regfile writes 666system.cpu0.misc_regfile_reads 1859375 # number of misc regfile reads 667system.cpu0.misc_regfile_writes 873240 # number of misc regfile writes 668system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 669system.cpu0.dcache.tags.replacements 1336574 # number of replacements 670system.cpu0.dcache.tags.tagsinuse 505.845930 # Cycle average of tags in use 671system.cpu0.dcache.tags.total_refs 11809421 # Total number of references to valid blocks. 672system.cpu0.dcache.tags.sampled_refs 1336976 # Sample count of references to valid blocks. 673system.cpu0.dcache.tags.avg_refs 8.832934 # Average number of references to valid blocks. | 665system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction 666system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached 667system.cpu0.rob.rob_reads 166055766 # The number of ROB reads 668system.cpu0.rob.rob_writes 122136916 # The number of ROB writes 669system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself 670system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling 671system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 672system.cpu0.committedInsts 47166151 # Number of Instructions Simulated 673system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated 674system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction 675system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads 676system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle 677system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads 678system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads 679system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes 680system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads 681system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes 682system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads 683system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes 684system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 685system.cpu0.dcache.tags.replacements 1260860 # number of replacements 686system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use 687system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks. 688system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks. 689system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks. |
| 674system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. | 690system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. |
| 675system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.845930 # Average occupied blocks per requestor 676system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987980 # Average percentage of cache occupancy 677system.cpu0.dcache.tags.occ_percent::total 0.987980 # Average percentage of cache occupancy 678system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id 679system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id 680system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 681system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id 682system.cpu0.dcache.tags.tag_accesses 62763513 # Number of tag accesses 683system.cpu0.dcache.tags.data_accesses 62763513 # Number of data accesses 684system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 685system.cpu0.dcache.ReadReq_hits::cpu0.data 7501117 # number of ReadReq hits 686system.cpu0.dcache.ReadReq_hits::total 7501117 # number of ReadReq hits 687system.cpu0.dcache.WriteReq_hits::cpu0.data 3904271 # number of WriteReq hits 688system.cpu0.dcache.WriteReq_hits::total 3904271 # number of WriteReq hits 689system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 200075 # number of LoadLockedReq hits 690system.cpu0.dcache.LoadLockedReq_hits::total 200075 # number of LoadLockedReq hits 691system.cpu0.dcache.StoreCondReq_hits::cpu0.data 202804 # number of StoreCondReq hits 692system.cpu0.dcache.StoreCondReq_hits::total 202804 # number of StoreCondReq hits 693system.cpu0.dcache.demand_hits::cpu0.data 11405388 # number of demand (read+write) hits 694system.cpu0.dcache.demand_hits::total 11405388 # number of demand (read+write) hits 695system.cpu0.dcache.overall_hits::cpu0.data 11405388 # number of overall hits 696system.cpu0.dcache.overall_hits::total 11405388 # number of overall hits 697system.cpu0.dcache.ReadReq_misses::cpu0.data 1695209 # number of ReadReq misses 698system.cpu0.dcache.ReadReq_misses::total 1695209 # number of ReadReq misses 699system.cpu0.dcache.WriteReq_misses::cpu0.data 1829361 # number of WriteReq misses 700system.cpu0.dcache.WriteReq_misses::total 1829361 # number of WriteReq misses 701system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22067 # number of LoadLockedReq misses 702system.cpu0.dcache.LoadLockedReq_misses::total 22067 # number of LoadLockedReq misses 703system.cpu0.dcache.StoreCondReq_misses::cpu0.data 927 # number of StoreCondReq misses 704system.cpu0.dcache.StoreCondReq_misses::total 927 # number of StoreCondReq misses 705system.cpu0.dcache.demand_misses::cpu0.data 3524570 # number of demand (read+write) misses 706system.cpu0.dcache.demand_misses::total 3524570 # number of demand (read+write) misses 707system.cpu0.dcache.overall_misses::cpu0.data 3524570 # number of overall misses 708system.cpu0.dcache.overall_misses::total 3524570 # number of overall misses 709system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40549578500 # number of ReadReq miss cycles 710system.cpu0.dcache.ReadReq_miss_latency::total 40549578500 # number of ReadReq miss cycles 711system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77276130293 # number of WriteReq miss cycles 712system.cpu0.dcache.WriteReq_miss_latency::total 77276130293 # number of WriteReq miss cycles 713system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333041000 # number of LoadLockedReq miss cycles 714system.cpu0.dcache.LoadLockedReq_miss_latency::total 333041000 # number of LoadLockedReq miss cycles 715system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6753500 # number of StoreCondReq miss cycles 716system.cpu0.dcache.StoreCondReq_miss_latency::total 6753500 # number of StoreCondReq miss cycles 717system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793 # number of demand (read+write) miss cycles 718system.cpu0.dcache.demand_miss_latency::total 117825708793 # number of demand (read+write) miss cycles 719system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793 # number of overall miss cycles 720system.cpu0.dcache.overall_miss_latency::total 117825708793 # number of overall miss cycles 721system.cpu0.dcache.ReadReq_accesses::cpu0.data 9196326 # number of ReadReq accesses(hits+misses) 722system.cpu0.dcache.ReadReq_accesses::total 9196326 # number of ReadReq accesses(hits+misses) 723system.cpu0.dcache.WriteReq_accesses::cpu0.data 5733632 # number of WriteReq accesses(hits+misses) 724system.cpu0.dcache.WriteReq_accesses::total 5733632 # number of WriteReq accesses(hits+misses) 725system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222142 # number of LoadLockedReq accesses(hits+misses) 726system.cpu0.dcache.LoadLockedReq_accesses::total 222142 # number of LoadLockedReq accesses(hits+misses) 727system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 203731 # number of StoreCondReq accesses(hits+misses) 728system.cpu0.dcache.StoreCondReq_accesses::total 203731 # number of StoreCondReq accesses(hits+misses) 729system.cpu0.dcache.demand_accesses::cpu0.data 14929958 # number of demand (read+write) accesses 730system.cpu0.dcache.demand_accesses::total 14929958 # number of demand (read+write) accesses 731system.cpu0.dcache.overall_accesses::cpu0.data 14929958 # number of overall (read+write) accesses 732system.cpu0.dcache.overall_accesses::total 14929958 # number of overall (read+write) accesses 733system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184335 # miss rate for ReadReq accesses 734system.cpu0.dcache.ReadReq_miss_rate::total 0.184335 # miss rate for ReadReq accesses 735system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319058 # miss rate for WriteReq accesses 736system.cpu0.dcache.WriteReq_miss_rate::total 0.319058 # miss rate for WriteReq accesses 737system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.099337 # miss rate for LoadLockedReq accesses 738system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.099337 # miss rate for LoadLockedReq accesses 739system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004550 # miss rate for StoreCondReq accesses 740system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004550 # miss rate for StoreCondReq accesses 741system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236074 # miss rate for demand accesses 742system.cpu0.dcache.demand_miss_rate::total 0.236074 # miss rate for demand accesses 743system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236074 # miss rate for overall accesses 744system.cpu0.dcache.overall_miss_rate::total 0.236074 # miss rate for overall accesses 745system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721 # average ReadReq miss latency 746system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721 # average ReadReq miss latency 747system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728 # average WriteReq miss latency 748system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728 # average WriteReq miss latency 749system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467 # average LoadLockedReq miss latency 750system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467 # average LoadLockedReq miss latency 751system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7285.329018 # average StoreCondReq miss latency 752system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7285.329018 # average StoreCondReq miss latency 753system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency 754system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954 # average overall miss latency 755system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency 756system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954 # average overall miss latency 757system.cpu0.dcache.blocked_cycles::no_mshrs 4313991 # number of cycles access was blocked 758system.cpu0.dcache.blocked_cycles::no_targets 8795 # number of cycles access was blocked 759system.cpu0.dcache.blocked::no_mshrs 119168 # number of cycles access was blocked 760system.cpu0.dcache.blocked::no_targets 132 # number of cycles access was blocked 761system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.200918 # average number of cycles each access was blocked 762system.cpu0.dcache.avg_blocked_cycles::no_targets 66.628788 # average number of cycles each access was blocked 763system.cpu0.dcache.writebacks::writebacks 791920 # number of writebacks 764system.cpu0.dcache.writebacks::total 791920 # number of writebacks 765system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 639925 # number of ReadReq MSHR hits 766system.cpu0.dcache.ReadReq_mshr_hits::total 639925 # number of ReadReq MSHR hits 767system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1556053 # number of WriteReq MSHR hits 768system.cpu0.dcache.WriteReq_mshr_hits::total 1556053 # number of WriteReq MSHR hits 769system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6507 # number of LoadLockedReq MSHR hits 770system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6507 # number of LoadLockedReq MSHR hits 771system.cpu0.dcache.demand_mshr_hits::cpu0.data 2195978 # number of demand (read+write) MSHR hits 772system.cpu0.dcache.demand_mshr_hits::total 2195978 # number of demand (read+write) MSHR hits 773system.cpu0.dcache.overall_mshr_hits::cpu0.data 2195978 # number of overall MSHR hits 774system.cpu0.dcache.overall_mshr_hits::total 2195978 # number of overall MSHR hits 775system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1055284 # number of ReadReq MSHR misses 776system.cpu0.dcache.ReadReq_mshr_misses::total 1055284 # number of ReadReq MSHR misses 777system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273308 # number of WriteReq MSHR misses 778system.cpu0.dcache.WriteReq_mshr_misses::total 273308 # number of WriteReq MSHR misses 779system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15560 # number of LoadLockedReq MSHR misses 780system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15560 # number of LoadLockedReq MSHR misses 781system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 926 # number of StoreCondReq MSHR misses 782system.cpu0.dcache.StoreCondReq_mshr_misses::total 926 # number of StoreCondReq MSHR misses 783system.cpu0.dcache.demand_mshr_misses::cpu0.data 1328592 # number of demand (read+write) MSHR misses 784system.cpu0.dcache.demand_mshr_misses::total 1328592 # number of demand (read+write) MSHR misses 785system.cpu0.dcache.overall_mshr_misses::cpu0.data 1328592 # number of overall MSHR misses 786system.cpu0.dcache.overall_mshr_misses::total 1328592 # number of overall MSHR misses 787system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable 788system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7032 # number of ReadReq MSHR uncacheable 789system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable 790system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9755 # number of WriteReq MSHR uncacheable 791system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses 792system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16787 # number of overall MSHR uncacheable misses 793system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30284931500 # number of ReadReq MSHR miss cycles 794system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30284931500 # number of ReadReq MSHR miss cycles 795system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12180596213 # number of WriteReq MSHR miss cycles 796system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12180596213 # number of WriteReq MSHR miss cycles 797system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 192236000 # number of LoadLockedReq MSHR miss cycles 798system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 192236000 # number of LoadLockedReq MSHR miss cycles 799system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5827500 # number of StoreCondReq MSHR miss cycles 800system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5827500 # number of StoreCondReq MSHR miss cycles 801system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42465527713 # number of demand (read+write) MSHR miss cycles 802system.cpu0.dcache.demand_mshr_miss_latency::total 42465527713 # number of demand (read+write) MSHR miss cycles 803system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42465527713 # number of overall MSHR miss cycles 804system.cpu0.dcache.overall_mshr_miss_latency::total 42465527713 # number of overall MSHR miss cycles 805system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566422000 # number of ReadReq MSHR uncacheable cycles 806system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566422000 # number of ReadReq MSHR uncacheable cycles 807system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566422000 # number of overall MSHR uncacheable cycles 808system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566422000 # number of overall MSHR uncacheable cycles 809system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114751 # mshr miss rate for ReadReq accesses 810system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114751 # mshr miss rate for ReadReq accesses 811system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047668 # mshr miss rate for WriteReq accesses 812system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047668 # mshr miss rate for WriteReq accesses 813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.070045 # mshr miss rate for LoadLockedReq accesses 814system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.070045 # mshr miss rate for LoadLockedReq accesses 815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004545 # mshr miss rate for StoreCondReq accesses 816system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004545 # mshr miss rate for StoreCondReq accesses 817system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for demand accesses 818system.cpu0.dcache.demand_mshr_miss_rate::total 0.088988 # mshr miss rate for demand accesses 819system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for overall accesses 820system.cpu0.dcache.overall_mshr_miss_rate::total 0.088988 # mshr miss rate for overall accesses 821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770 # average ReadReq mshr miss latency 822system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770 # average ReadReq mshr miss latency 823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503 # average WriteReq mshr miss latency 824system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503 # average WriteReq mshr miss latency 825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715 # average LoadLockedReq mshr miss latency 826system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715 # average LoadLockedReq mshr miss latency 827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6293.196544 # average StoreCondReq mshr miss latency 828system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6293.196544 # average StoreCondReq mshr miss latency 829system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency 830system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency 831system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency 833system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110 # average ReadReq mshr uncacheable latency 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110 # average ReadReq mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175 # average overall mshr uncacheable latency 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175 # average overall mshr uncacheable latency 837system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 838system.cpu0.icache.tags.replacements 1014611 # number of replacements 839system.cpu0.icache.tags.tagsinuse 509.545427 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 8173897 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 1015123 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 8.052125 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.545427 # Average occupied blocks per requestor 845system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995206 # Average percentage of cache occupancy 846system.cpu0.icache.tags.occ_percent::total 0.995206 # Average percentage of cache occupancy 847system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 848system.cpu0.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id 849system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 850system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 851system.cpu0.icache.tags.tag_accesses 10266395 # Number of tag accesses 852system.cpu0.icache.tags.data_accesses 10266395 # Number of data accesses 853system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 854system.cpu0.icache.ReadReq_hits::cpu0.inst 8173897 # number of ReadReq hits 855system.cpu0.icache.ReadReq_hits::total 8173897 # number of ReadReq hits 856system.cpu0.icache.demand_hits::cpu0.inst 8173897 # number of demand (read+write) hits 857system.cpu0.icache.demand_hits::total 8173897 # number of demand (read+write) hits 858system.cpu0.icache.overall_hits::cpu0.inst 8173897 # number of overall hits 859system.cpu0.icache.overall_hits::total 8173897 # number of overall hits 860system.cpu0.icache.ReadReq_misses::cpu0.inst 1077136 # number of ReadReq misses 861system.cpu0.icache.ReadReq_misses::total 1077136 # number of ReadReq misses 862system.cpu0.icache.demand_misses::cpu0.inst 1077136 # number of demand (read+write) misses 863system.cpu0.icache.demand_misses::total 1077136 # number of demand (read+write) misses 864system.cpu0.icache.overall_misses::cpu0.inst 1077136 # number of overall misses 865system.cpu0.icache.overall_misses::total 1077136 # number of overall misses 866system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15255278493 # number of ReadReq miss cycles 867system.cpu0.icache.ReadReq_miss_latency::total 15255278493 # number of ReadReq miss cycles 868system.cpu0.icache.demand_miss_latency::cpu0.inst 15255278493 # number of demand (read+write) miss cycles 869system.cpu0.icache.demand_miss_latency::total 15255278493 # number of demand (read+write) miss cycles 870system.cpu0.icache.overall_miss_latency::cpu0.inst 15255278493 # number of overall miss cycles 871system.cpu0.icache.overall_miss_latency::total 15255278493 # number of overall miss cycles 872system.cpu0.icache.ReadReq_accesses::cpu0.inst 9251033 # number of ReadReq accesses(hits+misses) 873system.cpu0.icache.ReadReq_accesses::total 9251033 # number of ReadReq accesses(hits+misses) 874system.cpu0.icache.demand_accesses::cpu0.inst 9251033 # number of demand (read+write) accesses 875system.cpu0.icache.demand_accesses::total 9251033 # number of demand (read+write) accesses 876system.cpu0.icache.overall_accesses::cpu0.inst 9251033 # number of overall (read+write) accesses 877system.cpu0.icache.overall_accesses::total 9251033 # number of overall (read+write) accesses 878system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116434 # miss rate for ReadReq accesses 879system.cpu0.icache.ReadReq_miss_rate::total 0.116434 # miss rate for ReadReq accesses 880system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116434 # miss rate for demand accesses 881system.cpu0.icache.demand_miss_rate::total 0.116434 # miss rate for demand accesses 882system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116434 # miss rate for overall accesses 883system.cpu0.icache.overall_miss_rate::total 0.116434 # miss rate for overall accesses 884system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553 # average ReadReq miss latency 885system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553 # average ReadReq miss latency 886system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency 887system.cpu0.icache.demand_avg_miss_latency::total 14162.815553 # average overall miss latency 888system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency 889system.cpu0.icache.overall_avg_miss_latency::total 14162.815553 # average overall miss latency 890system.cpu0.icache.blocked_cycles::no_mshrs 5826 # number of cycles access was blocked | 691system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor 692system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy 693system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy 694system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 695system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id 696system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 697system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id 698system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses 699system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses 700system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 701system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits 702system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits 703system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits 704system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits 705system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits 706system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits 707system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits 708system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits 709system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits 710system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits 711system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits 712system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits 713system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses 714system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses 715system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses 716system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses 717system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses 718system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses 719system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses 720system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses 721system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses 722system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses 723system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses 724system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses 725system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles 726system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles 727system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles 728system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles 729system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles 730system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles 731system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles 732system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles 733system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles 734system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles 735system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles 736system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles 737system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses) 738system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses) 739system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses) 740system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses) 741system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses) 742system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses) 743system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses) 744system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses) 745system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses 746system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses 747system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses 748system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses 749system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses 750system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses 751system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses 752system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses 753system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses 754system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses 755system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses 756system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses 757system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses 758system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses 759system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses 760system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses 761system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency 762system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency 763system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency 764system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency 765system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency 766system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency 767system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency 768system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency 769system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency 770system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency 771system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency 772system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency 773system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked 774system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked 775system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked 776system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked 777system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked 778system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked 779system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks 780system.cpu0.dcache.writebacks::total 743371 # number of writebacks 781system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits 782system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits 783system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits 784system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits 785system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits 786system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits 787system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits 788system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits 789system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits 790system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits 791system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses 792system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses 793system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses 794system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses 795system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses 796system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses 797system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses 798system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses 799system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses 800system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses 801system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses 802system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses 803system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable 804system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable 805system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable 806system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable 807system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses 808system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses 809system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles 810system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles 811system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles 812system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles 813system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles 814system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles 815system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles 816system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles 817system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles 818system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles 819system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles 820system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles 821system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles 822system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles 823system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles 824system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles 825system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses 826system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses 827system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses 828system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses 829system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses 830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses 831system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses 832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses 833system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses 834system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses 835system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses 836system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses 837system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency 838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency 839system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency 840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency 841system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency 842system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency 843system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency 844system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency 845system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency 846system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency 847system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency 848system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency 849system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency 850system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency 851system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency 852system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency 853system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 854system.cpu0.icache.tags.replacements 908505 # number of replacements 855system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use 856system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks. 857system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks. 858system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks. 859system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit. 860system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor 861system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy 862system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy 863system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 864system.cpu0.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id 865system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 866system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 867system.cpu0.icache.tags.tag_accesses 9473645 # Number of tag accesses 868system.cpu0.icache.tags.data_accesses 9473645 # Number of data accesses 869system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 870system.cpu0.icache.ReadReq_hits::cpu0.inst 7601055 # number of ReadReq hits 871system.cpu0.icache.ReadReq_hits::total 7601055 # number of ReadReq hits 872system.cpu0.icache.demand_hits::cpu0.inst 7601055 # number of demand (read+write) hits 873system.cpu0.icache.demand_hits::total 7601055 # number of demand (read+write) hits 874system.cpu0.icache.overall_hits::cpu0.inst 7601055 # number of overall hits 875system.cpu0.icache.overall_hits::total 7601055 # number of overall hits 876system.cpu0.icache.ReadReq_misses::cpu0.inst 963326 # number of ReadReq misses 877system.cpu0.icache.ReadReq_misses::total 963326 # number of ReadReq misses 878system.cpu0.icache.demand_misses::cpu0.inst 963326 # number of demand (read+write) misses 879system.cpu0.icache.demand_misses::total 963326 # number of demand (read+write) misses 880system.cpu0.icache.overall_misses::cpu0.inst 963326 # number of overall misses 881system.cpu0.icache.overall_misses::total 963326 # number of overall misses 882system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13819823495 # number of ReadReq miss cycles 883system.cpu0.icache.ReadReq_miss_latency::total 13819823495 # number of ReadReq miss cycles 884system.cpu0.icache.demand_miss_latency::cpu0.inst 13819823495 # number of demand (read+write) miss cycles 885system.cpu0.icache.demand_miss_latency::total 13819823495 # number of demand (read+write) miss cycles 886system.cpu0.icache.overall_miss_latency::cpu0.inst 13819823495 # number of overall miss cycles 887system.cpu0.icache.overall_miss_latency::total 13819823495 # number of overall miss cycles 888system.cpu0.icache.ReadReq_accesses::cpu0.inst 8564381 # number of ReadReq accesses(hits+misses) 889system.cpu0.icache.ReadReq_accesses::total 8564381 # number of ReadReq accesses(hits+misses) 890system.cpu0.icache.demand_accesses::cpu0.inst 8564381 # number of demand (read+write) accesses 891system.cpu0.icache.demand_accesses::total 8564381 # number of demand (read+write) accesses 892system.cpu0.icache.overall_accesses::cpu0.inst 8564381 # number of overall (read+write) accesses 893system.cpu0.icache.overall_accesses::total 8564381 # number of overall (read+write) accesses 894system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112481 # miss rate for ReadReq accesses 895system.cpu0.icache.ReadReq_miss_rate::total 0.112481 # miss rate for ReadReq accesses 896system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112481 # miss rate for demand accesses 897system.cpu0.icache.demand_miss_rate::total 0.112481 # miss rate for demand accesses 898system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112481 # miss rate for overall accesses 899system.cpu0.icache.overall_miss_rate::total 0.112481 # miss rate for overall accesses 900system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746 # average ReadReq miss latency 901system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746 # average ReadReq miss latency 902system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency 903system.cpu0.icache.demand_avg_miss_latency::total 14345.946746 # average overall miss latency 904system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency 905system.cpu0.icache.overall_avg_miss_latency::total 14345.946746 # average overall miss latency 906system.cpu0.icache.blocked_cycles::no_mshrs 6257 # number of cycles access was blocked |
| 891system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 907system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 892system.cpu0.icache.blocked::no_mshrs 231 # number of cycles access was blocked | 908system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked |
| 893system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 909system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 894system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.220779 # average number of cycles each access was blocked | 910system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.822660 # average number of cycles each access was blocked |
| 895system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 911system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 896system.cpu0.icache.writebacks::writebacks 1014611 # number of writebacks 897system.cpu0.icache.writebacks::total 1014611 # number of writebacks 898system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 61774 # number of ReadReq MSHR hits 899system.cpu0.icache.ReadReq_mshr_hits::total 61774 # number of ReadReq MSHR hits 900system.cpu0.icache.demand_mshr_hits::cpu0.inst 61774 # number of demand (read+write) MSHR hits 901system.cpu0.icache.demand_mshr_hits::total 61774 # number of demand (read+write) MSHR hits 902system.cpu0.icache.overall_mshr_hits::cpu0.inst 61774 # number of overall MSHR hits 903system.cpu0.icache.overall_mshr_hits::total 61774 # number of overall MSHR hits 904system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1015362 # number of ReadReq MSHR misses 905system.cpu0.icache.ReadReq_mshr_misses::total 1015362 # number of ReadReq MSHR misses 906system.cpu0.icache.demand_mshr_misses::cpu0.inst 1015362 # number of demand (read+write) MSHR misses 907system.cpu0.icache.demand_mshr_misses::total 1015362 # number of demand (read+write) MSHR misses 908system.cpu0.icache.overall_mshr_misses::cpu0.inst 1015362 # number of overall MSHR misses 909system.cpu0.icache.overall_mshr_misses::total 1015362 # number of overall MSHR misses 910system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13566878495 # number of ReadReq MSHR miss cycles 911system.cpu0.icache.ReadReq_mshr_miss_latency::total 13566878495 # number of ReadReq MSHR miss cycles 912system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13566878495 # number of demand (read+write) MSHR miss cycles 913system.cpu0.icache.demand_mshr_miss_latency::total 13566878495 # number of demand (read+write) MSHR miss cycles 914system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13566878495 # number of overall MSHR miss cycles 915system.cpu0.icache.overall_mshr_miss_latency::total 13566878495 # number of overall MSHR miss cycles 916system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for ReadReq accesses 917system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109757 # mshr miss rate for ReadReq accesses 918system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for demand accesses 919system.cpu0.icache.demand_mshr_miss_rate::total 0.109757 # mshr miss rate for demand accesses 920system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for overall accesses 921system.cpu0.icache.overall_mshr_miss_rate::total 0.109757 # mshr miss rate for overall accesses 922system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average ReadReq mshr miss latency 923system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330 # average ReadReq mshr miss latency 924system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency 925system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency 926system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency 927system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency 928system.cpu1.branchPred.lookups 2716012 # Number of BP lookups 929system.cpu1.branchPred.condPredicted 2349135 # Number of conditional branches predicted 930system.cpu1.branchPred.condIncorrect 64284 # Number of conditional branches incorrect 931system.cpu1.branchPred.BTBLookups 1339574 # Number of BTB lookups 932system.cpu1.branchPred.BTBHits 486642 # Number of BTB hits | 912system.cpu0.icache.writebacks::writebacks 908505 # number of writebacks 913system.cpu0.icache.writebacks::total 908505 # number of writebacks 914system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54062 # number of ReadReq MSHR hits 915system.cpu0.icache.ReadReq_mshr_hits::total 54062 # number of ReadReq MSHR hits 916system.cpu0.icache.demand_mshr_hits::cpu0.inst 54062 # number of demand (read+write) MSHR hits 917system.cpu0.icache.demand_mshr_hits::total 54062 # number of demand (read+write) MSHR hits 918system.cpu0.icache.overall_mshr_hits::cpu0.inst 54062 # number of overall MSHR hits 919system.cpu0.icache.overall_mshr_hits::total 54062 # number of overall MSHR hits 920system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909264 # number of ReadReq MSHR misses 921system.cpu0.icache.ReadReq_mshr_misses::total 909264 # number of ReadReq MSHR misses 922system.cpu0.icache.demand_mshr_misses::cpu0.inst 909264 # number of demand (read+write) MSHR misses 923system.cpu0.icache.demand_mshr_misses::total 909264 # number of demand (read+write) MSHR misses 924system.cpu0.icache.overall_mshr_misses::cpu0.inst 909264 # number of overall MSHR misses 925system.cpu0.icache.overall_mshr_misses::total 909264 # number of overall MSHR misses 926system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12278033496 # number of ReadReq MSHR miss cycles 927system.cpu0.icache.ReadReq_mshr_miss_latency::total 12278033496 # number of ReadReq MSHR miss cycles 928system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12278033496 # number of demand (read+write) MSHR miss cycles 929system.cpu0.icache.demand_mshr_miss_latency::total 12278033496 # number of demand (read+write) MSHR miss cycles 930system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12278033496 # number of overall MSHR miss cycles 931system.cpu0.icache.overall_mshr_miss_latency::total 12278033496 # number of overall MSHR miss cycles 932system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for ReadReq accesses 933system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.106168 # mshr miss rate for ReadReq accesses 934system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for demand accesses 935system.cpu0.icache.demand_mshr_miss_rate::total 0.106168 # mshr miss rate for demand accesses 936system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for overall accesses 937system.cpu0.icache.overall_mshr_miss_rate::total 0.106168 # mshr miss rate for overall accesses 938system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average ReadReq mshr miss latency 939system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824 # average ReadReq mshr miss latency 940system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency 941system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency 942system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency 943system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency 944system.cpu1.branchPred.lookups 4250134 # Number of BP lookups 945system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted 946system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect 947system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups 948system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits |
| 933system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 949system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 934system.cpu1.branchPred.BTBHitPct 36.328116 # BTB Hit Percentage 935system.cpu1.branchPred.usedRAS 131116 # Number of times the RAS was used to get a target. 936system.cpu1.branchPred.RASInCorrect 4300 # Number of incorrect RAS predictions. 937system.cpu1.branchPred.indirectLookups 740387 # Number of indirect predictor lookups. 938system.cpu1.branchPred.indirectHits 107863 # Number of indirect target hits. 939system.cpu1.branchPred.indirectMisses 632524 # Number of indirect misses. 940system.cpu1.branchPredindirectMispredicted 18463 # Number of mispredicted indirect branches. | 950system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage 951system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target. 952system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions. 953system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups. 954system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits. 955system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses. 956system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches. |
| 941system.cpu1.dtb.fetch_hits 0 # ITB hits 942system.cpu1.dtb.fetch_misses 0 # ITB misses 943system.cpu1.dtb.fetch_acv 0 # ITB acv 944system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 957system.cpu1.dtb.fetch_hits 0 # ITB hits 958system.cpu1.dtb.fetch_misses 0 # ITB misses 959system.cpu1.dtb.fetch_acv 0 # ITB acv 960system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 945system.cpu1.dtb.read_hits 1491854 # DTB read hits 946system.cpu1.dtb.read_misses 11707 # DTB read misses 947system.cpu1.dtb.read_acv 49 # DTB read access violations 948system.cpu1.dtb.read_accesses 336889 # DTB read accesses 949system.cpu1.dtb.write_hits 824931 # DTB write hits 950system.cpu1.dtb.write_misses 2806 # DTB write misses 951system.cpu1.dtb.write_acv 46 # DTB write access violations 952system.cpu1.dtb.write_accesses 126281 # DTB write accesses 953system.cpu1.dtb.data_hits 2316785 # DTB hits 954system.cpu1.dtb.data_misses 14513 # DTB misses 955system.cpu1.dtb.data_acv 95 # DTB access violations 956system.cpu1.dtb.data_accesses 463170 # DTB accesses 957system.cpu1.itb.fetch_hits 477856 # ITB hits 958system.cpu1.itb.fetch_misses 2662 # ITB misses 959system.cpu1.itb.fetch_acv 96 # ITB acv 960system.cpu1.itb.fetch_accesses 480518 # ITB accesses | 961system.cpu1.dtb.read_hits 2331871 # DTB read hits 962system.cpu1.dtb.read_misses 15400 # DTB read misses 963system.cpu1.dtb.read_acv 73 # DTB read access violations 964system.cpu1.dtb.read_accesses 429786 # DTB read accesses 965system.cpu1.dtb.write_hits 1381774 # DTB write hits 966system.cpu1.dtb.write_misses 3743 # DTB write misses 967system.cpu1.dtb.write_acv 71 # DTB write access violations 968system.cpu1.dtb.write_accesses 161427 # DTB write accesses 969system.cpu1.dtb.data_hits 3713645 # DTB hits 970system.cpu1.dtb.data_misses 19143 # DTB misses 971system.cpu1.dtb.data_acv 144 # DTB access violations 972system.cpu1.dtb.data_accesses 591213 # DTB accesses 973system.cpu1.itb.fetch_hits 662529 # ITB hits 974system.cpu1.itb.fetch_misses 3380 # ITB misses 975system.cpu1.itb.fetch_acv 133 # ITB acv 976system.cpu1.itb.fetch_accesses 665909 # ITB accesses |
| 961system.cpu1.itb.read_hits 0 # DTB read hits 962system.cpu1.itb.read_misses 0 # DTB read misses 963system.cpu1.itb.read_acv 0 # DTB read access violations 964system.cpu1.itb.read_accesses 0 # DTB read accesses 965system.cpu1.itb.write_hits 0 # DTB write hits 966system.cpu1.itb.write_misses 0 # DTB write misses 967system.cpu1.itb.write_acv 0 # DTB write access violations 968system.cpu1.itb.write_accesses 0 # DTB write accesses 969system.cpu1.itb.data_hits 0 # DTB hits 970system.cpu1.itb.data_misses 0 # DTB misses 971system.cpu1.itb.data_acv 0 # DTB access violations 972system.cpu1.itb.data_accesses 0 # DTB accesses | 977system.cpu1.itb.read_hits 0 # DTB read hits 978system.cpu1.itb.read_misses 0 # DTB read misses 979system.cpu1.itb.read_acv 0 # DTB read access violations 980system.cpu1.itb.read_accesses 0 # DTB read accesses 981system.cpu1.itb.write_hits 0 # DTB write hits 982system.cpu1.itb.write_misses 0 # DTB write misses 983system.cpu1.itb.write_acv 0 # DTB write access violations 984system.cpu1.itb.write_accesses 0 # DTB write accesses 985system.cpu1.itb.data_hits 0 # DTB hits 986system.cpu1.itb.data_misses 0 # DTB misses 987system.cpu1.itb.data_acv 0 # DTB access violations 988system.cpu1.itb.data_accesses 0 # DTB accesses |
| 973system.cpu1.numPwrStateTransitions 4646 # Number of power state transitions 974system.cpu1.pwrStateClkGateDist::samples 2323 # Distribution of time spent in the clock gated state 975system.cpu1.pwrStateClkGateDist::mean 818936669.177787 # Distribution of time spent in the clock gated state 976system.cpu1.pwrStateClkGateDist::stdev 339506423.560652 # Distribution of time spent in the clock gated state 977system.cpu1.pwrStateClkGateDist::1000-5e+10 2323 100.00% 100.00% # Distribution of time spent in the clock gated state | 989system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions 990system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state 991system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state 992system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state 993system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state |
| 978system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state | 994system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state |
| 979system.cpu1.pwrStateClkGateDist::max_value 975573000 # Distribution of time spent in the clock gated state 980system.cpu1.pwrStateClkGateDist::total 2323 # Distribution of time spent in the clock gated state 981system.cpu1.pwrStateResidencyTicks::ON 5282220000 # Cumulative time (in ticks) in various power states 982system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500 # Cumulative time (in ticks) in various power states 983system.cpu1.numCycles 10566764 # number of cpu cycles simulated | 995system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state 996system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state 997system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states 998system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states 999system.cpu1.numCycles 16541794 # number of cpu cycles simulated |
| 984system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 985system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1000system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1001system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 986system.cpu1.fetch.icacheStallCycles 3825216 # Number of cycles fetch is stalled on an Icache miss 987system.cpu1.fetch.Insts 10675597 # Number of instructions fetch has processed 988system.cpu1.fetch.Branches 2716012 # Number of branches that fetch encountered 989system.cpu1.fetch.predictedBranches 725621 # Number of branches that fetch has predicted taken 990system.cpu1.fetch.Cycles 5983543 # Number of cycles fetch has run and was not squashing or blocked 991system.cpu1.fetch.SquashCycles 229964 # Number of cycles fetch has spent squashing 992system.cpu1.fetch.MiscStallCycles 23815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 993system.cpu1.fetch.PendingTrapStallCycles 51735 # Number of stall cycles due to pending traps 994system.cpu1.fetch.PendingQuiesceStallCycles 41039 # Number of stall cycles due to pending quiesce instructions 995system.cpu1.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR 996system.cpu1.fetch.CacheLines 1221851 # Number of cache lines fetched 997system.cpu1.fetch.IcacheSquashes 48225 # Number of outstanding Icache misses that were squashed 998system.cpu1.fetch.rateDist::samples 10040370 # Number of instructions fetched each cycle (Total) 999system.cpu1.fetch.rateDist::mean 1.063267 # Number of instructions fetched each cycle (Total) 1000system.cpu1.fetch.rateDist::stdev 2.470833 # Number of instructions fetched each cycle (Total) | 1002system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss 1003system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed 1004system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered 1005system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken 1006system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked 1007system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing 1008system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1009system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps 1010system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions 1011system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR 1012system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched 1013system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed 1014system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total) 1015system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total) 1016system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total) |
| 1001system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1017system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1002system.cpu1.fetch.rateDist::0 8168289 81.35% 81.35% # Number of instructions fetched each cycle (Total) 1003system.cpu1.fetch.rateDist::1 102687 1.02% 82.38% # Number of instructions fetched each cycle (Total) 1004system.cpu1.fetch.rateDist::2 210133 2.09% 84.47% # Number of instructions fetched each cycle (Total) 1005system.cpu1.fetch.rateDist::3 146343 1.46% 85.93% # Number of instructions fetched each cycle (Total) 1006system.cpu1.fetch.rateDist::4 249317 2.48% 88.41% # Number of instructions fetched each cycle (Total) 1007system.cpu1.fetch.rateDist::5 97935 0.98% 89.39% # Number of instructions fetched each cycle (Total) 1008system.cpu1.fetch.rateDist::6 113554 1.13% 90.52% # Number of instructions fetched each cycle (Total) 1009system.cpu1.fetch.rateDist::7 71548 0.71% 91.23% # Number of instructions fetched each cycle (Total) 1010system.cpu1.fetch.rateDist::8 880564 8.77% 100.00% # Number of instructions fetched each cycle (Total) | 1018system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total) 1019system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total) 1020system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total) 1021system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total) 1022system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total) 1023system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total) 1024system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total) 1025system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total) 1026system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total) |
| 1011system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1012system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1013system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1027system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1028system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1029system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 1014system.cpu1.fetch.rateDist::total 10040370 # Number of instructions fetched each cycle (Total) 1015system.cpu1.fetch.branchRate 0.257033 # Number of branch fetches per cycle 1016system.cpu1.fetch.rate 1.010300 # Number of inst fetches per cycle 1017system.cpu1.decode.IdleCycles 3212898 # Number of cycles decode is idle 1018system.cpu1.decode.BlockedCycles 5233388 # Number of cycles decode is blocked 1019system.cpu1.decode.RunCycles 1306839 # Number of cycles decode is running 1020system.cpu1.decode.UnblockCycles 176592 # Number of cycles decode is unblocking 1021system.cpu1.decode.SquashCycles 110652 # Number of cycles decode is squashing 1022system.cpu1.decode.BranchResolved 87490 # Number of times decode resolved a branch 1023system.cpu1.decode.BranchMispred 4477 # Number of times decode detected a branch misprediction 1024system.cpu1.decode.DecodedInsts 8611500 # Number of instructions handled by decode 1025system.cpu1.decode.SquashedInsts 14236 # Number of squashed instructions handled by decode 1026system.cpu1.rename.SquashCycles 110652 # Number of cycles rename is squashing 1027system.cpu1.rename.IdleCycles 3332108 # Number of cycles rename is idle 1028system.cpu1.rename.BlockCycles 534859 # Number of cycles rename is blocking 1029system.cpu1.rename.serializeStallCycles 3861101 # count of cycles rename stalled for serializing inst 1030system.cpu1.rename.RunCycles 1363516 # Number of cycles rename is running 1031system.cpu1.rename.UnblockCycles 838132 # Number of cycles rename is unblocking 1032system.cpu1.rename.RenamedInsts 8128723 # Number of instructions processed by rename 1033system.cpu1.rename.ROBFullEvents 840 # Number of times rename has blocked due to ROB full 1034system.cpu1.rename.IQFullEvents 81504 # Number of times rename has blocked due to IQ full 1035system.cpu1.rename.LQFullEvents 20811 # Number of times rename has blocked due to LQ full 1036system.cpu1.rename.SQFullEvents 431912 # Number of times rename has blocked due to SQ full 1037system.cpu1.rename.RenamedOperands 5442265 # Number of destination operands rename has renamed 1038system.cpu1.rename.RenameLookups 9792683 # Number of register rename lookups that rename has made 1039system.cpu1.rename.int_rename_lookups 9760108 # Number of integer rename lookups 1040system.cpu1.rename.fp_rename_lookups 27875 # Number of floating rename lookups 1041system.cpu1.rename.CommittedMaps 4220598 # Number of HB maps that are committed 1042system.cpu1.rename.UndoneMaps 1221659 # Number of HB maps that are undone due to squashing 1043system.cpu1.rename.serializingInsts 323796 # count of serializing insts renamed 1044system.cpu1.rename.tempSerializingInsts 24055 # count of temporary serializing insts renamed 1045system.cpu1.rename.skidInsts 1462372 # count of insts added to the skid buffer 1046system.cpu1.memDep0.insertedLoads 1548375 # Number of loads inserted to the mem dependence unit. 1047system.cpu1.memDep0.insertedStores 895151 # Number of stores inserted to the mem dependence unit. 1048system.cpu1.memDep0.conflictingLoads 190303 # Number of conflicting loads. 1049system.cpu1.memDep0.conflictingStores 111620 # Number of conflicting stores. 1050system.cpu1.iq.iqInstsAdded 7151730 # Number of instructions added to the IQ (excludes non-spec) 1051system.cpu1.iq.iqNonSpecInstsAdded 356002 # Number of non-speculative instructions added to the IQ 1052system.cpu1.iq.iqInstsIssued 6823456 # Number of instructions issued 1053system.cpu1.iq.iqSquashedInstsIssued 19520 # Number of squashed instructions issued 1054system.cpu1.iq.iqSquashedInstsExamined 1627236 # Number of squashed instructions iterated over during squash; mainly for profiling 1055system.cpu1.iq.iqSquashedOperandsExamined 806919 # Number of squashed operands that are examined and possibly removed from graph 1056system.cpu1.iq.iqSquashedNonSpecRemoved 274884 # Number of squashed non-spec instructions that were removed 1057system.cpu1.iq.issued_per_cycle::samples 10040370 # Number of insts issued each cycle 1058system.cpu1.iq.issued_per_cycle::mean 0.679602 # Number of insts issued each cycle 1059system.cpu1.iq.issued_per_cycle::stdev 1.404814 # Number of insts issued each cycle | 1030system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total) 1031system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle 1032system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle 1033system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle 1034system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked 1035system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running 1036system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking 1037system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing 1038system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch 1039system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction 1040system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode 1041system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode 1042system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing 1043system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle 1044system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking 1045system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst 1046system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running 1047system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking 1048system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename 1049system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full 1050system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full 1051system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full 1052system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full 1053system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed 1054system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made 1055system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups 1056system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups 1057system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed 1058system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing 1059system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed 1060system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed 1061system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer 1062system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit. 1063system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit. 1064system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads. 1065system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores. 1066system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec) 1067system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ 1068system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued 1069system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued 1070system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling 1071system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph 1072system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed 1073system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle 1074system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle 1075system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle |
| 1060system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1076system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1061system.cpu1.iq.issued_per_cycle::0 7219551 71.91% 71.91% # Number of insts issued each cycle 1062system.cpu1.iq.issued_per_cycle::1 1226248 12.21% 84.12% # Number of insts issued each cycle 1063system.cpu1.iq.issued_per_cycle::2 523144 5.21% 89.33% # Number of insts issued each cycle 1064system.cpu1.iq.issued_per_cycle::3 383300 3.82% 93.15% # Number of insts issued each cycle 1065system.cpu1.iq.issued_per_cycle::4 329501 3.28% 96.43% # Number of insts issued each cycle 1066system.cpu1.iq.issued_per_cycle::5 173963 1.73% 98.16% # Number of insts issued each cycle 1067system.cpu1.iq.issued_per_cycle::6 102712 1.02% 99.18% # Number of insts issued each cycle 1068system.cpu1.iq.issued_per_cycle::7 58679 0.58% 99.77% # Number of insts issued each cycle 1069system.cpu1.iq.issued_per_cycle::8 23272 0.23% 100.00% # Number of insts issued each cycle | 1077system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle 1078system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle 1079system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle 1080system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle 1081system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle 1082system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle 1083system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle 1084system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle 1085system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle |
| 1070system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1071system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1072system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1086system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1087system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1088system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 1073system.cpu1.iq.issued_per_cycle::total 10040370 # Number of insts issued each cycle | 1089system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle |
| 1074system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1090system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1075system.cpu1.iq.fu_full::IntAlu 25321 11.84% 11.84% # attempts to use FU when none available 1076system.cpu1.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available 1077system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available 1078system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available 1079system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available 1080system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available 1081system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available 1082system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available 1083system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available 1084system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available 1085system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available 1086system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available 1087system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available 1088system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available 1089system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available 1090system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available 1091system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available 1092system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available 1093system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available 1094system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available 1095system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available 1096system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available 1097system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available 1098system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available 1099system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available 1100system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available 1101system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available 1102system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available 1103system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available 1104system.cpu1.iq.fu_full::MemRead 118979 55.64% 67.48% # attempts to use FU when none available 1105system.cpu1.iq.fu_full::MemWrite 69548 32.52% 100.00% # attempts to use FU when none available | 1091system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available 1092system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available 1093system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available 1094system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available 1095system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available 1096system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available 1097system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available 1098system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available 1099system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available 1100system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available 1101system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available 1102system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available 1103system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available 1104system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available 1105system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available 1106system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available 1107system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available 1108system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available 1109system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available 1110system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available 1111system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available 1112system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available 1113system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available 1114system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available 1115system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available 1116system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available 1117system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available 1118system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available 1119system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available 1120system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available 1121system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available |
| 1106system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1107system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1122system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1123system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1108system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued 1109system.cpu1.iq.FU_type_0::IntAlu 4192346 61.44% 61.50% # Type of FU issued 1110system.cpu1.iq.FU_type_0::IntMult 10770 0.16% 61.66% # Type of FU issued 1111system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.66% # Type of FU issued 1112system.cpu1.iq.FU_type_0::FloatAdd 10332 0.15% 61.81% # Type of FU issued 1113system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.81% # Type of FU issued 1114system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.81% # Type of FU issued 1115system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.81% # Type of FU issued 1116system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.84% # Type of FU issued 1117system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued 1118system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued 1119system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued 1120system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued 1121system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued 1122system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued 1123system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued 1124system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued 1125system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued 1126system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued 1127system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued 1128system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued 1129system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued 1130system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued 1131system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued 1132system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued 1133system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued 1134system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.84% # Type of FU issued 1135system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.84% # Type of FU issued 1136system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.84% # Type of FU issued 1137system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.84% # Type of FU issued 1138system.cpu1.iq.FU_type_0::MemRead 1560504 22.87% 84.71% # Type of FU issued 1139system.cpu1.iq.FU_type_0::MemWrite 845461 12.39% 97.10% # Type of FU issued 1140system.cpu1.iq.FU_type_0::IprAccess 198084 2.90% 100.00% # Type of FU issued | 1124system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued 1125system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued 1126system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued 1127system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued 1128system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued 1129system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued 1130system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued 1131system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued 1132system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued 1133system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued 1134system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued 1135system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued 1136system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued 1137system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued 1138system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued 1139system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued 1140system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued 1141system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued 1142system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued 1143system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued 1144system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued 1145system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued 1146system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued 1147system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued 1148system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued 1149system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued 1150system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued 1151system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued 1152system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued 1153system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued 1154system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued 1155system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued 1156system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued |
| 1141system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1157system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 1142system.cpu1.iq.FU_type_0::total 6823456 # Type of FU issued 1143system.cpu1.iq.rate 0.645747 # Inst issue rate 1144system.cpu1.iq.fu_busy_cnt 213848 # FU busy when requested 1145system.cpu1.iq.fu_busy_rate 0.031340 # FU busy rate (busy events/executed inst) 1146system.cpu1.iq.int_inst_queue_reads 23830038 # Number of integer instruction queue reads 1147system.cpu1.iq.int_inst_queue_writes 9093503 # Number of integer instruction queue writes 1148system.cpu1.iq.int_inst_queue_wakeup_accesses 6518367 # Number of integer instruction queue wakeup accesses 1149system.cpu1.iq.fp_inst_queue_reads 90611 # Number of floating instruction queue reads 1150system.cpu1.iq.fp_inst_queue_writes 45521 # Number of floating instruction queue writes 1151system.cpu1.iq.fp_inst_queue_wakeup_accesses 43008 # Number of floating instruction queue wakeup accesses 1152system.cpu1.iq.int_alu_accesses 6985974 # Number of integer alu accesses 1153system.cpu1.iq.fp_alu_accesses 47357 # Number of floating point alu accesses 1154system.cpu1.iew.lsq.thread0.forwLoads 77493 # Number of loads that had data forwarded from stores | 1158system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued 1159system.cpu1.iq.rate 0.664490 # Inst issue rate 1160system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested 1161system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst) 1162system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads 1163system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes 1164system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses 1165system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads 1166system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes 1167system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses 1168system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses 1169system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses 1170system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores |
| 1155system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1171system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 1156system.cpu1.iew.lsq.thread0.squashedLoads 335188 # Number of loads squashed 1157system.cpu1.iew.lsq.thread0.ignoredResponses 932 # Number of memory responses ignored because the instruction is squashed 1158system.cpu1.iew.lsq.thread0.memOrderViolation 4197 # Number of memory ordering violations 1159system.cpu1.iew.lsq.thread0.squashedStores 122462 # Number of stores squashed | 1172system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed 1173system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed 1174system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations 1175system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed |
| 1160system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1161system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1176system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1177system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 1162system.cpu1.iew.lsq.thread0.rescheduledLoads 439 # Number of loads that were rescheduled 1163system.cpu1.iew.lsq.thread0.cacheBlocked 72925 # Number of times an access to memory failed due to the cache being blocked | 1178system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled 1179system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked |
| 1164system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1180system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 1165system.cpu1.iew.iewSquashCycles 110652 # Number of cycles IEW is squashing 1166system.cpu1.iew.iewBlockCycles 347034 # Number of cycles IEW is blocking 1167system.cpu1.iew.iewUnblockCycles 152695 # Number of cycles IEW is unblocking 1168system.cpu1.iew.iewDispatchedInsts 7850434 # Number of instructions dispatched to IQ 1169system.cpu1.iew.iewDispSquashedInsts 37055 # Number of squashed instructions skipped by dispatch 1170system.cpu1.iew.iewDispLoadInsts 1548375 # Number of dispatched load instructions 1171system.cpu1.iew.iewDispStoreInsts 895151 # Number of dispatched store instructions 1172system.cpu1.iew.iewDispNonSpecInsts 329794 # Number of dispatched non-speculative instructions 1173system.cpu1.iew.iewIQFullEvents 4928 # Number of times the IQ has become full, causing a stall 1174system.cpu1.iew.iewLSQFullEvents 146829 # Number of times the LSQ has become full, causing a stall 1175system.cpu1.iew.memOrderViolationEvents 4197 # Number of memory order violations 1176system.cpu1.iew.predictedTakenIncorrect 25483 # Number of branches that were predicted taken incorrectly 1177system.cpu1.iew.predictedNotTakenIncorrect 92224 # Number of branches that were predicted not taken incorrectly 1178system.cpu1.iew.branchMispredicts 117707 # Number of branch mispredicts detected at execute 1179system.cpu1.iew.iewExecutedInsts 6707770 # Number of executed instructions 1180system.cpu1.iew.iewExecLoadInsts 1507715 # Number of load instructions executed 1181system.cpu1.iew.iewExecSquashedInsts 115685 # Number of squashed instructions skipped in execute | 1181system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing 1182system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking 1183system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking 1184system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ 1185system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch 1186system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions 1187system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions 1188system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions 1189system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall 1190system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall 1191system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations 1192system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly 1193system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly 1194system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute 1195system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions 1196system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed 1197system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute |
| 1182system.cpu1.iew.exec_swp 0 # number of swp insts executed | 1198system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 1183system.cpu1.iew.exec_nop 342702 # number of nop insts executed 1184system.cpu1.iew.exec_refs 2339108 # number of memory reference insts executed 1185system.cpu1.iew.exec_branches 982956 # Number of branches executed 1186system.cpu1.iew.exec_stores 831393 # Number of stores executed 1187system.cpu1.iew.exec_rate 0.634799 # Inst execution rate 1188system.cpu1.iew.wb_sent 6597173 # cumulative count of insts sent to commit 1189system.cpu1.iew.wb_count 6561375 # cumulative count of insts written-back 1190system.cpu1.iew.wb_producers 3197425 # num instructions producing a value 1191system.cpu1.iew.wb_consumers 4464974 # num instructions consuming a value 1192system.cpu1.iew.wb_rate 0.620945 # insts written-back per cycle 1193system.cpu1.iew.wb_fanout 0.716113 # average fanout of values written-back 1194system.cpu1.commit.commitSquashedInsts 1594434 # The number of squashed insts skipped by commit 1195system.cpu1.commit.commitNonSpecStalls 81118 # The number of times commit has been forced to stall to communicate backwards 1196system.cpu1.commit.branchMispredicts 100274 # The number of times a branch was mispredicted 1197system.cpu1.commit.committed_per_cycle::samples 9755465 # Number of insts commited each cycle 1198system.cpu1.commit.committed_per_cycle::mean 0.627758 # Number of insts commited each cycle 1199system.cpu1.commit.committed_per_cycle::stdev 1.585985 # Number of insts commited each cycle | 1199system.cpu1.iew.exec_nop 620849 # number of nop insts executed 1200system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed 1201system.cpu1.iew.exec_branches 1612675 # Number of branches executed 1202system.cpu1.iew.exec_stores 1391828 # Number of stores executed 1203system.cpu1.iew.exec_rate 0.653479 # Inst execution rate 1204system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit 1205system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back 1206system.cpu1.iew.wb_producers 5073681 # num instructions producing a value 1207system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value 1208system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle 1209system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back 1210system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit 1211system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards 1212system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted 1213system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle 1214system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle 1215system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle |
| 1200system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1216system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 1201system.cpu1.commit.committed_per_cycle::0 7484983 76.73% 76.73% # Number of insts commited each cycle 1202system.cpu1.commit.committed_per_cycle::1 1079374 11.06% 87.79% # Number of insts commited each cycle 1203system.cpu1.commit.committed_per_cycle::2 367183 3.76% 91.55% # Number of insts commited each cycle 1204system.cpu1.commit.committed_per_cycle::3 234920 2.41% 93.96% # Number of insts commited each cycle 1205system.cpu1.commit.committed_per_cycle::4 168491 1.73% 95.69% # Number of insts commited each cycle 1206system.cpu1.commit.committed_per_cycle::5 74517 0.76% 96.45% # Number of insts commited each cycle 1207system.cpu1.commit.committed_per_cycle::6 76064 0.78% 97.23% # Number of insts commited each cycle 1208system.cpu1.commit.committed_per_cycle::7 56824 0.58% 97.82% # Number of insts commited each cycle 1209system.cpu1.commit.committed_per_cycle::8 213109 2.18% 100.00% # Number of insts commited each cycle | 1217system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle 1218system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle 1219system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle 1220system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle 1221system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle 1222system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle 1223system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle 1224system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle 1225system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle |
| 1210system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1211system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1212system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1226system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1227system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1228system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 1213system.cpu1.commit.committed_per_cycle::total 9755465 # Number of insts commited each cycle 1214system.cpu1.commit.committedInsts 6124073 # Number of instructions committed 1215system.cpu1.commit.committedOps 6124073 # Number of ops (including micro ops) committed | 1229system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle 1230system.cpu1.commit.committedInsts 10006417 # Number of instructions committed 1231system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed |
| 1216system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 1232system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 1217system.cpu1.commit.refs 1985876 # Number of memory references committed 1218system.cpu1.commit.loads 1213187 # Number of loads committed 1219system.cpu1.commit.membars 22586 # Number of memory barriers committed 1220system.cpu1.commit.branches 866488 # Number of branches committed 1221system.cpu1.commit.fp_insts 41227 # Number of committed floating point instructions. 1222system.cpu1.commit.int_insts 5722327 # Number of committed integer instructions. 1223system.cpu1.commit.function_calls 95129 # Number of function calls committed. 1224system.cpu1.commit.op_class_0::No_OpClass 247554 4.04% 4.04% # Class of committed instruction 1225system.cpu1.commit.op_class_0::IntAlu 3646853 59.55% 63.59% # Class of committed instruction 1226system.cpu1.commit.op_class_0::IntMult 10597 0.17% 63.76% # Class of committed instruction 1227system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.76% # Class of committed instruction 1228system.cpu1.commit.op_class_0::FloatAdd 10326 0.17% 63.93% # Class of committed instruction 1229system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.93% # Class of committed instruction 1230system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.93% # Class of committed instruction 1231system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.93% # Class of committed instruction 1232system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.97% # Class of committed instruction 1233system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.97% # Class of committed instruction 1234system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.97% # Class of committed instruction 1235system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.97% # Class of committed instruction 1236system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.97% # Class of committed instruction 1237system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.97% # Class of committed instruction 1238system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.97% # Class of committed instruction 1239system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.97% # Class of committed instruction 1240system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.97% # Class of committed instruction 1241system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.97% # Class of committed instruction 1242system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.97% # Class of committed instruction 1243system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.97% # Class of committed instruction 1244system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.97% # Class of committed instruction 1245system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.97% # Class of committed instruction 1246system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.97% # Class of committed instruction 1247system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.97% # Class of committed instruction 1248system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.97% # Class of committed instruction 1249system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.97% # Class of committed instruction 1250system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.97% # Class of committed instruction 1251system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.97% # Class of committed instruction 1252system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.97% # Class of committed instruction 1253system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.97% # Class of committed instruction 1254system.cpu1.commit.op_class_0::MemRead 1235773 20.18% 84.14% # Class of committed instruction 1255system.cpu1.commit.op_class_0::MemWrite 772900 12.62% 96.77% # Class of committed instruction 1256system.cpu1.commit.op_class_0::IprAccess 198084 3.23% 100.00% # Class of committed instruction | 1233system.cpu1.commit.refs 3215320 # Number of memory references committed 1234system.cpu1.commit.loads 1906957 # Number of loads committed 1235system.cpu1.commit.membars 46297 # Number of memory barriers committed 1236system.cpu1.commit.branches 1432968 # Number of branches committed 1237system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions. 1238system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions. 1239system.cpu1.commit.function_calls 155642 # Number of function calls committed. 1240system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction 1241system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction 1242system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction 1243system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction 1244system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction 1245system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction 1246system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction 1247system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction 1248system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction 1249system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction 1250system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction 1251system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction 1252system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction 1253system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction 1254system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction 1255system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction 1256system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction 1257system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction 1258system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction 1259system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction 1260system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction 1261system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction 1262system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction 1263system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction 1264system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction 1265system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction 1266system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction 1267system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction 1268system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction 1269system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction 1270system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction 1271system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction 1272system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction |
| 1257system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1273system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1258system.cpu1.commit.op_class_0::total 6124073 # Class of committed instruction 1259system.cpu1.commit.bw_lim_events 213109 # number cycles where commit BW limit reached 1260system.cpu1.rob.rob_reads 17170417 # The number of ROB reads 1261system.cpu1.rob.rob_writes 15719262 # The number of ROB writes 1262system.cpu1.timesIdled 71397 # Number of times that the entire CPU went into an idle state and unscheduled itself 1263system.cpu1.idleCycles 526394 # Total number of cycles that the CPU has spent unscheduled due to idling 1264system.cpu1.quiesceCycles 3804777442 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1265system.cpu1.committedInsts 5880491 # Number of Instructions Simulated 1266system.cpu1.committedOps 5880491 # Number of Ops (including micro ops) Simulated 1267system.cpu1.cpi 1.796919 # CPI: Cycles Per Instruction 1268system.cpu1.cpi_total 1.796919 # CPI: Total CPI of All Threads 1269system.cpu1.ipc 0.556508 # IPC: Instructions Per Cycle 1270system.cpu1.ipc_total 0.556508 # IPC: Total IPC of All Threads 1271system.cpu1.int_regfile_reads 8685381 # number of integer regfile reads 1272system.cpu1.int_regfile_writes 4740732 # number of integer regfile writes 1273system.cpu1.fp_regfile_reads 27201 # number of floating regfile reads 1274system.cpu1.fp_regfile_writes 25643 # number of floating regfile writes 1275system.cpu1.misc_regfile_reads 310247 # number of misc regfile reads 1276system.cpu1.misc_regfile_writes 141917 # number of misc regfile writes 1277system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1278system.cpu1.dcache.tags.replacements 65099 # number of replacements 1279system.cpu1.dcache.tags.tagsinuse 463.722972 # Cycle average of tags in use 1280system.cpu1.dcache.tags.total_refs 1848833 # Total number of references to valid blocks. 1281system.cpu1.dcache.tags.sampled_refs 65611 # Sample count of references to valid blocks. 1282system.cpu1.dcache.tags.avg_refs 28.178705 # Average number of references to valid blocks. 1283system.cpu1.dcache.tags.warmup_cycle 1879972526500 # Cycle when the warmup percentage was hit. 1284system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.722972 # Average occupied blocks per requestor 1285system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905709 # Average percentage of cache occupancy 1286system.cpu1.dcache.tags.occ_percent::total 0.905709 # Average percentage of cache occupancy | 1274system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction 1275system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached 1276system.cpu1.rob.rob_reads 27350454 # The number of ROB reads 1277system.cpu1.rob.rob_writes 25410376 # The number of ROB writes 1278system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself 1279system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling 1280system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1281system.cpu1.committedInsts 9543281 # Number of Instructions Simulated 1282system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated 1283system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction 1284system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads 1285system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle 1286system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads 1287system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads 1288system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes 1289system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads 1290system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes 1291system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads 1292system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes 1293system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1294system.cpu1.dcache.tags.replacements 125899 # number of replacements 1295system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use 1296system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks. 1297system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks. 1298system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks. 1299system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit. 1300system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor 1301system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy 1302system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy |
| 1287system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1303system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1288system.cpu1.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id | 1304system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id |
| 1289system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id | 1305system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id |
| 1290system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id | 1306system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id |
| 1291system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1307system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1292system.cpu1.dcache.tags.tag_accesses 8556411 # Number of tag accesses 1293system.cpu1.dcache.tags.data_accesses 8556411 # Number of data accesses 1294system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1295system.cpu1.dcache.ReadReq_hits::cpu1.data 1222356 # number of ReadReq hits 1296system.cpu1.dcache.ReadReq_hits::total 1222356 # number of ReadReq hits 1297system.cpu1.dcache.WriteReq_hits::cpu1.data 588321 # number of WriteReq hits 1298system.cpu1.dcache.WriteReq_hits::total 588321 # number of WriteReq hits 1299system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 17437 # number of LoadLockedReq hits 1300system.cpu1.dcache.LoadLockedReq_hits::total 17437 # number of LoadLockedReq hits 1301system.cpu1.dcache.StoreCondReq_hits::cpu1.data 16296 # number of StoreCondReq hits 1302system.cpu1.dcache.StoreCondReq_hits::total 16296 # number of StoreCondReq hits 1303system.cpu1.dcache.demand_hits::cpu1.data 1810677 # number of demand (read+write) hits 1304system.cpu1.dcache.demand_hits::total 1810677 # number of demand (read+write) hits 1305system.cpu1.dcache.overall_hits::cpu1.data 1810677 # number of overall hits 1306system.cpu1.dcache.overall_hits::total 1810677 # number of overall hits 1307system.cpu1.dcache.ReadReq_misses::cpu1.data 112363 # number of ReadReq misses 1308system.cpu1.dcache.ReadReq_misses::total 112363 # number of ReadReq misses 1309system.cpu1.dcache.WriteReq_misses::cpu1.data 161965 # number of WriteReq misses 1310system.cpu1.dcache.WriteReq_misses::total 161965 # number of WriteReq misses 1311system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses 1312system.cpu1.dcache.LoadLockedReq_misses::total 1793 # number of LoadLockedReq misses 1313system.cpu1.dcache.StoreCondReq_misses::cpu1.data 891 # number of StoreCondReq misses 1314system.cpu1.dcache.StoreCondReq_misses::total 891 # number of StoreCondReq misses 1315system.cpu1.dcache.demand_misses::cpu1.data 274328 # number of demand (read+write) misses 1316system.cpu1.dcache.demand_misses::total 274328 # number of demand (read+write) misses 1317system.cpu1.dcache.overall_misses::cpu1.data 274328 # number of overall misses 1318system.cpu1.dcache.overall_misses::total 274328 # number of overall misses 1319system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1482127500 # number of ReadReq miss cycles 1320system.cpu1.dcache.ReadReq_miss_latency::total 1482127500 # number of ReadReq miss cycles 1321system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7331574147 # number of WriteReq miss cycles 1322system.cpu1.dcache.WriteReq_miss_latency::total 7331574147 # number of WriteReq miss cycles 1323system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19537500 # number of LoadLockedReq miss cycles 1324system.cpu1.dcache.LoadLockedReq_miss_latency::total 19537500 # number of LoadLockedReq miss cycles 1325system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6718500 # number of StoreCondReq miss cycles 1326system.cpu1.dcache.StoreCondReq_miss_latency::total 6718500 # number of StoreCondReq miss cycles 1327system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles 1328system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles 1329system.cpu1.dcache.demand_miss_latency::cpu1.data 8813701647 # number of demand (read+write) miss cycles 1330system.cpu1.dcache.demand_miss_latency::total 8813701647 # number of demand (read+write) miss cycles 1331system.cpu1.dcache.overall_miss_latency::cpu1.data 8813701647 # number of overall miss cycles 1332system.cpu1.dcache.overall_miss_latency::total 8813701647 # number of overall miss cycles 1333system.cpu1.dcache.ReadReq_accesses::cpu1.data 1334719 # number of ReadReq accesses(hits+misses) 1334system.cpu1.dcache.ReadReq_accesses::total 1334719 # number of ReadReq accesses(hits+misses) 1335system.cpu1.dcache.WriteReq_accesses::cpu1.data 750286 # number of WriteReq accesses(hits+misses) 1336system.cpu1.dcache.WriteReq_accesses::total 750286 # number of WriteReq accesses(hits+misses) 1337system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 19230 # number of LoadLockedReq accesses(hits+misses) 1338system.cpu1.dcache.LoadLockedReq_accesses::total 19230 # number of LoadLockedReq accesses(hits+misses) 1339system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 17187 # number of StoreCondReq accesses(hits+misses) 1340system.cpu1.dcache.StoreCondReq_accesses::total 17187 # number of StoreCondReq accesses(hits+misses) 1341system.cpu1.dcache.demand_accesses::cpu1.data 2085005 # number of demand (read+write) accesses 1342system.cpu1.dcache.demand_accesses::total 2085005 # number of demand (read+write) accesses 1343system.cpu1.dcache.overall_accesses::cpu1.data 2085005 # number of overall (read+write) accesses 1344system.cpu1.dcache.overall_accesses::total 2085005 # number of overall (read+write) accesses 1345system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.084185 # miss rate for ReadReq accesses 1346system.cpu1.dcache.ReadReq_miss_rate::total 0.084185 # miss rate for ReadReq accesses 1347system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.215871 # miss rate for WriteReq accesses 1348system.cpu1.dcache.WriteReq_miss_rate::total 0.215871 # miss rate for WriteReq accesses 1349system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093240 # miss rate for LoadLockedReq accesses 1350system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093240 # miss rate for LoadLockedReq accesses 1351system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.051842 # miss rate for StoreCondReq accesses 1352system.cpu1.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses 1353system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131572 # miss rate for demand accesses 1354system.cpu1.dcache.demand_miss_rate::total 0.131572 # miss rate for demand accesses 1355system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131572 # miss rate for overall accesses 1356system.cpu1.dcache.overall_miss_rate::total 0.131572 # miss rate for overall accesses 1357system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801 # average ReadReq miss latency 1358system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801 # average ReadReq miss latency 1359system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317 # average WriteReq miss latency 1360system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317 # average WriteReq miss latency 1361system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108 # average LoadLockedReq miss latency 1362system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108 # average LoadLockedReq miss latency 1363system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7540.404040 # average StoreCondReq miss latency 1364system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7540.404040 # average StoreCondReq miss latency 1365system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1366system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1367system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency 1368system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137 # average overall miss latency 1369system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency 1370system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137 # average overall miss latency 1371system.cpu1.dcache.blocked_cycles::no_mshrs 454264 # number of cycles access was blocked 1372system.cpu1.dcache.blocked_cycles::no_targets 482 # number of cycles access was blocked 1373system.cpu1.dcache.blocked::no_mshrs 15527 # number of cycles access was blocked 1374system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked 1375system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.256392 # average number of cycles each access was blocked 1376system.cpu1.dcache.avg_blocked_cycles::no_targets 48.200000 # average number of cycles each access was blocked 1377system.cpu1.dcache.writebacks::writebacks 38456 # number of writebacks 1378system.cpu1.dcache.writebacks::total 38456 # number of writebacks 1379system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66033 # number of ReadReq MSHR hits 1380system.cpu1.dcache.ReadReq_mshr_hits::total 66033 # number of ReadReq MSHR hits 1381system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137281 # number of WriteReq MSHR hits 1382system.cpu1.dcache.WriteReq_mshr_hits::total 137281 # number of WriteReq MSHR hits 1383system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 379 # number of LoadLockedReq MSHR hits 1384system.cpu1.dcache.LoadLockedReq_mshr_hits::total 379 # number of LoadLockedReq MSHR hits 1385system.cpu1.dcache.demand_mshr_hits::cpu1.data 203314 # number of demand (read+write) MSHR hits 1386system.cpu1.dcache.demand_mshr_hits::total 203314 # number of demand (read+write) MSHR hits 1387system.cpu1.dcache.overall_mshr_hits::cpu1.data 203314 # number of overall MSHR hits 1388system.cpu1.dcache.overall_mshr_hits::total 203314 # number of overall MSHR hits 1389system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 46330 # number of ReadReq MSHR misses 1390system.cpu1.dcache.ReadReq_mshr_misses::total 46330 # number of ReadReq MSHR misses 1391system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24684 # number of WriteReq MSHR misses 1392system.cpu1.dcache.WriteReq_mshr_misses::total 24684 # number of WriteReq MSHR misses 1393system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1414 # number of LoadLockedReq MSHR misses 1394system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1414 # number of LoadLockedReq MSHR misses 1395system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 891 # number of StoreCondReq MSHR misses 1396system.cpu1.dcache.StoreCondReq_mshr_misses::total 891 # number of StoreCondReq MSHR misses 1397system.cpu1.dcache.demand_mshr_misses::cpu1.data 71014 # number of demand (read+write) MSHR misses 1398system.cpu1.dcache.demand_mshr_misses::total 71014 # number of demand (read+write) MSHR misses 1399system.cpu1.dcache.overall_mshr_misses::cpu1.data 71014 # number of overall MSHR misses 1400system.cpu1.dcache.overall_mshr_misses::total 71014 # number of overall MSHR misses 1401system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable 1402system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable 1403system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable 1404system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2639 # number of WriteReq MSHR uncacheable 1405system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses 1406system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2801 # number of overall MSHR uncacheable misses 1407system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 590183000 # number of ReadReq MSHR miss cycles 1408system.cpu1.dcache.ReadReq_mshr_miss_latency::total 590183000 # number of ReadReq MSHR miss cycles 1409system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153615997 # number of WriteReq MSHR miss cycles 1410system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153615997 # number of WriteReq MSHR miss cycles 1411system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13566500 # number of LoadLockedReq MSHR miss cycles 1412system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13566500 # number of LoadLockedReq MSHR miss cycles 1413system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5828500 # number of StoreCondReq MSHR miss cycles 1414system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5828500 # number of StoreCondReq MSHR miss cycles 1415system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles 1416system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles 1417system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1743798997 # number of demand (read+write) MSHR miss cycles 1418system.cpu1.dcache.demand_mshr_miss_latency::total 1743798997 # number of demand (read+write) MSHR miss cycles 1419system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1743798997 # number of overall MSHR miss cycles 1420system.cpu1.dcache.overall_mshr_miss_latency::total 1743798997 # number of overall MSHR miss cycles 1421system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32350500 # number of ReadReq MSHR uncacheable cycles 1422system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32350500 # number of ReadReq MSHR uncacheable cycles 1423system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32350500 # number of overall MSHR uncacheable cycles 1424system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32350500 # number of overall MSHR uncacheable cycles 1425system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034711 # mshr miss rate for ReadReq accesses 1426system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034711 # mshr miss rate for ReadReq accesses 1427system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032899 # mshr miss rate for WriteReq accesses 1428system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032899 # mshr miss rate for WriteReq accesses 1429system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073531 # mshr miss rate for LoadLockedReq accesses 1430system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073531 # mshr miss rate for LoadLockedReq accesses 1431system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.051842 # mshr miss rate for StoreCondReq accesses 1432system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses 1433system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for demand accesses 1434system.cpu1.dcache.demand_mshr_miss_rate::total 0.034059 # mshr miss rate for demand accesses 1435system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for overall accesses 1436system.cpu1.dcache.overall_mshr_miss_rate::total 0.034059 # mshr miss rate for overall accesses 1437system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042 # average ReadReq mshr miss latency 1438system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042 # average ReadReq mshr miss latency 1439system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020 # average WriteReq mshr miss latency 1440system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020 # average WriteReq mshr miss latency 1441system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9594.413013 # average LoadLockedReq mshr miss latency 1442system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9594.413013 # average LoadLockedReq mshr miss latency 1443system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6541.526375 # average StoreCondReq mshr miss latency 1444system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6541.526375 # average StoreCondReq mshr miss latency 1445system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1446system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1447system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency 1448system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency 1449system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency 1450system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency 1451system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444 # average ReadReq mshr uncacheable latency 1452system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444 # average ReadReq mshr uncacheable latency 1453system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134 # average overall mshr uncacheable latency 1454system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134 # average overall mshr uncacheable latency 1455system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1456system.cpu1.icache.tags.replacements 129926 # number of replacements 1457system.cpu1.icache.tags.tagsinuse 466.448190 # Cycle average of tags in use 1458system.cpu1.icache.tags.total_refs 1084325 # Total number of references to valid blocks. 1459system.cpu1.icache.tags.sampled_refs 130435 # Sample count of references to valid blocks. 1460system.cpu1.icache.tags.avg_refs 8.313144 # Average number of references to valid blocks. 1461system.cpu1.icache.tags.warmup_cycle 1880575078500 # Cycle when the warmup percentage was hit. 1462system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.448190 # Average occupied blocks per requestor 1463system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911032 # Average percentage of cache occupancy 1464system.cpu1.icache.tags.occ_percent::total 0.911032 # Average percentage of cache occupancy | 1308system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses 1309system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses 1310system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1311system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits 1312system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits 1313system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits 1314system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits 1315system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits 1316system.cpu1.dcache.LoadLockedReq_hits::total 38120 # number of LoadLockedReq hits 1317system.cpu1.dcache.StoreCondReq_hits::cpu1.data 34857 # number of StoreCondReq hits 1318system.cpu1.dcache.StoreCondReq_hits::total 34857 # number of StoreCondReq hits 1319system.cpu1.dcache.demand_hits::cpu1.data 2847575 # number of demand (read+write) hits 1320system.cpu1.dcache.demand_hits::total 2847575 # number of demand (read+write) hits 1321system.cpu1.dcache.overall_hits::cpu1.data 2847575 # number of overall hits 1322system.cpu1.dcache.overall_hits::total 2847575 # number of overall hits 1323system.cpu1.dcache.ReadReq_misses::cpu1.data 231819 # number of ReadReq misses 1324system.cpu1.dcache.ReadReq_misses::total 231819 # number of ReadReq misses 1325system.cpu1.dcache.WriteReq_misses::cpu1.data 282423 # number of WriteReq misses 1326system.cpu1.dcache.WriteReq_misses::total 282423 # number of WriteReq misses 1327system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5078 # number of LoadLockedReq misses 1328system.cpu1.dcache.LoadLockedReq_misses::total 5078 # number of LoadLockedReq misses 1329system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2912 # number of StoreCondReq misses 1330system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses 1331system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses 1332system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses 1333system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses 1334system.cpu1.dcache.overall_misses::total 514242 # number of overall misses 1335system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles 1336system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles 1337system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles 1338system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles 1339system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles 1340system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles 1341system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles 1342system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles 1343system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles 1344system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles 1345system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles 1346system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles 1347system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses) 1348system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses) 1349system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses) 1350system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses) 1351system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses) 1352system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses) 1353system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses) 1354system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses) 1355system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses 1356system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses 1357system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses 1358system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses 1359system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses 1360system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses 1361system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses 1362system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses 1363system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses 1364system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses 1365system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses 1366system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses 1367system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses 1368system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses 1369system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses 1370system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses 1371system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency 1372system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency 1373system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency 1374system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency 1375system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency 1376system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency 1377system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency 1378system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency 1379system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency 1380system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency 1381system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency 1382system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency 1383system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked 1384system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked 1385system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked 1386system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked 1387system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked 1388system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked 1389system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks 1390system.cpu1.dcache.writebacks::total 81179 # number of writebacks 1391system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits 1392system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits 1393system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits 1394system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits 1395system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits 1396system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits 1397system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits 1398system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits 1399system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits 1400system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits 1401system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses 1402system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses 1403system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses 1404system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses 1405system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses 1406system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses 1407system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses 1408system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses 1409system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses 1410system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses 1411system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses 1412system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses 1413system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable 1414system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable 1415system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable 1416system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable 1417system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses 1418system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses 1419system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles 1420system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles 1421system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles 1422system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles 1423system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles 1424system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles 1425system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles 1426system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles 1427system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles 1428system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles 1429system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles 1430system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles 1431system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles 1432system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles 1433system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles 1434system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles 1435system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses 1436system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses 1437system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses 1438system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses 1439system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses 1440system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses 1441system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses 1442system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses 1443system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses 1444system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses 1445system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses 1446system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses 1447system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency 1448system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency 1449system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency 1450system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency 1451system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency 1452system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency 1453system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency 1454system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency 1455system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency 1456system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency 1457system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency 1458system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency 1459system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency 1460system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency 1461system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency 1462system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency 1463system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1464system.cpu1.icache.tags.replacements 243897 # number of replacements 1465system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use 1466system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks. 1467system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks. 1468system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks. 1469system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit. 1470system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor 1471system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy 1472system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy |
| 1465system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id | 1473system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id |
| 1466system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id | 1474system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id |
| 1467system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id | 1475system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id |
| 1468system.cpu1.icache.tags.age_task_id_blocks_1024::2 419 # Occupied blocks per task id | 1476system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id |
| 1469system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id | 1477system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id |
| 1470system.cpu1.icache.tags.tag_accesses 1352346 # Number of tag accesses 1471system.cpu1.icache.tags.data_accesses 1352346 # Number of data accesses 1472system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1473system.cpu1.icache.ReadReq_hits::cpu1.inst 1084325 # number of ReadReq hits 1474system.cpu1.icache.ReadReq_hits::total 1084325 # number of ReadReq hits 1475system.cpu1.icache.demand_hits::cpu1.inst 1084325 # number of demand (read+write) hits 1476system.cpu1.icache.demand_hits::total 1084325 # number of demand (read+write) hits 1477system.cpu1.icache.overall_hits::cpu1.inst 1084325 # number of overall hits 1478system.cpu1.icache.overall_hits::total 1084325 # number of overall hits 1479system.cpu1.icache.ReadReq_misses::cpu1.inst 137526 # number of ReadReq misses 1480system.cpu1.icache.ReadReq_misses::total 137526 # number of ReadReq misses 1481system.cpu1.icache.demand_misses::cpu1.inst 137526 # number of demand (read+write) misses 1482system.cpu1.icache.demand_misses::total 137526 # number of demand (read+write) misses 1483system.cpu1.icache.overall_misses::cpu1.inst 137526 # number of overall misses 1484system.cpu1.icache.overall_misses::total 137526 # number of overall misses 1485system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1969078999 # number of ReadReq miss cycles 1486system.cpu1.icache.ReadReq_miss_latency::total 1969078999 # number of ReadReq miss cycles 1487system.cpu1.icache.demand_miss_latency::cpu1.inst 1969078999 # number of demand (read+write) miss cycles 1488system.cpu1.icache.demand_miss_latency::total 1969078999 # number of demand (read+write) miss cycles 1489system.cpu1.icache.overall_miss_latency::cpu1.inst 1969078999 # number of overall miss cycles 1490system.cpu1.icache.overall_miss_latency::total 1969078999 # number of overall miss cycles 1491system.cpu1.icache.ReadReq_accesses::cpu1.inst 1221851 # number of ReadReq accesses(hits+misses) 1492system.cpu1.icache.ReadReq_accesses::total 1221851 # number of ReadReq accesses(hits+misses) 1493system.cpu1.icache.demand_accesses::cpu1.inst 1221851 # number of demand (read+write) accesses 1494system.cpu1.icache.demand_accesses::total 1221851 # number of demand (read+write) accesses 1495system.cpu1.icache.overall_accesses::cpu1.inst 1221851 # number of overall (read+write) accesses 1496system.cpu1.icache.overall_accesses::total 1221851 # number of overall (read+write) accesses 1497system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112555 # miss rate for ReadReq accesses 1498system.cpu1.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses 1499system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112555 # miss rate for demand accesses 1500system.cpu1.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses 1501system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112555 # miss rate for overall accesses 1502system.cpu1.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses 1503system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160 # average ReadReq miss latency 1504system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160 # average ReadReq miss latency 1505system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency 1506system.cpu1.icache.demand_avg_miss_latency::total 14317.867160 # average overall miss latency 1507system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency 1508system.cpu1.icache.overall_avg_miss_latency::total 14317.867160 # average overall miss latency 1509system.cpu1.icache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked | 1478system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses 1479system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses 1480system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1481system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits 1482system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits 1483system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits 1484system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits 1485system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits 1486system.cpu1.icache.overall_hits::total 1645008 # number of overall hits 1487system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses 1488system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses 1489system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses 1490system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses 1491system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses 1492system.cpu1.icache.overall_misses::total 255921 # number of overall misses 1493system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles 1494system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles 1495system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles 1496system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles 1497system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles 1498system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles 1499system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses) 1500system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses) 1501system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses 1502system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses 1503system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses 1504system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses 1505system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses 1506system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses 1507system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses 1508system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses 1509system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses 1510system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses 1511system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency 1512system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency 1513system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency 1514system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency 1515system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency 1516system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency 1517system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked |
| 1510system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1518system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1511system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked | 1519system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked |
| 1512system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 1520system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1513system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.400000 # average number of cycles each access was blocked | 1521system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked |
| 1514system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1522system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1515system.cpu1.icache.writebacks::writebacks 129926 # number of writebacks 1516system.cpu1.icache.writebacks::total 129926 # number of writebacks 1517system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7031 # number of ReadReq MSHR hits 1518system.cpu1.icache.ReadReq_mshr_hits::total 7031 # number of ReadReq MSHR hits 1519system.cpu1.icache.demand_mshr_hits::cpu1.inst 7031 # number of demand (read+write) MSHR hits 1520system.cpu1.icache.demand_mshr_hits::total 7031 # number of demand (read+write) MSHR hits 1521system.cpu1.icache.overall_mshr_hits::cpu1.inst 7031 # number of overall MSHR hits 1522system.cpu1.icache.overall_mshr_hits::total 7031 # number of overall MSHR hits 1523system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 130495 # number of ReadReq MSHR misses 1524system.cpu1.icache.ReadReq_mshr_misses::total 130495 # number of ReadReq MSHR misses 1525system.cpu1.icache.demand_mshr_misses::cpu1.inst 130495 # number of demand (read+write) MSHR misses 1526system.cpu1.icache.demand_mshr_misses::total 130495 # number of demand (read+write) MSHR misses 1527system.cpu1.icache.overall_mshr_misses::cpu1.inst 130495 # number of overall MSHR misses 1528system.cpu1.icache.overall_mshr_misses::total 130495 # number of overall MSHR misses 1529system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1753458499 # number of ReadReq MSHR miss cycles 1530system.cpu1.icache.ReadReq_mshr_miss_latency::total 1753458499 # number of ReadReq MSHR miss cycles 1531system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1753458499 # number of demand (read+write) MSHR miss cycles 1532system.cpu1.icache.demand_mshr_miss_latency::total 1753458499 # number of demand (read+write) MSHR miss cycles 1533system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1753458499 # number of overall MSHR miss cycles 1534system.cpu1.icache.overall_mshr_miss_latency::total 1753458499 # number of overall MSHR miss cycles 1535system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for ReadReq accesses 1536system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106801 # mshr miss rate for ReadReq accesses 1537system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for demand accesses 1538system.cpu1.icache.demand_mshr_miss_rate::total 0.106801 # mshr miss rate for demand accesses 1539system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for overall accesses 1540system.cpu1.icache.overall_mshr_miss_rate::total 0.106801 # mshr miss rate for overall accesses 1541system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average ReadReq mshr miss latency 1542system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421 # average ReadReq mshr miss latency 1543system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency 1544system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency 1545system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency 1546system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency | 1523system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks 1524system.cpu1.icache.writebacks::total 243897 # number of writebacks 1525system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits 1526system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits 1527system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits 1528system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits 1529system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits 1530system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits 1531system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses 1532system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses 1533system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses 1534system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses 1535system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses 1536system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses 1537system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles 1538system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles 1539system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles 1540system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles 1541system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles 1542system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles 1543system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses 1544system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses 1545system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses 1546system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses 1547system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses 1548system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses 1549system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency 1550system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency 1551system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency 1552system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency 1553system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency 1554system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency |
| 1547system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1548system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1549system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1550system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1551system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1552system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1553system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1554system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1555system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1556system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1557system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1558system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 1555system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1556system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1557system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1558system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1559system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1560system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1561system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1562system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1563system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1564system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1565system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1566system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 1559system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1560system.iobus.trans_dist::ReadReq 7367 # Transaction distribution 1561system.iobus.trans_dist::ReadResp 7367 # Transaction distribution 1562system.iobus.trans_dist::WriteReq 53946 # Transaction distribution 1563system.iobus.trans_dist::WriteResp 53946 # Transaction distribution 1564system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10580 # Packet count per connected master and slave (bytes) 1565system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) | 1567system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1568system.iobus.trans_dist::ReadReq 7374 # Transaction distribution 1569system.iobus.trans_dist::ReadResp 7374 # Transaction distribution 1570system.iobus.trans_dist::WriteReq 54571 # Transaction distribution 1571system.iobus.trans_dist::WriteResp 54571 # Transaction distribution 1572system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes) 1573system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) |
| 1566system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1567system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1568system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1569system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1570system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1571system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1572system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) | 1574system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1575system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1576system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1577system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1578system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1579system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1580system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| 1573system.iobus.pkt_count_system.bridge.master::total 39176 # Packet count per connected master and slave (bytes) 1574system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1575system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 1576system.iobus.pkt_count::total 122626 # Packet count per connected master and slave (bytes) 1577system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42320 # Cumulative packet size per connected master and slave (bytes) 1578system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) | 1581system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes) 1582system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) 1583system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) 1584system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes) 1585system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes) 1586system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) |
| 1579system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1580system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1581system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1582system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1583system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1584system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1585system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) | 1587system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1588system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1589system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1590system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1591system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1592system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1593system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| 1586system.iobus.pkt_size_system.bridge.master::total 68530 # Cumulative packet size per connected master and slave (bytes) 1587system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1588system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1589system.iobus.pkt_size::total 2730138 # Cumulative packet size per connected master and slave (bytes) 1590system.iobus.reqLayer0.occupancy 10859000 # Layer occupancy (ticks) | 1594system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes) 1595system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) 1596system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) 1597system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes) 1598system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks) |
| 1591system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1599system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1592system.iobus.reqLayer1.occupancy 821000 # Layer occupancy (ticks) | 1600system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) |
| 1593system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1594system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1595system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1601system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1602system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1603system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1596system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) | 1604system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) |
| 1597system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 1605system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 1598system.iobus.reqLayer22.occupancy 178000 # Layer occupancy (ticks) | 1606system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) |
| 1599system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1607system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1600system.iobus.reqLayer23.occupancy 14076000 # Layer occupancy (ticks) | 1608system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks) |
| 1601system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1602system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1603system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1609system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1610system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1611system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1604system.iobus.reqLayer25.occupancy 6060001 # Layer occupancy (ticks) | 1612system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks) |
| 1605system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1606system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1607system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1613system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1614system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1615system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1608system.iobus.reqLayer27.occupancy 216164058 # Layer occupancy (ticks) | 1616system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks) |
| 1609system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) | 1617system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1610system.iobus.respLayer0.occupancy 26782000 # Layer occupancy (ticks) | 1618system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks) |
| 1611system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1619system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1612system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) | 1620system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) |
| 1613system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1621system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1614system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1615system.iocache.tags.replacements 41693 # number of replacements 1616system.iocache.tags.tagsinuse 0.508375 # Cycle average of tags in use | 1622system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1623system.iocache.tags.replacements 41699 # number of replacements 1624system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use |
| 1617system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1625system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1618system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. | 1626system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. |
| 1619system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1627system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1620system.iocache.tags.warmup_cycle 1712300354000 # Cycle when the warmup percentage was hit. 1621system.iocache.tags.occ_blocks::tsunami.ide 0.508375 # Average occupied blocks per requestor 1622system.iocache.tags.occ_percent::tsunami.ide 0.031773 # Average percentage of cache occupancy 1623system.iocache.tags.occ_percent::total 0.031773 # Average percentage of cache occupancy | 1628system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit. 1629system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor 1630system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy 1631system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy |
| 1624system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id | 1632system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |
| 1625system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id | 1633system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id |
| 1626system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1634system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1627system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1628system.iocache.tags.data_accesses 375525 # Number of data accesses 1629system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1630system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1631system.iocache.ReadReq_misses::total 173 # number of ReadReq misses | 1635system.iocache.tags.tag_accesses 375579 # Number of tag accesses 1636system.iocache.tags.data_accesses 375579 # Number of data accesses 1637system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1638system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses 1639system.iocache.ReadReq_misses::total 179 # number of ReadReq misses |
| 1632system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1633system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses | 1640system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1641system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| 1634system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1635system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1636system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1637system.iocache.overall_misses::total 41725 # number of overall misses 1638system.iocache.ReadReq_miss_latency::tsunami.ide 21862383 # number of ReadReq miss cycles 1639system.iocache.ReadReq_miss_latency::total 21862383 # number of ReadReq miss cycles 1640system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858655675 # number of WriteLineReq miss cycles 1641system.iocache.WriteLineReq_miss_latency::total 4858655675 # number of WriteLineReq miss cycles 1642system.iocache.demand_miss_latency::tsunami.ide 4880518058 # number of demand (read+write) miss cycles 1643system.iocache.demand_miss_latency::total 4880518058 # number of demand (read+write) miss cycles 1644system.iocache.overall_miss_latency::tsunami.ide 4880518058 # number of overall miss cycles 1645system.iocache.overall_miss_latency::total 4880518058 # number of overall miss cycles 1646system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1647system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) | 1642system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses 1643system.iocache.demand_misses::total 41731 # number of demand (read+write) misses 1644system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses 1645system.iocache.overall_misses::total 41731 # number of overall misses 1646system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles 1647system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles 1648system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles 1649system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles 1650system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles 1651system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles 1652system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles 1653system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles 1654system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) 1655system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) |
| 1648system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1649system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) | 1656system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1657system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| 1650system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1651system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1652system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1653system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses | 1658system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses 1659system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses 1660system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses 1661system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses |
| 1654system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1655system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1656system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1657system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1658system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1659system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1660system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1661system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1662system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1663system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1664system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1665system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1666system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1667system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1668system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1669system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1662system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069 # average ReadReq miss latency 1663system.iocache.ReadReq_avg_miss_latency::total 126372.156069 # average ReadReq miss latency 1664system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256 # average WriteLineReq miss latency 1665system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256 # average WriteLineReq miss latency 1666system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency 1667system.iocache.demand_avg_miss_latency::total 116968.677244 # average overall miss latency 1668system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency 1669system.iocache.overall_avg_miss_latency::total 116968.677244 # average overall miss latency 1670system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1670system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency 1671system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency 1672system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency 1673system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency 1674system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency 1675system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency 1676system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency 1677system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency 1678system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked |
| 1671system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1679system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1672system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1680system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 1673system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1681system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1674system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1682system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked |
| 1675system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1676system.iocache.writebacks::writebacks 41520 # number of writebacks 1677system.iocache.writebacks::total 41520 # number of writebacks | 1683system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1684system.iocache.writebacks::writebacks 41520 # number of writebacks 1685system.iocache.writebacks::total 41520 # number of writebacks |
| 1678system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1679system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses | 1686system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses 1687system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses |
| 1680system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1681system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses | 1688system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1689system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| 1682system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1683system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1684system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1685system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1686system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13212383 # number of ReadReq MSHR miss cycles 1687system.iocache.ReadReq_mshr_miss_latency::total 13212383 # number of ReadReq MSHR miss cycles 1688system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778666661 # number of WriteLineReq MSHR miss cycles 1689system.iocache.WriteLineReq_mshr_miss_latency::total 2778666661 # number of WriteLineReq MSHR miss cycles 1690system.iocache.demand_mshr_miss_latency::tsunami.ide 2791879044 # number of demand (read+write) MSHR miss cycles 1691system.iocache.demand_mshr_miss_latency::total 2791879044 # number of demand (read+write) MSHR miss cycles 1692system.iocache.overall_mshr_miss_latency::tsunami.ide 2791879044 # number of overall MSHR miss cycles 1693system.iocache.overall_mshr_miss_latency::total 2791879044 # number of overall MSHR miss cycles | 1690system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses 1691system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses 1692system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses 1693system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses 1694system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13612883 # number of ReadReq MSHR miss cycles 1695system.iocache.ReadReq_mshr_miss_latency::total 13612883 # number of ReadReq MSHR miss cycles 1696system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778734565 # number of WriteLineReq MSHR miss cycles 1697system.iocache.WriteLineReq_mshr_miss_latency::total 2778734565 # number of WriteLineReq MSHR miss cycles 1698system.iocache.demand_mshr_miss_latency::tsunami.ide 2792347448 # number of demand (read+write) MSHR miss cycles 1699system.iocache.demand_mshr_miss_latency::total 2792347448 # number of demand (read+write) MSHR miss cycles 1700system.iocache.overall_mshr_miss_latency::tsunami.ide 2792347448 # number of overall MSHR miss cycles 1701system.iocache.overall_mshr_miss_latency::total 2792347448 # number of overall MSHR miss cycles |
| 1694system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1695system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1696system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1697system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1698system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1699system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1700system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1701system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1702system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1703system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1704system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1705system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1706system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1707system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1708system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1709system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1702system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069 # average ReadReq mshr miss latency 1703system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069 # average ReadReq mshr miss latency 1704system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695 # average WriteLineReq mshr miss latency 1705system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695 # average WriteLineReq mshr miss latency 1706system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66911.421067 # average overall mshr miss latency 1707system.iocache.demand_avg_mshr_miss_latency::total 66911.421067 # average overall mshr miss latency 1708system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66911.421067 # average overall mshr miss latency 1709system.iocache.overall_avg_mshr_miss_latency::total 66911.421067 # average overall mshr miss latency 1710system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1711system.l2c.tags.replacements 344445 # number of replacements 1712system.l2c.tags.tagsinuse 65257.633522 # Cycle average of tags in use 1713system.l2c.tags.total_refs 4040340 # Total number of references to valid blocks. 1714system.l2c.tags.sampled_refs 409472 # Sample count of references to valid blocks. 1715system.l2c.tags.avg_refs 9.867195 # Average number of references to valid blocks. 1716system.l2c.tags.warmup_cycle 7589084000 # Cycle when the warmup percentage was hit. 1717system.l2c.tags.occ_blocks::writebacks 53236.660660 # Average occupied blocks per requestor 1718system.l2c.tags.occ_blocks::cpu0.inst 5305.017555 # Average occupied blocks per requestor 1719system.l2c.tags.occ_blocks::cpu0.data 6468.149046 # Average occupied blocks per requestor 1720system.l2c.tags.occ_blocks::cpu1.inst 210.708528 # Average occupied blocks per requestor 1721system.l2c.tags.occ_blocks::cpu1.data 37.097733 # Average occupied blocks per requestor 1722system.l2c.tags.occ_percent::writebacks 0.812327 # Average percentage of cache occupancy 1723system.l2c.tags.occ_percent::cpu0.inst 0.080948 # Average percentage of cache occupancy 1724system.l2c.tags.occ_percent::cpu0.data 0.098696 # Average percentage of cache occupancy 1725system.l2c.tags.occ_percent::cpu1.inst 0.003215 # Average percentage of cache occupancy 1726system.l2c.tags.occ_percent::cpu1.data 0.000566 # Average percentage of cache occupancy 1727system.l2c.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy 1728system.l2c.tags.occ_task_id_blocks::1024 65027 # Occupied blocks per task id 1729system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id 1730system.l2c.tags.age_task_id_blocks_1024::1 3644 # Occupied blocks per task id 1731system.l2c.tags.age_task_id_blocks_1024::2 2937 # Occupied blocks per task id 1732system.l2c.tags.age_task_id_blocks_1024::3 5880 # Occupied blocks per task id 1733system.l2c.tags.age_task_id_blocks_1024::4 52328 # Occupied blocks per task id 1734system.l2c.tags.occ_task_id_percent::1024 0.992233 # Percentage of cache occupancy per task id 1735system.l2c.tags.tag_accesses 38778519 # Number of tag accesses 1736system.l2c.tags.data_accesses 38778519 # Number of data accesses 1737system.l2c.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 1738system.l2c.WritebackDirty_hits::writebacks 830376 # number of WritebackDirty hits 1739system.l2c.WritebackDirty_hits::total 830376 # number of WritebackDirty hits 1740system.l2c.WritebackClean_hits::writebacks 866904 # number of WritebackClean hits 1741system.l2c.WritebackClean_hits::total 866904 # number of WritebackClean hits 1742system.l2c.UpgradeReq_hits::cpu0.data 177 # number of UpgradeReq hits 1743system.l2c.UpgradeReq_hits::cpu1.data 78 # number of UpgradeReq hits 1744system.l2c.UpgradeReq_hits::total 255 # number of UpgradeReq hits 1745system.l2c.SCUpgradeReq_hits::cpu0.data 93 # number of SCUpgradeReq hits 1746system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits 1747system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits 1748system.l2c.ReadExReq_hits::cpu0.data 167638 # number of ReadExReq hits 1749system.l2c.ReadExReq_hits::cpu1.data 13954 # number of ReadExReq hits 1750system.l2c.ReadExReq_hits::total 181592 # number of ReadExReq hits 1751system.l2c.ReadCleanReq_hits::cpu0.inst 1001682 # number of ReadCleanReq hits 1752system.l2c.ReadCleanReq_hits::cpu1.inst 128599 # number of ReadCleanReq hits 1753system.l2c.ReadCleanReq_hits::total 1130281 # number of ReadCleanReq hits 1754system.l2c.ReadSharedReq_hits::cpu0.data 778846 # number of ReadSharedReq hits 1755system.l2c.ReadSharedReq_hits::cpu1.data 41539 # number of ReadSharedReq hits 1756system.l2c.ReadSharedReq_hits::total 820385 # number of ReadSharedReq hits 1757system.l2c.demand_hits::cpu0.inst 1001682 # number of demand (read+write) hits 1758system.l2c.demand_hits::cpu0.data 946484 # number of demand (read+write) hits 1759system.l2c.demand_hits::cpu1.inst 128599 # number of demand (read+write) hits 1760system.l2c.demand_hits::cpu1.data 55493 # number of demand (read+write) hits 1761system.l2c.demand_hits::total 2132258 # number of demand (read+write) hits 1762system.l2c.overall_hits::cpu0.inst 1001682 # number of overall hits 1763system.l2c.overall_hits::cpu0.data 946484 # number of overall hits 1764system.l2c.overall_hits::cpu1.inst 128599 # number of overall hits 1765system.l2c.overall_hits::cpu1.data 55493 # number of overall hits 1766system.l2c.overall_hits::total 2132258 # number of overall hits 1767system.l2c.UpgradeReq_misses::cpu0.data 2505 # number of UpgradeReq misses 1768system.l2c.UpgradeReq_misses::cpu1.data 627 # number of UpgradeReq misses 1769system.l2c.UpgradeReq_misses::total 3132 # number of UpgradeReq misses 1770system.l2c.SCUpgradeReq_misses::cpu0.data 74 # number of SCUpgradeReq misses 1771system.l2c.SCUpgradeReq_misses::cpu1.data 102 # number of SCUpgradeReq misses 1772system.l2c.SCUpgradeReq_misses::total 176 # number of SCUpgradeReq misses 1773system.l2c.ReadExReq_misses::cpu0.data 111923 # number of ReadExReq misses 1774system.l2c.ReadExReq_misses::cpu1.data 8380 # number of ReadExReq misses 1775system.l2c.ReadExReq_misses::total 120303 # number of ReadExReq misses 1776system.l2c.ReadCleanReq_misses::cpu0.inst 13465 # number of ReadCleanReq misses 1777system.l2c.ReadCleanReq_misses::cpu1.inst 1860 # number of ReadCleanReq misses 1778system.l2c.ReadCleanReq_misses::total 15325 # number of ReadCleanReq misses 1779system.l2c.ReadSharedReq_misses::cpu0.data 273663 # number of ReadSharedReq misses 1780system.l2c.ReadSharedReq_misses::cpu1.data 829 # number of ReadSharedReq misses 1781system.l2c.ReadSharedReq_misses::total 274492 # number of ReadSharedReq misses 1782system.l2c.demand_misses::cpu0.inst 13465 # number of demand (read+write) misses 1783system.l2c.demand_misses::cpu0.data 385586 # number of demand (read+write) misses 1784system.l2c.demand_misses::cpu1.inst 1860 # number of demand (read+write) misses 1785system.l2c.demand_misses::cpu1.data 9209 # number of demand (read+write) misses 1786system.l2c.demand_misses::total 410120 # number of demand (read+write) misses 1787system.l2c.overall_misses::cpu0.inst 13465 # number of overall misses 1788system.l2c.overall_misses::cpu0.data 385586 # number of overall misses 1789system.l2c.overall_misses::cpu1.inst 1860 # number of overall misses 1790system.l2c.overall_misses::cpu1.data 9209 # number of overall misses 1791system.l2c.overall_misses::total 410120 # number of overall misses 1792system.l2c.UpgradeReq_miss_latency::cpu0.data 1461500 # number of UpgradeReq miss cycles 1793system.l2c.UpgradeReq_miss_latency::cpu1.data 1509000 # number of UpgradeReq miss cycles 1794system.l2c.UpgradeReq_miss_latency::total 2970500 # number of UpgradeReq miss cycles 1795system.l2c.SCUpgradeReq_miss_latency::cpu0.data 588500 # number of SCUpgradeReq miss cycles 1796system.l2c.SCUpgradeReq_miss_latency::cpu1.data 59000 # number of SCUpgradeReq miss cycles 1797system.l2c.SCUpgradeReq_miss_latency::total 647500 # number of SCUpgradeReq miss cycles 1798system.l2c.ReadExReq_miss_latency::cpu0.data 9993512000 # number of ReadExReq miss cycles 1799system.l2c.ReadExReq_miss_latency::cpu1.data 942928000 # number of ReadExReq miss cycles 1800system.l2c.ReadExReq_miss_latency::total 10936440000 # number of ReadExReq miss cycles 1801system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1136019500 # number of ReadCleanReq miss cycles 1802system.l2c.ReadCleanReq_miss_latency::cpu1.inst 157980000 # number of ReadCleanReq miss cycles 1803system.l2c.ReadCleanReq_miss_latency::total 1293999500 # number of ReadCleanReq miss cycles 1804system.l2c.ReadSharedReq_miss_latency::cpu0.data 20211623000 # number of ReadSharedReq miss cycles 1805system.l2c.ReadSharedReq_miss_latency::cpu1.data 77550000 # number of ReadSharedReq miss cycles 1806system.l2c.ReadSharedReq_miss_latency::total 20289173000 # number of ReadSharedReq miss cycles 1807system.l2c.demand_miss_latency::cpu0.inst 1136019500 # number of demand (read+write) miss cycles 1808system.l2c.demand_miss_latency::cpu0.data 30205135000 # number of demand (read+write) miss cycles 1809system.l2c.demand_miss_latency::cpu1.inst 157980000 # number of demand (read+write) miss cycles 1810system.l2c.demand_miss_latency::cpu1.data 1020478000 # number of demand (read+write) miss cycles 1811system.l2c.demand_miss_latency::total 32519612500 # number of demand (read+write) miss cycles 1812system.l2c.overall_miss_latency::cpu0.inst 1136019500 # number of overall miss cycles 1813system.l2c.overall_miss_latency::cpu0.data 30205135000 # number of overall miss cycles 1814system.l2c.overall_miss_latency::cpu1.inst 157980000 # number of overall miss cycles 1815system.l2c.overall_miss_latency::cpu1.data 1020478000 # number of overall miss cycles 1816system.l2c.overall_miss_latency::total 32519612500 # number of overall miss cycles 1817system.l2c.WritebackDirty_accesses::writebacks 830376 # number of WritebackDirty accesses(hits+misses) 1818system.l2c.WritebackDirty_accesses::total 830376 # number of WritebackDirty accesses(hits+misses) 1819system.l2c.WritebackClean_accesses::writebacks 866904 # number of WritebackClean accesses(hits+misses) 1820system.l2c.WritebackClean_accesses::total 866904 # number of WritebackClean accesses(hits+misses) 1821system.l2c.UpgradeReq_accesses::cpu0.data 2682 # number of UpgradeReq accesses(hits+misses) 1822system.l2c.UpgradeReq_accesses::cpu1.data 705 # number of UpgradeReq accesses(hits+misses) 1823system.l2c.UpgradeReq_accesses::total 3387 # number of UpgradeReq accesses(hits+misses) 1824system.l2c.SCUpgradeReq_accesses::cpu0.data 167 # number of SCUpgradeReq accesses(hits+misses) 1825system.l2c.SCUpgradeReq_accesses::cpu1.data 128 # number of SCUpgradeReq accesses(hits+misses) 1826system.l2c.SCUpgradeReq_accesses::total 295 # number of SCUpgradeReq accesses(hits+misses) 1827system.l2c.ReadExReq_accesses::cpu0.data 279561 # number of ReadExReq accesses(hits+misses) 1828system.l2c.ReadExReq_accesses::cpu1.data 22334 # number of ReadExReq accesses(hits+misses) 1829system.l2c.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) 1830system.l2c.ReadCleanReq_accesses::cpu0.inst 1015147 # number of ReadCleanReq accesses(hits+misses) 1831system.l2c.ReadCleanReq_accesses::cpu1.inst 130459 # number of ReadCleanReq accesses(hits+misses) 1832system.l2c.ReadCleanReq_accesses::total 1145606 # number of ReadCleanReq accesses(hits+misses) 1833system.l2c.ReadSharedReq_accesses::cpu0.data 1052509 # number of ReadSharedReq accesses(hits+misses) 1834system.l2c.ReadSharedReq_accesses::cpu1.data 42368 # number of ReadSharedReq accesses(hits+misses) 1835system.l2c.ReadSharedReq_accesses::total 1094877 # number of ReadSharedReq accesses(hits+misses) 1836system.l2c.demand_accesses::cpu0.inst 1015147 # number of demand (read+write) accesses 1837system.l2c.demand_accesses::cpu0.data 1332070 # number of demand (read+write) accesses 1838system.l2c.demand_accesses::cpu1.inst 130459 # number of demand (read+write) accesses 1839system.l2c.demand_accesses::cpu1.data 64702 # number of demand (read+write) accesses 1840system.l2c.demand_accesses::total 2542378 # number of demand (read+write) accesses 1841system.l2c.overall_accesses::cpu0.inst 1015147 # number of overall (read+write) accesses 1842system.l2c.overall_accesses::cpu0.data 1332070 # number of overall (read+write) accesses 1843system.l2c.overall_accesses::cpu1.inst 130459 # number of overall (read+write) accesses 1844system.l2c.overall_accesses::cpu1.data 64702 # number of overall (read+write) accesses 1845system.l2c.overall_accesses::total 2542378 # number of overall (read+write) accesses 1846system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934004 # miss rate for UpgradeReq accesses 1847system.l2c.UpgradeReq_miss_rate::cpu1.data 0.889362 # miss rate for UpgradeReq accesses 1848system.l2c.UpgradeReq_miss_rate::total 0.924712 # miss rate for UpgradeReq accesses 1849system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.443114 # miss rate for SCUpgradeReq accesses 1850system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.796875 # miss rate for SCUpgradeReq accesses 1851system.l2c.SCUpgradeReq_miss_rate::total 0.596610 # miss rate for SCUpgradeReq accesses 1852system.l2c.ReadExReq_miss_rate::cpu0.data 0.400353 # miss rate for ReadExReq accesses 1853system.l2c.ReadExReq_miss_rate::cpu1.data 0.375213 # miss rate for ReadExReq accesses 1854system.l2c.ReadExReq_miss_rate::total 0.398493 # miss rate for ReadExReq accesses 1855system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.013264 # miss rate for ReadCleanReq accesses 1856system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.014257 # miss rate for ReadCleanReq accesses 1857system.l2c.ReadCleanReq_miss_rate::total 0.013377 # miss rate for ReadCleanReq accesses 1858system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.260010 # miss rate for ReadSharedReq accesses 1859system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.019567 # miss rate for ReadSharedReq accesses 1860system.l2c.ReadSharedReq_miss_rate::total 0.250706 # miss rate for ReadSharedReq accesses 1861system.l2c.demand_miss_rate::cpu0.inst 0.013264 # miss rate for demand accesses 1862system.l2c.demand_miss_rate::cpu0.data 0.289464 # miss rate for demand accesses 1863system.l2c.demand_miss_rate::cpu1.inst 0.014257 # miss rate for demand accesses 1864system.l2c.demand_miss_rate::cpu1.data 0.142329 # miss rate for demand accesses 1865system.l2c.demand_miss_rate::total 0.161314 # miss rate for demand accesses 1866system.l2c.overall_miss_rate::cpu0.inst 0.013264 # miss rate for overall accesses 1867system.l2c.overall_miss_rate::cpu0.data 0.289464 # miss rate for overall accesses 1868system.l2c.overall_miss_rate::cpu1.inst 0.014257 # miss rate for overall accesses 1869system.l2c.overall_miss_rate::cpu1.data 0.142329 # miss rate for overall accesses 1870system.l2c.overall_miss_rate::total 0.161314 # miss rate for overall accesses 1871system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 583.433134 # average UpgradeReq miss latency 1872system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2406.698565 # average UpgradeReq miss latency 1873system.l2c.UpgradeReq_avg_miss_latency::total 948.435504 # average UpgradeReq miss latency 1874system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7952.702703 # average SCUpgradeReq miss latency 1875system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 578.431373 # average SCUpgradeReq miss latency 1876system.l2c.SCUpgradeReq_avg_miss_latency::total 3678.977273 # average SCUpgradeReq miss latency 1877system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89289.172020 # average ReadExReq miss latency 1878system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112521.241050 # average ReadExReq miss latency 1879system.l2c.ReadExReq_avg_miss_latency::total 90907.458667 # average ReadExReq miss latency 1880system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84368.325288 # average ReadCleanReq miss latency 1881system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84935.483871 # average ReadCleanReq miss latency 1882system.l2c.ReadCleanReq_avg_miss_latency::total 84437.161501 # average ReadCleanReq miss latency 1883system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73855.884793 # average ReadSharedReq miss latency 1884system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93546.441496 # average ReadSharedReq miss latency 1885system.l2c.ReadSharedReq_avg_miss_latency::total 73915.352724 # average ReadSharedReq miss latency 1886system.l2c.demand_avg_miss_latency::cpu0.inst 84368.325288 # average overall miss latency 1887system.l2c.demand_avg_miss_latency::cpu0.data 78335.663121 # average overall miss latency 1888system.l2c.demand_avg_miss_latency::cpu1.inst 84935.483871 # average overall miss latency 1889system.l2c.demand_avg_miss_latency::cpu1.data 110813.117602 # average overall miss latency 1890system.l2c.demand_avg_miss_latency::total 79292.920365 # average overall miss latency 1891system.l2c.overall_avg_miss_latency::cpu0.inst 84368.325288 # average overall miss latency 1892system.l2c.overall_avg_miss_latency::cpu0.data 78335.663121 # average overall miss latency 1893system.l2c.overall_avg_miss_latency::cpu1.inst 84935.483871 # average overall miss latency 1894system.l2c.overall_avg_miss_latency::cpu1.data 110813.117602 # average overall miss latency 1895system.l2c.overall_avg_miss_latency::total 79292.920365 # average overall miss latency | 1710system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698 # average ReadReq mshr miss latency 1711system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698 # average ReadReq mshr miss latency 1712system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889 # average WriteLineReq mshr miss latency 1713system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889 # average WriteLineReq mshr miss latency 1714system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency 1715system.iocache.demand_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency 1716system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency 1717system.iocache.overall_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency 1718system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1719system.l2c.tags.replacements 345621 # number of replacements 1720system.l2c.tags.tagsinuse 65429.949099 # Cycle average of tags in use 1721system.l2c.tags.total_refs 4347999 # Total number of references to valid blocks. 1722system.l2c.tags.sampled_refs 411104 # Sample count of references to valid blocks. 1723system.l2c.tags.avg_refs 10.576397 # Average number of references to valid blocks. 1724system.l2c.tags.warmup_cycle 5987439000 # Cycle when the warmup percentage was hit. 1725system.l2c.tags.occ_blocks::writebacks 292.894251 # Average occupied blocks per requestor 1726system.l2c.tags.occ_blocks::cpu0.inst 5335.962916 # Average occupied blocks per requestor 1727system.l2c.tags.occ_blocks::cpu0.data 58874.943819 # Average occupied blocks per requestor 1728system.l2c.tags.occ_blocks::cpu1.inst 203.860157 # Average occupied blocks per requestor 1729system.l2c.tags.occ_blocks::cpu1.data 722.287955 # Average occupied blocks per requestor 1730system.l2c.tags.occ_percent::writebacks 0.004469 # Average percentage of cache occupancy 1731system.l2c.tags.occ_percent::cpu0.inst 0.081420 # Average percentage of cache occupancy 1732system.l2c.tags.occ_percent::cpu0.data 0.898360 # Average percentage of cache occupancy 1733system.l2c.tags.occ_percent::cpu1.inst 0.003111 # Average percentage of cache occupancy 1734system.l2c.tags.occ_percent::cpu1.data 0.011021 # Average percentage of cache occupancy 1735system.l2c.tags.occ_percent::total 0.998382 # Average percentage of cache occupancy 1736system.l2c.tags.occ_task_id_blocks::1024 65483 # Occupied blocks per task id 1737system.l2c.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 1738system.l2c.tags.age_task_id_blocks_1024::1 1723 # Occupied blocks per task id 1739system.l2c.tags.age_task_id_blocks_1024::2 1817 # Occupied blocks per task id 1740system.l2c.tags.age_task_id_blocks_1024::3 5637 # Occupied blocks per task id 1741system.l2c.tags.age_task_id_blocks_1024::4 56151 # Occupied blocks per task id 1742system.l2c.tags.occ_task_id_percent::1024 0.999191 # Percentage of cache occupancy per task id 1743system.l2c.tags.tag_accesses 38487323 # Number of tag accesses 1744system.l2c.tags.data_accesses 38487323 # Number of data accesses 1745system.l2c.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 1746system.l2c.WritebackDirty_hits::writebacks 824550 # number of WritebackDirty hits 1747system.l2c.WritebackDirty_hits::total 824550 # number of WritebackDirty hits 1748system.l2c.WritebackClean_hits::writebacks 880861 # number of WritebackClean hits 1749system.l2c.WritebackClean_hits::total 880861 # number of WritebackClean hits 1750system.l2c.UpgradeReq_hits::cpu0.data 2842 # number of UpgradeReq hits 1751system.l2c.UpgradeReq_hits::cpu1.data 1401 # number of UpgradeReq hits 1752system.l2c.UpgradeReq_hits::total 4243 # number of UpgradeReq hits 1753system.l2c.SCUpgradeReq_hits::cpu0.data 470 # number of SCUpgradeReq hits 1754system.l2c.SCUpgradeReq_hits::cpu1.data 444 # number of SCUpgradeReq hits 1755system.l2c.SCUpgradeReq_hits::total 914 # number of SCUpgradeReq hits 1756system.l2c.ReadExReq_hits::cpu0.data 147625 # number of ReadExReq hits 1757system.l2c.ReadExReq_hits::cpu1.data 30184 # number of ReadExReq hits 1758system.l2c.ReadExReq_hits::total 177809 # number of ReadExReq hits 1759system.l2c.ReadCleanReq_hits::cpu0.inst 895088 # number of ReadCleanReq hits 1760system.l2c.ReadCleanReq_hits::cpu1.inst 243149 # number of ReadCleanReq hits 1761system.l2c.ReadCleanReq_hits::total 1138237 # number of ReadCleanReq hits 1762system.l2c.ReadSharedReq_hits::cpu0.data 727494 # number of ReadSharedReq hits 1763system.l2c.ReadSharedReq_hits::cpu1.data 80955 # number of ReadSharedReq hits 1764system.l2c.ReadSharedReq_hits::total 808449 # number of ReadSharedReq hits 1765system.l2c.demand_hits::cpu0.inst 895088 # number of demand (read+write) hits 1766system.l2c.demand_hits::cpu0.data 875119 # number of demand (read+write) hits 1767system.l2c.demand_hits::cpu1.inst 243149 # number of demand (read+write) hits 1768system.l2c.demand_hits::cpu1.data 111139 # number of demand (read+write) hits 1769system.l2c.demand_hits::total 2124495 # number of demand (read+write) hits 1770system.l2c.overall_hits::cpu0.inst 895088 # number of overall hits 1771system.l2c.overall_hits::cpu0.data 875119 # number of overall hits 1772system.l2c.overall_hits::cpu1.inst 243149 # number of overall hits 1773system.l2c.overall_hits::cpu1.data 111139 # number of overall hits 1774system.l2c.overall_hits::total 2124495 # number of overall hits 1775system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses 1776system.l2c.UpgradeReq_misses::cpu1.data 3 # number of UpgradeReq misses 1777system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses 1778system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses 1779system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 1780system.l2c.ReadExReq_misses::cpu0.data 110021 # number of ReadExReq misses 1781system.l2c.ReadExReq_misses::cpu1.data 11230 # number of ReadExReq misses 1782system.l2c.ReadExReq_misses::total 121251 # number of ReadExReq misses 1783system.l2c.ReadCleanReq_misses::cpu0.inst 14005 # number of ReadCleanReq misses 1784system.l2c.ReadCleanReq_misses::cpu1.inst 1293 # number of ReadCleanReq misses 1785system.l2c.ReadCleanReq_misses::total 15298 # number of ReadCleanReq misses 1786system.l2c.ReadSharedReq_misses::cpu0.data 272996 # number of ReadSharedReq misses 1787system.l2c.ReadSharedReq_misses::cpu1.data 1575 # number of ReadSharedReq misses 1788system.l2c.ReadSharedReq_misses::total 274571 # number of ReadSharedReq misses 1789system.l2c.demand_misses::cpu0.inst 14005 # number of demand (read+write) misses 1790system.l2c.demand_misses::cpu0.data 383017 # number of demand (read+write) misses 1791system.l2c.demand_misses::cpu1.inst 1293 # number of demand (read+write) misses 1792system.l2c.demand_misses::cpu1.data 12805 # number of demand (read+write) misses 1793system.l2c.demand_misses::total 411120 # number of demand (read+write) misses 1794system.l2c.overall_misses::cpu0.inst 14005 # number of overall misses 1795system.l2c.overall_misses::cpu0.data 383017 # number of overall misses 1796system.l2c.overall_misses::cpu1.inst 1293 # number of overall misses 1797system.l2c.overall_misses::cpu1.data 12805 # number of overall misses 1798system.l2c.overall_misses::total 411120 # number of overall misses 1799system.l2c.UpgradeReq_miss_latency::cpu0.data 334500 # number of UpgradeReq miss cycles 1800system.l2c.UpgradeReq_miss_latency::cpu1.data 59000 # number of UpgradeReq miss cycles 1801system.l2c.UpgradeReq_miss_latency::total 393500 # number of UpgradeReq miss cycles 1802system.l2c.ReadExReq_miss_latency::cpu0.data 9803404500 # number of ReadExReq miss cycles 1803system.l2c.ReadExReq_miss_latency::cpu1.data 1283749500 # number of ReadExReq miss cycles 1804system.l2c.ReadExReq_miss_latency::total 11087154000 # number of ReadExReq miss cycles 1805system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1179329500 # number of ReadCleanReq miss cycles 1806system.l2c.ReadCleanReq_miss_latency::cpu1.inst 110888000 # number of ReadCleanReq miss cycles 1807system.l2c.ReadCleanReq_miss_latency::total 1290217500 # number of ReadCleanReq miss cycles 1808system.l2c.ReadSharedReq_miss_latency::cpu0.data 20156491500 # number of ReadSharedReq miss cycles 1809system.l2c.ReadSharedReq_miss_latency::cpu1.data 149319000 # number of ReadSharedReq miss cycles 1810system.l2c.ReadSharedReq_miss_latency::total 20305810500 # number of ReadSharedReq miss cycles 1811system.l2c.demand_miss_latency::cpu0.inst 1179329500 # number of demand (read+write) miss cycles 1812system.l2c.demand_miss_latency::cpu0.data 29959896000 # number of demand (read+write) miss cycles 1813system.l2c.demand_miss_latency::cpu1.inst 110888000 # number of demand (read+write) miss cycles 1814system.l2c.demand_miss_latency::cpu1.data 1433068500 # number of demand (read+write) miss cycles 1815system.l2c.demand_miss_latency::total 32683182000 # number of demand (read+write) miss cycles 1816system.l2c.overall_miss_latency::cpu0.inst 1179329500 # number of overall miss cycles 1817system.l2c.overall_miss_latency::cpu0.data 29959896000 # number of overall miss cycles 1818system.l2c.overall_miss_latency::cpu1.inst 110888000 # number of overall miss cycles 1819system.l2c.overall_miss_latency::cpu1.data 1433068500 # number of overall miss cycles 1820system.l2c.overall_miss_latency::total 32683182000 # number of overall miss cycles 1821system.l2c.WritebackDirty_accesses::writebacks 824550 # number of WritebackDirty accesses(hits+misses) 1822system.l2c.WritebackDirty_accesses::total 824550 # number of WritebackDirty accesses(hits+misses) 1823system.l2c.WritebackClean_accesses::writebacks 880861 # number of WritebackClean accesses(hits+misses) 1824system.l2c.WritebackClean_accesses::total 880861 # number of WritebackClean accesses(hits+misses) 1825system.l2c.UpgradeReq_accesses::cpu0.data 2848 # number of UpgradeReq accesses(hits+misses) 1826system.l2c.UpgradeReq_accesses::cpu1.data 1404 # number of UpgradeReq accesses(hits+misses) 1827system.l2c.UpgradeReq_accesses::total 4252 # number of UpgradeReq accesses(hits+misses) 1828system.l2c.SCUpgradeReq_accesses::cpu0.data 470 # number of SCUpgradeReq accesses(hits+misses) 1829system.l2c.SCUpgradeReq_accesses::cpu1.data 445 # number of SCUpgradeReq accesses(hits+misses) 1830system.l2c.SCUpgradeReq_accesses::total 915 # number of SCUpgradeReq accesses(hits+misses) 1831system.l2c.ReadExReq_accesses::cpu0.data 257646 # number of ReadExReq accesses(hits+misses) 1832system.l2c.ReadExReq_accesses::cpu1.data 41414 # number of ReadExReq accesses(hits+misses) 1833system.l2c.ReadExReq_accesses::total 299060 # number of ReadExReq accesses(hits+misses) 1834system.l2c.ReadCleanReq_accesses::cpu0.inst 909093 # number of ReadCleanReq accesses(hits+misses) 1835system.l2c.ReadCleanReq_accesses::cpu1.inst 244442 # number of ReadCleanReq accesses(hits+misses) 1836system.l2c.ReadCleanReq_accesses::total 1153535 # number of ReadCleanReq accesses(hits+misses) 1837system.l2c.ReadSharedReq_accesses::cpu0.data 1000490 # number of ReadSharedReq accesses(hits+misses) 1838system.l2c.ReadSharedReq_accesses::cpu1.data 82530 # number of ReadSharedReq accesses(hits+misses) 1839system.l2c.ReadSharedReq_accesses::total 1083020 # number of ReadSharedReq accesses(hits+misses) 1840system.l2c.demand_accesses::cpu0.inst 909093 # number of demand (read+write) accesses 1841system.l2c.demand_accesses::cpu0.data 1258136 # number of demand (read+write) accesses 1842system.l2c.demand_accesses::cpu1.inst 244442 # number of demand (read+write) accesses 1843system.l2c.demand_accesses::cpu1.data 123944 # number of demand (read+write) accesses 1844system.l2c.demand_accesses::total 2535615 # number of demand (read+write) accesses 1845system.l2c.overall_accesses::cpu0.inst 909093 # number of overall (read+write) accesses 1846system.l2c.overall_accesses::cpu0.data 1258136 # number of overall (read+write) accesses 1847system.l2c.overall_accesses::cpu1.inst 244442 # number of overall (read+write) accesses 1848system.l2c.overall_accesses::cpu1.data 123944 # number of overall (read+write) accesses 1849system.l2c.overall_accesses::total 2535615 # number of overall (read+write) accesses 1850system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002107 # miss rate for UpgradeReq accesses 1851system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for UpgradeReq accesses 1852system.l2c.UpgradeReq_miss_rate::total 0.002117 # miss rate for UpgradeReq accesses 1853system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002247 # miss rate for SCUpgradeReq accesses 1854system.l2c.SCUpgradeReq_miss_rate::total 0.001093 # miss rate for SCUpgradeReq accesses 1855system.l2c.ReadExReq_miss_rate::cpu0.data 0.427024 # miss rate for ReadExReq accesses 1856system.l2c.ReadExReq_miss_rate::cpu1.data 0.271164 # miss rate for ReadExReq accesses 1857system.l2c.ReadExReq_miss_rate::total 0.405440 # miss rate for ReadExReq accesses 1858system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015405 # miss rate for ReadCleanReq accesses 1859system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005290 # miss rate for ReadCleanReq accesses 1860system.l2c.ReadCleanReq_miss_rate::total 0.013262 # miss rate for ReadCleanReq accesses 1861system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.272862 # miss rate for ReadSharedReq accesses 1862system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.019084 # miss rate for ReadSharedReq accesses 1863system.l2c.ReadSharedReq_miss_rate::total 0.253523 # miss rate for ReadSharedReq accesses 1864system.l2c.demand_miss_rate::cpu0.inst 0.015405 # miss rate for demand accesses 1865system.l2c.demand_miss_rate::cpu0.data 0.304432 # miss rate for demand accesses 1866system.l2c.demand_miss_rate::cpu1.inst 0.005290 # miss rate for demand accesses 1867system.l2c.demand_miss_rate::cpu1.data 0.103313 # miss rate for demand accesses 1868system.l2c.demand_miss_rate::total 0.162138 # miss rate for demand accesses 1869system.l2c.overall_miss_rate::cpu0.inst 0.015405 # miss rate for overall accesses 1870system.l2c.overall_miss_rate::cpu0.data 0.304432 # miss rate for overall accesses 1871system.l2c.overall_miss_rate::cpu1.inst 0.005290 # miss rate for overall accesses 1872system.l2c.overall_miss_rate::cpu1.data 0.103313 # miss rate for overall accesses 1873system.l2c.overall_miss_rate::total 0.162138 # miss rate for overall accesses 1874system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55750 # average UpgradeReq miss latency 1875system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19666.666667 # average UpgradeReq miss latency 1876system.l2c.UpgradeReq_avg_miss_latency::total 43722.222222 # average UpgradeReq miss latency 1877system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89104.848165 # average ReadExReq miss latency 1878system.l2c.ReadExReq_avg_miss_latency::cpu1.data 114314.292075 # average ReadExReq miss latency 1879system.l2c.ReadExReq_avg_miss_latency::total 91439.691219 # average ReadExReq miss latency 1880system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84207.747233 # average ReadCleanReq miss latency 1881system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85760.247486 # average ReadCleanReq miss latency 1882system.l2c.ReadCleanReq_avg_miss_latency::total 84338.965878 # average ReadCleanReq miss latency 1883system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73834.384020 # average ReadSharedReq miss latency 1884system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94805.714286 # average ReadSharedReq miss latency 1885system.l2c.ReadSharedReq_avg_miss_latency::total 73954.680210 # average ReadSharedReq miss latency 1886system.l2c.demand_avg_miss_latency::cpu0.inst 84207.747233 # average overall miss latency 1887system.l2c.demand_avg_miss_latency::cpu0.data 78220.799599 # average overall miss latency 1888system.l2c.demand_avg_miss_latency::cpu1.inst 85760.247486 # average overall miss latency 1889system.l2c.demand_avg_miss_latency::cpu1.data 111914.759859 # average overall miss latency 1890system.l2c.demand_avg_miss_latency::total 79497.913018 # average overall miss latency 1891system.l2c.overall_avg_miss_latency::cpu0.inst 84207.747233 # average overall miss latency 1892system.l2c.overall_avg_miss_latency::cpu0.data 78220.799599 # average overall miss latency 1893system.l2c.overall_avg_miss_latency::cpu1.inst 85760.247486 # average overall miss latency 1894system.l2c.overall_avg_miss_latency::cpu1.data 111914.759859 # average overall miss latency 1895system.l2c.overall_avg_miss_latency::total 79497.913018 # average overall miss latency |
| 1896system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1897system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1898system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1899system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1900system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1901system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1896system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1897system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1898system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1899system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1900system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1901system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1902system.l2c.writebacks::writebacks 81059 # number of writebacks 1903system.l2c.writebacks::total 81059 # number of writebacks | 1902system.l2c.writebacks::writebacks 81993 # number of writebacks 1903system.l2c.writebacks::total 81993 # number of writebacks 1904system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits |
| 1904system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits | 1905system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits |
| 1905system.l2c.ReadCleanReq_mshr_hits::total 17 # number of ReadCleanReq MSHR hits | 1906system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 1907system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits |
| 1906system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits | 1908system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits |
| 1907system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits | 1909system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 1910system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits |
| 1908system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits | 1911system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits |
| 1909system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits | 1912system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits |
| 1910system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1911system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses | 1913system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1914system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses |
| 1912system.l2c.UpgradeReq_mshr_misses::cpu0.data 2505 # number of UpgradeReq MSHR misses 1913system.l2c.UpgradeReq_mshr_misses::cpu1.data 627 # number of UpgradeReq MSHR misses 1914system.l2c.UpgradeReq_mshr_misses::total 3132 # number of UpgradeReq MSHR misses 1915system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 74 # number of SCUpgradeReq MSHR misses 1916system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 102 # number of SCUpgradeReq MSHR misses 1917system.l2c.SCUpgradeReq_mshr_misses::total 176 # number of SCUpgradeReq MSHR misses 1918system.l2c.ReadExReq_mshr_misses::cpu0.data 111923 # number of ReadExReq MSHR misses 1919system.l2c.ReadExReq_mshr_misses::cpu1.data 8380 # number of ReadExReq MSHR misses 1920system.l2c.ReadExReq_mshr_misses::total 120303 # number of ReadExReq MSHR misses 1921system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13465 # number of ReadCleanReq MSHR misses 1922system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1843 # number of ReadCleanReq MSHR misses 1923system.l2c.ReadCleanReq_mshr_misses::total 15308 # number of ReadCleanReq MSHR misses 1924system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273663 # number of ReadSharedReq MSHR misses 1925system.l2c.ReadSharedReq_mshr_misses::cpu1.data 829 # number of ReadSharedReq MSHR misses 1926system.l2c.ReadSharedReq_mshr_misses::total 274492 # number of ReadSharedReq MSHR misses 1927system.l2c.demand_mshr_misses::cpu0.inst 13465 # number of demand (read+write) MSHR misses 1928system.l2c.demand_mshr_misses::cpu0.data 385586 # number of demand (read+write) MSHR misses 1929system.l2c.demand_mshr_misses::cpu1.inst 1843 # number of demand (read+write) MSHR misses 1930system.l2c.demand_mshr_misses::cpu1.data 9209 # number of demand (read+write) MSHR misses 1931system.l2c.demand_mshr_misses::total 410103 # number of demand (read+write) MSHR misses 1932system.l2c.overall_mshr_misses::cpu0.inst 13465 # number of overall MSHR misses 1933system.l2c.overall_mshr_misses::cpu0.data 385586 # number of overall MSHR misses 1934system.l2c.overall_mshr_misses::cpu1.inst 1843 # number of overall MSHR misses 1935system.l2c.overall_mshr_misses::cpu1.data 9209 # number of overall MSHR misses 1936system.l2c.overall_mshr_misses::total 410103 # number of overall MSHR misses 1937system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable 1938system.l2c.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable 1939system.l2c.ReadReq_mshr_uncacheable::total 7194 # number of ReadReq MSHR uncacheable 1940system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable 1941system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable 1942system.l2c.WriteReq_mshr_uncacheable::total 12394 # number of WriteReq MSHR uncacheable 1943system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses 1944system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses 1945system.l2c.overall_mshr_uncacheable_misses::total 19588 # number of overall MSHR uncacheable misses 1946system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 50228500 # number of UpgradeReq MSHR miss cycles 1947system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12653000 # number of UpgradeReq MSHR miss cycles 1948system.l2c.UpgradeReq_mshr_miss_latency::total 62881500 # number of UpgradeReq MSHR miss cycles 1949system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1467500 # number of SCUpgradeReq MSHR miss cycles 1950system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2009000 # number of SCUpgradeReq MSHR miss cycles 1951system.l2c.SCUpgradeReq_mshr_miss_latency::total 3476500 # number of SCUpgradeReq MSHR miss cycles 1952system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8874280004 # number of ReadExReq MSHR miss cycles 1953system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 859128000 # number of ReadExReq MSHR miss cycles 1954system.l2c.ReadExReq_mshr_miss_latency::total 9733408004 # number of ReadExReq MSHR miss cycles 1955system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1001369001 # number of ReadCleanReq MSHR miss cycles 1956system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 138309001 # number of ReadCleanReq MSHR miss cycles 1957system.l2c.ReadCleanReq_mshr_miss_latency::total 1139678002 # number of ReadCleanReq MSHR miss cycles 1958system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17481138002 # number of ReadSharedReq MSHR miss cycles 1959system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 69259501 # number of ReadSharedReq MSHR miss cycles 1960system.l2c.ReadSharedReq_mshr_miss_latency::total 17550397503 # number of ReadSharedReq MSHR miss cycles 1961system.l2c.demand_mshr_miss_latency::cpu0.inst 1001369001 # number of demand (read+write) MSHR miss cycles 1962system.l2c.demand_mshr_miss_latency::cpu0.data 26355418006 # number of demand (read+write) MSHR miss cycles 1963system.l2c.demand_mshr_miss_latency::cpu1.inst 138309001 # number of demand (read+write) MSHR miss cycles 1964system.l2c.demand_mshr_miss_latency::cpu1.data 928387501 # number of demand (read+write) MSHR miss cycles 1965system.l2c.demand_mshr_miss_latency::total 28423483509 # number of demand (read+write) MSHR miss cycles 1966system.l2c.overall_mshr_miss_latency::cpu0.inst 1001369001 # number of overall MSHR miss cycles 1967system.l2c.overall_mshr_miss_latency::cpu0.data 26355418006 # number of overall MSHR miss cycles 1968system.l2c.overall_mshr_miss_latency::cpu1.inst 138309001 # number of overall MSHR miss cycles 1969system.l2c.overall_mshr_miss_latency::cpu1.data 928387501 # number of overall MSHR miss cycles 1970system.l2c.overall_mshr_miss_latency::total 28423483509 # number of overall MSHR miss cycles 1971system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478504000 # number of ReadReq MSHR uncacheable cycles 1972system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30323500 # number of ReadReq MSHR uncacheable cycles 1973system.l2c.ReadReq_mshr_uncacheable_latency::total 1508827500 # number of ReadReq MSHR uncacheable cycles 1974system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478504000 # number of overall MSHR uncacheable cycles 1975system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30323500 # number of overall MSHR uncacheable cycles 1976system.l2c.overall_mshr_uncacheable_latency::total 1508827500 # number of overall MSHR uncacheable cycles | 1915system.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses 1916system.l2c.UpgradeReq_mshr_misses::cpu1.data 3 # number of UpgradeReq MSHR misses 1917system.l2c.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses 1918system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses 1919system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1920system.l2c.ReadExReq_mshr_misses::cpu0.data 110021 # number of ReadExReq MSHR misses 1921system.l2c.ReadExReq_mshr_misses::cpu1.data 11230 # number of ReadExReq MSHR misses 1922system.l2c.ReadExReq_mshr_misses::total 121251 # number of ReadExReq MSHR misses 1923system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 14004 # number of ReadCleanReq MSHR misses 1924system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1276 # number of ReadCleanReq MSHR misses 1925system.l2c.ReadCleanReq_mshr_misses::total 15280 # number of ReadCleanReq MSHR misses 1926system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272996 # number of ReadSharedReq MSHR misses 1927system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1575 # number of ReadSharedReq MSHR misses 1928system.l2c.ReadSharedReq_mshr_misses::total 274571 # number of ReadSharedReq MSHR misses 1929system.l2c.demand_mshr_misses::cpu0.inst 14004 # number of demand (read+write) MSHR misses 1930system.l2c.demand_mshr_misses::cpu0.data 383017 # number of demand (read+write) MSHR misses 1931system.l2c.demand_mshr_misses::cpu1.inst 1276 # number of demand (read+write) MSHR misses 1932system.l2c.demand_mshr_misses::cpu1.data 12805 # number of demand (read+write) MSHR misses 1933system.l2c.demand_mshr_misses::total 411102 # number of demand (read+write) MSHR misses 1934system.l2c.overall_mshr_misses::cpu0.inst 14004 # number of overall MSHR misses 1935system.l2c.overall_mshr_misses::cpu0.data 383017 # number of overall MSHR misses 1936system.l2c.overall_mshr_misses::cpu1.inst 1276 # number of overall MSHR misses 1937system.l2c.overall_mshr_misses::cpu1.data 12805 # number of overall MSHR misses 1938system.l2c.overall_mshr_misses::total 411102 # number of overall MSHR misses 1939system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable 1940system.l2c.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable 1941system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable 1942system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable 1943system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable 1944system.l2c.WriteReq_mshr_uncacheable::total 13019 # number of WriteReq MSHR uncacheable 1945system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses 1946system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses 1947system.l2c.overall_mshr_uncacheable_misses::total 20214 # number of overall MSHR uncacheable misses 1948system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 274500 # number of UpgradeReq MSHR miss cycles 1949system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 57500 # number of UpgradeReq MSHR miss cycles 1950system.l2c.UpgradeReq_mshr_miss_latency::total 332000 # number of UpgradeReq MSHR miss cycles 1951system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles 1952system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles 1953system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8703194500 # number of ReadExReq MSHR miss cycles 1954system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1171449500 # number of ReadExReq MSHR miss cycles 1955system.l2c.ReadExReq_mshr_miss_latency::total 9874644000 # number of ReadExReq MSHR miss cycles 1956system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1039194500 # number of ReadCleanReq MSHR miss cycles 1957system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 96887500 # number of ReadCleanReq MSHR miss cycles 1958system.l2c.ReadCleanReq_mshr_miss_latency::total 1136082000 # number of ReadCleanReq MSHR miss cycles 1959system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17432939000 # number of ReadSharedReq MSHR miss cycles 1960system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 133569000 # number of ReadSharedReq MSHR miss cycles 1961system.l2c.ReadSharedReq_mshr_miss_latency::total 17566508000 # number of ReadSharedReq MSHR miss cycles 1962system.l2c.demand_mshr_miss_latency::cpu0.inst 1039194500 # number of demand (read+write) MSHR miss cycles 1963system.l2c.demand_mshr_miss_latency::cpu0.data 26136133500 # number of demand (read+write) MSHR miss cycles 1964system.l2c.demand_mshr_miss_latency::cpu1.inst 96887500 # number of demand (read+write) MSHR miss cycles 1965system.l2c.demand_mshr_miss_latency::cpu1.data 1305018500 # number of demand (read+write) MSHR miss cycles 1966system.l2c.demand_mshr_miss_latency::total 28577234000 # number of demand (read+write) MSHR miss cycles 1967system.l2c.overall_mshr_miss_latency::cpu0.inst 1039194500 # number of overall MSHR miss cycles 1968system.l2c.overall_mshr_miss_latency::cpu0.data 26136133500 # number of overall MSHR miss cycles 1969system.l2c.overall_mshr_miss_latency::cpu1.inst 96887500 # number of overall MSHR miss cycles 1970system.l2c.overall_mshr_miss_latency::cpu1.data 1305018500 # number of overall MSHR miss cycles 1971system.l2c.overall_mshr_miss_latency::total 28577234000 # number of overall MSHR miss cycles 1972system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1475661000 # number of ReadReq MSHR uncacheable cycles 1973system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 33474500 # number of ReadReq MSHR uncacheable cycles 1974system.l2c.ReadReq_mshr_uncacheable_latency::total 1509135500 # number of ReadReq MSHR uncacheable cycles 1975system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1475661000 # number of overall MSHR uncacheable cycles 1976system.l2c.overall_mshr_uncacheable_latency::cpu1.data 33474500 # number of overall MSHR uncacheable cycles 1977system.l2c.overall_mshr_uncacheable_latency::total 1509135500 # number of overall MSHR uncacheable cycles |
| 1977system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1978system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 1978system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1979system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 1979system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934004 # mshr miss rate for UpgradeReq accesses 1980system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889362 # mshr miss rate for UpgradeReq accesses 1981system.l2c.UpgradeReq_mshr_miss_rate::total 0.924712 # mshr miss rate for UpgradeReq accesses 1982system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.443114 # mshr miss rate for SCUpgradeReq accesses 1983system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.796875 # mshr miss rate for SCUpgradeReq accesses 1984system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596610 # mshr miss rate for SCUpgradeReq accesses 1985system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.400353 # mshr miss rate for ReadExReq accesses 1986system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.375213 # mshr miss rate for ReadExReq accesses 1987system.l2c.ReadExReq_mshr_miss_rate::total 0.398493 # mshr miss rate for ReadExReq accesses 1988system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for ReadCleanReq accesses 1989system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for ReadCleanReq accesses 1990system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013362 # mshr miss rate for ReadCleanReq accesses 1991system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260010 # mshr miss rate for ReadSharedReq accesses 1992system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019567 # mshr miss rate for ReadSharedReq accesses 1993system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250706 # mshr miss rate for ReadSharedReq accesses 1994system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for demand accesses 1995system.l2c.demand_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for demand accesses 1996system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for demand accesses 1997system.l2c.demand_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for demand accesses 1998system.l2c.demand_mshr_miss_rate::total 0.161307 # mshr miss rate for demand accesses 1999system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for overall accesses 2000system.l2c.overall_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for overall accesses 2001system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for overall accesses 2002system.l2c.overall_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for overall accesses 2003system.l2c.overall_mshr_miss_rate::total 0.161307 # mshr miss rate for overall accesses 2004system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20051.297405 # average UpgradeReq mshr miss latency 2005system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20180.223285 # average UpgradeReq mshr miss latency 2006system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20077.107280 # average UpgradeReq mshr miss latency 2007system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19831.081081 # average SCUpgradeReq mshr miss latency 2008system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19696.078431 # average SCUpgradeReq mshr miss latency 2009system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19752.840909 # average SCUpgradeReq mshr miss latency 2010system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79289.154186 # average ReadExReq mshr miss latency 2011system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 102521.241050 # average ReadExReq mshr miss latency 2012system.l2c.ReadExReq_avg_mshr_miss_latency::total 80907.442075 # average ReadExReq mshr miss latency 2013system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average ReadCleanReq mshr miss latency 2014system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average ReadCleanReq mshr miss latency 2015system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74449.830285 # average ReadCleanReq mshr miss latency 2016system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63878.339425 # average ReadSharedReq mshr miss latency 2017system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83545.839566 # average ReadSharedReq mshr miss latency 2018system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63937.737723 # average ReadSharedReq mshr miss latency 2019system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average overall mshr miss latency 2020system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68351.594731 # average overall mshr miss latency 2021system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average overall mshr miss latency 2022system.l2c.demand_avg_mshr_miss_latency::cpu1.data 100813.063416 # average overall mshr miss latency 2023system.l2c.demand_avg_mshr_miss_latency::total 69308.157973 # average overall mshr miss latency 2024system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74368.288229 # average overall mshr miss latency 2025system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68351.594731 # average overall mshr miss latency 2026system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75045.578405 # average overall mshr miss latency 2027system.l2c.overall_avg_mshr_miss_latency::cpu1.data 100813.063416 # average overall mshr miss latency 2028system.l2c.overall_avg_mshr_miss_latency::total 69308.157973 # average overall mshr miss latency 2029system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210253.697383 # average ReadReq mshr uncacheable latency 2030system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187182.098765 # average ReadReq mshr uncacheable latency 2031system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209734.153461 # average ReadReq mshr uncacheable latency 2032system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88074.343242 # average overall mshr uncacheable latency 2033system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10825.955016 # average overall mshr uncacheable latency 2034system.l2c.overall_avg_mshr_uncacheable_latency::total 77028.154993 # average overall mshr uncacheable latency 2035system.membus.snoop_filter.tot_requests 844318 # Total number of requests made to the snoop filter. 2036system.membus.snoop_filter.hit_single_requests 393480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2037system.membus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1980system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for UpgradeReq accesses 1981system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for UpgradeReq accesses 1982system.l2c.UpgradeReq_mshr_miss_rate::total 0.002117 # mshr miss rate for UpgradeReq accesses 1983system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002247 # mshr miss rate for SCUpgradeReq accesses 1984system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001093 # mshr miss rate for SCUpgradeReq accesses 1985system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427024 # mshr miss rate for ReadExReq accesses 1986system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271164 # mshr miss rate for ReadExReq accesses 1987system.l2c.ReadExReq_mshr_miss_rate::total 0.405440 # mshr miss rate for ReadExReq accesses 1988system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for ReadCleanReq accesses 1989system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for ReadCleanReq accesses 1990system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses 1991system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272862 # mshr miss rate for ReadSharedReq accesses 1992system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for ReadSharedReq accesses 1993system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253523 # mshr miss rate for ReadSharedReq accesses 1994system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for demand accesses 1995system.l2c.demand_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for demand accesses 1996system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for demand accesses 1997system.l2c.demand_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for demand accesses 1998system.l2c.demand_mshr_miss_rate::total 0.162131 # mshr miss rate for demand accesses 1999system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for overall accesses 2000system.l2c.overall_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for overall accesses 2001system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for overall accesses 2002system.l2c.overall_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for overall accesses 2003system.l2c.overall_mshr_miss_rate::total 0.162131 # mshr miss rate for overall accesses 2004system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45750 # average UpgradeReq mshr miss latency 2005system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667 # average UpgradeReq mshr miss latency 2006system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889 # average UpgradeReq mshr miss latency 2007system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency 2008system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency 2009system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165 # average ReadExReq mshr miss latency 2010system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075 # average ReadExReq mshr miss latency 2011system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219 # average ReadExReq mshr miss latency 2012system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average ReadCleanReq mshr miss latency 2013system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average ReadCleanReq mshr miss latency 2014system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230 # average ReadCleanReq mshr miss latency 2015system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060 # average ReadSharedReq mshr miss latency 2016system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286 # average ReadSharedReq mshr miss latency 2017system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615 # average ReadSharedReq mshr miss latency 2018system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency 2019system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency 2020system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency 2021system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency 2022system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency 2023system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency 2024system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency 2025system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency 2026system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency 2027system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency 2028system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency 2029system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency 2030system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency 2031system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency 2032system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency 2033system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency 2034system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter. 2035system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2036system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2038system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2039system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2040system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2037system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2038system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2039system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2041system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2042system.membus.trans_dist::ReadReq 7194 # Transaction distribution 2043system.membus.trans_dist::ReadResp 297120 # Transaction distribution 2044system.membus.trans_dist::WriteReq 12394 # Transaction distribution 2045system.membus.trans_dist::WriteResp 12394 # Transaction distribution 2046system.membus.trans_dist::WritebackDirty 122579 # Transaction distribution 2047system.membus.trans_dist::CleanEvict 262673 # Transaction distribution 2048system.membus.trans_dist::UpgradeReq 5556 # Transaction distribution 2049system.membus.trans_dist::SCUpgradeReq 1697 # Transaction distribution | 2040system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2041system.membus.trans_dist::ReadReq 7195 # Transaction distribution 2042system.membus.trans_dist::ReadResp 297176 # Transaction distribution 2043system.membus.trans_dist::WriteReq 13019 # Transaction distribution 2044system.membus.trans_dist::WriteResp 13019 # Transaction distribution 2045system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution 2046system.membus.trans_dist::CleanEvict 262911 # Transaction distribution 2047system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution 2048system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution |
| 2050system.membus.trans_dist::UpgradeResp 3 # Transaction distribution | 2049system.membus.trans_dist::UpgradeResp 3 # Transaction distribution |
| 2051system.membus.trans_dist::ReadExReq 120271 # Transaction distribution 2052system.membus.trans_dist::ReadExResp 120125 # Transaction distribution 2053system.membus.trans_dist::ReadSharedReq 289973 # Transaction distribution 2054system.membus.trans_dist::BadAddressError 47 # Transaction distribution | 2050system.membus.trans_dist::ReadExReq 121549 # Transaction distribution 2051system.membus.trans_dist::ReadExResp 121146 # Transaction distribution 2052system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution 2053system.membus.trans_dist::BadAddressError 49 # Transaction distribution |
| 2055system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 2054system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 2056system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39176 # Packet count per connected master and slave (bytes) 2057system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1170427 # Packet count per connected master and slave (bytes) 2058system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) 2059system.membus.pkt_count_system.l2c.mem_side::total 1209697 # Packet count per connected master and slave (bytes) 2060system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83433 # Packet count per connected master and slave (bytes) 2061system.membus.pkt_count_system.iocache.mem_side::total 83433 # Packet count per connected master and slave (bytes) 2062system.membus.pkt_count::total 1293130 # Packet count per connected master and slave (bytes) 2063system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68530 # Cumulative packet size per connected master and slave (bytes) 2064system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31401600 # Cumulative packet size per connected master and slave (bytes) 2065system.membus.pkt_size_system.l2c.mem_side::total 31470130 # Cumulative packet size per connected master and slave (bytes) | 2055system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes) 2056system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes) 2057system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes) 2058system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes) 2059system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) 2060system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) 2061system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes) 2062system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes) 2063system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes) 2064system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes) |
| 2066system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 2067system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) | 2065system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 2066system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) |
| 2068system.membus.pkt_size::total 34128370 # Cumulative packet size per connected master and slave (bytes) 2069system.membus.snoops 4361 # Total snoops (count) 2070system.membus.snoopTraffic 28480 # Total snoop traffic (bytes) 2071system.membus.snoop_fanout::samples 478637 # Request fanout histogram 2072system.membus.snoop_fanout::mean 0.001444 # Request fanout histogram 2073system.membus.snoop_fanout::stdev 0.037968 # Request fanout histogram | 2067system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes) 2068system.membus.snoops 11676 # Total snoops (count) 2069system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) 2070system.membus.snoop_fanout::samples 484282 # Request fanout histogram 2071system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram 2072system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram |
| 2074system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2073system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2075system.membus.snoop_fanout::0 477946 99.86% 99.86% # Request fanout histogram 2076system.membus.snoop_fanout::1 691 0.14% 100.00% # Request fanout histogram | 2074system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram 2075system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram |
| 2077system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2078system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2079system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2080system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2076system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2077system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2078system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2079system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2081system.membus.snoop_fanout::total 478637 # Request fanout histogram 2082system.membus.reqLayer0.occupancy 34935499 # Layer occupancy (ticks) | 2080system.membus.snoop_fanout::total 484282 # Request fanout histogram 2081system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks) |
| 2083system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2082system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2084system.membus.reqLayer1.occupancy 1350989532 # Layer occupancy (ticks) | 2083system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks) |
| 2085system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 2084system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 2086system.membus.reqLayer2.occupancy 59500 # Layer occupancy (ticks) | 2085system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks) |
| 2087system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2086system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2088system.membus.respLayer1.occupancy 2172548749 # Layer occupancy (ticks) | 2087system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks) |
| 2089system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 2088system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 2090system.membus.respLayer2.occupancy 925113 # Layer occupancy (ticks) | 2089system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks) |
| 2091system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 2090system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2092system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2093system.toL2Bus.snoop_filter.tot_requests 5110475 # Total number of requests made to the snoop filter. 2094system.toL2Bus.snoop_filter.hit_single_requests 2554732 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2095system.toL2Bus.snoop_filter.hit_multi_requests 342217 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2096system.toL2Bus.snoop_filter.tot_snoops 1055 # Total number of snoops made to the snoop filter. 2097system.toL2Bus.snoop_filter.hit_single_snoops 987 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 2091system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2092system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter. 2093system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2094system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2095system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter. 2096system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 2098system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2097system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2099system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2100system.toL2Bus.trans_dist::ReadReq 7194 # Transaction distribution 2101system.toL2Bus.trans_dist::ReadResp 2261145 # Transaction distribution 2102system.toL2Bus.trans_dist::WriteReq 12394 # Transaction distribution 2103system.toL2Bus.trans_dist::WriteResp 12394 # Transaction distribution 2104system.toL2Bus.trans_dist::WritebackDirty 911435 # Transaction distribution 2105system.toL2Bus.trans_dist::WritebackClean 1144537 # Transaction distribution 2106system.toL2Bus.trans_dist::CleanEvict 834683 # Transaction distribution 2107system.toL2Bus.trans_dist::UpgradeReq 5633 # Transaction distribution 2108system.toL2Bus.trans_dist::SCUpgradeReq 1816 # Transaction distribution 2109system.toL2Bus.trans_dist::UpgradeResp 7449 # Transaction distribution 2110system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2111system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 2112system.toL2Bus.trans_dist::ReadExReq 302973 # Transaction distribution 2113system.toL2Bus.trans_dist::ReadExResp 302973 # Transaction distribution 2114system.toL2Bus.trans_dist::ReadCleanReq 1145857 # Transaction distribution 2115system.toL2Bus.trans_dist::ReadSharedReq 1108145 # Transaction distribution 2116system.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution 2117system.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution 2118system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3045120 # Packet count per connected master and slave (bytes) 2119system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4050284 # Packet count per connected master and slave (bytes) 2120system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 390880 # Packet count per connected master and slave (bytes) 2121system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 209583 # Packet count per connected master and slave (bytes) 2122system.toL2Bus.pkt_count::total 7695867 # Packet count per connected master and slave (bytes) 2123system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 129904512 # Cumulative packet size per connected master and slave (bytes) 2124system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 135990364 # Cumulative packet size per connected master and slave (bytes) 2125system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16664640 # Cumulative packet size per connected master and slave (bytes) 2126system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6622614 # Cumulative packet size per connected master and slave (bytes) 2127system.toL2Bus.pkt_size::total 289182130 # Cumulative packet size per connected master and slave (bytes) 2128system.toL2Bus.snoops 363206 # Total snoops (count) 2129system.toL2Bus.snoopTraffic 6121792 # Total snoop traffic (bytes) 2130system.toL2Bus.snoop_fanout::samples 2928698 # Request fanout histogram 2131system.toL2Bus.snoop_fanout::mean 0.120181 # Request fanout histogram 2132system.toL2Bus.snoop_fanout::stdev 0.325532 # Request fanout histogram | 2098system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2099system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution 2100system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution 2101system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution 2102system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution 2103system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution 2104system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution 2105system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution 2106system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution 2107system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution 2108system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution 2109system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution 2110system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution 2111system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution 2112system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution 2113system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution 2114system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution 2115system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes) 2116system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes) 2117system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes) 2118system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes) 2119system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes) 2120system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes) 2121system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes) 2122system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes) 2123system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes) 2124system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes) 2125system.toL2Bus.snoops 379909 # Total snoops (count) 2126system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes) 2127system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram 2128system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram 2129system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram |
| 2133system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2130system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2134system.toL2Bus.snoop_fanout::0 2577056 87.99% 87.99% # Request fanout histogram 2135system.toL2Bus.snoop_fanout::1 351320 12.00% 99.99% # Request fanout histogram 2136system.toL2Bus.snoop_fanout::2 312 0.01% 100.00% # Request fanout histogram 2137system.toL2Bus.snoop_fanout::3 10 0.00% 100.00% # Request fanout histogram | 2131system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram 2132system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram 2133system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram 2134system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram |
| 2138system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2139system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2140system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2141system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram | 2135system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2136system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2137system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2138system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| 2142system.toL2Bus.snoop_fanout::total 2928698 # Request fanout histogram 2143system.toL2Bus.reqLayer0.occupancy 4546181919 # Layer occupancy (ticks) | 2139system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram 2140system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks) |
| 2144system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 2141system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 2145system.toL2Bus.snoopLayer0.occupancy 291385 # Layer occupancy (ticks) | 2142system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) |
| 2146system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2143system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2147system.toL2Bus.respLayer0.occupancy 1524803969 # Layer occupancy (ticks) | 2144system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks) |
| 2148system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2145system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2149system.toL2Bus.respLayer1.occupancy 2026499354 # Layer occupancy (ticks) | 2146system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks) |
| 2150system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 2147system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 2151system.toL2Bus.respLayer2.occupancy 197300876 # Layer occupancy (ticks) | 2148system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks) |
| 2152system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2149system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2153system.toL2Bus.respLayer3.occupancy 108970290 # Layer occupancy (ticks) | 2150system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks) |
| 2154system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2151system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2155system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2156system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2157system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2158system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states | 2152system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2153system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2154system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2155system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states |
| 2159system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2160system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2161system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2162system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2163system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2164system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2165system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2166system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 2182system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2183system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2184system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2185system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2186system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2187system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2188system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2189system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 2156system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2157system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2158system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2159system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2160system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2161system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2162system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2163system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 2179system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2180system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2181system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2182system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2183system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2184system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2185system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2186system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 2190system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2191system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2192system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2193system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2194system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2195system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2196system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2197system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2198system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2199system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2200system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2201system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2202system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2203system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2204system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2205system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2206system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2207system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2208system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2209system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2210system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2211system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states 2212system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states | 2187system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2188system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2189system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2190system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2191system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2192system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2193system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2194system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2195system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2196system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2197system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2198system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2199system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2200system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2201system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2202system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2203system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2204system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2205system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2206system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2207system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2208system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states 2209system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states |
| 2213system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 2210system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 2214system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 2215system.cpu0.kern.inst.hwrei 197565 # number of hwrei instructions executed 2216system.cpu0.kern.ipl_count::0 70781 40.59% 40.59% # number of times we switched to this ipl 2217system.cpu0.kern.ipl_count::21 131 0.08% 40.66% # number of times we switched to this ipl 2218system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl 2219system.cpu0.kern.ipl_count::30 20 0.01% 41.78% # number of times we switched to this ipl 2220system.cpu0.kern.ipl_count::31 101534 58.22% 100.00% # number of times we switched to this ipl 2221system.cpu0.kern.ipl_count::total 174393 # number of times we switched to this ipl 2222system.cpu0.kern.ipl_good::0 69444 49.27% 49.27% # number of times we switched to this ipl from a different ipl 2223system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl 2224system.cpu0.kern.ipl_good::22 1927 1.37% 50.73% # number of times we switched to this ipl from a different ipl 2225system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl 2226system.cpu0.kern.ipl_good::31 69424 49.26% 100.00% # number of times we switched to this ipl from a different ipl 2227system.cpu0.kern.ipl_good::total 140946 # number of times we switched to this ipl from a different ipl 2228system.cpu0.kern.ipl_ticks::0 1863377945500 97.69% 97.69% # number of cycles we spent at this ipl 2229system.cpu0.kern.ipl_ticks::21 65817500 0.00% 97.70% # number of cycles we spent at this ipl 2230system.cpu0.kern.ipl_ticks::22 580544500 0.03% 97.73% # number of cycles we spent at this ipl 2231system.cpu0.kern.ipl_ticks::30 11361000 0.00% 97.73% # number of cycles we spent at this ipl 2232system.cpu0.kern.ipl_ticks::31 43328343000 2.27% 100.00% # number of cycles we spent at this ipl 2233system.cpu0.kern.ipl_ticks::total 1907364011500 # number of cycles we spent at this ipl 2234system.cpu0.kern.ipl_used::0 0.981111 # fraction of swpipl calls that actually changed the ipl | 2211system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed 2212system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed 2213system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl 2214system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl 2215system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl 2216system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl 2217system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl 2218system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl 2219system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl 2220system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl 2221system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl 2222system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl 2223system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl 2224system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl 2225system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl 2226system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl 2227system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl 2228system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl 2229system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl 2230system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl 2231system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl |
| 2235system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2236system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2237system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 2232system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2233system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2234system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 2238system.cpu0.kern.ipl_used::31 0.683751 # fraction of swpipl calls that actually changed the ipl 2239system.cpu0.kern.ipl_used::total 0.808209 # fraction of swpipl calls that actually changed the ipl 2240system.cpu0.kern.syscall::2 8 3.76% 3.76% # number of syscalls executed 2241system.cpu0.kern.syscall::3 18 8.45% 12.21% # number of syscalls executed 2242system.cpu0.kern.syscall::4 4 1.88% 14.08% # number of syscalls executed 2243system.cpu0.kern.syscall::6 32 15.02% 29.11% # number of syscalls executed 2244system.cpu0.kern.syscall::12 1 0.47% 29.58% # number of syscalls executed 2245system.cpu0.kern.syscall::17 8 3.76% 33.33% # number of syscalls executed 2246system.cpu0.kern.syscall::19 10 4.69% 38.03% # number of syscalls executed 2247system.cpu0.kern.syscall::20 6 2.82% 40.85% # number of syscalls executed 2248system.cpu0.kern.syscall::23 1 0.47% 41.31% # number of syscalls executed 2249system.cpu0.kern.syscall::24 3 1.41% 42.72% # number of syscalls executed 2250system.cpu0.kern.syscall::33 6 2.82% 45.54% # number of syscalls executed 2251system.cpu0.kern.syscall::41 2 0.94% 46.48% # number of syscalls executed 2252system.cpu0.kern.syscall::45 33 15.49% 61.97% # number of syscalls executed 2253system.cpu0.kern.syscall::47 3 1.41% 63.38% # number of syscalls executed 2254system.cpu0.kern.syscall::48 10 4.69% 68.08% # number of syscalls executed 2255system.cpu0.kern.syscall::54 10 4.69% 72.77% # number of syscalls executed 2256system.cpu0.kern.syscall::58 1 0.47% 73.24% # number of syscalls executed 2257system.cpu0.kern.syscall::59 6 2.82% 76.06% # number of syscalls executed 2258system.cpu0.kern.syscall::71 21 9.86% 85.92% # number of syscalls executed 2259system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed 2260system.cpu0.kern.syscall::74 5 2.35% 89.67% # number of syscalls executed 2261system.cpu0.kern.syscall::87 1 0.47% 90.14% # number of syscalls executed 2262system.cpu0.kern.syscall::90 3 1.41% 91.55% # number of syscalls executed 2263system.cpu0.kern.syscall::92 9 4.23% 95.77% # number of syscalls executed 2264system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed 2265system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed 2266system.cpu0.kern.syscall::132 1 0.47% 98.12% # number of syscalls executed 2267system.cpu0.kern.syscall::144 2 0.94% 99.06% # number of syscalls executed 2268system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed 2269system.cpu0.kern.syscall::total 213 # number of syscalls executed | 2235system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl 2236system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl 2237system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed 2238system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed 2239system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed 2240system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed 2241system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed 2242system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed 2243system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed 2244system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed 2245system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed 2246system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed 2247system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed 2248system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed 2249system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed 2250system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed 2251system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed 2252system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed 2253system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed 2254system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed 2255system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed 2256system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed 2257system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed 2258system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed 2259system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed 2260system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed 2261system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed 2262system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed 2263system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed 2264system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed 2265system.cpu0.kern.syscall::total 178 # number of syscalls executed |
| 2270system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 2266system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 2271system.cpu0.kern.callpal::wripir 120 0.07% 0.07% # number of callpals executed 2272system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2273system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2274system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 2275system.cpu0.kern.callpal::swpctx 3815 2.08% 2.15% # number of callpals executed 2276system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed 2277system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed 2278system.cpu0.kern.callpal::swpipl 167656 91.61% 93.80% # number of callpals executed 2279system.cpu0.kern.callpal::rdps 6177 3.38% 97.17% # number of callpals executed 2280system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed 2281system.cpu0.kern.callpal::wrusp 2 0.00% 97.17% # number of callpals executed 2282system.cpu0.kern.callpal::rdusp 9 0.00% 97.18% # number of callpals executed 2283system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed 2284system.cpu0.kern.callpal::rti 4658 2.55% 99.72% # number of callpals executed 2285system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed 2286system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 2287system.cpu0.kern.callpal::total 183007 # number of callpals executed 2288system.cpu0.kern.mode_switch::kernel 7158 # number of protection mode switches 2289system.cpu0.kern.mode_switch::user 1253 # number of protection mode switches | 2267system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed 2268system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed 2269system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed 2270system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed 2271system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed 2272system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed 2273system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed 2274system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed 2275system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed 2276system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed 2277system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed 2278system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed 2279system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed 2280system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed 2281system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed 2282system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed 2283system.cpu0.kern.callpal::total 165676 # number of callpals executed 2284system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches 2285system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches |
| 2290system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 2286system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 2291system.cpu0.kern.mode_good::kernel 1253 2292system.cpu0.kern.mode_good::user 1253 | 2287system.cpu0.kern.mode_good::kernel 1097 2288system.cpu0.kern.mode_good::user 1097 |
| 2293system.cpu0.kern.mode_good::idle 0 | 2289system.cpu0.kern.mode_good::idle 0 |
| 2294system.cpu0.kern.mode_switch_good::kernel 0.175049 # fraction of useful protection mode switches | 2290system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches |
| 2295system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2296system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 2291system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2292system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 2297system.cpu0.kern.mode_switch_good::total 0.297943 # fraction of useful protection mode switches 2298system.cpu0.kern.mode_ticks::kernel 1905453819000 99.90% 99.90% # number of ticks spent at the given mode 2299system.cpu0.kern.mode_ticks::user 1901068000 0.10% 100.00% # number of ticks spent at the given mode | 2293system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches 2294system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode 2295system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode |
| 2300system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 2296system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 2301system.cpu0.kern.swap_context 3816 # number of times the context was actually changed | 2297system.cpu0.kern.swap_context 3400 # number of times the context was actually changed |
| 2302system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2298system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2303system.cpu1.kern.inst.quiesce 2323 # number of quiesce instructions executed 2304system.cpu1.kern.inst.hwrei 40320 # number of hwrei instructions executed 2305system.cpu1.kern.ipl_count::0 10930 33.84% 33.84% # number of times we switched to this ipl 2306system.cpu1.kern.ipl_count::22 1925 5.96% 39.80% # number of times we switched to this ipl 2307system.cpu1.kern.ipl_count::30 120 0.37% 40.18% # number of times we switched to this ipl 2308system.cpu1.kern.ipl_count::31 19320 59.82% 100.00% # number of times we switched to this ipl 2309system.cpu1.kern.ipl_count::total 32295 # number of times we switched to this ipl 2310system.cpu1.kern.ipl_good::0 10890 45.94% 45.94% # number of times we switched to this ipl from a different ipl 2311system.cpu1.kern.ipl_good::22 1925 8.12% 54.06% # number of times we switched to this ipl from a different ipl 2312system.cpu1.kern.ipl_good::30 120 0.51% 54.57% # number of times we switched to this ipl from a different ipl 2313system.cpu1.kern.ipl_good::31 10770 45.43% 100.00% # number of times we switched to this ipl from a different ipl 2314system.cpu1.kern.ipl_good::total 23705 # number of times we switched to this ipl from a different ipl 2315system.cpu1.kern.ipl_ticks::0 1876314481500 98.36% 98.36% # number of cycles we spent at this ipl 2316system.cpu1.kern.ipl_ticks::22 564739500 0.03% 98.39% # number of cycles we spent at this ipl 2317system.cpu1.kern.ipl_ticks::30 58247500 0.00% 98.39% # number of cycles we spent at this ipl 2318system.cpu1.kern.ipl_ticks::31 30733817000 1.61% 100.00% # number of cycles we spent at this ipl 2319system.cpu1.kern.ipl_ticks::total 1907671285500 # number of cycles we spent at this ipl 2320system.cpu1.kern.ipl_used::0 0.996340 # fraction of swpipl calls that actually changed the ipl | 2299system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed 2300system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed 2301system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl 2302system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl 2303system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl 2304system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl 2305system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl 2306system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl 2307system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl 2308system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl 2309system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl 2310system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl 2311system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl 2312system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl 2313system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl 2314system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl 2315system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl 2316system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl |
| 2321system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2322system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 2317system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2318system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 2323system.cpu1.kern.ipl_used::31 0.557453 # fraction of swpipl calls that actually changed the ipl 2324system.cpu1.kern.ipl_used::total 0.734015 # fraction of swpipl calls that actually changed the ipl 2325system.cpu1.kern.syscall::3 12 10.62% 10.62% # number of syscalls executed 2326system.cpu1.kern.syscall::6 10 8.85% 19.47% # number of syscalls executed 2327system.cpu1.kern.syscall::15 1 0.88% 20.35% # number of syscalls executed 2328system.cpu1.kern.syscall::17 7 6.19% 26.55% # number of syscalls executed 2329system.cpu1.kern.syscall::23 3 2.65% 29.20% # number of syscalls executed 2330system.cpu1.kern.syscall::24 3 2.65% 31.86% # number of syscalls executed 2331system.cpu1.kern.syscall::33 5 4.42% 36.28% # number of syscalls executed 2332system.cpu1.kern.syscall::45 21 18.58% 54.87% # number of syscalls executed 2333system.cpu1.kern.syscall::47 3 2.65% 57.52% # number of syscalls executed 2334system.cpu1.kern.syscall::59 1 0.88% 58.41% # number of syscalls executed 2335system.cpu1.kern.syscall::71 33 29.20% 87.61% # number of syscalls executed 2336system.cpu1.kern.syscall::74 11 9.73% 97.35% # number of syscalls executed 2337system.cpu1.kern.syscall::132 3 2.65% 100.00% # number of syscalls executed 2338system.cpu1.kern.syscall::total 113 # number of syscalls executed | 2319system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl 2320system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl 2321system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed 2322system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed 2323system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed 2324system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed 2325system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed 2326system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed 2327system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed 2328system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed 2329system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed 2330system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed 2331system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed 2332system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed 2333system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed 2334system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed 2335system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed 2336system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed 2337system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed 2338system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed 2339system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed 2340system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed 2341system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed 2342system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed 2343system.cpu1.kern.syscall::total 148 # number of syscalls executed |
| 2339system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 2344system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 2340system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed 2341system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2342system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2343system.cpu1.kern.callpal::swpctx 449 1.34% 1.41% # number of callpals executed 2344system.cpu1.kern.callpal::tbi 3 0.01% 1.42% # number of callpals executed 2345system.cpu1.kern.callpal::wrent 7 0.02% 1.44% # number of callpals executed 2346system.cpu1.kern.callpal::swpipl 27672 82.56% 84.00% # number of callpals executed 2347system.cpu1.kern.callpal::rdps 2585 7.71% 91.71% # number of callpals executed 2348system.cpu1.kern.callpal::wrkgp 1 0.00% 91.71% # number of callpals executed 2349system.cpu1.kern.callpal::wrusp 5 0.01% 91.73% # number of callpals executed 2350system.cpu1.kern.callpal::whami 3 0.01% 91.74% # number of callpals executed 2351system.cpu1.kern.callpal::rti 2577 7.69% 99.42% # number of callpals executed 2352system.cpu1.kern.callpal::callsys 148 0.44% 99.87% # number of callpals executed 2353system.cpu1.kern.callpal::imb 44 0.13% 100.00% # number of callpals executed | 2345system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed 2346system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 2347system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 2348system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed 2349system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed 2350system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed 2351system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed 2352system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed 2353system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed 2354system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed 2355system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed 2356system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed 2357system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed 2358system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed 2359system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed |
| 2354system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 2360system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 2355system.cpu1.kern.callpal::total 33518 # number of callpals executed 2356system.cpu1.kern.mode_switch::kernel 911 # number of protection mode switches 2357system.cpu1.kern.mode_switch::user 493 # number of protection mode switches 2358system.cpu1.kern.mode_switch::idle 2088 # number of protection mode switches 2359system.cpu1.kern.mode_good::kernel 538 2360system.cpu1.kern.mode_good::user 493 2361system.cpu1.kern.mode_good::idle 45 2362system.cpu1.kern.mode_switch_good::kernel 0.590560 # fraction of useful protection mode switches | 2361system.cpu1.kern.callpal::total 52290 # number of callpals executed 2362system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches 2363system.cpu1.kern.mode_switch::user 640 # number of protection mode switches 2364system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches 2365system.cpu1.kern.mode_good::kernel 844 2366system.cpu1.kern.mode_good::user 640 2367system.cpu1.kern.mode_good::idle 204 2368system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches |
| 2363system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 2369system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 2364system.cpu1.kern.mode_switch_good::idle 0.021552 # fraction of useful protection mode switches 2365system.cpu1.kern.mode_switch_good::total 0.308133 # fraction of useful protection mode switches 2366system.cpu1.kern.mode_ticks::kernel 2257888000 0.12% 0.12% # number of ticks spent at the given mode 2367system.cpu1.kern.mode_ticks::user 790670500 0.04% 0.16% # number of ticks spent at the given mode 2368system.cpu1.kern.mode_ticks::idle 1904622719000 99.84% 100.00% # number of ticks spent at the given mode 2369system.cpu1.kern.swap_context 450 # number of times the context was actually changed | 2370system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches 2371system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches 2372system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode 2373system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode 2374system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode 2375system.cpu1.kern.swap_context 1167 # number of times the context was actually changed |
| 2370 2371---------- End Simulation Statistics ---------- | 2376 2377---------- End Simulation Statistics ---------- |