| stats.txt (10798:74e3c7359393) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.904438 # Number of seconds simulated 4sim_ticks 1904437574000 # Number of ticks simulated 5final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.904438 # Number of seconds simulated 4sim_ticks 1904437574000 # Number of ticks simulated 5final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 143053 # Simulator instruction rate (inst/s) 8host_op_rate 143053 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4814720142 # Simulator tick rate (ticks/s) 10host_mem_usage 313028 # Number of bytes of host memory used 11host_seconds 395.54 # Real time elapsed on the host | 7host_inst_rate 149880 # Simulator instruction rate (inst/s) 8host_op_rate 149880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5044505517 # Simulator tick rate (ticks/s) 10host_mem_usage 380636 # Number of bytes of host memory used 11host_seconds 377.53 # Real time elapsed on the host |
| 12sim_insts 56583768 # Number of instructions simulated 13sim_ops 56583768 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory --- 755 unchanged lines hidden (view full) --- 775system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses 776system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses 780system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses 782system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses | 12sim_insts 56583768 # Number of instructions simulated 13sim_ops 56583768 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory --- 755 unchanged lines hidden (view full) --- 775system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses 776system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses 780system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses 782system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses |
| 783system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable 784system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable 785system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable 786system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable 787system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses 788system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses |
|
| 783system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles 784system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 817system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency 818system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency 819system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency 820system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency 821system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 822system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency 823system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 824system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency | 789system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles 790system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles 791system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles 792system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles 793system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles 794system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles 795system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles 796system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 823system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency 830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency |
| 825system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 826system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 827system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 828system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 829system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 830system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency |
| 831system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 832system.cpu0.icache.tags.replacements 911417 # number of replacements 833system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use 834system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. 835system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. 836system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. 837system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. 838system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor --- 533 unchanged lines hidden (view full) --- 1372system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses 1373system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses 1374system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses 1375system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses 1376system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses 1377system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses 1378system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses 1379system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses | 837system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 838system.cpu0.icache.tags.replacements 911417 # number of replacements 839system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor --- 533 unchanged lines hidden (view full) --- 1378system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses 1379system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses 1380system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses 1381system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses 1382system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses 1383system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses 1384system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses 1385system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses |
| 1386system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable 1387system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable 1388system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable 1389system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable 1390system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses 1391system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses |
|
| 1380system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles 1381system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles 1382system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles 1383system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles 1384system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles 1385system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles 1386system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles 1387system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 1414system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency 1415system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency 1416system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency 1417system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency 1418system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 1419system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency 1420system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 1421system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency | 1392system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles 1393system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles 1394system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles 1395system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles 1396system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles 1397system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles 1398system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles 1399system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 1426system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency 1427system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency 1428system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency 1429system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency 1430system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 1431system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency 1432system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency 1433system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency |
| 1422system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1423system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1424system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1425system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1426system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1427system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1434system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency 1435system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency 1436system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency 1437system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency 1438system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency 1439system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency |
| 1428system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1429system.cpu1.icache.tags.replacements 211356 # number of replacements 1430system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use 1431system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. 1432system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. 1433system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. 1434system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. 1435system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor --- 473 unchanged lines hidden (view full) --- 1909system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses 1910system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses 1911system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses 1912system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses 1913system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses 1914system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses 1915system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses 1916system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses | 1440system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1441system.cpu1.icache.tags.replacements 211356 # number of replacements 1442system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use 1443system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. 1444system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. 1445system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. 1446system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. 1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor --- 473 unchanged lines hidden (view full) --- 1921system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses 1922system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses 1923system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses 1924system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses 1925system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses 1926system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses 1927system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses 1928system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses |
| 1929system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable 1930system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable 1931system.l2c.ReadReq_mshr_uncacheable::total 7197 # number of ReadReq MSHR uncacheable 1932system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable 1933system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable 1934system.l2c.WriteReq_mshr_uncacheable::total 12925 # number of WriteReq MSHR uncacheable 1935system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses 1936system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses 1937system.l2c.overall_mshr_uncacheable_misses::total 20122 # number of overall MSHR uncacheable misses |
|
| 1917system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles 1918system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles 1919system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles 1920system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles 1921system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles 1922system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles 1923system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles 1924system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles --- 65 unchanged lines hidden (view full) --- 1990system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 1991system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 1992system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency 1993system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency 1994system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency 1995system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 1996system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 1997system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency | 1938system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles 1939system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles 1940system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles 1941system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles 1942system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles 1943system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles 1944system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles 1945system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles --- 65 unchanged lines hidden (view full) --- 2011system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 2012system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 2013system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency 2014system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency 2015system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency 2016system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency 2017system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency 2018system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency |
| 1998system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1999system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2000system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2001system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2002system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2003system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2004system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2005system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2006system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2019system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194007.671544 # average ReadReq mshr uncacheable latency 2020system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171632.911392 # average ReadReq mshr uncacheable latency 2021system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193516.465194 # average ReadReq mshr uncacheable latency 2022system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 199279.057018 # average WriteReq mshr uncacheable latency 2023system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204473.902523 # average WriteReq mshr uncacheable latency 2024system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 200441.818182 # average WriteReq mshr uncacheable latency 2025system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 197105.471267 # average overall mshr uncacheable latency 2026system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 202773.189118 # average overall mshr uncacheable latency 2027system.l2c.overall_avg_mshr_uncacheable_latency::total 197964.839479 # average overall mshr uncacheable latency |
| 2007system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2008system.membus.trans_dist::ReadReq 296650 # Transaction distribution 2009system.membus.trans_dist::ReadResp 296572 # Transaction distribution 2010system.membus.trans_dist::WriteReq 12925 # Transaction distribution 2011system.membus.trans_dist::WriteResp 12925 # Transaction distribution 2012system.membus.trans_dist::Writeback 124744 # Transaction distribution 2013system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 2014system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution --- 12 unchanged lines hidden (view full) --- 2027system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) 2028system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) 2029system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) 2030system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) 2031system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 2032system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 2033system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) 2034system.membus.snoops 10437 # Total snoops (count) | 2028system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2029system.membus.trans_dist::ReadReq 296650 # Transaction distribution 2030system.membus.trans_dist::ReadResp 296572 # Transaction distribution 2031system.membus.trans_dist::WriteReq 12925 # Transaction distribution 2032system.membus.trans_dist::WriteResp 12925 # Transaction distribution 2033system.membus.trans_dist::Writeback 124744 # Transaction distribution 2034system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 2035system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution --- 12 unchanged lines hidden (view full) --- 2048system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) 2049system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) 2050system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) 2051system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) 2052system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 2053system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 2054system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) 2055system.membus.snoops 10437 # Total snoops (count) |
| 2035system.membus.snoop_fanout::samples 594010 # Request fanout histogram | 2056system.membus.snoop_fanout::samples 614132 # Request fanout histogram |
| 2036system.membus.snoop_fanout::mean 1 # Request fanout histogram 2037system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2038system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2039system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2057system.membus.snoop_fanout::mean 1 # Request fanout histogram 2058system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2059system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2060system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2040system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram | 2061system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram |
| 2041system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2042system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2043system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2044system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2062system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2063system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2064system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2065system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2045system.membus.snoop_fanout::total 594010 # Request fanout histogram | 2066system.membus.snoop_fanout::total 614132 # Request fanout histogram |
| 2046system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) 2047system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2048system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) 2049system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 2050system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) 2051system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2052system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) 2053system.membus.respLayer1.utilization 0.1 # Layer utilization (%) --- 17 unchanged lines hidden (view full) --- 2071system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) 2072system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) 2073system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) 2074system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) 2075system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) 2076system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) 2077system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) 2078system.toL2Bus.snoops 72565 # Total snoops (count) | 2067system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) 2068system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2069system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) 2070system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 2071system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) 2072system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2073system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) 2074system.membus.respLayer1.utilization 0.1 # Layer utilization (%) --- 17 unchanged lines hidden (view full) --- 2092system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) 2093system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) 2094system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) 2095system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) 2096system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) 2097system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) 2098system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) 2099system.toL2Bus.snoops 72565 # Total snoops (count) |
| 2079system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram 2080system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram 2081system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram | 2100system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram 2101system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram 2102system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram |
| 2082system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2083system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2084system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2085system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 2103system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2104system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2105system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2106system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 2086system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram 2087system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram | 2107system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram 2108system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram |
| 2088system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2089system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2090system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 2109system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2110system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2111system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 2091system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram | 2112system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram |
| 2092system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) 2093system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2094system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) 2095system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2096system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) 2097system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2098system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) 2099system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 204 unchanged lines hidden --- | 2113system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) 2114system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2115system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) 2116system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2117system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) 2118system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2119system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) 2120system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 204 unchanged lines hidden --- |