| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.904438 # Number of seconds simulated 4sim_ticks 1904437574000 # Number of ticks simulated 5final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 150033 # Simulator instruction rate (inst/s) 8host_op_rate 150033 # Simulator op (including micro ops) rate (op/s) --- 631 unchanged lines hidden (view full) --- 640system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction 642system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction 643system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction 644system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction 645system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 646system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction 647system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.904438 # Number of seconds simulated 4sim_ticks 1904437574000 # Number of ticks simulated 5final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 150033 # Simulator instruction rate (inst/s) 8host_op_rate 150033 # Simulator op (including micro ops) rate (op/s) --- 631 unchanged lines hidden (view full) --- 640system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction 642system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction 643system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction 644system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction 645system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 646system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction 647system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached |
| 648system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 649system.cpu0.rob.rob_reads 165216916 # The number of ROB reads 650system.cpu0.rob.rob_writes 117798939 # The number of ROB writes 651system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself 652system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling 653system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 654system.cpu0.committedInsts 48375955 # Number of Instructions Simulated 655system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated 656system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction --- 579 unchanged lines hidden (view full) --- 1236system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction 1237system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction 1238system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction 1239system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction 1240system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction 1241system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1242system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction 1243system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached | 648system.cpu0.rob.rob_reads 165216916 # The number of ROB reads 649system.cpu0.rob.rob_writes 117798939 # The number of ROB writes 650system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself 651system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling 652system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 653system.cpu0.committedInsts 48375955 # Number of Instructions Simulated 654system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated 655system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction --- 579 unchanged lines hidden (view full) --- 1235system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction 1236system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction 1237system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction 1238system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction 1239system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction 1240system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1241system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction 1242system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached |
| 1244system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 1245system.cpu1.rob.rob_reads 23176968 # The number of ROB reads 1246system.cpu1.rob.rob_writes 20704388 # The number of ROB writes 1247system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself 1248system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling 1249system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1250system.cpu1.committedInsts 8207813 # Number of Instructions Simulated 1251system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated 1252system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction --- 1053 unchanged lines hidden --- | 1243system.cpu1.rob.rob_reads 23176968 # The number of ROB reads 1244system.cpu1.rob.rob_writes 20704388 # The number of ROB writes 1245system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself 1246system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling 1247system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1248system.cpu1.committedInsts 8207813 # Number of Instructions Simulated 1249system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated 1250system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction --- 1053 unchanged lines hidden --- |