| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.905068 # Number of seconds simulated 4sim_ticks 1905067807000 # Number of ticks simulated 5final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.905068 # Number of seconds simulated 4sim_ticks 1905067807000 # Number of ticks simulated 5final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 133407 # Simulator instruction rate (inst/s) 8host_op_rate 133407 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4441980470 # Simulator tick rate (ticks/s) 10host_mem_usage 322876 # Number of bytes of host memory used 11host_seconds 428.88 # Real time elapsed on the host | 7host_inst_rate 163944 # Simulator instruction rate (inst/s) 8host_op_rate 163944 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5458738398 # Simulator tick rate (ticks/s) 10host_mem_usage 318552 # Number of bytes of host memory used 11host_seconds 348.99 # Real time elapsed on the host |
| 12sim_insts 57215334 # Number of instructions simulated 13sim_ops 57215334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory --- 714 unchanged lines hidden (view full) --- 734system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.iocache.blocked::no_targets 0 # number of cycles access was blocked 736system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.iocache.fast_writes 41552 # number of fast writes performed 739system.iocache.cache_copies 0 # number of cache copies performed 740system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 741system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses | 12sim_insts 57215334 # Number of instructions simulated 13sim_ops 57215334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory --- 714 unchanged lines hidden (view full) --- 734system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.iocache.blocked::no_targets 0 # number of cycles access was blocked 736system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.iocache.fast_writes 41552 # number of fast writes performed 739system.iocache.cache_copies 0 # number of cache copies performed 740system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses 741system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses |
| 742system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 743system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | |
| 744system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses 745system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses 746system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses 747system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses 748system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles 749system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles 750system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles 751system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles 752system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles 753system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles 754system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles 755system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles 756system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 757system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 742system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses 743system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses 744system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses 745system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses 746system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles 747system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles 748system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles 749system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles 750system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles 751system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles 752system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles 753system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles 754system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 755system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 758system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses 759system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses | |
| 760system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 761system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 762system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 763system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 764system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency 765system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency | 756system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 757system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 758system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 759system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 760system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency 761system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency |
| 766system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency 767system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency | 762system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 763system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 768system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency 769system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency 770system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency 771system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency 772system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 773system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 774system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 775system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 1508 unchanged lines hidden --- | 764system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency 765system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency 766system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency 767system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency 768system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 770system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 771system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 1508 unchanged lines hidden --- |