1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.929078 # Number of seconds simulated 4sim_ticks 1929077876500 # Number of ticks simulated 5final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 169237 # Simulator instruction rate (inst/s) 8host_op_rate 169237 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5749129790 # Simulator tick rate (ticks/s) |
10host_mem_usage 339544 # Number of bytes of host memory used |
11host_seconds 335.54 # Real time elapsed on the host |
12sim_insts 56786201 # Number of instructions simulated 13sim_ops 56786201 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory --- 721 unchanged lines hidden (view full) --- 741system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency 742system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency 743system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked 744system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked 745system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked 746system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked 747system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked 748system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked |
749system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks 750system.cpu0.dcache.writebacks::total 741086 # number of writebacks 751system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits 752system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits 753system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits 754system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits 755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits 756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles 786system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles |
793system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles |
795system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses 796system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses 800system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses 801system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses 802system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses --- 10 unchanged lines hidden (view full) --- 813system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency 814system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency 815system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 816system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 817system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 818system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 819system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency 820system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency |
821system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency 822system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency |
823system.cpu0.icache.tags.replacements 911237 # number of replacements 824system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use 825system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. 826system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. 827system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. 828system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. 829system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor 830system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 872system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency 873system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency 874system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked 875system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 876system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked 877system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 878system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked 879system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
880system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks 881system.cpu0.icache.writebacks::total 911237 # number of writebacks 882system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits 883system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits 884system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits 885system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits 886system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits 887system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 904system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses 905system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses 906system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency 907system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency 908system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 909system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency 910system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 911system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency |
912system.cpu1.branchPred.lookups 4129053 # Number of BP lookups 913system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted 914system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect 915system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups 916system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits 917system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 918system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage 919system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. --- 417 unchanged lines hidden (view full) --- 1337system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency 1338system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency 1339system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked 1340system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked 1341system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked 1342system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked 1343system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked 1344system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked |
1345system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks 1346system.cpu1.dcache.writebacks::total 79554 # number of writebacks 1347system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits 1348system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits 1349system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits 1350system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits 1351system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits 1352system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 1381system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles 1382system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles 1383system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles 1384system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles 1385system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles 1386system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles 1387system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles 1388system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles |
1389system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles 1390system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles |
1391system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses 1392system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses 1393system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses 1394system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses 1395system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses 1396system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses 1397system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses 1398system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses --- 10 unchanged lines hidden (view full) --- 1409system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency 1410system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency 1411system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1412system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1413system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1414system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1415system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency 1416system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency |
1417system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency 1418system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency |
1419system.cpu1.icache.tags.replacements 244089 # number of replacements 1420system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use 1421system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. 1422system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. 1423system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. 1424system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. 1425system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor 1426system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1469system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency 1470system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency 1471system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked 1472system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1473system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked 1474system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1475system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked 1476system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1477system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks 1478system.cpu1.icache.writebacks::total 244089 # number of writebacks 1479system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits 1480system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits 1481system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits 1482system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits 1483system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits 1484system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 1501system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses 1502system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses 1503system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency 1504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency 1505system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1506system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency 1507system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1508system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency |
1509system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1510system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1511system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1512system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1513system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1514system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1515system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1516system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). --- 68 unchanged lines hidden (view full) --- 1585system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1586system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1587system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1588system.iocache.tags.data_accesses 375543 # Number of data accesses 1589system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1590system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1591system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1592system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
1593system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 1594system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 1595system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 1596system.iocache.overall_misses::total 41727 # number of overall misses |
1597system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles 1598system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles 1599system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles 1600system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles |
1601system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles 1602system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles 1603system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles 1604system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles |
1605system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1606system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1607system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1608system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
1609system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 1610system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 1611system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 1612system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses |
1613system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1614system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1615system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1616system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1617system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1618system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1619system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1620system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1621system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency 1622system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency 1623system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency 1624system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency |
1625system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency 1626system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency 1627system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency 1628system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency |
1629system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1630system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1631system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1632system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1633system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1634system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1635system.iocache.writebacks::writebacks 41520 # number of writebacks 1636system.iocache.writebacks::total 41520 # number of writebacks 1637system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1638system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1639system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1640system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
1641system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses 1642system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses 1643system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses 1644system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses |
1645system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles 1646system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles 1647system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles 1648system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles |
1649system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles 1650system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles 1651system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles 1652system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles |
1653system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1654system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1655system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1656system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1657system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1658system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1659system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1660system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1661system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency 1662system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency 1663system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency 1664system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency |
1665system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency 1666system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency 1667system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency 1668system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency |
1669system.l2c.tags.replacements 345263 # number of replacements 1670system.l2c.tags.tagsinuse 65201.794559 # Cycle average of tags in use 1671system.l2c.tags.total_refs 4034348 # Total number of references to valid blocks. 1672system.l2c.tags.sampled_refs 410346 # Sample count of references to valid blocks. 1673system.l2c.tags.avg_refs 9.831576 # Average number of references to valid blocks. 1674system.l2c.tags.warmup_cycle 11176866000 # Cycle when the warmup percentage was hit. 1675system.l2c.tags.occ_blocks::writebacks 52690.467957 # Average occupied blocks per requestor 1676system.l2c.tags.occ_blocks::cpu0.inst 5287.969178 # Average occupied blocks per requestor --- 174 unchanged lines hidden (view full) --- 1851system.l2c.overall_avg_miss_latency::cpu1.data 158658.284709 # average overall miss latency 1852system.l2c.overall_avg_miss_latency::total 129335.602509 # average overall miss latency 1853system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1854system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1855system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1856system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1857system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1858system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1859system.l2c.writebacks::writebacks 81472 # number of writebacks 1860system.l2c.writebacks::total 81472 # number of writebacks 1861system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 1862system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits 1863system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 1864system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 1865system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 1866system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits --- 59 unchanged lines hidden (view full) --- 1926system.l2c.overall_mshr_miss_latency::cpu0.inst 1664693504 # number of overall MSHR miss cycles 1927system.l2c.overall_mshr_miss_latency::cpu0.data 45548475508 # number of overall MSHR miss cycles 1928system.l2c.overall_mshr_miss_latency::cpu1.inst 243245008 # number of overall MSHR miss cycles 1929system.l2c.overall_mshr_miss_latency::cpu1.data 1605061504 # number of overall MSHR miss cycles 1930system.l2c.overall_mshr_miss_latency::total 49061475524 # number of overall MSHR miss cycles 1931system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471043500 # number of ReadReq MSHR uncacheable cycles 1932system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30151000 # number of ReadReq MSHR uncacheable cycles 1933system.l2c.ReadReq_mshr_uncacheable_latency::total 1501194500 # number of ReadReq MSHR uncacheable cycles |
1934system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles 1935system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles 1936system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles |
1937system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1938system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1939system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941646 # mshr miss rate for UpgradeReq accesses 1940system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783217 # mshr miss rate for UpgradeReq accesses 1941system.l2c.UpgradeReq_mshr_miss_rate::total 0.889069 # mshr miss rate for UpgradeReq accesses 1942system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.871486 # mshr miss rate for SCUpgradeReq accesses 1943system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.941053 # mshr miss rate for SCUpgradeReq accesses 1944system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905447 # mshr miss rate for SCUpgradeReq accesses --- 39 unchanged lines hidden (view full) --- 1984system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124407.256857 # average overall mshr miss latency 1985system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118316.948095 # average overall mshr miss latency 1986system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126492.463859 # average overall mshr miss latency 1987system.l2c.overall_avg_mshr_miss_latency::cpu1.data 148658.099843 # average overall mshr miss latency 1988system.l2c.overall_avg_mshr_miss_latency::total 119350.368973 # average overall mshr miss latency 1989system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency 1990system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency 1991system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency |
1992system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency 1993system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency 1994system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency |
1995system.membus.trans_dist::ReadReq 7193 # Transaction distribution 1996system.membus.trans_dist::ReadResp 297247 # Transaction distribution 1997system.membus.trans_dist::WriteReq 13095 # Transaction distribution 1998system.membus.trans_dist::WriteResp 13095 # Transaction distribution 1999system.membus.trans_dist::WritebackDirty 122992 # Transaction distribution 2000system.membus.trans_dist::CleanEvict 263076 # Transaction distribution 2001system.membus.trans_dist::UpgradeReq 10346 # Transaction distribution 2002system.membus.trans_dist::SCUpgradeReq 5952 # Transaction distribution --- 298 unchanged lines hidden --- |