Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

Deleted Added

sdiff udiff text old ( 9978:81d7551dd3be ) new ( 9988:0b2e590c85be )

full compact

3,5c3,5
< sim_seconds 1.904665 # Number of seconds simulated
< sim_ticks 1904665099500 # Number of ticks simulated
< final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.903338 # Number of seconds simulated
> sim_ticks 1903338216000 # Number of ticks simulated
> final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,60c7,60
< host_inst_rate 126318 # Simulator instruction rate (inst/s)
< host_op_rate 126318 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4285588150 # Simulator tick rate (ticks/s)
< host_mem_usage 339596 # Number of bytes of host memory used
< host_seconds 444.44 # Real time elapsed on the host
< sim_insts 56140339 # Number of instructions simulated
< sim_ops 56140339 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory
< system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory
< system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 450624 # Number of read requests accepted
< system.physmem.writeReqs 122060 # Number of write requests accepted
< system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue
---
> host_inst_rate 100362 # Simulator instruction rate (inst/s)
> host_op_rate 100362 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3404824916 # Simulator tick rate (ticks/s)
> host_mem_usage 359096 # Number of bytes of host memory used
> host_seconds 559.01 # Real time elapsed on the host
> sim_insts 56103611 # Number of instructions simulated
> sim_ops 56103611 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory
> system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory
> system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 452659 # Number of read requests accepted
> system.physmem.writeReqs 123811 # Number of write requests accepted
> system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue
62,94c62,94
< system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 28171 # Per bank write bursts
< system.physmem.perBankRdBursts::1 27944 # Per bank write bursts
< system.physmem.perBankRdBursts::2 28133 # Per bank write bursts
< system.physmem.perBankRdBursts::3 27978 # Per bank write bursts
< system.physmem.perBankRdBursts::4 27881 # Per bank write bursts
< system.physmem.perBankRdBursts::5 28082 # Per bank write bursts
< system.physmem.perBankRdBursts::6 28123 # Per bank write bursts
< system.physmem.perBankRdBursts::7 28118 # Per bank write bursts
< system.physmem.perBankRdBursts::8 28377 # Per bank write bursts
< system.physmem.perBankRdBursts::9 28284 # Per bank write bursts
< system.physmem.perBankRdBursts::10 27947 # Per bank write bursts
< system.physmem.perBankRdBursts::11 28190 # Per bank write bursts
< system.physmem.perBankRdBursts::12 28259 # Per bank write bursts
< system.physmem.perBankRdBursts::13 28280 # Per bank write bursts
< system.physmem.perBankRdBursts::14 28300 # Per bank write bursts
< system.physmem.perBankRdBursts::15 28502 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7913 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7477 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7607 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7420 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7384 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7571 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7682 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7471 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7660 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7641 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7379 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7517 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7673 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7762 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7923 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7975 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 28542 # Per bank write bursts
> system.physmem.perBankRdBursts::1 28115 # Per bank write bursts
> system.physmem.perBankRdBursts::2 28449 # Per bank write bursts
> system.physmem.perBankRdBursts::3 28319 # Per bank write bursts
> system.physmem.perBankRdBursts::4 28001 # Per bank write bursts
> system.physmem.perBankRdBursts::5 28388 # Per bank write bursts
> system.physmem.perBankRdBursts::6 28437 # Per bank write bursts
> system.physmem.perBankRdBursts::7 28681 # Per bank write bursts
> system.physmem.perBankRdBursts::8 28670 # Per bank write bursts
> system.physmem.perBankRdBursts::9 28576 # Per bank write bursts
> system.physmem.perBankRdBursts::10 28034 # Per bank write bursts
> system.physmem.perBankRdBursts::11 27899 # Per bank write bursts
> system.physmem.perBankRdBursts::12 27884 # Per bank write bursts
> system.physmem.perBankRdBursts::13 28245 # Per bank write bursts
> system.physmem.perBankRdBursts::14 28268 # Per bank write bursts
> system.physmem.perBankRdBursts::15 28092 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8222 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7571 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7821 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7782 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7428 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7859 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7924 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7992 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7912 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7920 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7418 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7297 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7319 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7829 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7922 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7585 # Per bank write bursts
96,97c96,97
< system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
< system.physmem.totGap 1904663535000 # Total gap between requests
---
> system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
> system.physmem.totGap 1903333578000 # Total gap between requests
104c104
< system.physmem.readPktSize::6 450624 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 452659 # Read request sizes (log2)
111,127c111,127
< system.physmem.writePktSize::6 122060 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 123811 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see
129,135c129,135
< system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
144,173c144,173
< system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
175,337c175,338
< system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation
339,353c340,350
< system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation
355,374c352,367
< system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation
< system.physmem.totQLat 8608105750 # Total ticks spent queuing
< system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks
< system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation
> system.physmem.totQLat 8783315250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks
> system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst
376,380c369,373
< system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s
386,392c379,385
< system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing
< system.physmem.readRowHits 429097 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97193 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes
< system.physmem.avgGap 3325854.28 # Average gap between requests
< system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined
---
> system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing
> system.physmem.readRowHits 430734 # Number of row buffer hits during reads
> system.physmem.writeRowHits 98547 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes
> system.physmem.avgGap 3301704.47 # Average gap between requests
> system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined
394,404c387,397
< system.membus.throughput 19299112 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 296504 # Transaction distribution
< system.membus.trans_dist::ReadResp 296255 # Transaction distribution
< system.membus.trans_dist::WriteReq 12358 # Transaction distribution
< system.membus.trans_dist::WriteResp 12358 # Transaction distribution
< system.membus.trans_dist::Writeback 122060 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution
< system.membus.trans_dist::ReadExReq 162296 # Transaction distribution
< system.membus.trans_dist::ReadExResp 162161 # Transaction distribution
---
> system.membus.throughput 19439855 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 296479 # Transaction distribution
> system.membus.trans_dist::ReadResp 296230 # Transaction distribution
> system.membus.trans_dist::WriteReq 12351 # Transaction distribution
> system.membus.trans_dist::WriteResp 12351 # Transaction distribution
> system.membus.trans_dist::Writeback 123811 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution
> system.membus.trans_dist::ReadExReq 164353 # Transaction distribution
> system.membus.trans_dist::ReadExResp 164224 # Transaction distribution
406,407c399,400
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes)
409,419c402,412
< system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36720010 # Total data (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 36962282 # Total data (bytes)
421c414
< system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks)
423c416
< system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks)
425c418
< system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks)
427c420
< system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks)
429c422
< system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks)
431,435c424,428
< system.l2c.tags.replacements 343738 # number of replacements
< system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use
< system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 345713 # number of replacements
> system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use
> system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks.
437,595c430,588
< system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits
< system.l2c.Writeback_hits::total 840158 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits
< system.l2c.overall_hits::cpu0.data 712300 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits
< system.l2c.overall_hits::cpu1.data 300363 # number of overall hits
< system.l2c.overall_hits::total 2082980 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses
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< system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses
< system.l2c.demand_misses::total 409924 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses
< system.l2c.overall_misses::cpu0.data 378495 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses
< system.l2c.overall_misses::cpu1.data 16139 # number of overall misses
< system.l2c.overall_misses::total 409924 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency
---
> system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits
> system.l2c.Writeback_hits::total 840492 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits
> system.l2c.overall_hits::cpu0.data 716459 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits
> system.l2c.overall_hits::cpu1.data 293999 # number of overall hits
> system.l2c.overall_hits::total 2078562 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses
> system.l2c.demand_misses::total 411955 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses
> system.l2c.overall_misses::cpu0.data 380800 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses
> system.l2c.overall_misses::cpu1.data 15863 # number of overall misses
> system.l2c.overall_misses::total 411955 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 19081681477 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 842965 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1256946 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 2099911 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 221993 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 116495 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 338488 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 8947158383 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1452475204 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 10399633587 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 929054999 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 26640619633 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 314236981 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1597403451 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 29481315064 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 929054999 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 26640619633 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 314236981 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1597403451 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 29481315064 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 766133 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 844445 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 317263 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 251444 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2179285 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 840492 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 840492 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2695 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 661 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 3356 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 95 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 235 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 252814 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 58418 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 311232 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 766133 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1097259 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 317263 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 309862 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2490517 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 766133 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1097259 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 317263 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 309862 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2490517 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015123 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.322175 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.007059 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.132670 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951763 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888048 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.939213 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.610526 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.764286 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.702128 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.430123 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.241159 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.394654 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015123 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.347047 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.051194 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.165409 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015123 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.347047 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.051194 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.165409 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80187.726480 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 65035.382950 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84791.414193 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 81649.716620 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 65997.805376 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 328.641326 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2141.304940 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 666.215419 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3827.465517 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1088.738318 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 2051.442424 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82279.530104 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103100.170642 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 84667.575141 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 71564.406462 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 71564.406462 # average overall miss latency
604,605c597,598
< system.l2c.writebacks::writebacks 80540 # number of writebacks
< system.l2c.writebacks::total 80540 # number of writebacks
---
> system.l2c.writebacks::writebacks 82291 # number of writebacks
> system.l2c.writebacks::total 82291 # number of writebacks
618,722c611,715
< system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 11579 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 272058 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 3696 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 1775 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 289108 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2565 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 587 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 3152 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 58 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 107 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 165 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 108741 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 14088 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 122829 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 11579 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 380799 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 3696 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 15863 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 411937 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 11579 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 380799 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 3696 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 15863 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 411937 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 782519751 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14298950750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 266998019 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 147305751 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 15495774271 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25723531 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5884082 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 31607613 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 641556 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1072106 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1713662 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7614105115 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1279019296 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8893124411 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 782519751 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 21913055865 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 266998019 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1426325047 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 24388898682 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 782519751 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 21913055865 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 266998019 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1426325047 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 24388898682 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 931434500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458421000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1389855500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1577498000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 884169000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2461667000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2508932500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1342590000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 3851522500 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.322174 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007059 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.132662 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951763 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888048 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.939213 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.610526 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.764286 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702128 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430123 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241159 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.394654 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.165402 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.165402 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52558.464555 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82989.155493 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 53598.566179 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.667057 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.989779 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.796003 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 11061.310345 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.682243 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10385.830303 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70020.554483 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90787.854628 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 72402.481588 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
733,734c726,727
< system.iocache.tags.replacements 41697 # number of replacements
< system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use
---
> system.iocache.tags.replacements 41695 # number of replacements
> system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use
736c729
< system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
738,743c731,736
< system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
---
> system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
746,759c739,752
< system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses
< system.iocache.demand_misses::total 41729 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses
< system.iocache.overall_misses::total 41729 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
> system.iocache.overall_misses::total 41727 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
762,765c755,758
< system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
774,782c767,775
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked
784c777
< system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked
786c779
< system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked
792,793c785,786
< system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
796,807c789,800
< system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles
816,823c809,816
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
837,841c830,834
< system.cpu0.branchPred.lookups 10889682 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 11006012 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits
843,845c836,838
< system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions.
850,865c843,858
< system.cpu0.dtb.read_hits 7794998 # DTB read hits
< system.cpu0.dtb.read_misses 29740 # DTB read misses
< system.cpu0.dtb.read_acv 552 # DTB read access violations
< system.cpu0.dtb.read_accesses 624038 # DTB read accesses
< system.cpu0.dtb.write_hits 5176736 # DTB write hits
< system.cpu0.dtb.write_misses 7776 # DTB write misses
< system.cpu0.dtb.write_acv 327 # DTB write access violations
< system.cpu0.dtb.write_accesses 207382 # DTB write accesses
< system.cpu0.dtb.data_hits 12971734 # DTB hits
< system.cpu0.dtb.data_misses 37516 # DTB misses
< system.cpu0.dtb.data_acv 879 # DTB access violations
< system.cpu0.dtb.data_accesses 831420 # DTB accesses
< system.cpu0.itb.fetch_hits 929400 # ITB hits
< system.cpu0.itb.fetch_misses 28175 # ITB misses
< system.cpu0.itb.fetch_acv 908 # ITB acv
< system.cpu0.itb.fetch_accesses 957575 # ITB accesses
---
> system.cpu0.dtb.read_hits 7888949 # DTB read hits
> system.cpu0.dtb.read_misses 30101 # DTB read misses
> system.cpu0.dtb.read_acv 574 # DTB read access violations
> system.cpu0.dtb.read_accesses 665608 # DTB read accesses
> system.cpu0.dtb.write_hits 5247941 # DTB write hits
> system.cpu0.dtb.write_misses 8093 # DTB write misses
> system.cpu0.dtb.write_acv 365 # DTB write access violations
> system.cpu0.dtb.write_accesses 232480 # DTB write accesses
> system.cpu0.dtb.data_hits 13136890 # DTB hits
> system.cpu0.dtb.data_misses 38194 # DTB misses
> system.cpu0.dtb.data_acv 939 # DTB access violations
> system.cpu0.dtb.data_accesses 898088 # DTB accesses
> system.cpu0.itb.fetch_hits 973403 # ITB hits
> system.cpu0.itb.fetch_misses 31216 # ITB misses
> system.cpu0.itb.fetch_acv 1004 # ITB acv
> system.cpu0.itb.fetch_accesses 1004619 # ITB accesses
878c871
< system.cpu0.numCycles 103787820 # number of cpu cycles simulated
---
> system.cpu0.numCycles 104578589 # number of cpu cycles simulated
881,896c874,889
< system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total)
898,906c891,899
< system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total)
910,954c903,947
< system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle
956,964c949,957
< system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle
968c961
< system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle
970,1000c963,993
< system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available
1003,1035c996,1028
< system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued
1037,1049c1030,1042
< system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued
< system.cpu0.iq.rate 0.434084 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued
> system.cpu0.iq.rate 0.435588 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores
1051,1054c1044,1047
< system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed
1057,1058c1050,1051
< system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked
1060,1076c1053,1069
< system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute
1078,1086c1071,1079
< system.cpu0.iew.exec_nop 2780674 # number of nop insts executed
< system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 7066025 # Number of branches executed
< system.cpu0.iew.exec_stores 5196118 # Number of stores executed
< system.cpu0.iew.exec_rate 0.430889 # Inst execution rate
< system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 22095606 # num instructions producing a value
< system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 2802690 # number of nop insts executed
> system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 7146234 # Number of branches executed
> system.cpu0.iew.exec_stores 5267829 # Number of stores executed
> system.cpu0.iew.exec_rate 0.432362 # Inst execution rate
> system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 22315831 # num instructions producing a value
> system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value
1088,1089c1081,1082
< system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back
1091,1096c1084,1089
< system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle
1098,1106c1091,1099
< system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle
1110,1112c1103,1105
< system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 44873722 # Number of instructions committed
< system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 45343202 # Number of instructions committed
> system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed
1114,1121c1107,1114
< system.cpu0.commit.refs 12194166 # Number of memory references committed
< system.cpu0.commit.loads 7163069 # Number of loads committed
< system.cpu0.commit.membars 173899 # Number of memory barriers committed
< system.cpu0.commit.branches 6736138 # Number of branches committed
< system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 557213 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached
---
> system.cpu0.commit.refs 12347358 # Number of memory references committed
> system.cpu0.commit.loads 7249545 # Number of loads committed
> system.cpu0.commit.membars 175312 # Number of memory barriers committed
> system.cpu0.commit.branches 6808554 # Number of branches committed
> system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 564734 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached
1123,1140c1116,1133
< system.cpu0.rob.rob_reads 113567039 # The number of ROB reads
< system.cpu0.rob.rob_writes 101661188 # The number of ROB writes
< system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 42330060 # Number of Instructions Simulated
< system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated
< system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads
< system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes
---
> system.cpu0.rob.rob_reads 114710793 # The number of ROB reads
> system.cpu0.rob.rob_writes 102749676 # The number of ROB writes
> system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 42781436 # Number of Instructions Simulated
> system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated
> system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads
> system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes
1172,1182c1165,1175
< system.toL2Bus.throughput 112875870 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution
---
> system.toL2Bus.throughput 112873708 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution
1184,1196c1177,1189
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 213368266 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks)
---
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 213236842 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks)
1198c1191
< system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks)
1200c1193
< system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks)
1202c1195
< system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks)
1204c1197
< system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks)
1206c1199
< system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks)
1208,1214c1201,1207
< system.iobus.throughput 1433257 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
< system.iobus.trans_dist::WriteReq 53910 # Transaction distribution
< system.iobus.trans_dist::WriteResp 53910 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes)
---
> system.iobus.throughput 1434231 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
> system.iobus.trans_dist::WriteReq 53903 # Transaction distribution
> system.iobus.trans_dist::WriteResp 53903 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1225,1230c1218,1223
< system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1241,1246c1234,1239
< system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2729874 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2729826 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks)
1248c1241
< system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1268c1261
< system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks)
1272c1265
< system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks)
1274c1267
< system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks)
1276,1280c1269,1273
< system.cpu0.icache.tags.replacements 755849 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 765570 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks.
1282c1275
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor
1285,1321c1278,1314
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits
< system.cpu0.icache.overall_hits::total 6013634 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses
< system.cpu0.icache.overall_misses::total 794785 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked
---
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits
> system.cpu0.icache.overall_hits::total 6090993 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses
> system.cpu0.icache.overall_misses::total 805033 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked
1323c1316
< system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked
1325c1318
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked
1329,1358c1322,1351
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
1360,1364c1353,1357
< system.cpu0.dcache.tags.replacements 1092682 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.replacements 1099493 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks.
1366,1446c1359,1439
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits
< system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits
> system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked
1449,1514c1442,1507
< system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks
< system.cpu0.dcache.writebacks::total 588957 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks
> system.cpu0.dcache.writebacks::total 594718 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
1522,1526c1515,1519
< system.cpu1.branchPred.lookups 4005476 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3875512 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits
1528,1530c1521,1523
< system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions.
1535,1550c1528,1543
< system.cpu1.dtb.read_hits 2861061 # DTB read hits
< system.cpu1.dtb.read_misses 13171 # DTB read misses
< system.cpu1.dtb.read_acv 26 # DTB read access violations
< system.cpu1.dtb.read_accesses 327320 # DTB read accesses
< system.cpu1.dtb.write_hits 1771736 # DTB write hits
< system.cpu1.dtb.write_misses 2413 # DTB write misses
< system.cpu1.dtb.write_acv 61 # DTB write access violations
< system.cpu1.dtb.write_accesses 133954 # DTB write accesses
< system.cpu1.dtb.data_hits 4632797 # DTB hits
< system.cpu1.dtb.data_misses 15584 # DTB misses
< system.cpu1.dtb.data_acv 87 # DTB access violations
< system.cpu1.dtb.data_accesses 461274 # DTB accesses
< system.cpu1.itb.fetch_hits 484886 # ITB hits
< system.cpu1.itb.fetch_misses 6783 # ITB misses
< system.cpu1.itb.fetch_acv 213 # ITB acv
< system.cpu1.itb.fetch_accesses 491669 # ITB accesses
---
> system.cpu1.dtb.read_hits 2756439 # DTB read hits
> system.cpu1.dtb.read_misses 11971 # DTB read misses
> system.cpu1.dtb.read_acv 6 # DTB read access violations
> system.cpu1.dtb.read_accesses 281635 # DTB read accesses
> system.cpu1.dtb.write_hits 1697476 # DTB write hits
> system.cpu1.dtb.write_misses 2261 # DTB write misses
> system.cpu1.dtb.write_acv 35 # DTB write access violations
> system.cpu1.dtb.write_accesses 106637 # DTB write accesses
> system.cpu1.dtb.data_hits 4453915 # DTB hits
> system.cpu1.dtb.data_misses 14232 # DTB misses
> system.cpu1.dtb.data_acv 41 # DTB access violations
> system.cpu1.dtb.data_accesses 388272 # DTB accesses
> system.cpu1.itb.fetch_hits 435796 # ITB hits
> system.cpu1.itb.fetch_misses 5916 # ITB misses
> system.cpu1.itb.fetch_acv 132 # ITB acv
> system.cpu1.itb.fetch_accesses 441712 # ITB accesses
1563c1556
< system.cpu1.numCycles 26365345 # number of cpu cycles simulated
---
> system.cpu1.numCycles 25703316 # number of cpu cycles simulated
1566,1581c1559,1574
< system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total)
1583,1591c1576,1584
< system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total)
1595,1639c1588,1632
< system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle
1641,1649c1634,1642
< system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle
1653c1646
< system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle
1655,1685c1648,1678
< system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available
1688,1720c1681,1713
< system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued
1722,1734c1715,1727
< system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued
< system.cpu1.iq.rate 0.569740 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued
> system.cpu1.iq.rate 0.563522 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores
1736,1739c1729,1732
< system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed
1742,1743c1735,1736
< system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked
1745,1761c1738,1754
< system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute
1763,1771c1756,1764
< system.cpu1.iew.exec_nop 898529 # number of nop insts executed
< system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 2338044 # Number of branches executed
< system.cpu1.iew.exec_stores 1780212 # Number of stores executed
< system.cpu1.iew.exec_rate 0.564317 # Inst execution rate
< system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 7139948 # num instructions producing a value
< system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 875756 # number of nop insts executed
> system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 2254475 # Number of branches executed
> system.cpu1.iew.exec_stores 1705604 # Number of stores executed
> system.cpu1.iew.exec_rate 0.558247 # Inst execution rate
> system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 6903248 # num instructions producing a value
> system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value
1773,1774c1766,1767
< system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back
1776,1781c1769,1774
< system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle
1783,1791c1776,1784
< system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle
1795,1797c1788,1790
< system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 14604164 # Number of instructions committed
< system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 14096266 # Number of instructions committed
> system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed
1799,1806c1792,1799
< system.cpu1.commit.refs 4287363 # Number of memory references committed
< system.cpu1.commit.loads 2592870 # Number of loads committed
< system.cpu1.commit.membars 62980 # Number of memory barriers committed
< system.cpu1.commit.branches 2183593 # Number of branches committed
< system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 233831 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached
---
> system.cpu1.commit.refs 4123576 # Number of memory references committed
> system.cpu1.commit.loads 2500439 # Number of loads committed
> system.cpu1.commit.membars 61456 # Number of memory barriers committed
> system.cpu1.commit.branches 2105755 # Number of branches committed
> system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 225813 # Number of function calls committed.
> system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached
1808,1871c1801,1864
< system.cpu1.rob.rob_reads 39695803 # The number of ROB reads
< system.cpu1.rob.rob_writes 34392702 # The number of ROB writes
< system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 13810279 # Number of Instructions Simulated
< system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated
< system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads
< system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes
< system.cpu1.icache.tags.replacements 328629 # number of replacements
< system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits
< system.cpu1.icache.overall_hits::total 1927863 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses
< system.cpu1.icache.overall_misses::total 344335 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked
---
> system.cpu1.rob.rob_reads 38521772 # The number of ROB reads
> system.cpu1.rob.rob_writes 33194220 # The number of ROB writes
> system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 13322175 # Number of Instructions Simulated
> system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated
> system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads
> system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes
> system.cpu1.icache.tags.replacements 316719 # number of replacements
> system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits
> system.cpu1.icache.overall_hits::total 1849767 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses
> system.cpu1.icache.overall_misses::total 331536 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked
1873c1866
< system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked
1875c1868
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked
1879,1908c1872,1901
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
1910,1991c1903,1984
< system.cpu1.dcache.tags.replacements 330658 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits
< system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses
< system.cpu1.dcache.overall_misses::total 848896 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked
---
> system.cpu1.dcache.tags.replacements 323504 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits
> system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses
> system.cpu1.dcache.overall_misses::total 816274 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 13547153677 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 112298247 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 112298247 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5736606 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5736606 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 20834123377 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 20834123377 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 20834123377 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 20834123377 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2557049 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2557049 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.182849 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222006 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.222006 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157248 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157248 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017309 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017309 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197749 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.197749 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197749 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.197749 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7335.813299 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7335.813299 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 423453 # number of cycles access was blocked
1993c1986
< system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked
---
> system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked
1995c1988
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked
1999,2064c1992,2057
< system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks
< system.cpu1.dcache.writebacks::total 251201 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks
> system.cpu1.dcache.writebacks::total 245774 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
2073,2093c2066,2086
< system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl
2097,2128c2090,2121
< system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
< system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
< system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
< system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed
< system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed
< system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed
< system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed
< system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed
< system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed
< system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed
< system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed
< system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed
< system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed
< system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed
< system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed
< system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed
< system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed
< system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed
< system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed
< system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed
< system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed
< system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed
< system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed
< system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed
< system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed
< system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed
< system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed
< system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed
< system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
< system.cpu0.kern.syscall::total 202 # number of syscalls executed
---
> system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed
> system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed
> system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed
> system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed
> system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed
> system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed
> system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed
> system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed
> system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed
> system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed
> system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed
> system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed
> system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed
> system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed
> system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed
> system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed
> system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed
> system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed
> system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed
> system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed
> system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed
> system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed
> system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed
> system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed
> system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed
> system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed
> system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed
> system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed
> system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
> system.cpu0.kern.syscall::total 225 # number of syscalls executed
2130c2123
< system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed
---
> system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed
2134,2148c2127,2141
< system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed
< system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed
< system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed
< system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed
< system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 149930 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches
---
> system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed
> system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
> system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed
> system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed
> system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 151247 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches
2150,2151c2143,2144
< system.cpu0.kern.mode_good::kernel 1257
< system.cpu0.kern.mode_good::user 1258
---
> system.cpu0.kern.mode_good::kernel 1342
> system.cpu0.kern.mode_good::user 1343
2153c2146
< system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches
2156,2158c2149,2151
< system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode
2160c2153
< system.cpu0.kern.swap_context 2970 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3011 # number of times the context was actually changed
2162,2179c2155,2172
< system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl
2182,2205c2175,2190
< system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
< system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
< system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
< system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed
< system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed
< system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed
< system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed
< system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed
< system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed
< system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed
< system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed
< system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed
< system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed
< system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed
< system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed
< system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed
< system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed
< system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed
< system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed
< system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed
< system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
< system.cpu1.kern.syscall::total 124 # number of syscalls executed
---
> system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
> system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
> system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
> system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed
> system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed
> system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed
> system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed
> system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed
> system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed
> system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed
> system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed
> system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed
> system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
> system.cpu1.kern.syscall::total 101 # number of syscalls executed
2210,2221c2195,2205
< system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed
< system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed
< system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed
< system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed
< system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed
< system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed
> system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed
> system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed
> system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed
> system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
2223,2230c2207,2214
< system.cpu1.kern.callpal::total 66403 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 557
< system.cpu1.kern.mode_good::user 488
< system.cpu1.kern.mode_good::idle 69
< system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 65000 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 397 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 463
> system.cpu1.kern.mode_good::user 397
> system.cpu1.kern.mode_good::idle 66
> system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches
2232,2237c2216,2221
< system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1278 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1229 # number of times the context was actually changed