3,5c3,5
< sim_seconds 1.902739 # Number of seconds simulated
< sim_ticks 1902738973500 # Number of ticks simulated
< final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.904665 # Number of seconds simulated
> sim_ticks 1904665099500 # Number of ticks simulated
> final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,132c7,134
< host_inst_rate 132013 # Simulator instruction rate (inst/s)
< host_op_rate 132013 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4427958303 # Simulator tick rate (ticks/s)
< host_mem_usage 313120 # Number of bytes of host memory used
< host_seconds 429.71 # Real time elapsed on the host
< sim_insts 56727331 # Number of instructions simulated
< sim_ops 56727331 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory
< system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory
< system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 28869696 # Total number of bytes read from memory
< system.physmem.bytesWritten 7821440 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1902738952500 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 451089 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 122210 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
---
> host_inst_rate 126318 # Simulator instruction rate (inst/s)
> host_op_rate 126318 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4285588150 # Simulator tick rate (ticks/s)
> host_mem_usage 339596 # Number of bytes of host memory used
> host_seconds 444.44 # Real time elapsed on the host
> sim_insts 56140339 # Number of instructions simulated
> sim_ops 56140339 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory
> system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory
> system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 450624 # Number of read requests accepted
> system.physmem.writeReqs 122060 # Number of write requests accepted
> system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 28171 # Per bank write bursts
> system.physmem.perBankRdBursts::1 27944 # Per bank write bursts
> system.physmem.perBankRdBursts::2 28133 # Per bank write bursts
> system.physmem.perBankRdBursts::3 27978 # Per bank write bursts
> system.physmem.perBankRdBursts::4 27881 # Per bank write bursts
> system.physmem.perBankRdBursts::5 28082 # Per bank write bursts
> system.physmem.perBankRdBursts::6 28123 # Per bank write bursts
> system.physmem.perBankRdBursts::7 28118 # Per bank write bursts
> system.physmem.perBankRdBursts::8 28377 # Per bank write bursts
> system.physmem.perBankRdBursts::9 28284 # Per bank write bursts
> system.physmem.perBankRdBursts::10 27947 # Per bank write bursts
> system.physmem.perBankRdBursts::11 28190 # Per bank write bursts
> system.physmem.perBankRdBursts::12 28259 # Per bank write bursts
> system.physmem.perBankRdBursts::13 28280 # Per bank write bursts
> system.physmem.perBankRdBursts::14 28300 # Per bank write bursts
> system.physmem.perBankRdBursts::15 28502 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7913 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7477 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7607 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7420 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7384 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7571 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7682 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7471 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7660 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7641 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7379 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7517 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7673 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7762 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7923 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7975 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
> system.physmem.totGap 1904663535000 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 450624 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 122060 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 322714 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 66953 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 33909 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6366 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2356 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2321 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1375 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1339 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1454 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1311 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 970 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 967 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 951 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 952 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 951 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
142,321c144,381
< system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation
< system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests
< system.physmem.totBusLat 2255080000 # Total cycles spent in databus access
< system.physmem.totBankLat 5209710000 # Total cycles spent in bank access
< system.physmem.avgQLat 14198.08 # Average queueing delay per request
< system.physmem.avgBankLat 11551.05 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 30749.13 # Average memory access latency
< system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
---
> system.physmem.wrQLenPdf::0 4775 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4812 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4837 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5509 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5665 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5732 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5056 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5059 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5058 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5875 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5977 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 6013 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 6049 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5318 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5148 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6074 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 336 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 55 0.12% 94.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4611 21 0.05% 94.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 49 0.11% 94.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 50 0.11% 94.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4867 11 0.02% 94.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4931 26 0.06% 94.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5187 38 0.08% 95.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5315 26 0.06% 95.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5443 54 0.12% 95.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5507 52 0.11% 95.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5699 22 0.05% 95.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 49 0.11% 96.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 39 0.08% 96.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 31 0.07% 96.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6211 44 0.09% 96.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6403 9 0.02% 96.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6467 51 0.11% 97.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6531 50 0.11% 97.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6595 23 0.05% 97.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6659 20 0.04% 97.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 23 0.05% 97.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6787 51 0.11% 97.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6851 49 0.11% 97.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6915 7 0.02% 97.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6976-6979 28 0.06% 97.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 86 0.19% 97.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7107 45 0.10% 97.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 319 0.69% 98.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7427 8 0.02% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7683 15 0.03% 98.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7939 7 0.02% 98.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 319 0.69% 99.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11968-11971 4 0.01% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12800-12803 3 0.01% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12928-12931 3 0.01% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation
> system.physmem.totQLat 8608105750 # Total ticks spent queuing
> system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks
> system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
323,357c383,421
< system.physmem.avgRdQLen 0.01 # Average read queue length over time
< system.physmem.avgWrQLen 14.36 # Average write queue length over time
< system.physmem.readRowHits 435126 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97620 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes
< system.physmem.avgGap 3318929.48 # Average gap between requests
< system.membus.throughput 19341454 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 296468 # Transaction distribution
< system.membus.trans_dist::ReadResp 296394 # Transaction distribution
< system.membus.trans_dist::WriteReq 13061 # Transaction distribution
< system.membus.trans_dist::WriteResp 13061 # Transaction distribution
< system.membus.trans_dist::Writeback 122210 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution
< system.membus.trans_dist::ReadExReq 162867 # Transaction distribution
< system.membus.trans_dist::ReadExResp 162463 # Transaction distribution
< system.membus.trans_dist::BadAddressError 74 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36765002 # Total data (bytes)
< system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks)
---
> system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing
> system.physmem.readRowHits 429097 # Number of row buffer hits during reads
> system.physmem.writeRowHits 97193 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes
> system.physmem.avgGap 3325854.28 # Average gap between requests
> system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 19299112 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 296504 # Transaction distribution
> system.membus.trans_dist::ReadResp 296255 # Transaction distribution
> system.membus.trans_dist::WriteReq 12358 # Transaction distribution
> system.membus.trans_dist::WriteResp 12358 # Transaction distribution
> system.membus.trans_dist::Writeback 122060 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution
> system.membus.trans_dist::ReadExReq 162296 # Transaction distribution
> system.membus.trans_dist::ReadExResp 162161 # Transaction distribution
> system.membus.trans_dist::BadAddressError 249 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 36720010 # Total data (bytes)
> system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes)
> system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks)
359c423
< system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks)
361c425
< system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks)
363c427
< system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks)
365c429
< system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks)
367,531c431,595
< system.l2c.tags.replacements 344151 # number of replacements
< system.l2c.tags.tagsinuse 65253.870311 # Cycle average of tags in use
< system.l2c.tags.total_refs 2581362 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 409161 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 6.308915 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 53541.051154 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5362.839741 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6144.208257 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 141.383324 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 64.387836 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.816972 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.081830 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.093753 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.002157 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000982 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.995695 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 862836 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 735075 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 214357 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 69353 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1881621 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 822225 # number of Writeback hits
< system.l2c.Writeback_hits::total 822225 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 270 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 439 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 153625 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 26073 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 179698 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 862836 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 888700 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 214357 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 95426 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2061319 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 862836 # number of overall hits
< system.l2c.overall_hits::cpu0.data 888700 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 214357 # number of overall hits
< system.l2c.overall_hits::cpu1.data 95426 # number of overall hits
< system.l2c.overall_hits::total 2061319 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 14080 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 273430 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 427 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2676 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1075 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3751 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 454 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 879 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 114757 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 6453 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 121210 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 14080 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 388187 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 6880 # number of demand (read+write) misses
< system.l2c.demand_misses::total 410327 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 14080 # number of overall misses
< system.l2c.overall_misses::cpu0.data 388187 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses
< system.l2c.overall_misses::cpu1.data 6880 # number of overall misses
< system.l2c.overall_misses::total 410327 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 1210878995 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17193583984 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 109764250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 37725999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18551953228 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1076463 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 4839759 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 5916222 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 977458 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1070954 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 9311235979 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 722690467 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10033926446 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1210878995 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 26504819963 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 109764250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 760416466 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 28585879674 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1210878995 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 26504819963 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 109764250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 760416466 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 28585879674 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 876916 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 1008505 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 215537 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 69780 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2170738 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 822225 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 822225 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2845 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 1345 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 4190 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 479 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 947 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 268382 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 32526 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 300908 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 876916 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1276887 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 215537 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 102306 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2471646 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 876916 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1276887 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 215537 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 102306 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2471646 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.016056 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.271124 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.005475 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.006119 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.133188 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940598 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.799257 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.895227 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.908120 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947808 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.928194 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.427588 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.198395 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.402814 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.016056 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.304010 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.005475 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.067249 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.166014 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.016056 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.304010 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.005475 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.067249 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.166014 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85999.928622 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 62881.117595 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 93020.550847 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 88351.285714 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 64167.631886 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 402.265695 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4502.101395 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1577.238603 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2299.901176 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 205.938326 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1218.377702 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81138.719024 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111992.943902 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 82781.341853 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 69666.094783 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 69666.094783 # average overall miss latency
---
> system.l2c.tags.replacements 343738 # number of replacements
> system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use
> system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 325372 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits
> system.l2c.Writeback_hits::total 840158 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 143496 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 47101 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 744945 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 325372 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 300363 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2082980 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 744945 # number of overall hits
> system.l2c.overall_hits::cpu0.data 712300 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 325372 # number of overall hits
> system.l2c.overall_hits::cpu1.data 300363 # number of overall hits
> system.l2c.overall_hits::total 2082980 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 11483 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 272043 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 3807 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1819 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 289152 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2542 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 549 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 3091 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 55 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 155 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 106452 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 14320 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 120772 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 11483 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 378495 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 3807 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 16139 # number of demand (read+write) misses
> system.l2c.demand_misses::total 409924 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 11483 # number of overall misses
> system.l2c.overall_misses::cpu0.data 378495 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 3807 # number of overall misses
> system.l2c.overall_misses::cpu1.data 16139 # number of overall misses
> system.l2c.overall_misses::total 409924 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 923162249 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 17695673499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 318789981 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 142364996 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 19079990725 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 555479 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1281945 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1837424 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 201494 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 69497 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 270991 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 8670131391 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1451250197 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 10121381588 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 923162249 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 26365804890 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 318789981 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1593615193 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 29201372313 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 923162249 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 26365804890 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 318789981 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1593615193 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 29201372313 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 756428 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 840847 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 329179 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 255081 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2181535 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 840158 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 840158 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2683 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 636 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 3319 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 90 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 131 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 221 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 249948 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 61421 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 311369 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 756428 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1090795 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 329179 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 316502 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2492904 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 756428 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1090795 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 329179 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 316502 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2492904 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015181 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.323534 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.011565 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.007131 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.132545 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947447 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.863208 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.931305 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.611111 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.763359 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.701357 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.425897 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.233145 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.387874 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015181 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.346990 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.011565 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.050992 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.164436 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015181 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.346990 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.011565 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.050992 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.164436 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.821214 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 65047.339939 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83737.846336 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 78265.528312 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 65986.023700 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 218.520456 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2335.054645 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 594.443222 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3663.527273 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 694.970000 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1748.329032 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81446.392656 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101344.287500 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 83805.696585 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 71236.064034 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 80393.821214 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 69659.585701 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 83737.846336 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 98743.118719 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 71236.064034 # average overall miss latency
540,542c604,606
< system.l2c.writebacks::writebacks 80690 # number of writebacks
< system.l2c.writebacks::total 80690 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits
---
> system.l2c.writebacks::writebacks 80540 # number of writebacks
> system.l2c.writebacks::total 80540 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
544c608
< system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
---
> system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits
546c610
< system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
548c612
< system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
550c614
< system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
552c616
< system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
---
> system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
554,658c618,722
< system.l2c.ReadReq_mshr_misses::cpu0.inst 14072 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 273429 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 1171 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 427 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2676 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1075 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3751 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 454 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 879 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 114757 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 6453 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 121210 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 14072 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 388186 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 1171 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 6880 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 410309 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 14072 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 388186 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 1171 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 6880 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 410309 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1031878505 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13784019266 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 94337500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 32390501 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 14942625772 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26984633 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10773037 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 37757670 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4256416 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4544453 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 8800869 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7896551021 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 642755533 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8539306554 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1031878505 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 21680570287 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 94337500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 675146034 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 23481932326 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1031878505 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 21680570287 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 94337500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 675146034 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 23481932326 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367321000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22027000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1389348000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2025100000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 585946999 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2611046999 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3392421000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607973999 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4000394999 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271123 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006119 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.133180 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940598 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.799257 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.895227 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908120 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947808 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.928194 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427588 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198395 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.402814 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.166006 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.166006 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50411.694685 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75855.974239 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 51686.881560 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10083.943572 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.429767 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.027726 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.096471 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.808370 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 11476 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 272042 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 3797 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 1819 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 289134 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2542 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 549 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 3091 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 55 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 155 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 106452 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 14320 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 120772 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 11476 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 378494 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 3797 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 16139 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 409906 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 11476 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 378494 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 3797 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 16139 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 409906 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 777853501 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14301350001 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270265519 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 144194502 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 15493663523 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25563003 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5558045 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 31121048 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600552 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1003598 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1604150 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7364952609 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1275013301 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8639965910 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 777853501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 21666302610 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 270265519 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1419207803 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 24133629433 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 777853501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 21666302610 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 270265519 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1419207803 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 24133629433 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 929130500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 460152500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1389283000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1572515500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 890654999 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2463170499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2501646000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1350807499 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 3852453499 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.323533 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007131 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.132537 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.947447 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.863208 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.931305 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.611111 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.763359 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.701357 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425897 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.233145 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.387874 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.164429 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015171 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.346989 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011535 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.050992 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.164429 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52570.375166 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79271.304013 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 53586.446156 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.256098 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10123.943534 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.278227 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10919.127273 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.980000 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10349.354839 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69185.666864 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89037.241690 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 71539.478604 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67780.890641 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57243.450649 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.698710 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87936.539005 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 58876.009214 # average overall mshr miss latency
669,670c733,734
< system.iocache.tags.replacements 41695 # number of replacements
< system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use
---
> system.iocache.tags.replacements 41697 # number of replacements
> system.iocache.tags.tagsinuse 0.224170 # Cycle average of tags in use
672c736
< system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks.
674,679c738,743
< system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
---
> system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
682,695c746,759
< system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
< system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
< system.iocache.overall_misses::total 41727 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41729 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses
> system.iocache.overall_misses::total 41729 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
698,701c762,765
< system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses
710,718c774,782
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked
720c784
< system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked
722c786
< system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked
728,729c792,793
< system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
732,743c796,807
< system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles
752,759c816,823
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
773,777c837,841
< system.cpu0.branchPred.lookups 12458299 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 10889682 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits
779,781c843,845
< system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions.
786,801c850,865
< system.cpu0.dtb.read_hits 8872852 # DTB read hits
< system.cpu0.dtb.read_misses 32010 # DTB read misses
< system.cpu0.dtb.read_acv 540 # DTB read access violations
< system.cpu0.dtb.read_accesses 628428 # DTB read accesses
< system.cpu0.dtb.write_hits 5797852 # DTB write hits
< system.cpu0.dtb.write_misses 8130 # DTB write misses
< system.cpu0.dtb.write_acv 348 # DTB write access violations
< system.cpu0.dtb.write_accesses 210128 # DTB write accesses
< system.cpu0.dtb.data_hits 14670704 # DTB hits
< system.cpu0.dtb.data_misses 40140 # DTB misses
< system.cpu0.dtb.data_acv 888 # DTB access violations
< system.cpu0.dtb.data_accesses 838556 # DTB accesses
< system.cpu0.itb.fetch_hits 994919 # ITB hits
< system.cpu0.itb.fetch_misses 28800 # ITB misses
< system.cpu0.itb.fetch_acv 922 # ITB acv
< system.cpu0.itb.fetch_accesses 1023719 # ITB accesses
---
> system.cpu0.dtb.read_hits 7794998 # DTB read hits
> system.cpu0.dtb.read_misses 29740 # DTB read misses
> system.cpu0.dtb.read_acv 552 # DTB read access violations
> system.cpu0.dtb.read_accesses 624038 # DTB read accesses
> system.cpu0.dtb.write_hits 5176736 # DTB write hits
> system.cpu0.dtb.write_misses 7776 # DTB write misses
> system.cpu0.dtb.write_acv 327 # DTB write access violations
> system.cpu0.dtb.write_accesses 207382 # DTB write accesses
> system.cpu0.dtb.data_hits 12971734 # DTB hits
> system.cpu0.dtb.data_misses 37516 # DTB misses
> system.cpu0.dtb.data_acv 879 # DTB access violations
> system.cpu0.dtb.data_accesses 831420 # DTB accesses
> system.cpu0.itb.fetch_hits 929400 # ITB hits
> system.cpu0.itb.fetch_misses 28175 # ITB misses
> system.cpu0.itb.fetch_acv 908 # ITB acv
> system.cpu0.itb.fetch_accesses 957575 # ITB accesses
814c878
< system.cpu0.numCycles 114636003 # number of cpu cycles simulated
---
> system.cpu0.numCycles 103787820 # number of cpu cycles simulated
817,832c881,896
< system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total)
834,842c898,906
< system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total)
846,890c910,954
< system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle
892,900c956,964
< system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle
904c968
< system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle
906,936c970,1000
< system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available
939,971c1003,1035
< system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued
973,985c1037,1049
< system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued
< system.cpu0.iq.rate 0.448487 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued
> system.cpu0.iq.rate 0.434084 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores
987,990c1051,1054
< system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed
993,994c1057,1058
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked
996,1012c1060,1076
< system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute
1014,1022c1078,1086
< system.cpu0.iew.exec_nop 3225661 # number of nop insts executed
< system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 8123465 # Number of branches executed
< system.cpu0.iew.exec_stores 5819599 # Number of stores executed
< system.cpu0.iew.exec_rate 0.445079 # Inst execution rate
< system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 25247170 # num instructions producing a value
< system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 2780674 # number of nop insts executed
> system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 7066025 # Number of branches executed
> system.cpu0.iew.exec_stores 5196118 # Number of stores executed
> system.cpu0.iew.exec_rate 0.430889 # Inst execution rate
> system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 22095606 # num instructions producing a value
> system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value
1024,1025c1088,1089
< system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back
1027,1032c1091,1096
< system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle
1034,1042c1098,1106
< system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle
1046,1048c1110,1112
< system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 51137491 # Number of instructions committed
< system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 44873722 # Number of instructions committed
> system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed
1050,1057c1114,1121
< system.cpu0.commit.refs 13773046 # Number of memory references committed
< system.cpu0.commit.loads 8150974 # Number of loads committed
< system.cpu0.commit.membars 198820 # Number of memory barriers committed
< system.cpu0.commit.branches 7724848 # Number of branches committed
< system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 655486 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached
---
> system.cpu0.commit.refs 12194166 # Number of memory references committed
> system.cpu0.commit.loads 7163069 # Number of loads committed
> system.cpu0.commit.membars 173899 # Number of memory barriers committed
> system.cpu0.commit.branches 6736138 # Number of branches committed
> system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 557213 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached
1059,1076c1123,1140
< system.cpu0.rob.rob_reads 130752703 # The number of ROB reads
< system.cpu0.rob.rob_writes 116166541 # The number of ROB writes
< system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 48197169 # Number of Instructions Simulated
< system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated
< system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads
< system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes
---
> system.cpu0.rob.rob_reads 113567039 # The number of ROB reads
> system.cpu0.rob.rob_writes 101661188 # The number of ROB writes
> system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 42330060 # Number of Instructions Simulated
> system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated
> system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads
> system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes
1108,1132c1172,1196
< system.toL2Bus.throughput 111571177 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution
< system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 210876874 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks)
---
> system.toL2Bus.throughput 112875870 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution
> system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 213368266 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks)
1134c1198
< system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks)
1136c1200
< system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks)
1138c1202
< system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks)
1140c1204
< system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks)
1142,1150c1206,1214
< system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks)
< system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.iobus.throughput 1437659 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
< system.iobus.trans_dist::WriteReq 54613 # Transaction distribution
< system.iobus.trans_dist::WriteResp 54613 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks)
> system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
> system.iobus.throughput 1433257 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
> system.iobus.trans_dist::WriteReq 53910 # Transaction distribution
> system.iobus.trans_dist::WriteResp 53910 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes)
1161,1166c1225,1230
< system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes)
1177,1182c1241,1246
< system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2735490 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 68234 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size::total 2729874 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2729874 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 9865000 # Layer occupancy (ticks)
1184c1248
< system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks)
1204c1268
< system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 377768695 # Layer occupancy (ticks)
1208c1272
< system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 26744000 # Layer occupancy (ticks)
1210c1274
< system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42672507 # Layer occupancy (ticks)
1212,1262c1276,1326
< system.cpu0.icache.tags.replacements 876399 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits
< system.cpu0.icache.overall_hits::total 6802362 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses
< system.cpu0.icache.overall_misses::total 921891 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 1109 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 554.500000 # average number of cycles each access was blocked
---
> system.cpu0.icache.tags.replacements 755849 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.693536 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 6013634 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 756358 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 7.950777 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693536 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6013634 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6013634 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6013634 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6013634 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6013634 # number of overall hits
> system.cpu0.icache.overall_hits::total 6013634 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 794785 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 794785 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 794785 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 794785 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 794785 # number of overall misses
> system.cpu0.icache.overall_misses::total 794785 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11289773018 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11289773018 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11289773018 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11289773018 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11289773018 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11289773018 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 6808419 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 6808419 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 6808419 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 6808419 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 6808419 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 6808419 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116736 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.116736 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116736 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.116736 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116736 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.116736 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14204.813903 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14204.813903 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14204.813903 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14204.813903 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14204.813903 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 5327 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 127 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 41.944882 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1265,1294c1329,1358
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44872 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 44872 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 44872 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 44872 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 44872 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 44872 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 877019 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 877019 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 877019 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 877019 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38259 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 38259 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 38259 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 38259 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 38259 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 38259 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 756526 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 756526 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 756526 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 756526 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 756526 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 756526 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9285394312 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 9285394312 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9285394312 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 9285394312 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9285394312 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 9285394312 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111116 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.111116 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111116 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.111116 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12273.727951 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12273.727951 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12273.727951 # average overall mshr miss latency
1296,1382c1360,1446
< system.cpu0.dcache.tags.replacements 1278910 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3667453 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162740 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 162740 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187465 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 187465 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 10108289 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits
< system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 1258 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 179.714286 # average number of cycles each access was blocked
---
> system.cpu0.dcache.tags.replacements 1092682 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 465.850340 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 9201265 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1093194 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.416864 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 465.850340 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.909864 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.909864 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 5673895 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 5673895 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3199282 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3199282 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148885 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 148885 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172652 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 172652 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 8873177 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 8873177 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 8873177 # number of overall hits
> system.cpu0.dcache.overall_hits::total 8873177 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1348613 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1348613 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1646140 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1646140 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16729 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 16729 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 773 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 773 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 2994753 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 2994753 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 2994753 # number of overall misses
> system.cpu0.dcache.overall_misses::total 2994753 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36556454998 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 36556454998 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 72896722210 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 72896722210 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251362748 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 251362748 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4670052 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4670052 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 109453177208 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 109453177208 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 109453177208 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 109453177208 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7022508 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7022508 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4845422 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4845422 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 165614 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 165614 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 173425 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 173425 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 11867930 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 11867930 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 11867930 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 11867930 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192042 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.192042 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339731 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.339731 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101012 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101012 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004457 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004457 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252340 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.252340 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252340 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.252340 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27106.705184 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 27106.705184 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44283.428026 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 44283.428026 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15025.569251 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15025.569251 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6041.464424 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6041.464424 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 36548.315406 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36548.315406 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 36548.315406 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 2779952 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 1302 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 46345 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.983860 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 162.750000 # average number of cycles each access was blocked
1385,1450c1449,1514
< system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks
< system.cpu0.dcache.writebacks::total 752999 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 588957 # number of writebacks
> system.cpu0.dcache.writebacks::total 588957 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 514989 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 514989 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1392541 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1392541 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3960 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3960 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1907530 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1907530 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1907530 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1907530 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 833624 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 833624 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253599 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 253599 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12769 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12769 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 773 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 773 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1087223 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1087223 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1087223 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1087223 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24857542918 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24857542918 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10684541815 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10684541815 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 151212250 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 151212250 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3123948 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3123948 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35542084733 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 35542084733 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35542084733 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 35542084733 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 990981000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 990981000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668402499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668402499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2659383499 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2659383499 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118707 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118707 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052338 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052338 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.077101 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.077101 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004457 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004457 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.091610 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091610 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.091610 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29818.650756 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29818.650756 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42131.640168 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42131.640168 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11842.137207 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11842.137207 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4041.329884 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4041.329884 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32690.703501 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32690.703501 # average overall mshr miss latency
1458,1462c1522,1526
< system.cpu1.branchPred.lookups 2517085 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 4005476 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits
1464,1466c1528,1530
< system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions.
1471,1486c1535,1550
< system.cpu1.dtb.read_hits 1869470 # DTB read hits
< system.cpu1.dtb.read_misses 10476 # DTB read misses
< system.cpu1.dtb.read_acv 22 # DTB read access violations
< system.cpu1.dtb.read_accesses 321268 # DTB read accesses
< system.cpu1.dtb.write_hits 1203365 # DTB write hits
< system.cpu1.dtb.write_misses 2061 # DTB write misses
< system.cpu1.dtb.write_acv 64 # DTB write access violations
< system.cpu1.dtb.write_accesses 130567 # DTB write accesses
< system.cpu1.dtb.data_hits 3072835 # DTB hits
< system.cpu1.dtb.data_misses 12537 # DTB misses
< system.cpu1.dtb.data_acv 86 # DTB access violations
< system.cpu1.dtb.data_accesses 451835 # DTB accesses
< system.cpu1.itb.fetch_hits 424254 # ITB hits
< system.cpu1.itb.fetch_misses 6539 # ITB misses
< system.cpu1.itb.fetch_acv 190 # ITB acv
< system.cpu1.itb.fetch_accesses 430793 # ITB accesses
---
> system.cpu1.dtb.read_hits 2861061 # DTB read hits
> system.cpu1.dtb.read_misses 13171 # DTB read misses
> system.cpu1.dtb.read_acv 26 # DTB read access violations
> system.cpu1.dtb.read_accesses 327320 # DTB read accesses
> system.cpu1.dtb.write_hits 1771736 # DTB write hits
> system.cpu1.dtb.write_misses 2413 # DTB write misses
> system.cpu1.dtb.write_acv 61 # DTB write access violations
> system.cpu1.dtb.write_accesses 133954 # DTB write accesses
> system.cpu1.dtb.data_hits 4632797 # DTB hits
> system.cpu1.dtb.data_misses 15584 # DTB misses
> system.cpu1.dtb.data_acv 87 # DTB access violations
> system.cpu1.dtb.data_accesses 461274 # DTB accesses
> system.cpu1.itb.fetch_hits 484886 # ITB hits
> system.cpu1.itb.fetch_misses 6783 # ITB misses
> system.cpu1.itb.fetch_acv 213 # ITB acv
> system.cpu1.itb.fetch_accesses 491669 # ITB accesses
1499c1563
< system.cpu1.numCycles 15249987 # number of cpu cycles simulated
---
> system.cpu1.numCycles 26365345 # number of cpu cycles simulated
1502,1517c1566,1581
< system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total)
1519,1527c1583,1591
< system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total)
1531,1575c1595,1639
< system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle
1577,1585c1641,1649
< system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle
1589c1653
< system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle
1591,1621c1655,1685
< system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available
1624,1656c1688,1720
< system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued
1658,1670c1722,1734
< system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued
< system.cpu1.iq.rate 0.605480 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued
> system.cpu1.iq.rate 0.569740 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores
1672,1675c1736,1739
< system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed
1678,1679c1742,1743
< system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked
1681,1697c1745,1761
< system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute
1699,1707c1763,1771
< system.cpu1.iew.exec_nop 488162 # number of nop insts executed
< system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1362461 # Number of branches executed
< system.cpu1.iew.exec_stores 1211286 # Number of stores executed
< system.cpu1.iew.exec_rate 0.599873 # Inst execution rate
< system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 4254481 # num instructions producing a value
< system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 898529 # number of nop insts executed
> system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 2338044 # Number of branches executed
> system.cpu1.iew.exec_stores 1780212 # Number of stores executed
> system.cpu1.iew.exec_rate 0.564317 # Inst execution rate
> system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 7139948 # num instructions producing a value
> system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value
1709,1710c1773,1774
< system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back
1712,1717c1776,1781
< system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle
1719,1727c1783,1791
< system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle
1731,1733c1795,1797
< system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 8962351 # Number of instructions committed
< system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 23251022 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 14604164 # Number of instructions committed
> system.cpu1.commit.committedOps 14604164 # Number of ops (including micro ops) committed
1735,1742c1799,1806
< system.cpu1.commit.refs 2852844 # Number of memory references committed
< system.cpu1.commit.loads 1698881 # Number of loads committed
< system.cpu1.commit.membars 42409 # Number of memory barriers committed
< system.cpu1.commit.branches 1280511 # Number of branches committed
< system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 141484 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached
---
> system.cpu1.commit.refs 4287363 # Number of memory references committed
> system.cpu1.commit.loads 2592870 # Number of loads committed
> system.cpu1.commit.membars 62980 # Number of memory barriers committed
> system.cpu1.commit.branches 2183593 # Number of branches committed
> system.cpu1.commit.fp_insts 107360 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 233831 # Number of function calls committed.
> system.cpu1.commit.bw_lim_events 466797 # number cycles where commit BW limit reached
1744,1807c1808,1871
< system.cpu1.rob.rob_reads 24092433 # The number of ROB reads
< system.cpu1.rob.rob_writes 21005155 # The number of ROB writes
< system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 8530162 # Number of Instructions Simulated
< system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated
< system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads
< system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes
< system.cpu1.icache.tags.replacements 214995 # number of replacements
< system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits
< system.cpu1.icache.overall_hits::total 1210101 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses
< system.cpu1.icache.overall_misses::total 223312 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked
---
> system.cpu1.rob.rob_reads 39695803 # The number of ROB reads
> system.cpu1.rob.rob_writes 34392702 # The number of ROB writes
> system.cpu1.timesIdled 272923 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 2721078 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 13810279 # Number of Instructions Simulated
> system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated
> system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 19249115 # number of integer regfile reads
> system.cpu1.int_regfile_writes 10558811 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 58616 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 58623 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 636847 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 274262 # number of misc regfile writes
> system.cpu1.icache.tags.replacements 328629 # number of replacements
> system.cpu1.icache.tags.tagsinuse 504.249918 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1927863 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 329141 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 5.857256 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 49124844500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.249918 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984863 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1927863 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1927863 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1927863 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1927863 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1927863 # number of overall hits
> system.cpu1.icache.overall_hits::total 1927863 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses
> system.cpu1.icache.overall_misses::total 344335 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4815194513 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4815194513 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4815194513 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4815194513 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4815194513 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4815194513 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 2272198 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 2272198 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 2272198 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 2272198 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 2272198 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 2272198 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151543 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.151543 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151543 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.151543 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151543 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.151543 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13984.040289 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13984.040289 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 1435 # number of cycles access was blocked
1809c1873
< system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 51 # number of cycles access was blocked
1811c1875
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 28.137255 # average number of cycles each access was blocked
1815,1844c1879,1908
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150387 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.150387 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.150387 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15125 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 15125 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 15125 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 15125 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 15125 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 15125 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329210 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3979739752 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3979739752 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.144886 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.144886 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.144886 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.144886 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12088.757182 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 12088.757182 # average overall mshr miss latency
1846,1927c1910,1991
< system.cpu1.dcache.tags.replacements 104218 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 490.671059 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 2506866 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 104618 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 23.962091 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.671059 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958342 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.958342 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 1537129 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 1537129 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 905397 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 905397 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30937 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 30937 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29831 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 29831 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 2442526 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 2442526 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 2442526 # number of overall hits
< system.cpu1.dcache.overall_hits::total 2442526 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 200186 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 200186 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 209846 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 209846 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5149 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 5149 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2998 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 2998 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 410032 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 410032 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 410032 # number of overall misses
< system.cpu1.dcache.overall_misses::total 410032 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2816563957 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2816563957 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7378261443 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 7378261443 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51136995 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 51136995 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22092953 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 22092953 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 10194825400 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 10194825400 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 10194825400 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 10194825400 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 1737315 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1115243 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1115243 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36086 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 36086 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 32829 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 2852558 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 2852558 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 2852558 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188162 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.188162 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142687 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142687 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143742 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.143742 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143742 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked
---
> system.cpu1.dcache.tags.replacements 330658 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 495.877996 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 3531981 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 331060 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 10.668704 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 42038170500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.877996 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968512 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.968512 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 2174883 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 2174883 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1270139 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1270139 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 43234 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 43234 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 46255 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 3445022 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 3445022 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 3445022 # number of overall hits
> system.cpu1.dcache.overall_hits::total 3445022 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 478937 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 478937 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 369959 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 369959 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7995 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 815 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 815 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 848896 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 848896 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 848896 # number of overall misses
> system.cpu1.dcache.overall_misses::total 848896 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7393539723 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 7393539723 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13842081157 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 13842081157 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 114418247 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 114418247 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5712098 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5712098 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 21235620880 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 21235620880 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 21235620880 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 21235620880 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2653820 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2653820 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1640098 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1640098 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 51229 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 51229 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 47070 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 47070 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 4293918 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 4293918 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 4293918 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 4293918 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.180471 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.180471 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225571 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.225571 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156064 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156064 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017315 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017315 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197697 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.197697 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197697 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.197697 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15437.395154 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15437.395154 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37415.176160 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 37415.176160 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.225391 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14311.225391 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7008.709202 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7008.709202 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 25015.574205 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25015.574205 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 25015.574205 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 432228 # number of cycles access was blocked
1929c1993
< system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked
---
> system.cpu1.dcache.blocked::no_mshrs 7570 # number of cycles access was blocked
1931c1995
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57.097490 # average number of cycles each access was blocked
1935,2000c1999,2064
< system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks
< system.cpu1.dcache.writebacks::total 69226 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 251201 # number of writebacks
> system.cpu1.dcache.writebacks::total 251201 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211025 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 211025 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306586 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 306586 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1580 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1580 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 517611 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 517611 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 517611 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 517611 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267912 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 267912 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 63373 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 63373 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6415 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6415 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 815 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 815 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 331285 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 331285 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 331285 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 331285 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3418270202 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3418270202 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2068179649 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2068179649 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71253503 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71253503 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4081902 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4081902 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5486449851 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 5486449851 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5486449851 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5486449851 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491833500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491833500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 943255503 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 943255503 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1435089003 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1435089003 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.100953 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.100953 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038640 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038640 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.125222 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.125222 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017315 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017315 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.077152 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.077152 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.077152 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12758.929059 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12758.929059 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32635.028309 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32635.028309 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11107.327046 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11107.327046 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5008.468712 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5008.468712 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16561.117621 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16561.117621 # average overall mshr miss latency
2009,2029c2073,2093
< system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.09% 39.83% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1866804619500 98.01% 98.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1904664253500 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.983248 # fraction of swpipl calls that actually changed the ipl
2033,2064c2097,2128
< system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
< system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed
< system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
< system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
< system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
< system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed
< system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
< system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
< system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed
< system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
< system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
< system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed
< system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
< system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
< system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
< system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
< system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
< system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
< system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
< system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
< system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
< system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
< system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
< system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
< system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
< system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
< system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
< system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
< system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
< system.cpu0.kern.syscall::total 211 # number of syscalls executed
---
> system.cpu0.kern.ipl_used::31 0.664268 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
> system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
> system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
> system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed
> system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed
> system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed
> system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed
> system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed
> system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed
> system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed
> system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed
> system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed
> system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed
> system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed
> system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed
> system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed
> system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed
> system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed
> system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed
> system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed
> system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed
> system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed
> system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed
> system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed
> system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed
> system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed
> system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed
> system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed
> system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed
> system.cpu0.kern.syscall::total 202 # number of syscalls executed
2066,2084c2130,2148
< system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed
< system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed
< system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed
< system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed
< system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 169239 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches
---
> system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed
> system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6127 4.09% 96.83% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 96.83% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 3 0.00% 96.83% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 8 0.01% 96.83% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 96.84% # number of callpals executed
> system.cpu0.kern.callpal::rti 4274 2.85% 99.69% # number of callpals executed
> system.cpu0.kern.callpal::callsys 333 0.22% 99.91% # number of callpals executed
> system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 149930 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches
2086,2087c2150,2151
< system.cpu0.kern.mode_good::kernel 1285
< system.cpu0.kern.mode_good::user 1286
---
> system.cpu0.kern.mode_good::kernel 1257
> system.cpu0.kern.mode_good::user 1258
2089c2153
< system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches
2092,2094c2156,2158
< system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode
2096c2160
< system.cpu0.kern.swap_context 3515 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 2970 # number of times the context was actually changed
2098,2115c2162,2179
< system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl
2118,2141c2182,2205
< system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
< system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
< system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
< system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
< system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
< system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
< system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
< system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
< system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
< system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
< system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
< system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
< system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
< system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
< system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
< system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
< system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
< system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
< system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
< system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
< system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
< system.cpu1.kern.syscall::total 115 # number of syscalls executed
---
> system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
> system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
> system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
> system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed
> system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed
> system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed
> system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed
> system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed
> system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed
> system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed
> system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed
> system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed
> system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed
> system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed
> system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed
> system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed
> system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed
> system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed
> system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed
> system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed
> system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
> system.cpu1.kern.syscall::total 124 # number of syscalls executed
2143,2157c2207,2221
< system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed
< system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed
< system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed
< system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed
< system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed
< system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed
> system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed
> system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed
> system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed
> system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed
> system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed
2159,2166c2223,2230
< system.cpu1.kern.callpal::total 48756 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 668
< system.cpu1.kern.mode_good::user 459
< system.cpu1.kern.mode_good::idle 209
< system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 66403 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 557
> system.cpu1.kern.mode_good::user 488
> system.cpu1.kern.mode_good::idle 69
> system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches
2168,2173c2232,2237
< system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1096 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1278 # number of times the context was actually changed