3,5c3,5
< sim_seconds 1.904274 # Number of seconds simulated
< sim_ticks 1904273734500 # Number of ticks simulated
< final_tick 1904273734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.902739 # Number of seconds simulated
> sim_ticks 1902738973500 # Number of ticks simulated
> final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 95291 # Simulator instruction rate (inst/s)
< host_op_rate 95291 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3200085877 # Simulator tick rate (ticks/s)
< host_mem_usage 314408 # Number of bytes of host memory used
< host_seconds 595.07 # Real time elapsed on the host
< sim_insts 56704659 # Number of instructions simulated
< sim_ops 56704659 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 939456 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24909888 # Number of bytes read from this memory
---
> host_inst_rate 97410 # Simulator instruction rate (inst/s)
> host_op_rate 97410 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3267297836 # Simulator tick rate (ticks/s)
> host_mem_usage 312988 # Number of bytes of host memory used
> host_seconds 582.36 # Real time elapsed on the host
> sim_insts 56727331 # Number of instructions simulated
> sim_ops 56727331 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24806400 # Number of bytes read from this memory
17,26c17,26
< system.physmem.bytes_read::cpu1.inst 36288 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 341184 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28877632 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 939456 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 36288 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 975744 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7866880 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7866880 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 14679 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 389217 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu1.inst 74944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 436992 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28869696 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 900544 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 74944 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 975488 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7821440 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7821440 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 14071 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 387600 # Number of read requests responded to by this memory
28,91c28,92
< system.physmem.num_reads::cpu1.inst 567 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 5331 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 451213 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 122920 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 122920 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 493341 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 13081044 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1392035 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 19056 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 179168 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15164643 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 493341 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 19056 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 512397 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4131171 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4131171 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4131171 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 493341 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 13081044 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1392035 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 19056 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 179168 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19295814 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 451213 # Total number of read requests seen
< system.physmem.writeReqs 122920 # Total number of write requests seen
< system.physmem.cpureqs 579004 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28877632 # Total number of bytes read from memory
< system.physmem.bytesWritten 7866880 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28877632 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7866880 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 4871 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28315 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 28267 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 28452 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 27960 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 28079 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 27988 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 28494 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27838 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28154 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 28095 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 28334 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 27996 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 28689 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 28482 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 28304 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27691 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 8030 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7738 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7941 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7420 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7615 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7448 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 8007 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7267 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7422 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7442 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7742 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7420 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 8140 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 8013 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7952 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7323 # Track writes on a per bank basis
---
> system.physmem.num_reads::cpu1.inst 1171 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 6828 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 451089 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 122210 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 122210 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 473288 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 13037206 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1393158 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 39387 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 229665 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15172704 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 473288 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 39387 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 512676 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4110622 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4110622 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4110622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 473288 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 13037206 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1393158 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 39387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 229665 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19283326 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 451089 # Total number of read requests accepted by DRAM controller
> system.physmem.writeReqs 122210 # Total number of write requests accepted by DRAM controller
> system.physmem.readBursts 451089 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
> system.physmem.writeBursts 122210 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
> system.physmem.bytesRead 28869696 # Total number of bytes read from memory
> system.physmem.bytesWritten 7821440 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28869696 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7821440 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
> system.physmem.neitherReadNorWrite 4926 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 28134 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 28249 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 28671 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 28418 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 27918 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 28169 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 28110 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 27493 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 27636 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 28106 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 28006 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 28071 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 28522 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 28683 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 28473 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 28357 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7885 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7743 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 8146 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 7856 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 7637 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7614 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 6924 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 6873 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 7305 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 7296 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 7454 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7954 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 8175 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 8091 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7908 # Track writes on a per bank basis
93,94c94,95
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1904269209000 # Total gap between requests
---
> system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1902738952500 # Total gap between requests
101c102
< system.physmem.readPktSize::6 451213 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 451089 # Categorize read packet sizes
108,122c109,123
< system.physmem.writePktSize::6 122920 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 323687 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 64950 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 30594 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 6666 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3343 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 3044 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1568 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1533 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1488 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1465 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1421 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1414 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1398 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 122210 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 323917 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 64738 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 30395 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3317 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 3023 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1574 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1542 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1506 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1471 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1443 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1440 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 2046 # What read queue length does an incoming req see
124,128c125,129
< system.physmem.rdQLenPdf::15 2211 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1201 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 450 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::15 2216 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1205 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 449 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 234 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see
130c131
< system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
141,271c142,275
< system.physmem.wrQLenPdf::0 3741 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 5058 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 5341 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 5343 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 1604 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1370 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 40619 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 904.415372 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 224.615874 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 2354.830128 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 14269 35.13% 35.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 6234 15.35% 50.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 3791 9.33% 59.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 2540 6.25% 66.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 1773 4.36% 70.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 1547 3.81% 74.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 1102 2.71% 76.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 849 2.09% 79.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 692 1.70% 80.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 549 1.35% 82.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 540 1.33% 83.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 500 1.23% 84.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 249 0.61% 85.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 230 0.57% 85.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 188 0.46% 86.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 304 0.75% 87.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 110 0.27% 87.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 108 0.27% 87.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 118 0.29% 87.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 201 0.49% 88.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 117 0.29% 89.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 501 1.23% 90.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 643 1.58% 91.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 97 0.24% 92.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 31 0.08% 92.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 107 0.26% 92.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 9 0.02% 92.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 14 0.03% 92.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 38 0.09% 92.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 26 0.06% 92.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 3 0.01% 92.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 4 0.01% 92.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 21 0.05% 92.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 11 0.03% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 2 0.00% 92.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 6 0.01% 93.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 4 0.01% 93.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 1 0.00% 93.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 3 0.01% 93.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 5 0.01% 93.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 3 0.01% 93.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 1 0.00% 93.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 1 0.00% 93.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 2 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 1 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 1 0.00% 93.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 2 0.00% 93.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 2 0.00% 93.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 2 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 3 0.01% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4803 2 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5123 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7104-7107 1 0.00% 93.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 2429 5.98% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.22% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::0 3729 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3933 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 5016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5304 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 5307 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5307 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 1585 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1381 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 298 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 40469 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 906.491388 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 223.789110 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 2353.116019 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 14451 35.71% 35.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 6072 15.00% 50.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 3826 9.45% 60.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 2468 6.10% 66.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 1670 4.13% 70.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 1520 3.76% 74.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1058 2.61% 76.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 819 2.02% 78.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 687 1.70% 80.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 564 1.39% 81.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 556 1.37% 83.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 509 1.26% 84.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 268 0.66% 85.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 232 0.57% 85.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 203 0.50% 86.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 288 0.71% 86.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 119 0.29% 87.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 109 0.27% 87.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 110 0.27% 87.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 196 0.48% 88.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 187 0.46% 88.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 119 0.29% 89.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 500 1.24% 90.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 628 1.55% 91.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 91 0.22% 92.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 33 0.08% 92.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 28 0.07% 92.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 99 0.24% 92.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 30 0.07% 92.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 12 0.03% 92.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 48 0.12% 92.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 23 0.06% 92.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 33 0.08% 92.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 8 0.02% 92.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 6 0.01% 92.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 7 0.02% 92.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 2 0.00% 93.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 1 0.00% 93.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 3 0.01% 93.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 4 0.01% 93.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 1 0.00% 93.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 2 0.00% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 2 0.00% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 3 0.01% 93.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 2 0.00% 93.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 1 0.00% 93.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 3 0.01% 93.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 4 0.01% 93.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 1 0.00% 93.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 1 0.00% 93.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 2 0.00% 93.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 3 0.01% 93.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 1 0.00% 93.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4291 1 0.00% 93.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 2 0.00% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4611 1 0.00% 93.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 3 0.01% 93.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5187 1 0.00% 93.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5379 2 0.00% 93.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5443 1 0.00% 93.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5635 1 0.00% 93.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 1 0.00% 93.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 1 0.00% 93.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 1 0.00% 93.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 1 0.00% 93.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 1 0.00% 93.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6851 2 0.00% 93.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 1 0.00% 93.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7107 2 0.00% 93.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 3 0.01% 93.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7360-7363 2 0.00% 93.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7427 1 0.00% 93.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7811 2 0.00% 93.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7939 1 0.00% 93.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8067 3 0.01% 93.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 7 0.02% 93.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 2429 6.00% 99.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.23% # Bytes accessed per row activation
273,310c277,314
< system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 14 0.03% 99.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16387 248 0.61% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16512-16515 5 0.01% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16576-16579 7 0.02% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16768-16771 2 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16832-16835 2 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17088-17091 4 0.01% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17216-17219 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 40619 # Bytes accessed per row activation
< system.physmem.totQLat 6391304750 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13854944750 # Sum of mem lat for all requests
< system.physmem.totBusLat 2255690000 # Total cycles spent in databus access
< system.physmem.totBankLat 5207950000 # Total cycles spent in bank access
< system.physmem.avgQLat 14167.07 # Average queueing delay per request
< system.physmem.avgBankLat 11544.03 # Average bank access latency per request
---
> system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16387 243 0.60% 99.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16576-16579 5 0.01% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17088-17091 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17344-17347 2 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 40469 # Bytes accessed per row activation
> system.physmem.totQLat 6403559750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 13868349750 # Sum of mem lat for all requests
> system.physmem.totBusLat 2255080000 # Total cycles spent in databus access
> system.physmem.totBankLat 5209710000 # Total cycles spent in bank access
> system.physmem.avgQLat 14198.08 # Average queueing delay per request
> system.physmem.avgBankLat 11551.05 # Average bank access latency per request
312,316c316,320
< system.physmem.avgMemAccLat 30711.10 # Average memory access latency
< system.physmem.avgRdBW 15.16 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 4.13 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 15.16 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 4.13 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 30749.13 # Average memory access latency
> system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s
320,341c324,345
< system.physmem.avgWrQLen 14.33 # Average write queue length over time
< system.physmem.readRowHits 435283 # Number of row buffer hits during reads
< system.physmem.writeRowHits 98148 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 96.49 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.85 # Row buffer hit rate for writes
< system.physmem.avgGap 3316773.66 # Average gap between requests
< system.membus.throughput 19353836 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 296513 # Transaction distribution
< system.membus.trans_dist::ReadResp 296436 # Transaction distribution
< system.membus.trans_dist::WriteReq 13046 # Transaction distribution
< system.membus.trans_dist::WriteResp 13046 # Transaction distribution
< system.membus.trans_dist::Writeback 122920 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 9558 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 5502 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4874 # Transaction distribution
< system.membus.trans_dist::ReadExReq 162935 # Transaction distribution
< system.membus.trans_dist::ReadExResp 162546 # Transaction distribution
< system.membus.trans_dist::BadAddressError 77 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40482 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921574 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 962210 # Packet count per connected master and slave (bytes)
---
> system.physmem.avgWrQLen 14.36 # Average write queue length over time
> system.physmem.readRowHits 435126 # Number of row buffer hits during reads
> system.physmem.writeRowHits 97620 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 96.48 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 79.88 # Row buffer hit rate for writes
> system.physmem.avgGap 3318929.48 # Average gap between requests
> system.membus.throughput 19341454 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 296468 # Transaction distribution
> system.membus.trans_dist::ReadResp 296394 # Transaction distribution
> system.membus.trans_dist::WriteReq 13061 # Transaction distribution
> system.membus.trans_dist::WriteResp 13061 # Transaction distribution
> system.membus.trans_dist::Writeback 122210 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 9880 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 5735 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4929 # Transaction distribution
> system.membus.trans_dist::ReadExReq 162867 # Transaction distribution
> system.membus.trans_dist::ReadExResp 162463 # Transaction distribution
> system.membus.trans_dist::BadAddressError 74 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40510 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 921241 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 961899 # Packet count per connected master and slave (bytes)
344,350c348,351
< system.membus.pkt_count::system.bridge.slave 40482 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::system.physmem.port 1046240 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::system.membus.badaddr_responder.pio 154 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1086876 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31436416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 31510170 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1086565 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73866 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31383040 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 31456906 # Cumulative packet size per connected master and slave (bytes)
353,356c354,355
< system.membus.tot_pkt_size::system.bridge.slave 73754 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::system.physmem.port 36744512 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36818266 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36818266 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 36765002 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 36765002 # Total data (bytes)
358c357
< system.membus.reqLayer0.occupancy 37871498 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 37911498 # Layer occupancy (ticks)
360c359
< system.membus.reqLayer1.occupancy 1615737499 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1609327499 # Layer occupancy (ticks)
362c361
< system.membus.reqLayer2.occupancy 99000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 93500 # Layer occupancy (ticks)
364c363
< system.membus.respLayer1.occupancy 3831920118 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3831145563 # Layer occupancy (ticks)
366c365
< system.membus.respLayer2.occupancy 376228744 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376230495 # Layer occupancy (ticks)
368,532c367,531
< system.l2c.tags.replacements 344278 # number of replacements
< system.l2c.tags.tagsinuse 65254.004539 # Cycle average of tags in use
< system.l2c.tags.total_refs 2578331 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 409473 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 6.296706 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 53538.058266 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5369.862130 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6148.232371 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 134.758747 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 63.093024 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.816926 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.081938 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.093815 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.002056 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000963 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.995697 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 876771 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 739535 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 198332 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 63825 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1878463 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 821103 # number of Writeback hits
< system.l2c.Writeback_hits::total 821103 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 177 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 433 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 46 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 156398 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 23000 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 179398 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 876771 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 895933 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 198332 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 86825 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2057861 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 876771 # number of overall hits
< system.l2c.overall_hits::cpu0.data 895933 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 198332 # number of overall hits
< system.l2c.overall_hits::cpu1.data 86825 # number of overall hits
< system.l2c.overall_hits::total 2057861 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 14688 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 273591 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 576 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 306 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 289161 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2677 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1042 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3719 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 416 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 865 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 116243 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 5041 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 121284 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 14688 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 389834 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 576 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 5347 # number of demand (read+write) misses
< system.l2c.demand_misses::total 410445 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 14688 # number of overall misses
< system.l2c.overall_misses::cpu0.data 389834 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 576 # number of overall misses
< system.l2c.overall_misses::cpu1.data 5347 # number of overall misses
< system.l2c.overall_misses::total 410445 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 1267720492 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17201796982 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 49661500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 29444499 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18548623473 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1381450 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 4584270 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 5965720 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 930960 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 99997 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1030957 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 9514647474 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 547564734 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10062212208 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1267720492 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 26716444456 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 49661500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 577009233 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 28610835681 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1267720492 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 26716444456 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 49661500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 577009233 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 28610835681 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 891459 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 1013126 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 198908 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 64131 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2167624 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 821103 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 821103 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2854 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 1298 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 4152 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 462 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 469 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 931 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 272641 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 28041 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 300682 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 891459 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1285767 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 198908 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 92172 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2468306 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 891459 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1285767 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 198908 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 92172 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2468306 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.016476 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.270046 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.002896 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.004771 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.133400 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.802773 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.895713 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.900433 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.957356 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.929108 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.426359 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.179772 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.403363 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.016476 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.303192 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.002896 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.058011 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.166286 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.016476 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.303192 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.002896 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.058011 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.166286 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86309.946351 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 62874.133221 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86217.881944 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 96223.852941 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 64146.352631 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 516.044079 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4399.491363 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1604.119387 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2237.884615 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 222.710468 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1191.857803 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81851.358568 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108622.244396 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 82964.053033 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 86309.946351 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 68532.874136 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 86217.881944 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 107912.704881 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 69706.868596 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 86309.946351 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 68532.874136 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 86217.881944 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 107912.704881 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 69706.868596 # average overall miss latency
---
> system.l2c.tags.replacements 344151 # number of replacements
> system.l2c.tags.tagsinuse 65253.870311 # Cycle average of tags in use
> system.l2c.tags.total_refs 2581362 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 409161 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 6.308915 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 6889943750 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 53541.051154 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5362.839741 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6144.208257 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 141.383324 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 64.387836 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.816972 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.081830 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.093753 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.002157 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000982 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.995695 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 862836 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 735075 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 214357 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 69353 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1881621 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 822225 # number of Writeback hits
> system.l2c.Writeback_hits::total 822225 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 270 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 439 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 153625 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 26073 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 179698 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 862836 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 888700 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 214357 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 95426 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2061319 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 862836 # number of overall hits
> system.l2c.overall_hits::cpu0.data 888700 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 214357 # number of overall hits
> system.l2c.overall_hits::cpu1.data 95426 # number of overall hits
> system.l2c.overall_hits::total 2061319 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 14080 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 273430 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 427 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2676 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1075 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 3751 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 454 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 879 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 114757 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 6453 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 121210 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 14080 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 388187 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 6880 # number of demand (read+write) misses
> system.l2c.demand_misses::total 410327 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 14080 # number of overall misses
> system.l2c.overall_misses::cpu0.data 388187 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses
> system.l2c.overall_misses::cpu1.data 6880 # number of overall misses
> system.l2c.overall_misses::total 410327 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 1210878995 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 17193583984 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 109764250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 37725999 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18551953228 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1076463 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 4839759 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 5916222 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 977458 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 1070954 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 9311235979 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 722690467 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 10033926446 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1210878995 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 26504819963 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 109764250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 760416466 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 28585879674 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1210878995 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 26504819963 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 109764250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 760416466 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 28585879674 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 876916 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 1008505 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 215537 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 69780 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2170738 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 822225 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 822225 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2845 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 1345 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 4190 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 468 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 479 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 947 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 268382 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 32526 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 300908 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 876916 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1276887 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 215537 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 102306 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2471646 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 876916 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1276887 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 215537 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 102306 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2471646 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.016056 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.271124 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.005475 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.006119 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.133188 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940598 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.799257 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.895227 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.908120 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947808 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.928194 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.427588 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.198395 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.402814 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.016056 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.304010 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.005475 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.067249 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.166014 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.016056 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.304010 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.005475 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.067249 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.166014 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85999.928622 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 62881.117595 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 93020.550847 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 88351.285714 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 64167.631886 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 402.265695 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4502.101395 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1577.238603 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2299.901176 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 205.938326 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1218.377702 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81138.719024 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 111992.943902 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 82781.341853 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 69666.094783 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 85999.928622 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 68278.484243 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 93020.550847 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 110525.649128 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 69666.094783 # average overall miss latency
541,542c540,541
< system.l2c.writebacks::writebacks 81400 # number of writebacks
< system.l2c.writebacks::total 81400 # number of writebacks
---
> system.l2c.writebacks::writebacks 80690 # number of writebacks
> system.l2c.writebacks::total 80690 # number of writebacks
555,659c554,658
< system.l2c.ReadReq_mshr_misses::cpu0.inst 14680 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 273590 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 567 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 306 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 289143 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2677 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1042 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3719 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 416 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 449 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 865 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 116243 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 5041 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 121284 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 14680 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 389833 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 567 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 5347 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 410427 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 14680 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 389833 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 567 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 5347 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 410427 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1080994508 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13790759768 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 41895250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 25609501 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 14939259027 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26999133 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10444004 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 37443137 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4166407 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4502447 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 8668854 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8081951526 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 484942766 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8566894292 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1080994508 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 21872711294 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 41895250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 510552267 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 23506153319 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1080994508 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 21872711294 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 41895250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 510552267 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 23506153319 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372582500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16978000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1389560500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2039994500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 567881499 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2607875999 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3412577000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 584859499 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 3997436499 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270045 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004771 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.133392 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.802773 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.895713 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.900433 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957356 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.929108 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426359 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.179772 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.403363 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.303191 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.058011 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.166279 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016467 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.303191 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002851 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.058011 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.166279 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50406.666062 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83691.179739 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 51667.372293 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10085.593201 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.036468 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10068.065878 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.401442 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.721604 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.796532 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69526.350197 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96199.715533 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 70634.991359 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56107.900804 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73637.228065 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56107.900804 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73889.329806 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95483.872639 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 57272.434121 # average overall mshr miss latency
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 14072 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 273429 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 1171 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 427 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2676 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1075 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 3751 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 454 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 879 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 114757 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 6453 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 121210 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 14072 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 388186 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1171 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 6880 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 410309 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 14072 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 388186 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1171 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 6880 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 410309 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1031878505 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13784019266 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 94337500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 32390501 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 14942625772 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26984633 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10773037 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 37757670 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4256416 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4544453 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 8800869 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7896551021 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 642755533 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8539306554 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1031878505 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 21680570287 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 94337500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 675146034 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 23481932326 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1031878505 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 21680570287 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 94337500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 675146034 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 23481932326 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367321000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22027000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1389348000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2025100000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 585946999 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2611046999 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3392421000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607973999 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4000394999 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.271123 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006119 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.133180 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940598 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.799257 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.895227 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908120 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947808 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.928194 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427588 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198395 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.402814 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.166006 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016047 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.304010 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005433 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.067249 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.166006 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50411.694685 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75855.974239 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 51686.881560 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10083.943572 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.429767 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.027726 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.096471 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.808370 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.365188 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68811.061818 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99605.692391 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 70450.511954 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73328.489554 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55850.984546 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80561.485909 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98131.690988 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 57229.873890 # average overall mshr miss latency
670,678c669,677
< system.iocache.tags.replacements 41695 # number of replacements
< system.iocache.tags.tagsinuse 0.488928 # Cycle average of tags in use
< system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.488928 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.030558 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.030558 # Average percentage of cache occupancy
---
> system.iocache.tags.replacements 41695 # number of replacements
> system.iocache.tags.tagsinuse 0.476417 # Cycle average of tags in use
> system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 1711329338000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.476417 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.029776 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.029776 # Average percentage of cache occupancy
687,694c686,693
< system.iocache.ReadReq_miss_latency::tsunami.ide 21574383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21574383 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 10460928278 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10460928278 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10482502661 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10482502661 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10482502661 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10482502661 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21570383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21570383 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 10493964012 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10493964012 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10515534395 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10515534395 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10515534395 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10515534395 # number of overall miss cycles
711,719c710,718
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123282.188571 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123282.188571 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251755.108731 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 251755.108731 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 251216.302658 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 251216.302658 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 251216.302658 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 272971 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123259.331429 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 123259.331429 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252550.154313 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 252550.154313 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 252007.918015 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 252007.918015 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 252007.918015 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 275771 # number of cycles access was blocked
721c720
< system.iocache.blocked::no_mshrs 27017 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27285 # number of cycles access was blocked
723c722
< system.iocache.avg_blocked_cycles::no_mshrs 10.103675 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.107055 # average number of cycles each access was blocked
737,744c736,743
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12472883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12472883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8298854290 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8298854290 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8311327173 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8311327173 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8311327173 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8311327173 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12468883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8331886522 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8331886522 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8344355405 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8344355405 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8344355405 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8344355405 # number of overall MSHR miss cycles
753,760c752,759
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71273.617143 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 71273.617143 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199722.138285 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 199722.138285 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199183.434539 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 199183.434539 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71250.760000 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 71250.760000 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200517.099586 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 200517.099586 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199974.965969 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 199974.965969 # average overall mshr miss latency
774,778c773,777
< system.cpu0.branchPred.lookups 12622908 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 10616030 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 342195 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 8196943 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 5349460 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 12458299 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 10491650 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 332886 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 8054816 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 5283733 # Number of BTB hits
780,782c779,781
< system.cpu0.branchPred.BTBHitPct 65.261647 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 815211 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 29656 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 65.597191 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 799392 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 28656 # Number of incorrect RAS predictions.
787,802c786,801
< system.cpu0.dtb.read_hits 9003860 # DTB read hits
< system.cpu0.dtb.read_misses 33263 # DTB read misses
< system.cpu0.dtb.read_acv 538 # DTB read access violations
< system.cpu0.dtb.read_accesses 672573 # DTB read accesses
< system.cpu0.dtb.write_hits 5893133 # DTB write hits
< system.cpu0.dtb.write_misses 8284 # DTB write misses
< system.cpu0.dtb.write_acv 368 # DTB write access violations
< system.cpu0.dtb.write_accesses 235576 # DTB write accesses
< system.cpu0.dtb.data_hits 14896993 # DTB hits
< system.cpu0.dtb.data_misses 41547 # DTB misses
< system.cpu0.dtb.data_acv 906 # DTB access violations
< system.cpu0.dtb.data_accesses 908149 # DTB accesses
< system.cpu0.itb.fetch_hits 1042149 # ITB hits
< system.cpu0.itb.fetch_misses 31540 # ITB misses
< system.cpu0.itb.fetch_acv 1064 # ITB acv
< system.cpu0.itb.fetch_accesses 1073689 # ITB accesses
---
> system.cpu0.dtb.read_hits 8872852 # DTB read hits
> system.cpu0.dtb.read_misses 32010 # DTB read misses
> system.cpu0.dtb.read_acv 540 # DTB read access violations
> system.cpu0.dtb.read_accesses 628428 # DTB read accesses
> system.cpu0.dtb.write_hits 5797852 # DTB write hits
> system.cpu0.dtb.write_misses 8130 # DTB write misses
> system.cpu0.dtb.write_acv 348 # DTB write access violations
> system.cpu0.dtb.write_accesses 210128 # DTB write accesses
> system.cpu0.dtb.data_hits 14670704 # DTB hits
> system.cpu0.dtb.data_misses 40140 # DTB misses
> system.cpu0.dtb.data_acv 888 # DTB access violations
> system.cpu0.dtb.data_accesses 838556 # DTB accesses
> system.cpu0.itb.fetch_hits 994919 # ITB hits
> system.cpu0.itb.fetch_misses 28800 # ITB misses
> system.cpu0.itb.fetch_acv 922 # ITB acv
> system.cpu0.itb.fetch_accesses 1023719 # ITB accesses
815c814
< system.cpu0.numCycles 115698572 # number of cpu cycles simulated
---
> system.cpu0.numCycles 114636003 # number of cpu cycles simulated
818,833c817,832
< system.cpu0.fetch.icacheStallCycles 25430461 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 64765722 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 12622908 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 6164671 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 12173111 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1754282 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.BlockedCycles 37681561 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 33129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 206182 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 360791 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 463 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 7843120 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 77014869 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.840951 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.178782 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 25048083 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 63888139 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 12458299 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 6083125 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 12009946 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1716539 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.BlockedCycles 37364333 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 31995 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 196940 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 358937 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 467 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 7724257 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 222992 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 76114982 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.839364 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.177033 # Number of instructions fetched each cycle (Total)
835,843c834,842
< system.cpu0.fetch.rateDist::0 64841758 84.19% 84.19% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 778083 1.01% 85.20% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1579221 2.05% 87.25% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 722075 0.94% 88.19% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2615191 3.40% 91.59% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 535253 0.69% 92.28% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 589170 0.77% 93.05% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 842021 1.09% 94.14% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 4512097 5.86% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 64105036 84.22% 84.22% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 766655 1.01% 85.23% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1565630 2.06% 87.29% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 705022 0.93% 88.21% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2586372 3.40% 91.61% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 523946 0.69% 92.30% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 578047 0.76% 93.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 832534 1.09% 94.15% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 4451740 5.85% 100.00% # Number of instructions fetched each cycle (Total)
847,891c846,890
< system.cpu0.fetch.rateDist::total 77014869 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.109102 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.559780 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 26714732 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 37197398 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 11068686 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 941364 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1092688 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 522796 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 36882 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 63559406 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 110759 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1092688 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 27743135 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 15107351 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 18539290 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 10375436 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 4156967 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 60135459 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 7108 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 639244 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1468640 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.RenamedOperands 40265671 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 73230382 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 72843642 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 386740 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 35289688 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4975975 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1473731 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 214800 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 11344202 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 9431276 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 6179329 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1162337 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 768163 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 53333771 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1831002 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 52106137 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 101747 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 6058761 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 3179609 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1240264 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 77014869 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.676572 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.327910 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 76114982 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.108677 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.557313 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 26317520 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 36878715 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 10917325 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 932522 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1068899 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 511897 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 35733 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 62704701 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 106993 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1068899 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 27334042 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 15040257 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 18326535 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 10227103 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 4118144 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 59323627 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 7153 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 638131 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 71847381 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 384293 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 211881 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 11242711 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 9290886 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 6078694 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1146384 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 744084 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 52609114 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1811011 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 51412755 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 100173 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 5939256 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 3114263 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1226583 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 76114982 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.675462 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.326460 # Number of insts issued each cycle
893,901c892,900
< system.cpu0.iq.issued_per_cycle::0 53895136 69.98% 69.98% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 10485242 13.61% 83.59% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 4754218 6.17% 89.77% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 3135006 4.07% 93.84% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2479570 3.22% 97.06% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1230098 1.60% 98.66% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 664050 0.86% 99.52% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 318021 0.41% 99.93% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 53528 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 53279780 70.00% 70.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 10372988 13.63% 83.63% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 4693410 6.17% 89.79% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 3092664 4.06% 93.86% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2443569 3.21% 97.07% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1213853 1.59% 98.66% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 652140 0.86% 99.52% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 314050 0.41% 99.93% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 52528 0.07% 100.00% # Number of insts issued each cycle
905c904
< system.cpu0.iq.issued_per_cycle::total 77014869 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 76114982 # Number of insts issued each cycle
907,937c906,936
< system.cpu0.iq.fu_full::IntAlu 83201 11.94% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 325493 46.71% 58.64% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 288201 41.36% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 82827 12.15% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 318873 46.78% 58.93% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 279966 41.07% 100.00% # attempts to use FU when none available
941,972c940,971
< system.cpu0.iq.FU_type_0::IntAlu 35867732 68.84% 68.84% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 57468 0.11% 68.95% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.95% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 15763 0.03% 68.98% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.98% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.98% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.98% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.99% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 9368607 17.98% 86.97% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5962928 11.44% 98.41% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 827971 1.59% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 35420825 68.90% 68.90% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 56384 0.11% 69.01% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 15702 0.03% 69.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9231506 17.96% 87.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5866326 11.41% 98.41% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 816348 1.59% 100.00% # Type of FU issued
974,986c973,985
< system.cpu0.iq.FU_type_0::total 52106137 # Type of FU issued
< system.cpu0.iq.rate 0.450361 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 696895 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.013375 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 181470771 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 60967498 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 51029740 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 555013 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 268874 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 261978 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 52508945 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 290302 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 547963 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 51412755 # Type of FU issued
> system.cpu0.iq.rate 0.448487 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 681666 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.013259 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 179170597 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 60104783 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 50356616 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 551733 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 267128 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 260409 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 51801972 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 288664 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 541765 # Number of loads that had data forwarded from stores
988,991c987,990
< system.cpu0.iew.lsq.thread0.squashedLoads 1165767 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 4234 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 13137 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 465736 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1139912 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 4116 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 12815 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 456622 # Number of stores squashed
994,995c993,994
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18478 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 155290 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18431 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 154294 # Number of times an access to memory failed due to the cache being blocked
997,1013c996,1012
< system.cpu0.iew.iewSquashCycles 1092688 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 10796951 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 798319 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 58424017 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 633798 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 9431276 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 6179329 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1612922 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 582630 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 5498 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 13137 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 168729 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 358890 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 527619 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 51705429 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 9061014 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 400707 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 1068899 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 10746647 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 795792 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 57645786 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 623000 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 9290886 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 6078694 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1595130 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 581617 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 5318 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 12815 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 164656 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 351489 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 516145 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 51022070 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 8928198 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 390684 # Number of squashed instructions skipped in execute
1015,1023c1014,1022
< system.cpu0.iew.exec_nop 3259244 # number of nop insts executed
< system.cpu0.iew.exec_refs 14976241 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 8231181 # Number of branches executed
< system.cpu0.iew.exec_stores 5915227 # Number of stores executed
< system.cpu0.iew.exec_rate 0.446898 # Inst execution rate
< system.cpu0.iew.wb_sent 51387761 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 51291718 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 25550537 # num instructions producing a value
< system.cpu0.iew.wb_consumers 34415470 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 3225661 # number of nop insts executed
> system.cpu0.iew.exec_refs 14747797 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 8123465 # Number of branches executed
> system.cpu0.iew.exec_stores 5819599 # Number of stores executed
> system.cpu0.iew.exec_rate 0.445079 # Inst execution rate
> system.cpu0.iew.wb_sent 50710143 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 50617025 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 25247170 # num instructions producing a value
> system.cpu0.iew.wb_consumers 34011376 # num instructions consuming a value
1025,1026c1024,1025
< system.cpu0.iew.wb_rate 0.443322 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.742414 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.441546 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.742315 # average fanout of values written-back
1028,1033c1027,1032
< system.cpu0.commit.commitSquashedInsts 6546847 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 590738 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 492268 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 75922181 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.681996 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.596696 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6411331 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 584428 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 481702 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 75046083 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.681415 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.595696 # Number of insts commited each cycle
1035,1043c1034,1042
< system.cpu0.commit.committed_per_cycle::0 56427011 74.32% 74.32% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 8133810 10.71% 85.04% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 4455745 5.87% 90.90% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2411043 3.18% 94.08% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1335893 1.76% 95.84% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 570067 0.75% 96.59% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 478554 0.63% 97.22% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 445477 0.59% 97.81% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1664581 2.19% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 55785925 74.34% 74.34% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 8029512 10.70% 85.04% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 4410175 5.88% 90.91% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2388789 3.18% 94.09% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1317256 1.76% 95.85% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 560978 0.75% 96.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 472301 0.63% 97.23% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 435634 0.58% 97.81% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1645513 2.19% 100.00% # Number of insts commited each cycle
1047,1049c1046,1048
< system.cpu0.commit.committed_per_cycle::total 75922181 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 51778647 # Number of instructions committed
< system.cpu0.commit.committedOps 51778647 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 75046083 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 51137491 # Number of instructions committed
> system.cpu0.commit.committedOps 51137491 # Number of ops (including micro ops) committed
1051,1058c1050,1057
< system.cpu0.commit.refs 13979102 # Number of memory references committed
< system.cpu0.commit.loads 8265509 # Number of loads committed
< system.cpu0.commit.membars 200777 # Number of memory barriers committed
< system.cpu0.commit.branches 7822311 # Number of branches committed
< system.cpu0.commit.fp_insts 259967 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 47959803 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 666551 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1664581 # number cycles where commit BW limit reached
---
> system.cpu0.commit.refs 13773046 # Number of memory references committed
> system.cpu0.commit.loads 8150974 # Number of loads committed
> system.cpu0.commit.membars 198820 # Number of memory barriers committed
> system.cpu0.commit.branches 7724848 # Number of branches committed
> system.cpu0.commit.fp_insts 258424 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 47356368 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 655486 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1645513 # number cycles where commit BW limit reached
1060,1077c1059,1076
< system.cpu0.rob.rob_reads 132380203 # The number of ROB reads
< system.cpu0.rob.rob_writes 117743806 # The number of ROB writes
< system.cpu0.timesIdled 1106178 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 38683703 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3692842270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 48811521 # Number of Instructions Simulated
< system.cpu0.committedOps 48811521 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 48811521 # Number of Instructions Simulated
< system.cpu0.cpi 2.370313 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.370313 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.421885 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.421885 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 68020458 # number of integer regfile reads
< system.cpu0.int_regfile_writes 37124303 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 128594 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 130201 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1727987 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 827975 # number of misc regfile writes
---
> system.cpu0.rob.rob_reads 130752703 # The number of ROB reads
> system.cpu0.rob.rob_writes 116166541 # The number of ROB writes
> system.cpu0.timesIdled 1097555 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 38521021 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3690835342 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 48197169 # Number of Instructions Simulated
> system.cpu0.committedOps 48197169 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 48197169 # Number of Instructions Simulated
> system.cpu0.cpi 2.378480 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.378480 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.420437 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.420437 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 67125195 # number of integer regfile reads
> system.cpu0.int_regfile_writes 36645952 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 127833 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 129422 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1709874 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 817230 # number of misc regfile writes
1109,1133c1108,1132
< system.toL2Bus.throughput 111303171 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2194950 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2194857 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 13046 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 13046 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 821103 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 9701 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 5568 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 15269 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 343378 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 301828 # Transaction distribution
< system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1783020 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3388598 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 397843 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 270349 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count 5839810 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 57053376 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 131002064 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 12730112 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 9815754 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size 210601306 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 210591002 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 1360704 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 4964254488 # Layer occupancy (ticks)
---
> system.toL2Bus.throughput 111571177 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2198759 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2198668 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 13061 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 13061 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 822225 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 10020 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 5803 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 15823 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 343740 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 302191 # Transaction distribution
> system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1753935 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3363647 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 431103 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 300395 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5849080 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56122624 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 129969996 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13794368 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 11000190 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 210887178 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 210876874 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 1413952 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 4971684979 # Layer occupancy (ticks)
1137c1136
< system.toL2Bus.respLayer0.occupancy 4017252621 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3951712593 # Layer occupancy (ticks)
1139c1138
< system.toL2Bus.respLayer1.occupancy 5927096055 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 5887546567 # Layer occupancy (ticks)
1141,1143c1140,1142
< system.toL2Bus.respLayer2.occupancy 895637092 # Layer occupancy (ticks)
< system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer3.occupancy 468506529 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 970657716 # Layer occupancy (ticks)
> system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer3.occupancy 517795038 # Layer occupancy (ticks)
1145,1151c1144,1150
< system.iobus.throughput 1436442 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
< system.iobus.trans_dist::WriteReq 54598 # Transaction distribution
< system.iobus.trans_dist::WriteResp 54598 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
---
> system.iobus.throughput 1437659 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
> system.iobus.trans_dist::WriteReq 54613 # Transaction distribution
> system.iobus.trans_dist::WriteResp 54613 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11914 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
1162c1161
< system.iobus.pkt_count_system.bridge.master::total 40482 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 40510 # Packet count per connected master and slave (bytes)
1165,1180c1164,1166
< system.iobus.pkt_count::system.tsunami.cchip.pio 11882 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 123936 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 123964 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47656 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
1191c1177
< system.iobus.tot_pkt_size_system.bridge.master::total 73754 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 73866 # Cumulative packet size per connected master and slave (bytes)
1194,1209c1180,1182
< system.iobus.tot_pkt_size::system.tsunami.cchip.pio 47528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2735378 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2735378 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 11237000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size::total 2735490 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2735490 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 11269000 # Layer occupancy (ticks)
1211c1184
< system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
1231c1204
< system.iobus.reqLayer29.occupancy 378252917 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 378285900 # Layer occupancy (ticks)
1235c1208
< system.iobus.respLayer0.occupancy 27436000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks)
1237c1210
< system.iobus.respLayer1.occupancy 43098256 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 43112505 # Layer occupancy (ticks)
1239,1284c1212,1257
< system.cpu0.icache.tags.replacements 890887 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.759385 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 6905559 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 891396 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 7.746904 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.759385 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995624 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.995624 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6905559 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6905559 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6905559 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6905559 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6905559 # number of overall hits
< system.cpu0.icache.overall_hits::total 6905559 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 937559 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 937559 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 937559 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 937559 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 937559 # number of overall misses
< system.cpu0.icache.overall_misses::total 937559 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13556216106 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13556216106 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13556216106 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13556216106 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13556216106 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13556216106 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 7843118 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 7843118 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 7843118 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 7843118 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 7843118 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 7843118 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119539 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.119539 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119539 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.119539 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119539 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.119539 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14459.053890 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14459.053890 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14459.053890 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14459.053890 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14459.053890 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 6417 # number of cycles access was blocked
---
> system.cpu0.icache.tags.replacements 876399 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.760309 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 6802362 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 876908 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 7.757213 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 26019048250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.760309 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995626 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.995626 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6802362 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6802362 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6802362 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6802362 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6802362 # number of overall hits
> system.cpu0.icache.overall_hits::total 6802362 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 921891 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 921891 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 921891 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 921891 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 921891 # number of overall misses
> system.cpu0.icache.overall_misses::total 921891 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13290047828 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13290047828 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13290047828 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13290047828 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13290047828 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13290047828 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 7724253 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 7724253 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 7724253 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 7724253 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 7724253 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 7724253 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119350 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.119350 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119350 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.119350 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119350 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.119350 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14416.072863 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14416.072863 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14416.072863 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14416.072863 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14416.072863 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked
1286c1259
< system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 232 # number of cycles access was blocked
1288c1261
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.168182 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.685345 # average number of cycles each access was blocked
1292,1321c1265,1294
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45998 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 45998 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 45998 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 45998 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 45998 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 45998 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 891561 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 891561 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 891561 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 891561 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 891561 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 891561 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11118457121 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11118457121 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11118457121 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11118457121 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11118457121 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11118457121 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113674 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.113674 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113674 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.113674 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12470.775551 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12470.775551 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.775551 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44872 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 44872 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 44872 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 44872 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 44872 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 44872 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 877019 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 877019 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 877019 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 877019 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 877019 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 877019 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10904529395 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 10904529395 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10904529395 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 10904529395 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10904529395 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 10904529395 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113541 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.113541 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113541 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.113541 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12433.629596 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12433.629596 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12433.629596 # average overall mshr miss latency
1323,1404c1296,1377
< system.cpu0.dcache.tags.replacements 1288020 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.688069 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 10644807 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1288532 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.261189 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.688069 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987672 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.987672 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6550900 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6550900 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3728429 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3728429 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165070 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 165070 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189835 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 189835 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 10279329 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 10279329 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 10279329 # number of overall hits
< system.cpu0.dcache.overall_hits::total 10279329 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1597921 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1597921 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1777729 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1777729 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20672 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 20672 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2669 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 2669 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3375650 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3375650 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3375650 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3375650 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40268021859 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 40268021859 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79880065793 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 79880065793 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 301767496 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 301767496 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20162915 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 20162915 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 120148087652 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 120148087652 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 120148087652 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 120148087652 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 8148821 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 8148821 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5506158 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5506158 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185742 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 185742 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192504 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 192504 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 13654979 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 13654979 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 13654979 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 13654979 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196092 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.196092 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322862 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.322862 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111294 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111294 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013865 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013865 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247210 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.247210 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247210 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.247210 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25200.258247 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 25200.258247 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44933.769879 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 44933.769879 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14597.885836 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14597.885836 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7554.482952 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7554.482952 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 35592.578511 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35592.578511 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 35592.578511 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 2948269 # number of cycles access was blocked
---
> system.cpu0.dcache.tags.replacements 1278910 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 505.619274 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 10469394 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1279422 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.182909 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 25842000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.619274 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987538 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.987538 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6440836 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6440836 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3667453 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3667453 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162740 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 162740 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187465 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 187465 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 10108289 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 10108289 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 10108289 # number of overall hits
> system.cpu0.dcache.overall_hits::total 10108289 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1585845 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1585845 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1749611 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1749611 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20563 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 20563 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2808 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 2808 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3335456 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3335456 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3335456 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3335456 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40055257591 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 40055257591 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78246234000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 78246234000 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 299434996 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 299434996 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20885924 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 20885924 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 118301491591 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 118301491591 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 118301491591 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 118301491591 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 8026681 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 8026681 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417064 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5417064 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183303 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 183303 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190273 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 190273 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 13443745 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 13443745 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 13443745 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 13443745 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197572 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.197572 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322981 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.322981 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112180 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112180 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014758 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014758 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248105 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.248105 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248105 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.248105 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25257.990277 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 25257.990277 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44722.074793 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 44722.074793 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14561.834168 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14561.834168 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7438.007123 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7438.007123 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 35467.861543 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35467.861543 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 35467.861543 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 2886351 # number of cycles access was blocked
1406c1379
< system.cpu0.dcache.blocked::no_mshrs 52342 # number of cycles access was blocked
---
> system.cpu0.dcache.blocked::no_mshrs 51822 # number of cycles access was blocked
1408c1381
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 56.327022 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 55.697407 # average number of cycles each access was blocked
1412,1477c1385,1450
< system.cpu0.dcache.writebacks::writebacks 760237 # number of writebacks
< system.cpu0.dcache.writebacks::total 760237 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 590547 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 590547 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1499620 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1499620 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4585 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4585 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 2090167 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 2090167 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 2090167 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 2090167 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007374 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 1007374 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 278109 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 278109 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16087 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16087 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2668 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 2668 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1285483 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1285483 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1285483 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1285483 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26624787726 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26624787726 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11708735082 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11708735082 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178034254 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178034254 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14826085 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14826085 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38333522808 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 38333522808 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38333522808 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 38333522808 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465041000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465041000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2164117998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2164117998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3629158998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3629158998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123622 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123622 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050509 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050509 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086609 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086609 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013859 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013859 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.094140 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094140 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.094140 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26429.893690 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26429.893690 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42101.244771 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42101.244771 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11066.964257 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11066.964257 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5557.003373 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5557.003373 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29820.326529 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29820.326529 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 752999 # number of writebacks
> system.cpu0.dcache.writebacks::total 752999 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 583027 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 583027 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1475561 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1475561 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4528 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4528 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 2058588 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 2058588 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 2058588 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 2058588 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002818 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 1002818 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274050 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 274050 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16035 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16035 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2807 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 2807 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1276868 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1276868 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1276868 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1276868 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26563866972 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26563866972 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11468217837 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11468217837 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177500254 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177500254 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15271076 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15271076 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38032084809 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 38032084809 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38032084809 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 38032084809 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459298500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459298500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2147907499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2147907499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607205999 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607205999 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124936 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124936 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050590 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050590 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087478 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087478 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014752 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014752 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.094979 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094979 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.094979 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26489.220349 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26489.220349 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41847.173279 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41847.173279 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11069.551232 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11069.551232 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5440.354827 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5440.354827 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29785.447524 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29785.447524 # average overall mshr miss latency
1485,1489c1458,1462
< system.cpu1.branchPred.lookups 2340238 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 1946356 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 62804 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 1358794 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 776922 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 2517085 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 2083961 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 72869 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 1481224 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 844711 # Number of BTB hits
1491,1493c1464,1466
< system.cpu1.branchPred.BTBHitPct 57.177320 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 157214 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 6628 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 57.027904 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 172550 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 7415 # Number of incorrect RAS predictions.
1498,1513c1471,1486
< system.cpu1.dtb.read_hits 1733483 # DTB read hits
< system.cpu1.dtb.read_misses 9288 # DTB read misses
< system.cpu1.dtb.read_acv 9 # DTB read access violations
< system.cpu1.dtb.read_accesses 276268 # DTB read accesses
< system.cpu1.dtb.write_hits 1103623 # DTB write hits
< system.cpu1.dtb.write_misses 1818 # DTB write misses
< system.cpu1.dtb.write_acv 38 # DTB write access violations
< system.cpu1.dtb.write_accesses 104203 # DTB write accesses
< system.cpu1.dtb.data_hits 2837106 # DTB hits
< system.cpu1.dtb.data_misses 11106 # DTB misses
< system.cpu1.dtb.data_acv 47 # DTB access violations
< system.cpu1.dtb.data_accesses 380471 # DTB accesses
< system.cpu1.itb.fetch_hits 375000 # ITB hits
< system.cpu1.itb.fetch_misses 5508 # ITB misses
< system.cpu1.itb.fetch_acv 148 # ITB acv
< system.cpu1.itb.fetch_accesses 380508 # ITB accesses
---
> system.cpu1.dtb.read_hits 1869470 # DTB read hits
> system.cpu1.dtb.read_misses 10476 # DTB read misses
> system.cpu1.dtb.read_acv 22 # DTB read access violations
> system.cpu1.dtb.read_accesses 321268 # DTB read accesses
> system.cpu1.dtb.write_hits 1203365 # DTB write hits
> system.cpu1.dtb.write_misses 2061 # DTB write misses
> system.cpu1.dtb.write_acv 64 # DTB write access violations
> system.cpu1.dtb.write_accesses 130567 # DTB write accesses
> system.cpu1.dtb.data_hits 3072835 # DTB hits
> system.cpu1.dtb.data_misses 12537 # DTB misses
> system.cpu1.dtb.data_acv 86 # DTB access violations
> system.cpu1.dtb.data_accesses 451835 # DTB accesses
> system.cpu1.itb.fetch_hits 424254 # ITB hits
> system.cpu1.itb.fetch_misses 6539 # ITB misses
> system.cpu1.itb.fetch_acv 190 # ITB acv
> system.cpu1.itb.fetch_accesses 430793 # ITB accesses
1526c1499
< system.cpu1.numCycles 14113255 # number of cpu cycles simulated
---
> system.cpu1.numCycles 15249987 # number of cpu cycles simulated
1529,1544c1502,1517
< system.cpu1.fetch.icacheStallCycles 5353605 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 10974333 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 2340238 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 934136 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 1960258 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 346091 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.BlockedCycles 5695969 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 25528 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 53832 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 54284 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1309338 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 41617 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 13363974 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.821188 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.197770 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 5781097 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 11894429 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 2517085 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1017261 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 2131045 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 385761 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.BlockedCycles 6016414 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 25794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 62392 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 56888 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1433413 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 48410 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 14320297 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.830599 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.206016 # Number of instructions fetched each cycle (Total)
1546,1554c1519,1527
< system.cpu1.fetch.rateDist::0 11403716 85.33% 85.33% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 124023 0.93% 86.26% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 213549 1.60% 87.86% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 153465 1.15% 89.01% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 264643 1.98% 90.99% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 105166 0.79% 91.77% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 115273 0.86% 92.64% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 186335 1.39% 94.03% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 797804 5.97% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 12189252 85.12% 85.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 136413 0.95% 86.07% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 229060 1.60% 87.67% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 170637 1.19% 88.86% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 294592 2.06% 90.92% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 114916 0.80% 91.72% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 126454 0.88% 92.61% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 195471 1.36% 93.97% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 863502 6.03% 100.00% # Number of instructions fetched each cycle (Total)
1558,1602c1531,1575
< system.cpu1.fetch.rateDist::total 13363974 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.165818 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.777590 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 5293087 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 5922521 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 1836128 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 97560 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 214677 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 97799 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 5876 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 10774764 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 17225 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 214677 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 5481600 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 352411 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 4990949 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 1741665 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 582670 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 9967248 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 54670 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 132191 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.RenamedOperands 6553947 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 11886744 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 11748684 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 138060 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 5636582 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 917365 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 415822 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 37623 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 1815514 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 1827244 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1170543 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 163690 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 89610 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 8737156 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 452580 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 8518295 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 27160 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1245229 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 620627 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 325893 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 13363974 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.637407 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.312561 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 14320297 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.165055 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.779963 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 5724387 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 6255039 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 1992849 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 108261 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 239760 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 108451 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 6971 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 11669639 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 20547 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 239760 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 5925475 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 420572 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 5212839 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 1896462 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 625187 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 10812976 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 55937 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 12790175 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 140614 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 40484 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 1926881 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 1976180 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1276143 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 178422 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 98267 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 9491737 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 473513 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 9233560 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 29148 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1376057 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 698810 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 340347 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 14320297 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.644788 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.319506 # Number of insts issued each cycle
1604,1612c1577,1585
< system.cpu1.iq.issued_per_cycle::0 9608930 71.90% 71.90% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 1736625 12.99% 84.90% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 727835 5.45% 90.34% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 487296 3.65% 93.99% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 421265 3.15% 97.14% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 191133 1.43% 98.57% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 120060 0.90% 99.47% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 63613 0.48% 99.95% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 7217 0.05% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 10263877 71.67% 71.67% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 1860247 12.99% 84.66% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 792265 5.53% 90.20% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 533948 3.73% 93.92% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 454852 3.18% 97.10% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 207190 1.45% 98.55% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 132078 0.92% 99.47% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 67607 0.47% 99.94% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 8233 0.06% 100.00% # Number of insts issued each cycle
1616c1589
< system.cpu1.iq.issued_per_cycle::total 13363974 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 14320297 # Number of insts issued each cycle
1618,1648c1591,1621
< system.cpu1.iq.fu_full::IntAlu 2685 1.53% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 94663 54.03% 55.56% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 77863 44.44% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 3147 1.66% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 101977 53.82% 55.48% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 84363 44.52% 100.00% # attempts to use FU when none available
1651,1683c1624,1656
< system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 5299330 62.21% 62.25% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 14840 0.17% 62.43% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 10732 0.13% 62.55% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.55% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.55% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.55% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.57% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 1812344 21.28% 83.85% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1125275 13.21% 97.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 250497 2.94% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 5756733 62.35% 62.38% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 16005 0.17% 62.56% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 10795 0.12% 62.67% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 1955574 21.18% 83.87% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1226577 13.28% 97.16% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 262587 2.84% 100.00% # Type of FU issued
1685,1697c1658,1670
< system.cpu1.iq.FU_type_0::total 8518295 # Type of FU issued
< system.cpu1.iq.rate 0.603567 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 175211 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.020569 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 30403276 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 10338814 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 8274405 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 199659 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 97460 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 94461 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 8585899 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 104089 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 83773 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 9233560 # Type of FU issued
> system.cpu1.iq.rate 0.605480 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 189487 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.020522 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 32803401 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 11243674 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 8968182 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 202651 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 99238 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 96146 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 9314130 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 105391 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 90243 # Number of loads that had data forwarded from stores
1699,1702c1672,1675
< system.cpu1.iew.lsq.thread0.squashedLoads 247116 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 1193 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 1397 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 111584 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 277299 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 1341 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 1688 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 122180 # Number of stores squashed
1705,1706c1678,1679
< system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 14213 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 318 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 14956 # Number of times an access to memory failed due to the cache being blocked
1708,1724c1681,1697
< system.cpu1.iew.iewSquashCycles 214677 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 210872 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 38123 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 9643840 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 131515 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 1827244 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1170543 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 410565 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 32525 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 1557 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 1397 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 28168 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 87904 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 116072 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 8443529 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 1749257 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 74766 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 239760 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 255964 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 40163 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 10453412 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 142319 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 1976180 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1276143 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 429143 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 33341 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 1750 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 1688 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 32963 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 95419 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 128382 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 9148055 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 1886987 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 85505 # Number of squashed instructions skipped in execute
1726,1734c1699,1707
< system.cpu1.iew.exec_nop 454104 # number of nop insts executed
< system.cpu1.iew.exec_refs 2860324 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1252098 # Number of branches executed
< system.cpu1.iew.exec_stores 1111067 # Number of stores executed
< system.cpu1.iew.exec_rate 0.598269 # Inst execution rate
< system.cpu1.iew.wb_sent 8394111 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 8368866 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 3943473 # num instructions producing a value
< system.cpu1.iew.wb_consumers 5568899 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 488162 # number of nop insts executed
> system.cpu1.iew.exec_refs 3098273 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1362461 # Number of branches executed
> system.cpu1.iew.exec_stores 1211286 # Number of stores executed
> system.cpu1.iew.exec_rate 0.599873 # Inst execution rate
> system.cpu1.iew.wb_sent 9092483 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 9064328 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 4254481 # num instructions producing a value
> system.cpu1.iew.wb_consumers 5984515 # num instructions consuming a value
1736,1737c1709,1710
< system.cpu1.iew.wb_rate 0.592979 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.708124 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.594383 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.710915 # average fanout of values written-back
1739,1744c1712,1717
< system.cpu1.commit.commitSquashedInsts 1277535 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 126687 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 110026 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 13149297 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.631052 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.572436 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 1421128 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 133166 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 121427 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 14080537 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.636506 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.577564 # Number of insts commited each cycle
1746,1754c1719,1727
< system.cpu1.commit.committed_per_cycle::0 10035587 76.32% 76.32% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 1461499 11.11% 87.43% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 536339 4.08% 91.51% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 329312 2.50% 94.02% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 237007 1.80% 95.82% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 91157 0.69% 96.51% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 98866 0.75% 97.27% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 97470 0.74% 98.01% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 262060 1.99% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 10719102 76.13% 76.13% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 1572221 11.17% 87.29% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 583613 4.14% 91.44% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 356342 2.53% 93.97% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 255998 1.82% 95.79% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 100117 0.71% 96.50% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 105425 0.75% 97.25% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 105001 0.75% 97.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 282718 2.01% 100.00% # Number of insts commited each cycle
1758,1760c1731,1733
< system.cpu1.commit.committed_per_cycle::total 13149297 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 8297892 # Number of instructions committed
< system.cpu1.commit.committedOps 8297892 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 14080537 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 8962351 # Number of instructions committed
> system.cpu1.commit.committedOps 8962351 # Number of ops (including micro ops) committed
1762,1769c1735,1742
< system.cpu1.commit.refs 2639087 # Number of memory references committed
< system.cpu1.commit.loads 1580128 # Number of loads committed
< system.cpu1.commit.membars 40354 # Number of memory barriers committed
< system.cpu1.commit.branches 1179945 # Number of branches committed
< system.cpu1.commit.fp_insts 93281 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 7680197 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 130349 # Number of function calls committed.
< system.cpu1.commit.bw_lim_events 262060 # number cycles where commit BW limit reached
---
> system.cpu1.commit.refs 2852844 # Number of memory references committed
> system.cpu1.commit.loads 1698881 # Number of loads committed
> system.cpu1.commit.membars 42409 # Number of memory barriers committed
> system.cpu1.commit.branches 1280511 # Number of branches committed
> system.cpu1.commit.fp_insts 94891 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 8306060 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 141484 # Number of function calls committed.
> system.cpu1.commit.bw_lim_events 282718 # number cycles where commit BW limit reached
1771,1834c1744,1807
< system.cpu1.rob.rob_reads 22380631 # The number of ROB reads
< system.cpu1.rob.rob_writes 19363835 # The number of ROB writes
< system.cpu1.timesIdled 119058 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 749281 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3793736462 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 7893138 # Number of Instructions Simulated
< system.cpu1.committedOps 7893138 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 7893138 # Number of Instructions Simulated
< system.cpu1.cpi 1.788041 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.788041 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.559271 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.559271 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 10874027 # number of integer regfile reads
< system.cpu1.int_regfile_writes 5958512 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 51748 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 51512 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 484557 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 198633 # number of misc regfile writes
< system.cpu1.icache.tags.replacements 198364 # number of replacements
< system.cpu1.icache.tags.tagsinuse 470.505741 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 1103940 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 198874 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 5.550952 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 1894556454000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.505741 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918957 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.918957 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1103940 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1103940 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1103940 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1103940 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1103940 # number of overall hits
< system.cpu1.icache.overall_hits::total 1103940 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 205398 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 205398 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 205398 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 205398 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 205398 # number of overall misses
< system.cpu1.icache.overall_misses::total 205398 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2726676790 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 2726676790 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 2726676790 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 2726676790 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 2726676790 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 2726676790 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1309338 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1309338 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1309338 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1309338 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1309338 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1309338 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.156872 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.156872 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.156872 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.156872 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.156872 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.156872 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13275.089290 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13275.089290 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13275.089290 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13275.089290 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13275.089290 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked
---
> system.cpu1.rob.rob_reads 24092433 # The number of ROB reads
> system.cpu1.rob.rob_writes 21005155 # The number of ROB writes
> system.cpu1.timesIdled 128904 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 929690 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3789568266 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 8530162 # Number of Instructions Simulated
> system.cpu1.committedOps 8530162 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 8530162 # Number of Instructions Simulated
> system.cpu1.cpi 1.787772 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.787772 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.559355 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.559355 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 11798212 # number of integer regfile reads
> system.cpu1.int_regfile_writes 6449971 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 52607 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 52314 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 504098 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 209723 # number of misc regfile writes
> system.cpu1.icache.tags.replacements 214995 # number of replacements
> system.cpu1.icache.tags.tagsinuse 470.564735 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1210101 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 215507 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 5.615135 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1878702632250 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.564735 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919072 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.919072 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1210101 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1210101 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1210101 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1210101 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1210101 # number of overall hits
> system.cpu1.icache.overall_hits::total 1210101 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 223312 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 223312 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 223312 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 223312 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 223312 # number of overall misses
> system.cpu1.icache.overall_misses::total 223312 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3028009139 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 3028009139 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 3028009139 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 3028009139 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 3028009139 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 3028009139 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1433413 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1433413 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1433413 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1433413 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1433413 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1433413 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155790 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.155790 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155790 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.155790 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155790 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.155790 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13559.545116 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13559.545116 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13559.545116 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13559.545116 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13559.545116 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked
1836c1809
< system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 32 # number of cycles access was blocked
1838c1811
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.166667 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 8.531250 # average number of cycles each access was blocked
1842,1871c1815,1844
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6463 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 6463 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 6463 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 6463 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 6463 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 6463 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 198935 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 198935 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 198935 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 198935 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 198935 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 198935 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2267895657 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 2267895657 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2267895657 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 2267895657 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2267895657 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 2267895657 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151936 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.151936 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151936 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.151936 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11400.184266 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11400.184266 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11400.184266 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7746 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 7746 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 7746 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 215566 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 215566 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 215566 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 215566 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 215566 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 215566 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2508977533 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 2508977533 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2508977533 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 2508977533 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2508977533 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 2508977533 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150387 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.150387 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150387 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.150387 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11639.022541 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11639.022541 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11639.022541 # average overall mshr miss latency
1873,1933c1846,1906
< system.cpu1.dcache.tags.replacements 93782 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 490.645175 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 2322631 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 94098 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 24.683107 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.645175 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958291 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.958291 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 1425624 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 1425624 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 844173 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 844173 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 28774 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 28774 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27671 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 27671 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 2269797 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 2269797 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 2269797 # number of overall hits
< system.cpu1.dcache.overall_hits::total 2269797 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 184725 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 184725 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 178548 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 178548 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4789 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 4789 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2902 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 2902 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 363273 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 363273 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 363273 # number of overall misses
< system.cpu1.dcache.overall_misses::total 363273 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2584165220 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2584165220 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5809552721 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 5809552721 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46614997 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 46614997 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21574947 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 21574947 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 8393717941 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 8393717941 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 8393717941 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 8393717941 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 1610349 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 1610349 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1022721 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1022721 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33563 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 33563 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30573 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 30573 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 2633070 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 2633070 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 2633070 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 2633070 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114711 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.114711 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174581 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.174581 # miss rate for WriteReq accesses
---
> system.cpu1.dcache.tags.replacements 104218 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 490.671059 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 2506866 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 104618 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 23.962091 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 44824844250 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 490.671059 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.958342 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.958342 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1537129 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1537129 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 905397 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 905397 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30937 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 30937 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29831 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 29831 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 2442526 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 2442526 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 2442526 # number of overall hits
> system.cpu1.dcache.overall_hits::total 2442526 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 200186 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 200186 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 209846 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 209846 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5149 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 5149 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2998 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 2998 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 410032 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 410032 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 410032 # number of overall misses
> system.cpu1.dcache.overall_misses::total 410032 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2816563957 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2816563957 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7378261443 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 7378261443 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51136995 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 51136995 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22092953 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 22092953 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 10194825400 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 10194825400 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 10194825400 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 10194825400 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 1737315 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 1737315 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1115243 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1115243 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36086 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 36086 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32829 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 32829 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 2852558 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 2852558 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 2852558 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 2852558 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.115227 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.115227 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188162 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.188162 # miss rate for WriteReq accesses
1936,1954c1909,1927
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094920 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094920 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.137966 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.137966 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.137966 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.137966 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.255488 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.255488 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32537.764192 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 32537.764192 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9733.764251 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9733.764251 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7434.509649 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7434.509649 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 23105.812821 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23105.812821 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 23105.812821 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 188355 # number of cycles access was blocked
---
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091322 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091322 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143742 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.143742 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143742 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.143742 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14069.734932 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14069.734932 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35160.362566 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 35160.362566 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9931.442028 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9931.442028 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7369.230487 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7369.230487 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 24863.487240 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24863.487240 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 24863.487240 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 240672 # number of cycles access was blocked
1956c1929
< system.cpu1.dcache.blocked::no_mshrs 3483 # number of cycles access was blocked
---
> system.cpu1.dcache.blocked::no_mshrs 3904 # number of cycles access was blocked
1958c1931
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 54.078381 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.647541 # average number of cycles each access was blocked
1962,2027c1935,2000
< system.cpu1.dcache.writebacks::writebacks 60866 # number of writebacks
< system.cpu1.dcache.writebacks::total 60866 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 114750 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 114750 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 145883 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 145883 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 398 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 398 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 260633 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 260633 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 260633 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 260633 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69975 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 69975 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32665 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 32665 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4391 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4391 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2900 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 2900 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 102640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 102640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 102640 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 102640 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 781048941 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 781048941 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 869596715 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 869596715 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32787753 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32787753 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15774053 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15774053 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1650645656 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 1650645656 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1650645656 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 1650645656 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18096000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18096000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600498502 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 600498502 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 618594502 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 618594502 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043453 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043453 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031939 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031939 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130829 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130829 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094855 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094855 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.038981 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038981 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.038981 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11161.828382 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11161.828382 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26621.665850 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26621.665850 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7467.035527 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7467.035527 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5439.328621 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5439.328621 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16081.894544 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16081.894544 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 69226 # number of writebacks
> system.cpu1.dcache.writebacks::total 69226 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 124077 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 124077 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 172447 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 172447 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 558 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 558 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 296524 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 296524 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 296524 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 296524 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 76109 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 76109 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 37399 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 37399 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4591 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4591 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2996 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 2996 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 113508 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 113508 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 113508 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 113508 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 856275217 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 856275217 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1088322932 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1088322932 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34640753 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34640753 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16100047 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16100047 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1944598149 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 1944598149 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1944598149 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 1944598149 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23613000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23613000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 620064002 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 620064002 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643677002 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643677002 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043808 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043808 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033534 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033534 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.127224 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.127224 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091261 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091261 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.039792 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039792 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.039792 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11250.643380 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11250.643380 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29100.321720 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29100.321720 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7545.361141 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7545.361141 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5373.847463 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5373.847463 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17131.815810 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17131.815810 # average overall mshr miss latency
2036,2056c2009,2029
< system.cpu0.kern.inst.quiesce 6628 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 186556 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 65870 40.60% 40.60% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.08% 40.68% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1925 1.19% 41.86% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 193 0.12% 41.98% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 94141 58.02% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 162260 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 64876 49.22% 49.22% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1925 1.46% 50.78% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 193 0.15% 50.93% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 64684 49.07% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 131809 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1863192383000 97.84% 97.84% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 64528500 0.00% 97.85% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 571927000 0.03% 97.88% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 92721000 0.00% 97.88% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 40351323000 2.12% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1904272882500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.984910 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 6603 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 184198 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 65080 40.52% 40.52% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.08% 40.60% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1924 1.20% 41.80% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 193 0.12% 41.92% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 93271 58.08% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 160599 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 64086 49.21% 49.21% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1924 1.48% 50.79% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 193 0.15% 50.94% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 63894 49.06% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 130228 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1861779564000 97.85% 97.85% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 63861000 0.00% 97.85% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 571607000 0.03% 97.88% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 92660000 0.00% 97.89% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 40230450500 2.11% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1902738142500 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.984726 # fraction of swpipl calls that actually changed the ipl
2060,2091c2033,2064
< system.cpu0.kern.ipl_used::31 0.687097 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.812332 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
< system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
< system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
< system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
< system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
< system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
< system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
< system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
< system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
< system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
< system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
< system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
< system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
< system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
< system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
< system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
< system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
< system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
< system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
< system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
< system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
< system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
< system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
< system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
< system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
< system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
< system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
< system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
< system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
< system.cpu0.kern.syscall::total 234 # number of syscalls executed
---
> system.cpu0.kern.ipl_used::31 0.685036 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.810889 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
> system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed
> system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
> system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
> system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
> system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed
> system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
> system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
> system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed
> system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
> system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
> system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed
> system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
> system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
> system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
> system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
> system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
> system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
> system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
> system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
> system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
> system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
> system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
> system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
> system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
> system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
> system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
> system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
> system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
> system.cpu0.kern.syscall::total 211 # number of syscalls executed
2093,2098c2066,2071
< system.cpu0.kern.callpal::wripir 275 0.16% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 3568 2.09% 2.25% # number of callpals executed
< system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed
---
> system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 3514 2.08% 2.25% # number of callpals executed
> system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed
2100,2111c2073,2084
< system.cpu0.kern.callpal::swpipl 155408 90.82% 93.10% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6655 3.89% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 4 0.00% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed
< system.cpu0.kern.callpal::rti 4603 2.69% 99.69% # number of callpals executed
< system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed
< system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 171120 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 7202 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches
---
> system.cpu0.kern.callpal::swpipl 153834 90.90% 93.18% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6534 3.86% 97.04% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 4 0.00% 97.04% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed
> system.cpu0.kern.callpal::rti 4517 2.67% 99.72% # number of callpals executed
> system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed
> system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 169239 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 7061 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches
2113,2114c2086,2087
< system.cpu0.kern.mode_good::kernel 1370
< system.cpu0.kern.mode_good::user 1371
---
> system.cpu0.kern.mode_good::kernel 1285
> system.cpu0.kern.mode_good::user 1286
2116c2089
< system.cpu0.kern.mode_switch_good::kernel 0.190225 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.181986 # fraction of useful protection mode switches
2119,2121c2092,2094
< system.cpu0.kern.mode_switch_good::total 0.319725 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1902171924000 99.89% 99.89% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 2100950500 0.11% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.308015 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1900726417500 99.89% 99.89% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 2011717000 0.11% 100.00% # number of ticks spent at the given mode
2123c2096
< system.cpu0.kern.swap_context 3569 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3515 # number of times the context was actually changed
2125,2142c2098,2115
< system.cpu1.kern.inst.quiesce 2405 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 53020 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 16452 36.11% 36.11% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1923 4.22% 40.33% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 275 0.60% 40.93% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 26914 59.07% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 45564 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 16069 47.18% 47.18% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1923 5.65% 52.82% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 275 0.81% 53.63% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 15794 46.37% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 34061 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1873583378500 98.41% 98.41% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 531505500 0.03% 98.43% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 123925000 0.01% 98.44% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 29687237000 1.56% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1903926046000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.976720 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2440 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 55424 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 17233 36.50% 36.50% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1922 4.07% 40.57% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 284 0.60% 41.17% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 27775 58.83% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 47214 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 16850 47.30% 47.30% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1922 5.40% 52.70% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 284 0.80% 53.50% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 16566 46.50% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 35622 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1871948155000 98.40% 98.40% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 531300500 0.03% 98.43% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 128640500 0.01% 98.43% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 29802235500 1.57% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1902410331500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.977775 # fraction of swpipl calls that actually changed the ipl
2145,2160c2118,2141
< system.cpu1.kern.ipl_used::31 0.586832 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.747542 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
< system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
< system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
< system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
< system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
< system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
< system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
< system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
< system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
< system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
< system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
< system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
< system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
< system.cpu1.kern.syscall::total 92 # number of syscalls executed
---
> system.cpu1.kern.ipl_used::31 0.596436 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.754480 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
> system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
> system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
> system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
> system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
> system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
> system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
> system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
> system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
> system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
> system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
> system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
> system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
> system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
> system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
> system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
> system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
> system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
> system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
> system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
> system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
> system.cpu1.kern.syscall::total 115 # number of syscalls executed
2162,2175c2143,2157
< system.cpu1.kern.callpal::wripir 193 0.41% 0.41% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 1035 2.21% 2.63% # number of callpals executed
< system.cpu1.kern.callpal::tbi 3 0.01% 2.63% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 2.65% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 40418 86.22% 88.87% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2100 4.48% 93.35% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 93.35% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 3 0.01% 93.36% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.01% 93.36% # number of callpals executed
< system.cpu1.kern.callpal::rti 2947 6.29% 99.65% # number of callpals executed
< system.cpu1.kern.callpal::callsys 121 0.26% 99.91% # number of callpals executed
< system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 193 0.40% 0.40% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.40% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.40% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 1095 2.25% 2.65% # number of callpals executed
> system.cpu1.kern.callpal::tbi 6 0.01% 2.66% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.01% 2.67% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 41959 86.06% 88.73% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2221 4.56% 93.29% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 93.29% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 3 0.01% 93.30% # number of callpals executed
> system.cpu1.kern.callpal::rdusp 1 0.00% 93.30% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.01% 93.31% # number of callpals executed
> system.cpu1.kern.callpal::rti 3048 6.25% 99.56% # number of callpals executed
> system.cpu1.kern.callpal::callsys 172 0.35% 99.91% # number of callpals executed
> system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed
2177,2184c2159,2166
< system.cpu1.kern.callpal::total 46877 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 1217 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2392 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 567
< system.cpu1.kern.mode_good::user 367
< system.cpu1.kern.mode_good::idle 200
< system.cpu1.kern.mode_switch_good::kernel 0.465900 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 48756 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1363 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2408 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 668
> system.cpu1.kern.mode_good::user 459
> system.cpu1.kern.mode_good::idle 209
> system.cpu1.kern.mode_switch_good::kernel 0.490095 # fraction of useful protection mode switches
2186,2191c2168,2173
< system.cpu1.kern.mode_switch_good::idle 0.083612 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.285211 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 3949860500 0.21% 0.21% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 686482000 0.04% 0.24% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1898967291500 99.76% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1036 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.086794 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.315839 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 4405402000 0.23% 0.23% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 814709500 0.04% 0.27% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1897179577000 99.73% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1096 # number of times the context was actually changed