3,5c3,5
< sim_seconds 1.900727 # Number of seconds simulated
< sim_ticks 1900727015500 # Number of ticks simulated
< final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.900728 # Number of seconds simulated
> sim_ticks 1900727697500 # Number of ticks simulated
> final_tick 1900727697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 47037 # Simulator instruction rate (inst/s)
< host_op_rate 47037 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1570523818 # Simulator tick rate (ticks/s)
< host_mem_usage 354648 # Number of bytes of host memory used
< host_seconds 1210.25 # Real time elapsed on the host
< sim_insts 56926994 # Number of instructions simulated
< sim_ops 56926994 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory
---
> host_inst_rate 95395 # Simulator instruction rate (inst/s)
> host_op_rate 95395 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3185234659 # Simulator tick rate (ticks/s)
> host_mem_usage 355712 # Number of bytes of host memory used
> host_seconds 596.73 # Real time elapsed on the host
> sim_insts 56925219 # Number of instructions simulated
> sim_ops 56925219 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 854208 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24595840 # Number of bytes read from this memory
17,26c17,26
< system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu1.inst 123328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 541952 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28767232 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 854208 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 123328 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7730048 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7730048 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13347 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 384310 # Number of read requests responded to by this memory
28,34c28,34
< system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu1.inst 1927 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8468 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 449488 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 120782 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 120782 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 449411 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12940223 # Total read bandwidth from this memory (bytes/s)
36,46c36,46
< system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 64885 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 285129 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15134852 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 449411 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 64885 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 514296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4066889 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4066889 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4066889 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 449411 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12940223 # Total bandwidth to/from this memory (bytes/s)
48,63c48,63
< system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 449493 # Total number of read requests seen
< system.physmem.writeReqs 120791 # Total number of write requests seen
< system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28767552 # Total number of bytes read from memory
< system.physmem.bytesWritten 7730624 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis
---
> system.physmem.bw_total::cpu1.inst 64885 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 285129 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19201740 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 449488 # Total number of read requests seen
> system.physmem.writeReqs 120782 # Total number of write requests seen
> system.physmem.cpureqs 575881 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 28767232 # Total number of bytes read from memory
> system.physmem.bytesWritten 7730048 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28767232 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7730048 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 76 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 5601 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 28386 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 28227 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 28192 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 27982 # Track reads on a per bank basis
65,69c65,69
< system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::5 28241 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 28220 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 28022 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 28087 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 28039 # Track reads on a per bank basis
71,79c71,79
< system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7707 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7701 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis
---
> system.physmem.perBankRdReqs::11 27938 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 27835 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 28000 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 27859 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 27848 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7706 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 7703 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 7519 # Track writes on a per bank basis
81,91c81,91
< system.physmem.perBankWrReqs::5 7578 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7608 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7520 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7649 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7589 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7579 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7352 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7235 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7444 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7276 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7350 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7606 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 7518 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 7651 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 7586 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 7578 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 7350 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7241 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 7443 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 7270 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7347 # Track writes on a per bank basis
93,94c93,94
< system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1900722456000 # Total gap between requests
---
> system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1900723138000 # Total gap between requests
101c101
< system.physmem.readPktSize::6 449493 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 449488 # Categorize read packet sizes
108,128c108,128
< system.physmem.writePktSize::6 120791 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 7610 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2961 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2698 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2655 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1511 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1447 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1362 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1348 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1369 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1521 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 120782 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 319759 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 59264 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 32659 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 7637 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2688 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2676 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2637 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2595 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1524 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1455 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1389 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1622 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1546 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 914 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see
130,131c130,131
< system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
141,146c141,146
< system.physmem.wrQLenPdf::0 3171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3801 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4360 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5224 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3807 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4886 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5229 # What write queue length does an incoming req see
148,158c148,158
< system.physmem.wrQLenPdf::7 5238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5252 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::7 5236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5239 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5251 # What write queue length does an incoming req see
164,169c164,169
< system.physmem.wrQLenPdf::23 2081 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1451 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 955 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 2083 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 878 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 366 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
171,178c171,178
< system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
< system.physmem.totQLat 7695436000 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 15487088500 # Sum of mem lat for all requests
< system.physmem.totBusLat 2247130000 # Total cycles spent in databus access
< system.physmem.totBankLat 5544522500 # Total cycles spent in bank access
< system.physmem.avgQLat 17122.81 # Average queueing delay per request
< system.physmem.avgBankLat 12336.90 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
> system.physmem.totQLat 7717714750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 15508692250 # Sum of mem lat for all requests
> system.physmem.totBusLat 2247060000 # Total cycles spent in databus access
> system.physmem.totBankLat 5543917500 # Total cycles spent in bank access
> system.physmem.avgQLat 17172.92 # Average queueing delay per request
> system.physmem.avgBankLat 12335.94 # Average bank access latency per request
180,181c180,181
< system.physmem.avgMemAccLat 34459.71 # Average memory access latency
< system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 34508.85 # Average memory access latency
> system.physmem.avgRdBW 15.13 # Average achieved read bandwidth in MB/s
183c183
< system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 15.13 # Average consumed read bandwidth in MB/s
188,196c188,196
< system.physmem.avgWrQLen 9.46 # Average write queue length over time
< system.physmem.readRowHits 421587 # Number of row buffer hits during reads
< system.physmem.writeRowHits 92850 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 76.87 # Row buffer hit rate for writes
< system.physmem.avgGap 3332940.18 # Average gap between requests
< system.l2c.replacements 342617 # number of replacements
< system.l2c.tagsinuse 65285.001346 # Cycle average of tags in use
< system.l2c.total_refs 2569094 # Total number of references to valid blocks.
---
> system.physmem.avgWrQLen 9.47 # Average write queue length over time
> system.physmem.readRowHits 421565 # Number of row buffer hits during reads
> system.physmem.writeRowHits 92877 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.80 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 76.90 # Row buffer hit rate for writes
> system.physmem.avgGap 3333023.20 # Average gap between requests
> system.l2c.replacements 342612 # number of replacements
> system.l2c.tagsinuse 65284.978501 # Cycle average of tags in use
> system.l2c.total_refs 2568846 # Total number of references to valid blocks.
198c198
< system.l2c.avg_refs 6.303118 # Average number of references to valid blocks.
---
> system.l2c.avg_refs 6.302509 # Average number of references to valid blocks.
200,208c200,208
< system.l2c.occ_blocks::writebacks 53776.663341 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 5305.450361 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 5913.032495 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 209.604016 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 80.251133 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.820567 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.inst 0.080955 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.090226 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.inst 0.003198 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 53776.613719 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 5305.208058 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 5913.214949 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 209.652371 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 80.289403 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.820566 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.inst 0.080951 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.090228 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.inst 0.003199 # Average percentage of cache occupancy
211,220c211,220
< system.l2c.ReadReq_hits::cpu0.inst 815796 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 714354 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 262043 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 83568 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1875761 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 814734 # number of Writeback hits
< system.l2c.Writeback_hits::total 814734 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 351 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 525 # number of UpgradeReq hits
---
> system.l2c.ReadReq_hits::cpu0.inst 815517 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 714323 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 262022 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 83603 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1875465 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 814738 # number of Writeback hits
> system.l2c.Writeback_hits::total 814738 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 171 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 348 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 519 # number of UpgradeReq hits
222,244c222,244
< system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 146833 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 31831 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 178664 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 815796 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 861187 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 262043 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 115399 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2054425 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 815796 # number of overall hits
< system.l2c.overall_hits::cpu0.data 861187 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 262043 # number of overall hits
< system.l2c.overall_hits::cpu1.data 115399 # number of overall hits
< system.l2c.overall_hits::total 2054425 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 13356 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 272983 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 1945 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 897 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 289181 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2769 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1340 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 4109 # number of UpgradeReq misses
---
> system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 146870 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 31835 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 178705 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 815517 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 861193 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 262022 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 115438 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2054170 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 815517 # number of overall hits
> system.l2c.overall_hits::cpu0.data 861193 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 262022 # number of overall hits
> system.l2c.overall_hits::cpu1.data 115438 # number of overall hits
> system.l2c.overall_hits::total 2054170 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 13350 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 272975 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 1943 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 909 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 289177 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2763 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1336 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 4099 # number of UpgradeReq misses
248,294c248,294
< system.l2c.ReadExReq_misses::cpu0.data 111939 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 7676 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 119615 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 13356 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 384922 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 1945 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 8573 # number of demand (read+write) misses
< system.l2c.demand_misses::total 408796 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 13356 # number of overall misses
< system.l2c.overall_misses::cpu0.data 384922 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 1945 # number of overall misses
< system.l2c.overall_misses::cpu1.data 8573 # number of overall misses
< system.l2c.overall_misses::total 408796 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 905864000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 11898970000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 151230500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 68201999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 13024266499 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 960000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 6372986 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 7332986 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 888499 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 136000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1024499 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 7329049500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 758770499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 8087819999 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 905864000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 19228019500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 151230500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 826972498 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 21112086498 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 905864000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 19228019500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 151230500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 826972498 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 21112086498 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 829152 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 987337 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 263988 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 84465 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2164942 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 814734 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 814734 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2943 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 1691 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 4634 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.ReadExReq_misses::cpu0.data 111935 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7677 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 119612 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 13350 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 384910 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1943 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8586 # number of demand (read+write) misses
> system.l2c.demand_misses::total 408789 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13350 # number of overall misses
> system.l2c.overall_misses::cpu0.data 384910 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1943 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8586 # number of overall misses
> system.l2c.overall_misses::total 408789 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 905376000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 11896032500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 147196500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 67006500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 13015611500 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1013500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 6347986 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 7361486 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 894999 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 135500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 1030499 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 7317066000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 777197999 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 8094263999 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 905376000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 19213098500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 147196500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 844204499 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 21109875499 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 905376000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 19213098500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 147196500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 844204499 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 21109875499 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 828867 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 987298 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 263965 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 84512 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2164642 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 814738 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 814738 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2934 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 1684 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 4618 # number of UpgradeReq accesses(hits+misses)
296,318c296,318
< system.l2c.SCUpgradeReq_accesses::cpu1.data 615 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1223 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 258772 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 39507 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 298279 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 829152 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1246109 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 263988 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 123972 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2463221 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 829152 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1246109 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 263988 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 123972 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2463221 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.016108 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.276484 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.007368 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.010620 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.133574 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940877 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792431 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.886707 # miss rate for UpgradeReq accesses
---
> system.l2c.SCUpgradeReq_accesses::cpu1.data 614 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1222 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 258805 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 39512 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 298317 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 828867 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1246103 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 263965 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 124024 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2462959 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 828867 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1246103 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 263965 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 124024 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2462959 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.016106 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.276487 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.007361 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.010756 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.133591 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941718 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793349 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.887614 # miss rate for UpgradeReq accesses
320,322c320,322
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.954472 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.937858 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.432578 # miss rate for ReadExReq accesses
---
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956026 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.938625 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.432507 # miss rate for ReadExReq accesses
324,358c324,358
< system.l2c.ReadExReq_miss_rate::total 0.401017 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.016108 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.308899 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.007368 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.069153 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.165960 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.016108 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.308899 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.007368 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.069153 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.165960 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67824.498353 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 43588.685010 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77753.470437 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 76033.443701 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 45038.458609 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 346.695558 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4755.959701 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1784.615722 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1586.605357 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 231.686542 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 893.198779 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65473.601694 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 98849.726290 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 67615.432839 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 51644.552535 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 67824.498353 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 49953.028146 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 77753.470437 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 96462.439986 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 51644.552535 # average overall miss latency
---
> system.l2c.ReadExReq_miss_rate::total 0.400956 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.016106 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.308891 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.007361 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.069229 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.165975 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.016106 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.308891 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.007361 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.069229 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.165975 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67818.426966 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 43579.201392 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75757.334020 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 73714.521452 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 45009.151834 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 366.811437 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4751.486527 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1795.922420 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1598.212500 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 230.834753 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 898.429817 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65368.883727 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101237.201902 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 67671.002901 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 67818.426966 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 49915.820581 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 75757.334020 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 98323.375146 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 51640.028227 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 67818.426966 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 49915.820581 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 75757.334020 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 98323.375146 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 51640.028227 # average overall miss latency
367,368c367,368
< system.l2c.writebacks::writebacks 79271 # number of writebacks
< system.l2c.writebacks::total 79271 # number of writebacks
---
> system.l2c.writebacks::writebacks 79262 # number of writebacks
> system.l2c.writebacks::total 79262 # number of writebacks
381,388c381,388
< system.l2c.ReadReq_mshr_misses::cpu0.inst 13355 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 272983 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 1929 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 896 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 289163 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2769 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1340 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 4109 # number of UpgradeReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 13349 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 272975 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 1927 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 908 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 289159 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2763 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1336 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 4099 # number of UpgradeReq MSHR misses
392,413c392,413
< system.l2c.ReadExReq_mshr_misses::cpu0.data 111939 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 7676 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 119615 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 13355 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 384922 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 1929 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 8572 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 408778 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 13355 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 384922 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 1929 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 8572 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 408778 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 739303821 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8556722771 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 126469885 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 57202686 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 9479699163 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27888734 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13415324 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 41304058 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5612547 # number of SCUpgradeReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_misses::cpu0.data 111935 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7677 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 119612 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13349 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 384910 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1927 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8585 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 408771 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13349 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 384910 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1927 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8585 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 408771 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 738885342 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8553784026 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122441645 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 55847948 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 9470958961 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27836728 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13416820 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 41253548 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5620046 # number of SCUpgradeReq MSHR miss cycles
415,445c415,445
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 11492133 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5964907547 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 664977742 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 6629885289 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 739303821 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 14521630318 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 126469885 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 722180428 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 16109584452 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 739303821 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 14521630318 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 126469885 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 722180428 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 16109584452 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1362723500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28760000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1391483500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2034614500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637502000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2672116500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3397338000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 666262000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4063600000 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276484 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010608 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.133566 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940877 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792431 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.886707 # mshr miss rate for UpgradeReq accesses
---
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 11499632 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5952955820 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 683390713 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 6636346533 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 738885342 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 14506739846 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 122441645 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 739238661 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 16107305494 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 738885342 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 14506739846 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 122441645 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 739238661 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 16107305494 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1360324000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28759000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1389083000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2032921000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 637490500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2670411500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3393245000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 666249500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4059494500 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.276487 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010744 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.133583 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941718 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.793349 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.887614 # mshr miss rate for UpgradeReq accesses
447,449c447,449
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954472 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.937858 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.432578 # mshr miss rate for ReadExReq accesses
---
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956026 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.938625 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.432507 # mshr miss rate for ReadExReq accesses
451,470c451,470
< system.l2c.ReadExReq_mshr_miss_rate::total 0.401017 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.165953 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016107 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.308899 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.165953 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31345.258756 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63842.283482 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 32783.237008 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10071.771036 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.435821 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.094914 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.405357 # average SCUpgradeReq mshr miss latency
---
> system.l2c.ReadExReq_mshr_miss_rate::total 0.400956 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.165967 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.165967 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31335.411763 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61506.550661 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 32753.464222 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10074.820123 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.529940 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10064.295682 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.796429 # average SCUpgradeReq mshr miss latency
472,485c472,485
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10019.296425 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53287.125551 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86630.763679 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 55426.871956 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency
---
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.834350 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53182.255952 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89017.938387 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 55482.280482 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
497c497
< system.iocache.tagsinuse 0.509415 # Cycle average of tags in use
---
> system.iocache.tagsinuse 0.509421 # Cycle average of tags in use
502,504c502,504
< system.iocache.occ_blocks::tsunami.ide 0.509415 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.031838 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.031838 # Average percentage of cache occupancy
---
> system.iocache.occ_blocks::tsunami.ide 0.509421 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.031839 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.031839 # Average percentage of cache occupancy
513,520c513,520
< system.iocache.ReadReq_miss_latency::tsunami.ide 21612998 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21612998 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 10624659943 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10624659943 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10646272941 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10646272941 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10646272941 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10646272941 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21615998 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21615998 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 10647231164 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10647231164 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10668847162 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10668847162 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10668847162 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10668847162 # number of overall miss cycles
537,545c537,545
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120743.005587 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 120743.005587 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255695.512683 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 255695.512683 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 255116.650476 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 255116.650476 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 284705 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120759.765363 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 120759.765363 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 256238.716885 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 255657.596559 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 255657.596559 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 286486 # number of cycles access was blocked
547c547
< system.iocache.blocked::no_mshrs 27170 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27218 # number of cycles access was blocked
549c549
< system.iocache.avg_blocked_cycles::no_mshrs 10.478653 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.525608 # average number of cycles each access was blocked
563,570c563,570
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12304249 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12304249 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8462672446 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8462672446 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8474976695 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8474976695 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8474976695 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8474976695 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12307249 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12307249 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8485239667 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8485239667 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8497546916 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8497546916 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8497546916 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8497546916 # number of overall MSHR miss cycles
579,586c579,586
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68755.581006 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204207.731686 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
600,604c600,604
< system.cpu0.branchPred.lookups 12043910 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 12035820 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 10146181 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 320311 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 7799891 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 5138186 # Number of BTB hits
606,608c606,608
< system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 65.875100 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 760204 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 30176 # Number of incorrect RAS predictions.
613,628c613,628
< system.cpu0.dtb.read_hits 8552844 # DTB read hits
< system.cpu0.dtb.read_misses 30306 # DTB read misses
< system.cpu0.dtb.read_acv 545 # DTB read access violations
< system.cpu0.dtb.read_accesses 625084 # DTB read accesses
< system.cpu0.dtb.write_hits 5600708 # DTB write hits
< system.cpu0.dtb.write_misses 7703 # DTB write misses
< system.cpu0.dtb.write_acv 337 # DTB write access violations
< system.cpu0.dtb.write_accesses 207517 # DTB write accesses
< system.cpu0.dtb.data_hits 14153552 # DTB hits
< system.cpu0.dtb.data_misses 38009 # DTB misses
< system.cpu0.dtb.data_acv 882 # DTB access violations
< system.cpu0.dtb.data_accesses 832601 # DTB accesses
< system.cpu0.itb.fetch_hits 972187 # ITB hits
< system.cpu0.itb.fetch_misses 27447 # ITB misses
< system.cpu0.itb.fetch_acv 929 # ITB acv
< system.cpu0.itb.fetch_accesses 999634 # ITB accesses
---
> system.cpu0.dtb.read_hits 8551483 # DTB read hits
> system.cpu0.dtb.read_misses 30199 # DTB read misses
> system.cpu0.dtb.read_acv 541 # DTB read access violations
> system.cpu0.dtb.read_accesses 624803 # DTB read accesses
> system.cpu0.dtb.write_hits 5601236 # DTB write hits
> system.cpu0.dtb.write_misses 7972 # DTB write misses
> system.cpu0.dtb.write_acv 345 # DTB write access violations
> system.cpu0.dtb.write_accesses 208308 # DTB write accesses
> system.cpu0.dtb.data_hits 14152719 # DTB hits
> system.cpu0.dtb.data_misses 38171 # DTB misses
> system.cpu0.dtb.data_acv 886 # DTB access violations
> system.cpu0.dtb.data_accesses 833111 # DTB accesses
> system.cpu0.itb.fetch_hits 970030 # ITB hits
> system.cpu0.itb.fetch_misses 28776 # ITB misses
> system.cpu0.itb.fetch_acv 920 # ITB acv
> system.cpu0.itb.fetch_accesses 998806 # ITB accesses
641c641
< system.cpu0.numCycles 100158206 # number of cpu cycles simulated
---
> system.cpu0.numCycles 100119117 # number of cpu cycles simulated
644,659c644,659
< system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 24086973 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 61837518 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 12035820 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 5898390 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 11653378 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1636628 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.BlockedCycles 36048574 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 32004 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 195358 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 286105 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 7499654 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 215735 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 73358875 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.842945 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.179502 # Number of instructions fetched each cycle (Total)
661,669c661,669
< system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 61705497 84.11% 84.11% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 747609 1.02% 85.13% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1536097 2.09% 87.23% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 679694 0.93% 88.15% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2532720 3.45% 91.61% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 506441 0.69% 92.30% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 557934 0.76% 93.06% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 775120 1.06% 94.11% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 4317763 5.89% 100.00% # Number of instructions fetched each cycle (Total)
673,717c673,717
< system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 73358875 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.120215 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.617639 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 25314409 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 35520182 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 10594612 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 907065 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1022606 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 498090 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 33900 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 60717129 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 100549 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1022606 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 26293542 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 14517617 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 17593984 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9931348 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 3999776 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 57516764 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 6773 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 634732 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1395914 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.RenamedOperands 38573698 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 70135572 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 69772127 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 363445 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 33935332 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4638358 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1391962 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 201915 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 10849961 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 8944130 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5848227 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1106835 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 734658 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 51076458 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1725873 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 49974476 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 73247 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 5675710 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 2876244 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1167818 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 73358875 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.681233 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.330312 # Number of insts issued each cycle
719,727c719,727
< system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 51151747 69.73% 69.73% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 10102031 13.77% 83.50% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 4555933 6.21% 89.71% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2996125 4.08% 93.79% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2381484 3.25% 97.04% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1187378 1.62% 98.66% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 631915 0.86% 99.52% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 300208 0.41% 99.93% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 52054 0.07% 100.00% # Number of insts issued each cycle
731c731
< system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 73358875 # Number of insts issued each cycle
733,763c733,763
< system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 82701 12.59% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 300975 45.82% 58.41% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 273171 41.59% 100.00% # attempts to use FU when none available
767,768c767,768
< system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 34554089 69.14% 69.15% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 54830 0.11% 69.26% # Type of FU issued
796,798c796,798
< system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 8894109 17.80% 87.09% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5667707 11.34% 98.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 782820 1.57% 100.00% # Type of FU issued
800,812c800,812
< system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued
< system.cpu0.iq.rate 0.498985 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 49974476 # Type of FU issued
> system.cpu0.iq.rate 0.499150 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 656847 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 173517181 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 58238103 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 48994356 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 520739 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 252277 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 246003 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 50355146 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 272403 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 532794 # Number of loads that had data forwarded from stores
814,817c814,817
< system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1055829 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 3465 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 12581 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 434891 # Number of stores squashed
820,821c820,821
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18411 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 121190 # Number of times an access to memory failed due to the cache being blocked
823,839c823,839
< system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 1022606 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 10355478 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 778603 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 55935625 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 586886 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 8944130 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5848227 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1520110 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 566642 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 4768 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 12581 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 160372 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 334885 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 495257 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 49597141 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 8604090 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 377334 # Number of squashed instructions skipped in execute
841,849c841,849
< system.cpu0.iew.exec_nop 3133489 # number of nop insts executed
< system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 7905275 # Number of branches executed
< system.cpu0.iew.exec_stores 5621640 # Number of stores executed
< system.cpu0.iew.exec_rate 0.495223 # Inst execution rate
< system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 24627791 # num instructions producing a value
< system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 3133294 # number of nop insts executed
> system.cpu0.iew.exec_refs 14226525 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 7904799 # Number of branches executed
> system.cpu0.iew.exec_stores 5622435 # Number of stores executed
> system.cpu0.iew.exec_rate 0.495381 # Inst execution rate
> system.cpu0.iew.wb_sent 49326582 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 49240359 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 24624844 # num instructions producing a value
> system.cpu0.iew.wb_consumers 33143444 # num instructions consuming a value
851c851
< system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle
---
> system.cpu0.iew.wb_rate 0.491818 # insts written-back per cycle
854,859c854,859
< system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6108836 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 558055 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 462633 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 72336269 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.687326 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.603373 # Number of insts commited each cycle
861,869c861,869
< system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 53637775 74.15% 74.15% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7794815 10.78% 84.93% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 4279099 5.92% 90.84% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2307939 3.19% 94.03% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1284633 1.78% 95.81% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 537599 0.74% 96.55% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 458507 0.63% 97.19% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 423032 0.58% 97.77% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1612870 2.23% 100.00% # Number of insts commited each cycle
873,875c873,875
< system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 49720528 # Number of instructions committed
< system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 72336269 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 49718583 # Number of instructions committed
> system.cpu0.commit.committedOps 49718583 # Number of ops (including micro ops) committed
877,880c877,880
< system.cpu0.commit.refs 13302179 # Number of memory references committed
< system.cpu0.commit.loads 7888682 # Number of loads committed
< system.cpu0.commit.membars 189617 # Number of memory barriers committed
< system.cpu0.commit.branches 7516247 # Number of branches committed
---
> system.cpu0.commit.refs 13301637 # Number of memory references committed
> system.cpu0.commit.loads 7888301 # Number of loads committed
> system.cpu0.commit.membars 189589 # Number of memory barriers committed
> system.cpu0.commit.branches 7515884 # Number of branches committed
882,884c882,884
< system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 629253 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached
---
> system.cpu0.commit.int_insts 46055357 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 629203 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1612870 # number cycles where commit BW limit reached
886,903c886,903
< system.cpu0.rob.rob_reads 126376352 # The number of ROB reads
< system.cpu0.rob.rob_writes 112693596 # The number of ROB writes
< system.cpu0.timesIdled 1033507 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 26786615 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3701289214 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 46865102 # Number of Instructions Simulated
< system.cpu0.committedOps 46865102 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 46865102 # Number of Instructions Simulated
< system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.467911 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.467911 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 65365755 # number of integer regfile reads
< system.cpu0.int_regfile_writes 35683177 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 120752 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 122064 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1632145 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 781535 # number of misc regfile writes
---
> system.cpu0.rob.rob_reads 126355419 # The number of ROB reads
> system.cpu0.rob.rob_writes 112677687 # The number of ROB writes
> system.cpu0.timesIdled 1033455 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 26760242 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3701329669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 46863203 # Number of Instructions Simulated
> system.cpu0.committedOps 46863203 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 46863203 # Number of Instructions Simulated
> system.cpu0.cpi 2.136412 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.136412 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.468074 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.468074 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 65361385 # number of integer regfile reads
> system.cpu0.int_regfile_writes 35679513 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 120846 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 122066 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1631915 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 781460 # number of misc regfile writes
935,939c935,939
< system.cpu0.icache.replacements 828572 # number of replacements
< system.cpu0.icache.tagsinuse 510.309366 # Cycle average of tags in use
< system.cpu0.icache.total_refs 6631345 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 829084 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 7.998399 # Average number of references to valid blocks.
---
> system.cpu0.icache.replacements 828283 # number of replacements
> system.cpu0.icache.tagsinuse 510.309737 # Cycle average of tags in use
> system.cpu0.icache.total_refs 6629306 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 828795 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 7.998728 # Average number of references to valid blocks.
941,980c941,980
< system.cpu0.icache.occ_blocks::cpu0.inst 510.309366 # Average occupied blocks per requestor
< system.cpu0.icache.occ_percent::cpu0.inst 0.996698 # Average percentage of cache occupancy
< system.cpu0.icache.occ_percent::total 0.996698 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6631345 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6631345 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6631345 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6631345 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6631345 # number of overall hits
< system.cpu0.icache.overall_hits::total 6631345 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 870628 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 870628 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 870628 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 870628 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 870628 # number of overall misses
< system.cpu0.icache.overall_misses::total 870628 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12335909994 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 12335909994 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 12335909994 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 12335909994 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 12335909994 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 12335909994 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 7501973 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 7501973 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 7501973 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 7501973 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 7501973 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 7501973 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116053 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.116053 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116053 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.116053 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116053 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.116053 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14168.979167 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14168.979167 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14168.979167 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14168.979167 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 2773 # number of cycles access was blocked
---
> system.cpu0.icache.occ_blocks::cpu0.inst 510.309737 # Average occupied blocks per requestor
> system.cpu0.icache.occ_percent::cpu0.inst 0.996699 # Average percentage of cache occupancy
> system.cpu0.icache.occ_percent::total 0.996699 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6629306 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6629306 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6629306 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6629306 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6629306 # number of overall hits
> system.cpu0.icache.overall_hits::total 6629306 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 870348 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 870348 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 870348 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 870348 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 870348 # number of overall misses
> system.cpu0.icache.overall_misses::total 870348 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12313538494 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 12313538494 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 12313538494 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 12313538494 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 12313538494 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 12313538494 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 7499654 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 7499654 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 7499654 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 7499654 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 7499654 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 7499654 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116052 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.116052 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116052 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.116052 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116052 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.116052 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14147.833388 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14147.833388 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 3221 # number of cycles access was blocked
982c982
< system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 147 # number of cycles access was blocked
984c984
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.124138 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.911565 # average number of cycles each access was blocked
988,1017c988,1017
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41361 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 41361 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 41361 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 41361 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 41361 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 41361 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 829267 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 829267 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 829267 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 829267 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 829267 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 829267 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10145672495 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 10145672495 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10145672495 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 10145672495 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10145672495 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 10145672495 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110540 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.110540 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110540 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.110540 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.506492 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41379 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 41379 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 41379 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 41379 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 41379 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 41379 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 828969 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 828969 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 828969 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 828969 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 828969 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 828969 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10141631994 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 10141631994 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10141631994 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 10141631994 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10141631994 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 10141631994 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110534 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.110534 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.110534 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.030457 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency
1019,1023c1019,1023
< system.cpu0.dcache.replacements 1248443 # number of replacements
< system.cpu0.dcache.tagsinuse 505.648747 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 10075338 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 1248955 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 8.067014 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 1248455 # number of replacements
> system.cpu0.dcache.tagsinuse 505.645673 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 10073371 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 1248967 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 8.065362 # Average number of references to valid blocks.
1025,1043c1025,1043
< system.cpu0.dcache.occ_blocks::cpu0.data 505.648747 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.987595 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.987595 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6210455 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6210455 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3519332 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3519332 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154524 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 154524 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177828 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 177828 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 9729787 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 9729787 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 9729787 # number of overall hits
< system.cpu0.dcache.overall_hits::total 9729787 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1542913 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1542913 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1697969 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1697969 # number of WriteReq misses
---
> system.cpu0.dcache.occ_blocks::cpu0.data 505.645673 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.987589 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.987589 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6208704 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6208704 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3519183 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3519183 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154511 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 154511 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177820 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 177820 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 9727887 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 9727887 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 9727887 # number of overall hits
> system.cpu0.dcache.overall_hits::total 9727887 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1543041 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1543041 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1697976 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1697976 # number of WriteReq misses
1046,1100c1046,1100
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3731 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 3731 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3240882 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3240882 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3240882 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3240882 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33525948000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 33525948000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65021398230 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 65021398230 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277810500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 277810500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27308500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 27308500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 98547346230 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 98547346230 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 98547346230 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 98547346230 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 7753368 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 7753368 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217301 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5217301 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174253 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 174253 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181559 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 181559 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12970669 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12970669 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12970669 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12970669 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.198999 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.198999 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325450 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.325450 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113220 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113220 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020550 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020550 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249862 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.249862 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249862 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.249862 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21728.994441 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 21728.994441 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.630938 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.630938 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14081.326981 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14081.326981 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7319.351380 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7319.351380 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 30407.569986 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 30407.569986 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 2105320 # number of cycles access was blocked
---
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3730 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 3730 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3241017 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3241017 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3241017 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3241017 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33524463000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 33524463000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64948533233 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 64948533233 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277752500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 277752500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27309500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 27309500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 98472996233 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 98472996233 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 98472996233 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 98472996233 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7751745 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7751745 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217159 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5217159 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174240 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 174240 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181550 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 181550 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12968904 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12968904 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12968904 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12968904 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199057 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.199057 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325460 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.325460 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113229 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113229 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020545 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020545 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249907 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.249907 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249907 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.249907 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21726.229569 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 21726.229569 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38250.560216 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 38250.560216 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14078.387146 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7321.581769 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7321.581769 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 30383.363072 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 30383.363072 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 2097721 # number of cycles access was blocked
1102c1102
< system.cpu0.dcache.blocked::no_mshrs 47301 # number of cycles access was blocked
---
> system.cpu0.dcache.blocked::no_mshrs 47310 # number of cycles access was blocked
1104c1104
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.508996 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.339907 # average number of cycles each access was blocked
1108,1173c1108,1173
< system.cpu0.dcache.writebacks::writebacks 729881 # number of writebacks
< system.cpu0.dcache.writebacks::total 729881 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558235 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 558235 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432207 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1432207 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4308 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4308 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990442 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1990442 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990442 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1990442 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984678 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 984678 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265762 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 265762 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15421 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15421 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3731 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 3731 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250440 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1250440 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250440 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1250440 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21285796500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21285796500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9471560262 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9471560262 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170594000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170594000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19846500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19846500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30757356762 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 30757356762 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30757356762 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 30757356762 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454223000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454223000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2157391999 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 729852 # number of writebacks
> system.cpu0.dcache.writebacks::total 729852 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558383 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 558383 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432185 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1432185 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4312 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4312 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990568 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1990568 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990568 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1990568 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984658 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 984658 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265791 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 265791 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15417 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15417 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3730 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 3730 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250449 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1250449 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250449 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1250449 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21282308500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21282308500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9459587261 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9459587261 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170557000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170557000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19849500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19849500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30741895761 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 30741895761 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30741895761 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 30741895761 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451668000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451668000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2155602499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2155602499 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607270499 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607270499 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127024 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127024 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050946 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050946 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088481 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088481 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020545 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020545 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.096419 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.096419 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5321.581769 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5321.581769 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
1181,1185c1181,1185
< system.cpu1.branchPred.lookups 2951549 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 2951275 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 2437405 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 83356 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 1836683 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 994148 # Number of BTB hits
1187,1189c1187,1189
< system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 54.127359 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 203977 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 9132 # Number of incorrect RAS predictions.
1194,1199c1194,1199
< system.cpu1.dtb.read_hits 2175312 # DTB read hits
< system.cpu1.dtb.read_misses 10933 # DTB read misses
< system.cpu1.dtb.read_acv 25 # DTB read access violations
< system.cpu1.dtb.read_accesses 324345 # DTB read accesses
< system.cpu1.dtb.write_hits 1433020 # DTB write hits
< system.cpu1.dtb.write_misses 2283 # DTB write misses
---
> system.cpu1.dtb.read_hits 2175721 # DTB read hits
> system.cpu1.dtb.read_misses 10990 # DTB read misses
> system.cpu1.dtb.read_acv 22 # DTB read access violations
> system.cpu1.dtb.read_accesses 324709 # DTB read accesses
> system.cpu1.dtb.write_hits 1432957 # DTB write hits
> system.cpu1.dtb.write_misses 2208 # DTB write misses
1201,1209c1201,1209
< system.cpu1.dtb.write_accesses 133154 # DTB write accesses
< system.cpu1.dtb.data_hits 3608332 # DTB hits
< system.cpu1.dtb.data_misses 13216 # DTB misses
< system.cpu1.dtb.data_acv 89 # DTB access violations
< system.cpu1.dtb.data_accesses 457499 # DTB accesses
< system.cpu1.itb.fetch_hits 457840 # ITB hits
< system.cpu1.itb.fetch_misses 7553 # ITB misses
< system.cpu1.itb.fetch_acv 250 # ITB acv
< system.cpu1.itb.fetch_accesses 465393 # ITB accesses
---
> system.cpu1.dtb.write_accesses 133156 # DTB write accesses
> system.cpu1.dtb.data_hits 3608678 # DTB hits
> system.cpu1.dtb.data_misses 13198 # DTB misses
> system.cpu1.dtb.data_acv 86 # DTB access violations
> system.cpu1.dtb.data_accesses 457865 # DTB accesses
> system.cpu1.itb.fetch_hits 458401 # ITB hits
> system.cpu1.itb.fetch_misses 7664 # ITB misses
> system.cpu1.itb.fetch_acv 238 # ITB acv
> system.cpu1.itb.fetch_accesses 466065 # ITB accesses
1222c1222
< system.cpu1.numCycles 18134862 # number of cpu cycles simulated
---
> system.cpu1.numCycles 18142763 # number of cpu cycles simulated
1225,1240c1225,1240
< system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 7059665 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 13904860 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 2951275 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1198125 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 2489767 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 435348 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.BlockedCycles 7028149 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 27735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 66683 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 53717 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1666090 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 56854 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 17001992 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.817837 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.192062 # Number of instructions fetched each cycle (Total)
1242,1250c1242,1250
< system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 14512225 85.36% 85.36% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 164132 0.97% 86.32% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 264549 1.56% 87.88% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 196224 1.15% 89.03% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 340931 2.01% 91.04% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 130664 0.77% 91.81% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 146583 0.86% 92.67% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 247056 1.45% 94.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 999628 5.88% 100.00% # Number of instructions fetched each cycle (Total)
1254,1298c1254,1298
< system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 17001992 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.162670 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.766414 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 6935204 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 7342187 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 2328189 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 128213 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 268198 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 130237 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 8176 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 13648246 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 24564 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 268198 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 7169583 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 530321 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6090332 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2220482 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 723074 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 12659443 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 62425 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 176745 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.RenamedOperands 8295078 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 15050859 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 14876046 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 174813 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 7154813 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1140265 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 506846 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 51390 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 2247067 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 2298271 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1513317 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 213048 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 119189 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 11099753 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 565057 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 10829119 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 31632 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1536258 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 758334 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 401417 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 17001992 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.636932 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.310611 # Number of insts issued each cycle
1300,1308c1300,1308
< system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 12225446 71.91% 71.91% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 2205450 12.97% 84.88% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 929224 5.47% 90.34% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 621702 3.66% 94.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 537509 3.16% 97.16% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 242497 1.43% 98.59% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 153407 0.90% 99.49% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 76904 0.45% 99.94% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 9853 0.06% 100.00% # Number of insts issued each cycle
1312c1312
< system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 17001992 # Number of insts issued each cycle
1314,1344c1314,1344
< system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 3913 1.80% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 115549 53.23% 55.03% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 97618 44.97% 100.00% # attempts to use FU when none available
1348,1354c1348,1354
< system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 6756968 62.40% 62.43% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 17928 0.17% 62.59% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.70% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued
1377,1378c1377,1378
< system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 2278200 21.04% 83.75% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1457808 13.46% 97.22% # Type of FU issued
1381,1393c1381,1393
< system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued
< system.cpu1.iq.rate 0.597126 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 10829119 # Type of FU issued
> system.cpu1.iq.rate 0.596884 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 217080 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.020046 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 38657394 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 13080099 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 10523969 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 251548 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 122819 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 119141 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 10911695 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 130978 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 103489 # Number of loads that had data forwarded from stores
1395,1398c1395,1398
< system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 301882 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 1924 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 130297 # Number of stores squashed
1401,1402c1401,1402
< system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 383 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 9692 # Number of times an access to memory failed due to the cache being blocked
1404,1420c1404,1420
< system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 268198 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 347966 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 52179 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 12265641 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 165598 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 2298271 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1513317 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 508976 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 44383 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 2331 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 1924 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 37819 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 111790 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 149609 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 10726333 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 2195343 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 102786 # Number of squashed instructions skipped in execute
1422,1430c1422,1430
< system.cpu1.iew.exec_nop 600729 # number of nop insts executed
< system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1609931 # Number of branches executed
< system.cpu1.iew.exec_stores 1442207 # Number of stores executed
< system.cpu1.iew.exec_rate 0.591458 # Inst execution rate
< system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 4954529 # num instructions producing a value
< system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 600831 # number of nop insts executed
> system.cpu1.iew.exec_refs 3637407 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1609945 # Number of branches executed
> system.cpu1.iew.exec_stores 1442064 # Number of stores executed
> system.cpu1.iew.exec_rate 0.591218 # Inst execution rate
> system.cpu1.iew.wb_sent 10671459 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 10643110 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 4954176 # num instructions producing a value
> system.cpu1.iew.wb_consumers 6965889 # num instructions consuming a value
1432,1433c1432,1433
< system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.586631 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.711205 # average fanout of values written-back
1435,1440c1435,1440
< system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 1581528 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 163640 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 139954 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 16733794 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.633013 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.579692 # Number of insts commited each cycle
1442,1450c1442,1450
< system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 12789139 76.43% 76.43% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 1829893 10.94% 87.36% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 688745 4.12% 91.48% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 420012 2.51% 93.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 300647 1.80% 95.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 117990 0.71% 96.49% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 119790 0.72% 97.21% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 126616 0.76% 97.96% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 340962 2.04% 100.00% # Number of insts commited each cycle
1454,1456c1454,1456
< system.cpu1.commit.committed_per_cycle::total 16732673 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 10592581 # Number of instructions committed
< system.cpu1.commit.committedOps 10592581 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 16733794 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 10592705 # Number of instructions committed
> system.cpu1.commit.committedOps 10592705 # Number of ops (including micro ops) committed
1458,1459c1458,1459
< system.cpu1.commit.refs 3379323 # Number of memory references committed
< system.cpu1.commit.loads 1996302 # Number of loads committed
---
> system.cpu1.commit.refs 3379409 # Number of memory references committed
> system.cpu1.commit.loads 1996389 # Number of loads committed
1461c1461
< system.cpu1.commit.branches 1516852 # Number of branches committed
---
> system.cpu1.commit.branches 1516939 # Number of branches committed
1463c1463
< system.cpu1.commit.int_insts 9798554 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 9798676 # Number of committed integer instructions.
1465c1465
< system.cpu1.commit.bw_lim_events 341197 # number cycles where commit BW limit reached
---
> system.cpu1.commit.bw_lim_events 340962 # number cycles where commit BW limit reached
1467,1483c1467,1483
< system.cpu1.rob.rob_reads 28468767 # The number of ROB reads
< system.cpu1.rob.rob_writes 24605693 # The number of ROB writes
< system.cpu1.timesIdled 153691 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 1134548 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3782736336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 10061892 # Number of Instructions Simulated
< system.cpu1.committedOps 10061892 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 10061892 # Number of Instructions Simulated
< system.cpu1.cpi 1.802331 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.802331 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.554837 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.554837 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 13798288 # number of integer regfile reads
< system.cpu1.int_regfile_writes 7546279 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 63929 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 63981 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 608468 # number of misc regfile reads
---
> system.cpu1.rob.rob_reads 28474562 # The number of ROB reads
> system.cpu1.rob.rob_writes 24615096 # The number of ROB writes
> system.cpu1.timesIdled 153586 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 1140771 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3782727730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 10062016 # Number of Instructions Simulated
> system.cpu1.committedOps 10062016 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 10062016 # Number of Instructions Simulated
> system.cpu1.cpi 1.803094 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.803094 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.554602 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.554602 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 13798564 # number of integer regfile reads
> system.cpu1.int_regfile_writes 7546386 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 63884 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 63971 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 608483 # number of misc regfile reads
1485,1491c1485,1491
< system.cpu1.icache.replacements 263438 # number of replacements
< system.cpu1.icache.tagsinuse 470.047000 # Cycle average of tags in use
< system.cpu1.icache.total_refs 1391700 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 263950 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 5.272590 # Average number of references to valid blocks.
< system.cpu1.icache.warmup_cycle 1875178456000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.occ_blocks::cpu1.inst 470.047000 # Average occupied blocks per requestor
---
> system.cpu1.icache.replacements 263412 # number of replacements
> system.cpu1.icache.tagsinuse 470.047023 # Cycle average of tags in use
> system.cpu1.icache.total_refs 1392951 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 263924 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 5.277849 # Average number of references to valid blocks.
> system.cpu1.icache.warmup_cycle 1875177958000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.occ_blocks::cpu1.inst 470.047023 # Average occupied blocks per requestor
1494,1530c1494,1530
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1391700 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1391700 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1391700 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1391700 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1391700 # number of overall hits
< system.cpu1.icache.overall_hits::total 1391700 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 273170 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 273170 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 273170 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 273170 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 273170 # number of overall misses
< system.cpu1.icache.overall_misses::total 273170 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3762343999 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 3762343999 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 3762343999 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 3762343999 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 3762343999 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 3762343999 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1664870 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1664870 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1664870 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1664870 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1664870 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1664870 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164079 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.164079 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164079 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.164079 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.164079 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.164079 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13772.903317 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13772.903317 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13772.903317 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13772.903317 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked
---
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1392951 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1392951 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1392951 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1392951 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1392951 # number of overall hits
> system.cpu1.icache.overall_hits::total 1392951 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 273139 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 273139 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 273139 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 273139 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 273139 # number of overall misses
> system.cpu1.icache.overall_misses::total 273139 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3753112000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 3753112000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 3753112000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 3753112000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 3753112000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 3753112000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1666090 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1666090 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1666090 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1666090 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1666090 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1666090 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163940 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.163940 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163940 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.163940 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163940 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.163940 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13740.666840 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13740.666840 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13740.666840 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 264 # number of cycles access was blocked
1532c1532
< system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked
1534c1534
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 42.857143 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.666667 # average number of cycles each access was blocked
1538,1567c1538,1567
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9145 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 9145 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 9145 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 9145 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 9145 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 9145 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 264025 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 264025 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 264025 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 264025 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 264025 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 264025 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3130972999 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3130972999 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3130972999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3130972999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3130972999 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3130972999 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158586 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.158586 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.158586 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.623233 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9144 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 9144 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 9144 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 9144 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 9144 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 9144 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 263995 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 263995 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 263995 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 263995 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 263995 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 263995 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3126547000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3126547000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3126547000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3126547000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3126547000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3126547000 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158452 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.158452 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.158452 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
1569,1573c1569,1573
< system.cpu1.dcache.replacements 126485 # number of replacements
< system.cpu1.dcache.tagsinuse 490.826755 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 2951833 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 126890 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 23.262929 # Average number of references to valid blocks.
---
> system.cpu1.dcache.replacements 126526 # number of replacements
> system.cpu1.dcache.tagsinuse 490.827782 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 2952051 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 126931 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 23.257132 # Average number of references to valid blocks.
1575,1615c1575,1615
< system.cpu1.dcache.occ_blocks::cpu1.data 490.826755 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.958646 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.958646 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 1783497 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 1783497 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1082553 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1082553 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39938 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 39938 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38621 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 38621 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 2866050 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 2866050 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 2866050 # number of overall hits
< system.cpu1.dcache.overall_hits::total 2866050 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 242860 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 242860 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 251463 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 251463 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6629 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 6629 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3956 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 3956 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 494323 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 494323 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 494323 # number of overall misses
< system.cpu1.dcache.overall_misses::total 494323 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3676780500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3676780500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8111413586 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 8111413586 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67692000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 67692000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29045500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 29045500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 11788194086 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 11788194086 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 11788194086 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 11788194086 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026357 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2026357 # number of ReadReq accesses(hits+misses)
---
> system.cpu1.dcache.occ_blocks::cpu1.data 490.827782 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.958648 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.958648 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1783702 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1783702 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1082593 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1082593 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39936 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 39936 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38619 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 38619 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 2866295 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 2866295 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 2866295 # number of overall hits
> system.cpu1.dcache.overall_hits::total 2866295 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 242985 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 242985 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 251423 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 251423 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6626 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 6626 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3957 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 3957 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 494408 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 494408 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 494408 # number of overall misses
> system.cpu1.dcache.overall_misses::total 494408 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3665622000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3665622000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8223225631 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 8223225631 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67675500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 67675500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29039500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 29039500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 11888847631 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 11888847631 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 11888847631 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 11888847631 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026687 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2026687 # number of ReadReq accesses(hits+misses)
1618,1650c1618,1650
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46567 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 46567 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42577 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 42577 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 3360373 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 3360373 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 3360373 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 3360373 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119851 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.119851 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188501 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.188501 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142354 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142354 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092914 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092914 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147104 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.147104 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147104 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.147104 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15139.506300 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15139.506300 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32256.887041 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 32256.887041 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10211.494946 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10211.494946 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.138524 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.138524 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 23847.148698 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 23847.148698 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 244071 # number of cycles access was blocked
---
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46562 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 46562 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42576 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 42576 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 3360703 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 3360703 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 3360703 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 3360703 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119893 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.119893 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188471 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.188471 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142305 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142305 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092940 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092940 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147114 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.147114 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147114 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.147114 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15085.795419 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32706.735784 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10213.628132 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7338.766742 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7338.766742 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 255815 # number of cycles access was blocked
1652c1652
< system.cpu1.dcache.blocked::no_mshrs 4071 # number of cycles access was blocked
---
> system.cpu1.dcache.blocked::no_mshrs 3992 # number of cycles access was blocked
1654c1654
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 59.953574 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 64.081914 # average number of cycles each access was blocked
1658,1723c1658,1723
< system.cpu1.dcache.writebacks::writebacks 84853 # number of writebacks
< system.cpu1.dcache.writebacks::total 84853 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150731 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 150731 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205632 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 205632 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 643 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 643 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 356363 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 356363 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 356363 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 356363 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92129 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 92129 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45831 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 45831 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5986 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5986 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3956 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 3956 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 137960 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 137960 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 137960 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 137960 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1123159500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1123159500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1210930487 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1210930487 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47601500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47601500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21133500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21133500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2334089987 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 2334089987 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2334089987 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 2334089987 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30974500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30974500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675233500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675233500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706208000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706208000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045465 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045465 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034356 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034356 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128546 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128546 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092914 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092914 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.041055 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041055 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.041055 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12191.161306 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12191.161306 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 84886 # number of writebacks
> system.cpu1.dcache.writebacks::total 84886 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150812 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 150812 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205594 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 205594 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 644 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 644 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 356406 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 356406 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 356406 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 356406 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92173 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 92173 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45829 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 45829 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5982 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5982 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3957 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 3957 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 138002 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 138002 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 138002 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 138002 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1122474000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1122474000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1228877987 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1228877987 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47579000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47579000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21125500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21125500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2351351987 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 2351351987 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2351351987 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 2351351987 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30976000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30976000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675219000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675219000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706195000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706195000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045480 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045480 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034354 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034354 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128474 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128474 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092940 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092940 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.041063 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.041063 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7953.694417 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7953.694417 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5338.766742 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5338.766742 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
1732,1735c1732,1735
< system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl
---
> system.cpu0.kern.inst.quiesce 6610 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 175912 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 61740 40.36% 40.36% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl
1737,1741c1737,1741
< system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl
---
> system.cpu0.kern.ipl_count::30 255 0.17% 41.88% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 88907 58.12% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 152961 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 60876 49.17% 49.17% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.11% 49.27% # number of times we switched to this ipl from a different ipl
1744,1751c1744,1751
< system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl
---
> system.cpu0.kern.ipl_good::31 60621 48.96% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 123811 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1865672058500 98.16% 98.16% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 62377000 0.00% 98.16% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 564179500 0.03% 98.19% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 124028500 0.01% 98.20% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 34304214500 1.80% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1900726858000 # number of cycles we spent at this ipl
1756,1757c1756,1757
< system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.681847 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.809429 # fraction of swpipl calls that actually changed the ipl
1793c1793
< system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed
---
> system.cpu0.kern.callpal::swpctx 3342 2.08% 2.30% # number of callpals executed
1796c1796
< system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed
---
> system.cpu0.kern.callpal::swpipl 146221 90.79% 93.12% # number of callpals executed
1802c1802
< system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed
---
> system.cpu0.kern.callpal::rti 4425 2.75% 99.71% # number of callpals executed
1805,1807c1805,1807
< system.cpu0.kern.callpal::total 161075 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches
---
> system.cpu0.kern.callpal::total 161059 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 6926 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches
1809,1810c1809,1810
< system.cpu0.kern.mode_good::kernel 1258
< system.cpu0.kern.mode_good::user 1259
---
> system.cpu0.kern.mode_good::kernel 1256
> system.cpu0.kern.mode_good::user 1257
1812c1812
< system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.181346 # fraction of useful protection mode switches
1815,1817c1815,1817
< system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.307100 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1898828643000 99.90% 99.90% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1898207000 0.10% 100.00% # number of ticks spent at the given mode
1821c1821
< system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 2523 # number of quiesce instructions executed
1833,1837c1833,1837
< system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl
---
> system.cpu1.kern.ipl_ticks::0 1875010715500 98.66% 98.66% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 532408500 0.03% 98.69% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 162327000 0.01% 98.70% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 24731034000 1.30% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1900436485000 # number of cycles we spent at this ipl
1893,1895c1893,1895
< system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode
---
> system.cpu1.kern.mode_ticks::kernel 5768410500 0.30% 0.30% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 833727500 0.04% 0.35% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1893823776000 99.65% 100.00% # number of ticks spent at the given mode