7,11c7,11
< host_inst_rate 131170 # Simulator instruction rate (inst/s)
< host_op_rate 131170 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4437782045 # Simulator tick rate (ticks/s)
< host_mem_usage 332328 # Number of bytes of host memory used
< host_seconds 427.66 # Real time elapsed on the host
---
> host_inst_rate 54087 # Simulator instruction rate (inst/s)
> host_op_rate 54087 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1829896991 # Simulator tick rate (ticks/s)
> host_mem_usage 335972 # Number of bytes of host memory used
> host_seconds 1037.14 # Real time elapsed on the host
916,917c916,917
< system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes
---
> system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes
1068,1069c1068,1069
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles
1072,1077c1072,1077
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles
---
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles
1104,1105c1104,1105
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency
1108,1113c1108,1113
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency
---
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency
1148,1149c1148,1149
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles
1152,1157c1152,1157
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles
1178,1179c1178,1179
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency
1182,1187c1182,1187
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
---
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
1239c1239
< system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed
---
> system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed
1242c1242
< system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked
1244c1244
< system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked
---
> system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked
1249,1250c1249,1250
< system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed
---
> system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed
1255c1255
< system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total)
1259c1259
< system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total)
1280,1283c1280,1283
< system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running
---
> system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running
1285c1285
< system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename
---
> system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename
1289,1291c1289,1291
< system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups
---
> system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups
1294c1294
< system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing
---
> system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing
1418c1418
< system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking
---
> system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking
1421c1421
< system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch
---
> system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch
1496,1497c1496,1497
< system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes
---
> system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes
1500c1500
< system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks.
---
> system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks.
1502c1502
< system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks.
---
> system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks.
1507,1512c1507,1512
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits
< system.cpu1.icache.overall_hits::total 1814154 # number of overall hits
---
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits
> system.cpu1.icache.overall_hits::total 1814153 # number of overall hits
1525,1530c1525,1530
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses
---
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses
1609,1610c1609,1610
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses
---
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses
1615,1616c1615,1616
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles
---
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles
1623,1626c1623,1626
< system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles
1633,1634c1633,1634
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses)
---
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses)
1645,1646c1645,1646
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses
---
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses
1651,1652c1651,1652
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency
1657,1662c1657,1662
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency
---
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency
1695,1696c1695,1696
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles
---
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles
1703,1706c1703,1706
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles
1719,1720c1719,1720
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses
---
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses
1725,1726c1725,1726
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency
---
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency
1733,1736c1733,1736
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
< host_inst_rate 131170 # Simulator instruction rate (inst/s)
< host_op_rate 131170 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4437782045 # Simulator tick rate (ticks/s)
< host_mem_usage 332328 # Number of bytes of host memory used
< host_seconds 427.66 # Real time elapsed on the host
---
> host_inst_rate 54087 # Simulator instruction rate (inst/s)
> host_op_rate 54087 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1829896991 # Simulator tick rate (ticks/s)
> host_mem_usage 335972 # Number of bytes of host memory used
> host_seconds 1037.14 # Real time elapsed on the host
916,917c916,917
< system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes
---
> system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes
1068,1069c1068,1069
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles
1072,1077c1072,1077
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles
---
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles
1104,1105c1104,1105
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency
1108,1113c1108,1113
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency
---
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency
1148,1149c1148,1149
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles
1152,1157c1152,1157
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles
1178,1179c1178,1179
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency
1182,1187c1182,1187
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency
---
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency
1239c1239
< system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed
---
> system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed
1242c1242
< system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked
1244c1244
< system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked
---
> system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked
1249,1250c1249,1250
< system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed
---
> system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed
1255c1255
< system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total)
1259c1259
< system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total)
1280,1283c1280,1283
< system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running
---
> system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running
1285c1285
< system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename
---
> system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename
1289,1291c1289,1291
< system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups
---
> system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups
1294c1294
< system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing
---
> system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing
1418c1418
< system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking
---
> system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking
1421c1421
< system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch
---
> system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch
1496,1497c1496,1497
< system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes
---
> system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes
1500c1500
< system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks.
---
> system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks.
1502c1502
< system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks.
---
> system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks.
1507,1512c1507,1512
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits
< system.cpu1.icache.overall_hits::total 1814154 # number of overall hits
---
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits
> system.cpu1.icache.overall_hits::total 1814153 # number of overall hits
1525,1530c1525,1530
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses
---
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses
1609,1610c1609,1610
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses
---
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 718 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 718 # number of StoreCondReq misses
1615,1616c1615,1616
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles
---
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736455500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6736455500 # number of ReadReq miss cycles
1623,1626c1623,1626
< system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 20256380174 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 20256380174 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 20256380174 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 20256380174 # number of overall miss cycles
1633,1634c1633,1634
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses)
---
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43241 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 43241 # number of StoreCondReq accesses(hits+misses)
1645,1646c1645,1646
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses
---
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses
1651,1652c1651,1652
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency
1657,1662c1657,1662
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency
---
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7069.637883 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7069.637883 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 26150.525588 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.525588 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 26150.525588 # average overall miss latency
1695,1696c1695,1696
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles
---
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles
1703,1706c1703,1706
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles
1719,1720c1719,1720
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses
---
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses
1725,1726c1725,1726
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency
---
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency
1733,1736c1733,1736
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency