3,5c3,5
< sim_seconds 1.900531 # Number of seconds simulated
< sim_ticks 1900530800500 # Number of ticks simulated
< final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.900530 # Number of seconds simulated
> sim_ticks 1900530295500 # Number of ticks simulated
> final_tick 1900530295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 119697 # Simulator instruction rate (inst/s)
< host_op_rate 119697 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 3968630665 # Simulator tick rate (ticks/s)
< host_mem_usage 303044 # Number of bytes of host memory used
< host_seconds 478.89 # Real time elapsed on the host
< sim_insts 57321719 # Number of instructions simulated
< sim_ops 57321719 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory
---
> host_inst_rate 128893 # Simulator instruction rate (inst/s)
> host_op_rate 128893 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 4273489918 # Simulator tick rate (ticks/s)
> host_mem_usage 307500 # Number of bytes of host memory used
> host_seconds 444.73 # Real time elapsed on the host
> sim_insts 57321882 # Number of instructions simulated
> sim_ops 57321882 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 875200 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24658176 # Number of bytes read from this memory
17,26c17,26
< system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu1.inst 108032 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 692736 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28984960 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 875200 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 108032 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 983232 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7922432 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7922432 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13675 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 385284 # Number of read requests responded to by this memory
28,34c28,34
< system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu1.inst 1688 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 10824 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 452890 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 123788 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 123788 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 460503 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12974366 # Total read bandwidth from this memory (bytes/s)
36,46c36,46
< system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 56843 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 364496 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 15250986 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 460503 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 56843 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 517346 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4168538 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4168538 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4168538 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 460503 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12974366 # Total bandwidth to/from this memory (bytes/s)
48,55c48,55
< system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s)
< system.l2c.replacements 345959 # number of replacements
< system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use
< system.l2c.total_refs 2564962 # Total number of references to valid blocks.
< system.l2c.sampled_refs 411131 # Sample count of references to valid blocks.
< system.l2c.avg_refs 6.238795 # Average number of references to valid blocks.
---
> system.physmem.bw_total::cpu1.inst 56843 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 364496 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 19419523 # Total bandwidth to/from this memory (bytes/s)
> system.l2c.replacements 345965 # number of replacements
> system.l2c.tagsinuse 65264.028554 # Cycle average of tags in use
> system.l2c.total_refs 2565305 # Total number of references to valid blocks.
> system.l2c.sampled_refs 411137 # Sample count of references to valid blocks.
> system.l2c.avg_refs 6.239538 # Average number of references to valid blocks.
57,65c57,65
< system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 53566.065326 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 5313.128544 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 6099.641645 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 209.824884 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 75.368156 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.817353 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.inst 0.081072 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.093073 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.inst 0.003202 # Average percentage of cache occupancy
68,97c68,97
< system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits
< system.l2c.Writeback_hits::total 806312 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits
< system.l2c.overall_hits::cpu0.data 817538 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits
< system.l2c.overall_hits::cpu1.data 145338 # number of overall hits
< system.l2c.overall_hits::total 2054695 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses
---
> system.l2c.ReadReq_hits::cpu0.inst 778193 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 689575 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 314248 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 100958 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1882974 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 806039 # number of Writeback hits
> system.l2c.Writeback_hits::total 806039 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 439 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 613 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 128167 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 44386 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 172553 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 778193 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 817742 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 314248 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 145344 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2055527 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 778193 # number of overall hits
> system.l2c.overall_hits::cpu0.data 817742 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 314248 # number of overall hits
> system.l2c.overall_hits::cpu1.data 145344 # number of overall hits
> system.l2c.overall_hits::total 2055527 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 13677 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 272973 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 1705 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 853 # number of ReadReq misses
99,102c99,102
< system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses
---
> system.l2c.UpgradeReq_misses::cpu0.data 2871 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1574 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 4445 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 724 # number of SCUpgradeReq misses
104,122c104,122
< system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses
< system.l2c.demand_misses::total 412362 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses
< system.l2c.overall_misses::cpu0.data 386058 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses
< system.l2c.overall_misses::cpu1.data 10924 # number of overall misses
< system.l2c.overall_misses::total 412362 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles
---
> system.l2c.SCUpgradeReq_misses::total 1471 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 113108 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 10072 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 123180 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 13677 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 386081 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1705 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 10925 # number of demand (read+write) misses
> system.l2c.demand_misses::total 412388 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13677 # number of overall misses
> system.l2c.overall_misses::cpu0.data 386081 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1705 # number of overall misses
> system.l2c.overall_misses::cpu1.data 10925 # number of overall misses
> system.l2c.overall_misses::total 412388 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 728382998 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 14214430499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 91270500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 46668499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 15080752496 # number of ReadReq miss cycles
124,126c124,126
< system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles
---
> system.l2c.UpgradeReq_miss_latency::cpu1.data 19818914 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 22402914 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2792500 # number of SCUpgradeReq miss cycles
128,153c128,153
< system.l2c.SCUpgradeReq_miss_latency::total 3107000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 549004499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6610096496 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 728665998 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 20275260996 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 90803000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 596081998 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 21690811992 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 728665998 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 20275260996 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 90803000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 596081998 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 21690811992 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 791216 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 962482 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 315983 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 101848 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2171529 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 806312 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 806312 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 3043 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 2008 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 5051 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 777 # number of SCUpgradeReq accesses(hits+misses)
---
> system.l2c.SCUpgradeReq_miss_latency::total 3106500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 6061979997 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 549631499 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6611611496 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 728382998 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 20276410496 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 91270500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 596299998 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 21692363992 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 728382998 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 20276410496 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 91270500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 596299998 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 21692363992 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 791870 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 962548 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 315953 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 101811 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2172182 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 806039 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 806039 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 3045 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 2013 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 5058 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 778 # number of SCUpgradeReq accesses(hits+misses)
155,200c155,200
< system.l2c.ReadExReq_accesses::cpu0.data 241114 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 54414 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 791216 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1203596 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 315983 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 156262 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2467057 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 791216 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1203596 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 315983 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 156262 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2467057 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.017295 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.283607 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.005367 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.008454 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.133182 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942162 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780876 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.878044 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934363 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.961390 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.947876 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.469035 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.184934 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.416725 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.017295 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.320754 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.005367 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.069908 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.167147 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.017295 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.320754 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.005367 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.069908 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency
---
> system.l2c.ReadExReq_accesses::cpu0.data 241275 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 54458 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 295733 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 791870 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1203823 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 315953 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 156269 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2467915 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 791870 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1203823 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 315953 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 156269 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2467915 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.017272 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.283594 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.005396 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.008378 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.133142 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942857 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781918 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.878806 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.932990 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.960154 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.946589 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.468793 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.184950 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.416524 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.017272 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.320712 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.005396 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.069911 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.167100 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.017272 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.320712 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.005396 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.069911 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.167100 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 52145.004620 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 900.034831 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 5040.025647 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3857.044199 # average SCUpgradeReq miss latency
202,215c202,215
< system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency
---
> system.l2c.SCUpgradeReq_avg_miss_latency::total 2111.828688 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 53674.391102 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 52601.831266 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 52601.831266 # average overall miss latency
224,225c224,225
< system.l2c.writebacks::writebacks 82258 # number of writebacks
< system.l2c.writebacks::total 82258 # number of writebacks
---
> system.l2c.writebacks::writebacks 82268 # number of writebacks
> system.l2c.writebacks::total 82268 # number of writebacks
235,238c235,238
< system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 13676 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 272973 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 1688 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 853 # number of ReadReq MSHR misses
240,243c240,243
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2871 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1574 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 4445 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 724 # number of SCUpgradeReq MSHR misses
245,267c245,267
< system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles
---
> system.l2c.SCUpgradeReq_mshr_misses::total 1471 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 113108 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 10072 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 123180 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13676 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 386081 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1688 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 10925 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 412370 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13676 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 386081 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1688 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 10925 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 412370 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561190998 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939303500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69880000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36325000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 11606699498 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114956000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62989500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 177945500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29007500 # number of SCUpgradeReq MSHR miss cycles
269,283c269,283
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 58887500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4696029997 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427574999 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 5123604996 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 561190998 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 15635333497 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 69880000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 463899999 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 16730304494 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 561190998 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 15635333497 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 69880000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 463899999 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 16730304494 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820944530 # number of ReadReq MSHR uncacheable cycles
285,286c285,286
< system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::total 837594530 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194274500 # number of WriteReq MSHR uncacheable cycles
288,289c288,289
< system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles
---
> system.l2c.WriteReq_mshr_uncacheable_latency::total 1553694500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015219030 # number of overall MSHR uncacheable cycles
291,324c291,324
< system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency
---
> system.l2c.overall_mshr_uncacheable_latency::total 2391289030 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283594 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008378 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.133133 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942857 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781918 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.878806 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.932990 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960154 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.946589 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.468793 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184950 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.416524 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.167092 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017271 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.320712 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005343 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.069911 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.167092 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735 # average SCUpgradeReq mshr miss latency
326,339c326,339
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency
---
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 40571.099968 # average overall mshr miss latency
351c351
< system.iocache.tagsinuse 0.465240 # Cycle average of tags in use
---
> system.iocache.tagsinuse 0.465235 # Cycle average of tags in use
356c356
< system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor
---
> system.iocache.occ_blocks::tsunami.ide 0.465235 # Average occupied blocks per requestor
369,374c369,374
< system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::tsunami.ide 7637828806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 7637828806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 7659067804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 7659067804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 7659067804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 7659067804 # number of overall miss cycles
393,399c393,399
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 183813.746775 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 183538.648550 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 183538.648550 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 7685000 # number of cycles access was blocked
401c401
< system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked
403c403
< system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 1074.524609 # average number of cycles each access was blocked
419,424c419,424
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles
---
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476969000 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 5476969000 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 5488951000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 5488951000 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 5488951000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 5488951000 # number of overall MSHR miss cycles
435,440c435,440
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency
---
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 131534.890966 # average overall mshr miss latency
458,473c458,473
< system.cpu0.dtb.read_hits 8334313 # DTB read hits
< system.cpu0.dtb.read_misses 29661 # DTB read misses
< system.cpu0.dtb.read_acv 416 # DTB read access violations
< system.cpu0.dtb.read_accesses 650050 # DTB read accesses
< system.cpu0.dtb.write_hits 5360515 # DTB write hits
< system.cpu0.dtb.write_misses 6017 # DTB write misses
< system.cpu0.dtb.write_acv 275 # DTB write access violations
< system.cpu0.dtb.write_accesses 211537 # DTB write accesses
< system.cpu0.dtb.data_hits 13694828 # DTB hits
< system.cpu0.dtb.data_misses 35678 # DTB misses
< system.cpu0.dtb.data_acv 691 # DTB access violations
< system.cpu0.dtb.data_accesses 861587 # DTB accesses
< system.cpu0.itb.fetch_hits 972456 # ITB hits
< system.cpu0.itb.fetch_misses 29747 # ITB misses
< system.cpu0.itb.fetch_acv 802 # ITB acv
< system.cpu0.itb.fetch_accesses 1002203 # ITB accesses
---
> system.cpu0.dtb.read_hits 8334041 # DTB read hits
> system.cpu0.dtb.read_misses 29708 # DTB read misses
> system.cpu0.dtb.read_acv 432 # DTB read access violations
> system.cpu0.dtb.read_accesses 650283 # DTB read accesses
> system.cpu0.dtb.write_hits 5360343 # DTB write hits
> system.cpu0.dtb.write_misses 6029 # DTB write misses
> system.cpu0.dtb.write_acv 281 # DTB write access violations
> system.cpu0.dtb.write_accesses 211361 # DTB write accesses
> system.cpu0.dtb.data_hits 13694384 # DTB hits
> system.cpu0.dtb.data_misses 35737 # DTB misses
> system.cpu0.dtb.data_acv 713 # DTB access violations
> system.cpu0.dtb.data_accesses 861644 # DTB accesses
> system.cpu0.itb.fetch_hits 975254 # ITB hits
> system.cpu0.itb.fetch_misses 26821 # ITB misses
> system.cpu0.itb.fetch_acv 801 # ITB acv
> system.cpu0.itb.fetch_accesses 1002075 # ITB accesses
486c486
< system.cpu0.numCycles 107494535 # number of cpu cycles simulated
---
> system.cpu0.numCycles 107505653 # number of cpu cycles simulated
489,493c489,493
< system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups
< system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted
< system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect
< system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups
< system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits
---
> system.cpu0.BPredUnit.lookups 11783453 # Number of BP lookups
> system.cpu0.BPredUnit.condPredicted 9875598 # Number of conditional branches predicted
> system.cpu0.BPredUnit.condIncorrect 345606 # Number of conditional branches incorrect
> system.cpu0.BPredUnit.BTBLookups 8356965 # Number of BTB lookups
> system.cpu0.BPredUnit.BTBHits 5072042 # Number of BTB hits
495,512c495,512
< system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target.
< system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions.
< system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked
< system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.BPredUnit.usedRAS 768478 # Number of times the RAS was used to get a target.
> system.cpu0.BPredUnit.RASInCorrect 29315 # Number of incorrect RAS predictions.
> system.cpu0.fetch.icacheStallCycles 25158431 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 60438649 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 11783453 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 5840520 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 11478099 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1678793 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.BlockedCycles 36446213 # Number of cycles fetch has spent blocked
> system.cpu0.fetch.MiscStallCycles 35059 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 187963 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 310129 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 7506544 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 232672 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 74721559 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.808852 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 2.135528 # Number of instructions fetched each cycle (Total)
514,522c514,522
< system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 63243460 84.64% 84.64% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 740935 0.99% 85.63% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1559450 2.09% 87.72% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 686263 0.92% 88.64% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2492339 3.34% 91.97% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 528695 0.71% 92.68% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 568727 0.76% 93.44% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 718688 0.96% 94.40% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 4183002 5.60% 100.00% # Number of instructions fetched each cycle (Total)
526,570c526,570
< system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full
< system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 74721559 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.109608 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.562190 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 26241114 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 36078495 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 10432905 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 895868 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 1073176 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 504459 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 32663 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 59394337 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 93513 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 1073176 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 27177088 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 15322085 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 17293060 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9793199 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 4062949 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 56409108 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 7164 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 656382 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LSQFullEvents 1492215 # Number of times rename has blocked due to LSQ full
> system.cpu0.rename.RenamedOperands 37953965 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 68862069 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 68509500 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 352569 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 33051447 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4902518 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1333146 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 200213 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 10586539 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 8773665 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 5638420 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1132750 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 738704 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 50116530 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1671338 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 48856724 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 108345 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 5942974 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 3041199 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1133867 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 74721559 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.653850 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.297886 # Number of insts issued each cycle
572,580c572,580
< system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 52677257 70.50% 70.50% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 10184833 13.63% 84.13% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 4563049 6.11% 90.24% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2984127 3.99% 94.23% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2257312 3.02% 97.25% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1142410 1.53% 98.78% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 582471 0.78% 99.56% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 283512 0.38% 99.94% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 46588 0.06% 100.00% # Number of insts issued each cycle
584c584
< system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 74721559 # Number of insts issued each cycle
586,616c586,616
< system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 73394 11.97% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 287556 46.90% 58.87% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 252163 41.13% 100.00% # attempts to use FU when none available
620,622c620,622
< system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 33933939 69.46% 69.47% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 53607 0.11% 69.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.57% # Type of FU issued
649,651c649,651
< system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::MemRead 8676123 17.76% 87.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5426873 11.11% 98.48% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 742938 1.52% 100.00% # Type of FU issued
653,665c653,665
< system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued
< system.cpu0.iq.rate 0.454505 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 48856724 # Type of FU issued
> system.cpu0.iq.rate 0.454457 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 613113 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.012549 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 172655307 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 57499462 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 47860573 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 501158 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 243682 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 236026 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 49203092 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 262278 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 518007 # Number of loads that had data forwarded from stores
667,670c667,670
< system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1116542 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2532 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 12656 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 476196 # Number of stores squashed
673,674c673,674
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18844 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 94055 # Number of times an access to memory failed due to the cache being blocked
676,692c676,692
< system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 1073176 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 10803844 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 780020 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 54838073 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 560128 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 8773665 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 5638420 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1470903 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 544426 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 8361 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 12656 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 186168 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 328100 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 514268 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 48431034 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 8384906 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 425690 # Number of squashed instructions skipped in execute
694,702c694,702
< system.cpu0.iew.exec_nop 3050834 # number of nop insts executed
< system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 7758760 # Number of branches executed
< system.cpu0.iew.exec_stores 5379143 # Number of stores executed
< system.cpu0.iew.exec_rate 0.450548 # Inst execution rate
< system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 24100280 # num instructions producing a value
< system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 3050205 # number of nop insts executed
> system.cpu0.iew.exec_refs 13763900 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 7759085 # Number of branches executed
> system.cpu0.iew.exec_stores 5378994 # Number of stores executed
> system.cpu0.iew.exec_rate 0.450498 # Inst execution rate
> system.cpu0.iew.wb_sent 48183963 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 48096599 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 24100955 # num instructions producing a value
> system.cpu0.iew.wb_consumers 32404442 # num instructions consuming a value
704,705c704,705
< system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.447387 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.743755 # average fanout of values written-back
707,714c707,714
< system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions
< system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions
< system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle
---
> system.cpu0.commit.commitCommittedInsts 48294855 # The number of committed instructions
> system.cpu0.commit.commitCommittedOps 48294855 # The number of committed instructions
> system.cpu0.commit.commitSquashedInsts 6449755 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 537471 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 480800 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 73648383 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.655749 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.560255 # Number of insts commited each cycle
716,724c716,724
< system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 55233499 75.00% 75.00% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7733418 10.50% 85.50% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 4278651 5.81% 91.31% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2283988 3.10% 94.41% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1242605 1.69% 96.09% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 524240 0.71% 96.81% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 434900 0.59% 97.40% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 385505 0.52% 97.92% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1531577 2.08% 100.00% # Number of insts commited each cycle
728,730c728,730
< system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 48294177 # Number of instructions committed
< system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 73648383 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 48294855 # Number of instructions committed
> system.cpu0.commit.committedOps 48294855 # Number of ops (including micro ops) committed
732,733c732,733
< system.cpu0.commit.refs 12819276 # Number of memory references committed
< system.cpu0.commit.loads 7657070 # Number of loads committed
---
> system.cpu0.commit.refs 12819347 # Number of memory references committed
> system.cpu0.commit.loads 7657123 # Number of loads committed
735c735
< system.cpu0.commit.branches 7325526 # Number of branches committed
---
> system.cpu0.commit.branches 7325688 # Number of branches committed
737,739c737,739
< system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 610965 # Number of function calls committed.
< system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached
---
> system.cpu0.commit.int_insts 44748779 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 610967 # Number of function calls committed.
> system.cpu0.commit.bw_lim_events 1531577 # number cycles where commit BW limit reached
741,758c741,758
< system.cpu0.rob.rob_reads 126666255 # The number of ROB reads
< system.cpu0.rob.rob_writes 110560293 # The number of ROB writes
< system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 45532520 # Number of Instructions Simulated
< system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated
< system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated
< system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads
< system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes
---
> system.cpu0.rob.rob_reads 126676900 # The number of ROB reads
> system.cpu0.rob.rob_writes 110562172 # The number of ROB writes
> system.cpu0.timesIdled 1222053 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 32784094 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3693280483 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 45533193 # Number of Instructions Simulated
> system.cpu0.committedOps 45533193 # Number of Ops (including micro ops) Simulated
> system.cpu0.committedInsts_total 45533193 # Number of Instructions Simulated
> system.cpu0.cpi 2.361039 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.361039 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.423542 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.423542 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 63859411 # number of integer regfile reads
> system.cpu0.int_regfile_writes 34945756 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 117042 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 117632 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1550181 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 750158 # number of misc regfile writes
790,794c790,794
< system.cpu0.icache.replacements 790628 # number of replacements
< system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use
< system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks.
---
> system.cpu0.icache.replacements 791282 # number of replacements
> system.cpu0.icache.tagsinuse 510.000823 # Cycle average of tags in use
> system.cpu0.icache.total_refs 6671308 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 791794 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 8.425560 # Average number of references to valid blocks.
796c796
< system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor
---
> system.cpu0.icache.occ_blocks::cpu0.inst 510.000823 # Average occupied blocks per requestor
799,835c799,835
< system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits
< system.cpu0.icache.overall_hits::total 6669453 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses
< system.cpu0.icache.overall_misses::total 834673 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked
---
> system.cpu0.icache.ReadReq_hits::cpu0.inst 6671308 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 6671308 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 6671308 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 6671308 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 6671308 # number of overall hits
> system.cpu0.icache.overall_hits::total 6671308 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 835236 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 835236 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 835236 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 835236 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 835236 # number of overall misses
> system.cpu0.icache.overall_misses::total 835236 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13775160993 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13775160993 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13775160993 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13775160993 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13775160993 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13775160993 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 7506544 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 7506544 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 7506544 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 7506544 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 7506544 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 7506544 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111268 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.111268 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111268 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.111268 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111268 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.111268 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 16492.537430 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 16492.537430 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 1463996 # number of cycles access was blocked
837c837
< system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked
839c839
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 9265.797468 # average number of cycles each access was blocked
843,874c843,872
< system.cpu0.icache.writebacks::writebacks 247 # number of writebacks
< system.cpu0.icache.writebacks::total 247 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43249 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 43249 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 43249 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 43249 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 43249 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 43249 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791987 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 791987 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 791987 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 791987 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 791987 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 791987 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10696262996 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 10696262996 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10696262996 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 10696262996 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10696262996 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 10696262996 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105506 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.105506 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105506 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.105506 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254 # average overall mshr miss latency
876,880c874,878
< system.cpu0.dcache.replacements 1206208 # number of replacements
< system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 1206262 # number of replacements
> system.cpu0.dcache.tagsinuse 505.874752 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 9821312 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 1206702 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 8.138971 # Average number of references to valid blocks.
882,957c880,955
< system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits
< system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked
---
> system.cpu0.dcache.occ_blocks::cpu0.data 505.874752 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.988037 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.988037 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6113380 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6113380 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3377082 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3377082 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150588 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 150588 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171660 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 171660 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 9490462 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 9490462 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 9490462 # number of overall hits
> system.cpu0.dcache.overall_hits::total 9490462 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1478592 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1478592 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1593723 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1593723 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18660 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 18660 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4698 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 4698 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3072315 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3072315 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3072315 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3072315 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41280324500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 41280324500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65318664554 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 65318664554 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315332000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 315332000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68573000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 68573000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 106598989054 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 106598989054 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591972 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7591972 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970805 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4970805 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169248 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 169248 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176358 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 176358 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12562777 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12562777 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12562777 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12562777 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194757 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.194757 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320617 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.320617 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110252 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110252 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026639 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026639 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244557 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.244557 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244557 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.244557 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 716919646 # number of cycles access was blocked
959c957
< system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked
---
> system.cpu0.dcache.blocked::no_mshrs 65391 # number of cycles access was blocked
961c959
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848 # average number of cycles each access was blocked
965,1030c963,1028
< system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks
< system.cpu0.dcache.writebacks::total 693284 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 693314 # number of writebacks
> system.cpu0.dcache.writebacks::total 693314 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515793 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 515793 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344404 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1344404 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3762 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3762 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1860197 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1860197 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1860197 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1860197 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962799 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 962799 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249319 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 249319 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14898 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14898 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4698 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 4698 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212118 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1212118 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212118 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1212118 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25944695097 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25944695097 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8701407966 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8701407966 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186837501 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186837501 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 53961001 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 53961001 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34646103063 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 34646103063 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34646103063 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 34646103063 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918480000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918480000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327721998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327721998 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246201998 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246201998 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126818 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126818 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050157 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050157 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088025 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088025 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026639 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026639 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.096485 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096485 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.096485 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772 # average overall mshr miss latency
1042,1043c1040,1041
< system.cpu1.dtb.read_hits 2499316 # DTB read hits
< system.cpu1.dtb.read_misses 12569 # DTB read misses
---
> system.cpu1.dtb.read_hits 2497958 # DTB read hits
> system.cpu1.dtb.read_misses 12385 # DTB read misses
1045,1057c1043,1055
< system.cpu1.dtb.read_accesses 313735 # DTB read accesses
< system.cpu1.dtb.write_hits 1734639 # DTB write hits
< system.cpu1.dtb.write_misses 3525 # DTB write misses
< system.cpu1.dtb.write_acv 140 # DTB write access violations
< system.cpu1.dtb.write_accesses 132367 # DTB write accesses
< system.cpu1.dtb.data_hits 4233955 # DTB hits
< system.cpu1.dtb.data_misses 16094 # DTB misses
< system.cpu1.dtb.data_acv 245 # DTB access violations
< system.cpu1.dtb.data_accesses 446102 # DTB accesses
< system.cpu1.itb.fetch_hits 489806 # ITB hits
< system.cpu1.itb.fetch_misses 8851 # ITB misses
< system.cpu1.itb.fetch_acv 360 # ITB acv
< system.cpu1.itb.fetch_accesses 498657 # ITB accesses
---
> system.cpu1.dtb.read_accesses 312687 # DTB read accesses
> system.cpu1.dtb.write_hits 1734137 # DTB write hits
> system.cpu1.dtb.write_misses 3404 # DTB write misses
> system.cpu1.dtb.write_acv 137 # DTB write access violations
> system.cpu1.dtb.write_accesses 131810 # DTB write accesses
> system.cpu1.dtb.data_hits 4232095 # DTB hits
> system.cpu1.dtb.data_misses 15789 # DTB misses
> system.cpu1.dtb.data_acv 242 # DTB access violations
> system.cpu1.dtb.data_accesses 444497 # DTB accesses
> system.cpu1.itb.fetch_hits 488697 # ITB hits
> system.cpu1.itb.fetch_misses 8773 # ITB misses
> system.cpu1.itb.fetch_acv 366 # ITB acv
> system.cpu1.itb.fetch_accesses 497470 # ITB accesses
1070c1068
< system.cpu1.numCycles 22717311 # number of cpu cycles simulated
---
> system.cpu1.numCycles 22715640 # number of cpu cycles simulated
1073,1077c1071,1075
< system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups
< system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted
< system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect
< system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups
< system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits
---
> system.cpu1.BPredUnit.lookups 3441563 # Number of BP lookups
> system.cpu1.BPredUnit.condPredicted 2848590 # Number of conditional branches predicted
> system.cpu1.BPredUnit.condIncorrect 108508 # Number of conditional branches incorrect
> system.cpu1.BPredUnit.BTBLookups 2344214 # Number of BTB lookups
> system.cpu1.BPredUnit.BTBHits 1191088 # Number of BTB hits
1079,1096c1077,1094
< system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target.
< system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions.
< system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked
< system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.BPredUnit.usedRAS 236176 # Number of times the RAS was used to get a target.
> system.cpu1.BPredUnit.RASInCorrect 10617 # Number of incorrect RAS predictions.
> system.cpu1.fetch.icacheStallCycles 9035553 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 16314409 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 3441563 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1427264 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 2922038 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 525528 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.BlockedCycles 8308395 # Number of cycles fetch has spent blocked
> system.cpu1.fetch.MiscStallCycles 28029 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 86548 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 64086 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1962045 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 75286 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 20775175 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.785284 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.154306 # Number of instructions fetched each cycle (Total)
1098,1106c1096,1104
< system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 17853137 85.93% 85.93% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 203247 0.98% 86.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 300737 1.45% 88.36% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 225181 1.08% 89.44% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 403762 1.94% 91.39% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 151742 0.73% 92.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 164996 0.79% 92.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 308573 1.49% 94.40% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1163800 5.60% 100.00% # Number of instructions fetched each cycle (Total)
1110,1154c1108,1152
< system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full
< system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 20775175 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.151506 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.718202 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 8809071 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 8765539 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 2707216 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 172890 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 320458 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 151147 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 10158 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 16014026 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 29482 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 320458 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 9091295 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 884150 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6951341 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2592964 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 934965 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 14837454 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 127 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 84091 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LSQFullEvents 280482 # Number of times rename has blocked due to LSQ full
> system.cpu1.rename.RenamedOperands 9656446 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 17623003 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 17415204 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 207799 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 8330618 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1325820 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 594023 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 64559 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 2775443 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 2639269 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1825014 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 248716 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 160479 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 12970444 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 664664 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 12696455 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 35550 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1743951 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 828101 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 468923 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 20775175 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.611136 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.284217 # Number of insts issued each cycle
1156,1164c1154,1162
< system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 15113498 72.75% 72.75% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 2653136 12.77% 85.52% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 1113601 5.36% 90.88% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 723121 3.48% 94.36% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 602829 2.90% 97.26% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 288191 1.39% 98.65% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 181892 0.88% 99.52% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 88125 0.42% 99.95% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 10782 0.05% 100.00% # Number of insts issued each cycle
1168c1166
< system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 20775175 # Number of insts issued each cycle
1170,1200c1168,1198
< system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 3857 1.52% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 134714 53.16% 54.69% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 114823 45.31% 100.00% # attempts to use FU when none available
1204,1207c1202,1205
< system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 7925481 62.42% 62.45% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 20760 0.16% 62.61% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 10544 0.08% 62.69% # Type of FU issued
1233,1235c1231,1233
< system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::MemRead 2621698 20.65% 83.35% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1764339 13.90% 97.25% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 349399 2.75% 100.00% # Type of FU issued
1237,1249c1235,1247
< system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued
< system.cpu1.iq.rate 0.559079 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 12696455 # Type of FU issued
> system.cpu1.iq.rate 0.558930 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 253394 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.019958 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 46157750 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 15236198 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 12337265 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 299278 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 145041 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 140795 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 12790304 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 156722 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 115188 # Number of loads that had data forwarded from stores
1251,1254c1249,1252
< system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 346106 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 806 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 2268 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 152574 # Number of stores squashed
1257,1258c1255,1256
< system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 376 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 11381 # Number of times an access to memory failed due to the cache being blocked
1260,1276c1258,1274
< system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 320458 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 536973 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 73252 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 14361364 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 205800 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 2639269 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1825014 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 596393 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 55379 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 5710 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 2268 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 53644 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 129908 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 183552 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 12575424 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 2521777 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 121030 # Number of squashed instructions skipped in execute
1278,1286c1276,1284
< system.cpu1.iew.exec_nop 726447 # number of nop insts executed
< system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1887172 # Number of branches executed
< system.cpu1.iew.exec_stores 1746592 # Number of stores executed
< system.cpu1.iew.exec_rate 0.553740 # Inst execution rate
< system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 5700900 # num instructions producing a value
< system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 726256 # number of nop insts executed
> system.cpu1.iew.exec_refs 4267761 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1886646 # Number of branches executed
> system.cpu1.iew.exec_stores 1745984 # Number of stores executed
> system.cpu1.iew.exec_rate 0.553602 # Inst execution rate
> system.cpu1.iew.wb_sent 12512047 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 12478060 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 5698826 # num instructions producing a value
> system.cpu1.iew.wb_consumers 8037620 # num instructions consuming a value
1288,1289c1286,1287
< system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.549316 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.709019 # average fanout of values written-back
1291,1298c1289,1296
< system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions
< system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions
< system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle
---
> system.cpu1.commit.commitCommittedInsts 12432644 # The number of committed instructions
> system.cpu1.commit.commitCommittedOps 12432644 # The number of committed instructions
> system.cpu1.commit.commitSquashedInsts 1853978 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 195741 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 172939 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 20454717 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.607813 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.554325 # Number of insts commited each cycle
1300,1308c1298,1306
< system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 15840554 77.44% 77.44% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 2123906 10.38% 87.83% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 810748 3.96% 91.79% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 497113 2.43% 94.22% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 362163 1.77% 95.99% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 133438 0.65% 96.64% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 130960 0.64% 97.28% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 152379 0.74% 98.03% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 403456 1.97% 100.00% # Number of insts commited each cycle
1312,1314c1310,1312
< system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 12433159 # Number of instructions committed
< system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 20454717 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 12432644 # Number of instructions committed
> system.cpu1.commit.committedOps 12432644 # Number of ops (including micro ops) committed
1316,1319c1314,1317
< system.cpu1.commit.refs 3965647 # Number of memory references committed
< system.cpu1.commit.loads 2293191 # Number of loads committed
< system.cpu1.commit.membars 64658 # Number of memory barriers committed
< system.cpu1.commit.branches 1777478 # Number of branches committed
---
> system.cpu1.commit.refs 3965603 # Number of memory references committed
> system.cpu1.commit.loads 2293163 # Number of loads committed
> system.cpu1.commit.membars 64660 # Number of memory barriers committed
> system.cpu1.commit.branches 1777364 # Number of branches committed
1321c1319
< system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions.
---
> system.cpu1.commit.int_insts 11487490 # Number of committed integer instructions.
1323c1321
< system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached
---
> system.cpu1.commit.bw_lim_events 403456 # number cycles where commit BW limit reached
1325,1347c1323,1345
< system.cpu1.rob.rob_reads 34238592 # The number of ROB reads
< system.cpu1.rob.rob_writes 28901418 # The number of ROB writes
< system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 11789199 # Number of Instructions Simulated
< system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated
< system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated
< system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads
< system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes
< system.cpu1.icache.replacements 315447 # number of replacements
< system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use
< system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks.
---
> system.cpu1.rob.rob_reads 34231845 # The number of ROB reads
> system.cpu1.rob.rob_writes 28892260 # The number of ROB writes
> system.cpu1.timesIdled 230897 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 1940465 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3778342351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 11788689 # Number of Instructions Simulated
> system.cpu1.committedOps 11788689 # Number of Ops (including micro ops) Simulated
> system.cpu1.committedInsts_total 11788689 # Number of Instructions Simulated
> system.cpu1.cpi 1.926901 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.926901 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.518968 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.518968 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 16191128 # number of integer regfile reads
> system.cpu1.int_regfile_writes 8793643 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 73550 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 74224 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 699686 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 299450 # number of misc regfile writes
> system.cpu1.icache.replacements 315418 # number of replacements
> system.cpu1.icache.tagsinuse 471.006638 # Cycle average of tags in use
> system.cpu1.icache.total_refs 1633897 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 315930 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 5.171706 # Average number of references to valid blocks.
1349,1388c1347,1386
< system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor
< system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy
< system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits
< system.cpu1.icache.overall_hits::total 1635327 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses
< system.cpu1.icache.overall_misses::total 328187 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked
---
> system.cpu1.icache.occ_blocks::cpu1.inst 471.006638 # Average occupied blocks per requestor
> system.cpu1.icache.occ_percent::cpu1.inst 0.919935 # Average percentage of cache occupancy
> system.cpu1.icache.occ_percent::total 0.919935 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1633897 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1633897 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1633897 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1633897 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1633897 # number of overall hits
> system.cpu1.icache.overall_hits::total 1633897 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 328148 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 328148 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 328148 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 328148 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 328148 # number of overall misses
> system.cpu1.icache.overall_misses::total 328148 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323185498 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5323185498 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5323185498 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5323185498 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5323185498 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5323185498 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1962045 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1962045 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1962045 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1962045 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1962045 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1962045 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167248 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.167248 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167248 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.167248 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167248 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.167248 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 16221.904439 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 16221.904439 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 248998 # number of cycles access was blocked
1390c1388
< system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked
1392c1390
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 5928.523810 # average number of cycles each access was blocked
1396,1427c1394,1423
< system.cpu1.icache.writebacks::writebacks 38 # number of writebacks
< system.cpu1.icache.writebacks::total 38 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12162 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 12162 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 12162 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 12162 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 12162 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 12162 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315986 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 315986 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 315986 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 315986 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 315986 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 315986 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183764998 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183764998 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183764998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4183764998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183764998 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4183764998 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.161049 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.161049 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.161049 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.161049 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250 # average overall mshr miss latency
1429,1433c1425,1429
< system.cpu1.dcache.replacements 159076 # number of replacements
< system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks.
---
> system.cpu1.dcache.replacements 159031 # number of replacements
> system.cpu1.dcache.tagsinuse 488.853384 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 3387429 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 159543 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 21.232075 # Average number of references to valid blocks.
1435,1443c1431,1439
< system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits
---
> system.cpu1.dcache.occ_blocks::cpu1.data 488.853384 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.954792 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.954792 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 2021122 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 2021122 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1250999 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1250999 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49956 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 49956 # number of LoadLockedReq hits
1446,1510c1442,1506
< system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits
< system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses
< system.cpu1.dcache.overall_misses::total 668020 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked
---
> system.cpu1.dcache.demand_hits::cpu1.data 3272121 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 3272121 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 3272121 # number of overall hits
> system.cpu1.dcache.overall_hits::total 3272121 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 307358 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 307358 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 360875 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 360875 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8692 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 8692 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5047 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 5047 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 668233 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 668233 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 668233 # number of overall misses
> system.cpu1.dcache.overall_misses::total 668233 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6376981500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 6376981500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11324805298 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 11324805298 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121402000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 121402000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68410000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 68410000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 17701786798 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 17701786798 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 17701786798 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 17701786798 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2328480 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2328480 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611874 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1611874 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58648 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 58648 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53648 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 53648 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 3940354 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 3940354 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 3940354 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 3940354 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131999 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.131999 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223885 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.223885 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148206 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148206 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094076 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094076 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169587 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.169587 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169587 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.169587 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 57267488 # number of cycles access was blocked
1512c1508
< system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked
---
> system.cpu1.dcache.blocked::no_mshrs 6761 # number of cycles access was blocked
1514c1510
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked
---
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8470.268895 # average number of cycles each access was blocked
1518,1583c1514,1579
< system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks
< system.cpu1.dcache.writebacks::total 112743 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 112725 # number of writebacks
> system.cpu1.dcache.writebacks::total 112725 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 197085 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 197085 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298748 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 298748 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1016 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1016 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 495833 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 495833 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 495833 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 495833 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110273 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 110273 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62127 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 62127 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7676 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7676 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5047 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 5047 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 172400 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 172400 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 172400 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 172400 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1761266064 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1761266064 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471935334 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471935334 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78208000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78208000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52884501 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52884501 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3233201398 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3233201398 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3233201398 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3233201398 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18624000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18624000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400633000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400633000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419257000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419257000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047358 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047358 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038543 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038543 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130883 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130883 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094076 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094076 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.043752 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043752 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.043752 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434 # average overall mshr miss latency
1593c1589
< system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed
---
> system.cpu0.kern.inst.hwrei 167511 # number of hwrei instructions executed
1598,1599c1594,1595
< system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl
---
> system.cpu0.kern.ipl_count::31 84510 58.04% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 145602 # number of times we switched to this ipl
1606,1611c1602,1607
< system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl
---
> system.cpu0.kern.ipl_ticks::0 1862592154000 98.01% 98.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 96215500 0.01% 98.02% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 394866000 0.02% 98.04% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 155183500 0.01% 98.04% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 37157983500 1.96% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1900396402500 # number of cycles we spent at this ipl
1616,1617c1612,1613
< system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.681008 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.810058 # fraction of swpipl calls that actually changed the ipl
1657c1653
< system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed
---
> system.cpu0.kern.callpal::swpipl 138811 90.43% 92.75% # number of callpals executed
1666c1662
< system.cpu0.kern.callpal::total 153507 # number of callpals executed
---
> system.cpu0.kern.callpal::total 153508 # number of callpals executed
1668c1664
< system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches
---
> system.cpu0.kern.mode_switch::user 1099 # number of protection mode switches
1670,1671c1666,1667
< system.cpu0.kern.mode_good::kernel 1098
< system.cpu0.kern.mode_good::user 1098
---
> system.cpu0.kern.mode_good::kernel 1099
> system.cpu0.kern.mode_good::user 1099
1673c1669
< system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.164275 # fraction of useful protection mode switches
1676,1678c1672,1674
< system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.282193 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1897960603000 99.90% 99.90% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1864923000 0.10% 100.00% # number of ticks spent at the given mode
1683,1685c1679,1681
< system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl
---
> system.cpu1.kern.inst.hwrei 74469 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 24566 38.36% 38.36% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1923 3.00% 41.37% # number of times we switched to this ipl
1687,1689c1683,1685
< system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl
---
> system.cpu1.kern.ipl_count::31 37109 57.95% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 64037 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 23887 48.07% 48.07% # number of times we switched to this ipl from a different ipl
1692,1699c1688,1695
< system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_good::31 23448 47.18% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 49697 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1870827131500 98.44% 98.44% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 343570500 0.02% 98.46% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 182754500 0.01% 98.46% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 29175936000 1.54% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1900529392500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.972360 # fraction of swpipl calls that actually changed the ipl
1702,1703c1698,1699
< system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.631868 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.776067 # fraction of swpipl calls that actually changed the ipl
1733c1729
< system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed
---
> system.cpu1.kern.callpal::swpipl 57994 87.22% 90.51% # number of callpals executed
1735c1731
< system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed
---
> system.cpu1.kern.callpal::wrkgp 1 0.00% 94.12% # number of callpals executed
1743c1739
< system.cpu1.kern.callpal::total 66490 # number of callpals executed
---
> system.cpu1.kern.callpal::total 66492 # number of callpals executed
1754,1756c1750,1752
< system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode
---
> system.cpu1.kern.mode_ticks::kernel 7877089500 0.41% 0.41% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 911545000 0.05% 0.46% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1891740750000 99.54% 100.00% # number of ticks spent at the given mode