3,5c3,5
< sim_seconds 1.907549 # Number of seconds simulated
< sim_ticks 1907549438500 # Number of ticks simulated
< final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.909484 # Number of seconds simulated
> sim_ticks 1909483951500 # Number of ticks simulated
> final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 237406 # Simulator instruction rate (inst/s)
< host_op_rate 237406 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7990338524 # Simulator tick rate (ticks/s)
< host_mem_usage 342872 # Number of bytes of host memory used
< host_seconds 238.73 # Real time elapsed on the host
< sim_insts 56676315 # Number of instructions simulated
< sim_ops 56676315 # Number of ops (including micro ops) simulated
---
> host_inst_rate 164890 # Simulator instruction rate (inst/s)
> host_op_rate 164890 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5556117262 # Simulator tick rate (ticks/s)
> host_mem_usage 341236 # Number of bytes of host memory used
> host_seconds 343.67 # Real time elapsed on the host
> sim_insts 56668174 # Number of instructions simulated
> sim_ops 56668174 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory
22,30c22,30
< system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory
33,39c33,39
< system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s)
41,51c41,51
< system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s)
53,63c53,63
< system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 411070 # Number of read requests accepted
< system.physmem.writeReqs 123616 # Number of write requests accepted
< system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 411061 # Number of read requests accepted
> system.physmem.writeReqs 123600 # Number of write requests accepted
> system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
66,73c66,73
< system.physmem.perBankRdBursts::0 26240 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25986 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25958 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25690 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25582 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25570 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25628 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25343 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 26241 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25988 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25972 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25684 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25579 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25567 # Per bank write bursts
> system.physmem.perBankRdBursts::6 25634 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25346 # Per bank write bursts
75,77c75,77
< system.physmem.perBankRdBursts::9 25698 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25929 # Per bank write bursts
< system.physmem.perBankRdBursts::11 25525 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 25694 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25928 # Per bank write bursts
> system.physmem.perBankRdBursts::11 25514 # Per bank write bursts
79,82c79,82
< system.physmem.perBankRdBursts::13 25420 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25099 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25608 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8587 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 25422 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25093 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25620 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8582 # Per bank write bursts
84,89c84,89
< system.physmem.perBankWrBursts::2 7940 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7436 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7275 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7415 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7544 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7156 # Per bank write bursts
---
> system.physmem.perBankWrBursts::2 7941 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7423 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7276 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7412 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7548 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7160 # Per bank write bursts
91,97c91,97
< system.physmem.perBankWrBursts::9 7639 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7820 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7739 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8260 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7848 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7518 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7790 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 7637 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7817 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7733 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8265 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7849 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7512 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7803 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 73 # Number of times write queue was full causing retry
< system.physmem.totGap 1907545081500 # Total gap between requests
---
> system.physmem.numWrRetry 80 # Number of times write queue was full causing retry
> system.physmem.totGap 1909479571500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 411070 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 411061 # Read request sizes (log2)
114,120c114,120
< system.physmem.writePktSize::6 123616 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 123600 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see
162,189c162,189
< system.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see
192,228c192,228
< system.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes
232,262c232,261
< system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads
265,269c264,268
< system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads
< system.physmem.totQLat 8174654750 # Total ticks spent queuing
< system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads
> system.physmem.totQLat 8180795500 # Total ticks spent queuing
> system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst
271,275c270,274
< system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s
280,283c279,282
< system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing
< system.physmem.readRowHits 370634 # Number of row buffer hits during reads
< system.physmem.writeRowHits 99508 # Number of row buffer hits during writes
---
> system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing
> system.physmem.readRowHits 370615 # Number of row buffer hits during reads
> system.physmem.writeRowHits 99546 # Number of row buffer hits during writes
285,286c284,285
< system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes
< system.physmem.avgGap 3567598.71 # Average gap between requests
---
> system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes
> system.physmem.avgGap 3571383.68 # Average gap between requests
288,332c287,331
< system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ)
< system.physmem_0.averagePower 247.583627 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states
< system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.455703 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu0.branchPred.lookups 16746871 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits
---
> system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.578716 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states
> system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.436414 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu0.branchPred.lookups 16749334 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits
334,340c333,339
< system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions.
< system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups.
< system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits.
< system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses.
< system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches.
---
> system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions.
> system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups.
> system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits.
> system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses.
> system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches.
346,361c345,360
< system.cpu0.dtb.read_hits 9412979 # DTB read hits
< system.cpu0.dtb.read_misses 34328 # DTB read misses
< system.cpu0.dtb.read_acv 621 # DTB read access violations
< system.cpu0.dtb.read_accesses 567042 # DTB read accesses
< system.cpu0.dtb.write_hits 5709982 # DTB write hits
< system.cpu0.dtb.write_misses 8326 # DTB write misses
< system.cpu0.dtb.write_acv 453 # DTB write access violations
< system.cpu0.dtb.write_accesses 184750 # DTB write accesses
< system.cpu0.dtb.data_hits 15122961 # DTB hits
< system.cpu0.dtb.data_misses 42654 # DTB misses
< system.cpu0.dtb.data_acv 1074 # DTB access violations
< system.cpu0.dtb.data_accesses 751792 # DTB accesses
< system.cpu0.itb.fetch_hits 1307701 # ITB hits
< system.cpu0.itb.fetch_misses 6903 # ITB misses
< system.cpu0.itb.fetch_acv 605 # ITB acv
< system.cpu0.itb.fetch_accesses 1314604 # ITB accesses
---
> system.cpu0.dtb.read_hits 9423503 # DTB read hits
> system.cpu0.dtb.read_misses 34044 # DTB read misses
> system.cpu0.dtb.read_acv 602 # DTB read access violations
> system.cpu0.dtb.read_accesses 567323 # DTB read accesses
> system.cpu0.dtb.write_hits 5707426 # DTB write hits
> system.cpu0.dtb.write_misses 8375 # DTB write misses
> system.cpu0.dtb.write_acv 432 # DTB write access violations
> system.cpu0.dtb.write_accesses 185068 # DTB write accesses
> system.cpu0.dtb.data_hits 15130929 # DTB hits
> system.cpu0.dtb.data_misses 42419 # DTB misses
> system.cpu0.dtb.data_acv 1034 # DTB access violations
> system.cpu0.dtb.data_accesses 752391 # DTB accesses
> system.cpu0.itb.fetch_hits 1309826 # ITB hits
> system.cpu0.itb.fetch_misses 6979 # ITB misses
> system.cpu0.itb.fetch_acv 608 # ITB acv
> system.cpu0.itb.fetch_accesses 1316805 # ITB accesses
374,379c373,379
< system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state
---
> system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
381,384c381,384
< system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 119482029 # number of cpu cycles simulated
---
> system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 119453997 # number of cpu cycles simulated
387,392c387,392
< system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing
---
> system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing
394,402c394,402
< system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total)
404,412c404,412
< system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total)
416,461c416,461
< system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle
463,471c463,471
< system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle
475c475
< system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle
477,511c477,511
< system.cpu0.iq.fu_full::IntAlu 168885 16.81% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.81% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 486832 48.47% 65.28% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 300564 29.92% 95.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMemRead 26620 2.65% 97.85% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMemWrite 21571 2.15% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available
514,550c514,550
< system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 9721676 18.48% 87.27% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 5686986 10.81% 98.08% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMemRead 122455 0.23% 98.31% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMemWrite 110756 0.21% 98.52% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued
552,564c552,564
< system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued
< system.cpu0.iq.rate 0.440369 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 1004472 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.019091 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 219643746 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 569416 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 53310020 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 308067 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued
> system.cpu0.iq.rate 0.440485 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores
566,569c566,569
< system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed
572,573c572,573
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked
575,591c575,591
< system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute
593,609c593,609
< system.cpu0.iew.exec_nop 3539791 # number of nop insts executed
< system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 8258466 # Number of branches executed
< system.cpu0.iew.exec_stores 5735212 # Number of stores executed
< system.cpu0.iew.exec_rate 0.434663 # Inst execution rate
< system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 26224773 # num instructions producing a value
< system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 3535809 # number of nop insts executed
> system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 8258108 # Number of branches executed
> system.cpu0.iew.exec_stores 5732729 # Number of stores executed
> system.cpu0.iew.exec_rate 0.434781 # Inst execution rate
> system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 26231692 # num instructions producing a value
> system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle
611,619c611,619
< system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle
623,625c623,625
< system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 49598051 # Number of instructions committed
< system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 49593272 # Number of instructions committed
> system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed
627,636c627,636
< system.cpu0.commit.refs 13266916 # Number of memory references committed
< system.cpu0.commit.loads 7864510 # Number of loads committed
< system.cpu0.commit.membars 192309 # Number of memory barriers committed
< system.cpu0.commit.branches 7509354 # Number of branches committed
< system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 632192 # Number of function calls committed.
< system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction
---
> system.cpu0.commit.refs 13266986 # Number of memory references committed
> system.cpu0.commit.loads 7864361 # Number of loads committed
> system.cpu0.commit.membars 192313 # Number of memory barriers committed
> system.cpu0.commit.branches 7507748 # Number of branches committed
> system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 632222 # Number of function calls committed.
> system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction
638c638
< system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction
666,670c666,670
< system.cpu0.commit.op_class_0::MemRead 7943636 16.02% 87.30% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 5298998 10.68% 97.98% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction
< system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction
> system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction
672,696c672,696
< system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 169680194 # The number of ROB reads
< system.cpu0.rob.rob_writes 120607262 # The number of ROB writes
< system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 46714728 # Number of Instructions Simulated
< system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 68002319 # number of integer regfile reads
< system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 1253317 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks.
---
> system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 169631516 # The number of ROB reads
> system.cpu0.rob.rob_writes 120597460 # The number of ROB writes
> system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 46709842 # Number of Instructions Simulated
> system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads
> system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 1252644 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks.
698,809c698,809
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits
< system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked
< system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks
< system.cpu0.dcache.writebacks::total 737739 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits
> system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked
> system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks
> system.cpu0.dcache.writebacks::total 737573 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses
812,869c812,869
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 894430 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy
---
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 892272 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy
874,913c874,913
< system.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits
< system.cpu0.icache.overall_hits::total 7502081 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses
< system.cpu0.icache.overall_misses::total 949140 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked
---
> system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits
> system.cpu0.icache.overall_hits::total 7503325 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses
> system.cpu0.icache.overall_misses::total 945376 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked
915c915
< system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked
917c917
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked
919,955c919,955
< system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks
< system.cpu0.icache.writebacks::total 894430 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency
< system.cpu1.branchPred.lookups 4438770 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits
---
> system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks
> system.cpu0.icache.writebacks::total 892272 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency
> system.cpu1.branchPred.lookups 4441555 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits
957,963c957,963
< system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions.
< system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups.
< system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits.
< system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses.
< system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches.
---
> system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions.
> system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups.
> system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits.
> system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses.
> system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches.
968,983c968,983
< system.cpu1.dtb.read_hits 2431495 # DTB read hits
< system.cpu1.dtb.read_misses 15697 # DTB read misses
< system.cpu1.dtb.read_acv 126 # DTB read access violations
< system.cpu1.dtb.read_accesses 432376 # DTB read accesses
< system.cpu1.dtb.write_hits 1439190 # DTB write hits
< system.cpu1.dtb.write_misses 3913 # DTB write misses
< system.cpu1.dtb.write_acv 68 # DTB write access violations
< system.cpu1.dtb.write_accesses 163232 # DTB write accesses
< system.cpu1.dtb.data_hits 3870685 # DTB hits
< system.cpu1.dtb.data_misses 19610 # DTB misses
< system.cpu1.dtb.data_acv 194 # DTB access violations
< system.cpu1.dtb.data_accesses 595608 # DTB accesses
< system.cpu1.itb.fetch_hits 677547 # ITB hits
< system.cpu1.itb.fetch_misses 3477 # ITB misses
< system.cpu1.itb.fetch_acv 144 # ITB acv
< system.cpu1.itb.fetch_accesses 681024 # ITB accesses
---
> system.cpu1.dtb.read_hits 2431988 # DTB read hits
> system.cpu1.dtb.read_misses 15687 # DTB read misses
> system.cpu1.dtb.read_acv 78 # DTB read access violations
> system.cpu1.dtb.read_accesses 432427 # DTB read accesses
> system.cpu1.dtb.write_hits 1439876 # DTB write hits
> system.cpu1.dtb.write_misses 3853 # DTB write misses
> system.cpu1.dtb.write_acv 69 # DTB write access violations
> system.cpu1.dtb.write_accesses 163205 # DTB write accesses
> system.cpu1.dtb.data_hits 3871864 # DTB hits
> system.cpu1.dtb.data_misses 19540 # DTB misses
> system.cpu1.dtb.data_acv 147 # DTB access violations
> system.cpu1.dtb.data_accesses 595632 # DTB accesses
> system.cpu1.itb.fetch_hits 677957 # ITB hits
> system.cpu1.itb.fetch_misses 3440 # ITB misses
> system.cpu1.itb.fetch_acv 149 # ITB acv
> system.cpu1.itb.fetch_accesses 681397 # ITB accesses
996,1001c996,1001
< system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state
---
> system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state
1003,1006c1003,1006
< system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 17543632 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 17559475 # number of cpu cycles simulated
1009,1023c1009,1023
< system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total)
1025,1033c1025,1033
< system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total)
1037,1082c1037,1082
< system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle
1084,1092c1084,1092
< system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle
1096c1096
< system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle
1098,1132c1098,1132
< system.cpu1.iq.fu_full::IntAlu 33628 10.29% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 174409 53.35% 63.64% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 103464 31.65% 95.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMemRead 7989 2.44% 97.74% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMemWrite 7397 2.26% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available
1136,1171c1136,1171
< system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 2510604 21.88% 84.19% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1425191 12.42% 96.61% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMemRead 45057 0.39% 97.01% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMemWrite 43675 0.38% 97.39% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued
1173,1185c1173,1185
< system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued
< system.cpu1.iq.rate 0.653939 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 326887 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.028493 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 39721827 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 225631 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 11674105 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 120495 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued
> system.cpu1.iq.rate 0.653242 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores
1187,1190c1187,1190
< system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed
1193,1194c1193,1194
< system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked
1196,1212c1196,1212
< system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute
1214,1230c1214,1230
< system.cpu1.iew.exec_nop 650401 # number of nop insts executed
< system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1687752 # Number of branches executed
< system.cpu1.iew.exec_stores 1449670 # Number of stores executed
< system.cpu1.iew.exec_rate 0.643141 # Inst execution rate
< system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 5287384 # num instructions producing a value
< system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 650640 # number of nop insts executed
> system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1689156 # Number of branches executed
> system.cpu1.iew.exec_stores 1450305 # Number of stores executed
> system.cpu1.iew.exec_rate 0.642403 # Inst execution rate
> system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 5286560 # num instructions producing a value
> system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle
1232,1240c1232,1240
< system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle
1244,1246c1244,1246
< system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 10447204 # Number of instructions committed
< system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 10444029 # Number of instructions committed
> system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed
1248,1291c1248,1291
< system.cpu1.commit.refs 3352983 # Number of memory references committed
< system.cpu1.commit.loads 1987935 # Number of loads committed
< system.cpu1.commit.membars 48912 # Number of memory barriers committed
< system.cpu1.commit.branches 1499265 # Number of branches committed
< system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 163857 # Number of function calls committed.
< system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.54% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 1992105 19.07% 83.63% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 1323963 12.67% 96.30% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction
< system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction
---
> system.cpu1.commit.refs 3355674 # Number of memory references committed
> system.cpu1.commit.loads 1990378 # Number of loads committed
> system.cpu1.commit.membars 48933 # Number of memory barriers committed
> system.cpu1.commit.branches 1499197 # Number of branches committed
> system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 163891 # Number of function calls committed.
> system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction
> system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction
1293,1321c1293,1321
< system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 28744557 # The number of ROB reads
< system.cpu1.rob.rob_writes 26537349 # The number of ROB writes
< system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 9961587 # Number of Instructions Simulated
< system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 14521611 # number of integer regfile reads
< system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 130966 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy
---
> system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 28763808 # The number of ROB reads
> system.cpu1.rob.rob_writes 26546353 # The number of ROB writes
> system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 9958332 # Number of Instructions Simulated
> system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads
> system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 131073 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy
1323,1324c1323,1324
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
1327,1431c1327,1431
< system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits
< system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses
< system.cpu1.dcache.overall_misses::total 533959 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked
< system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks
< system.cpu1.dcache.writebacks::total 84601 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses
---
> system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits
> system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses
> system.cpu1.dcache.overall_misses::total 533406 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked
> system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks
> system.cpu1.dcache.writebacks::total 84598 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses
1434,1491c1434,1491
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 256896 # number of replacements
< system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy
---
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 256867 # number of replacements
> system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy
1493c1493
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
1495c1495
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
1497,1536c1497,1536
< system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits
< system.cpu1.icache.overall_hits::total 1710963 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses
< system.cpu1.icache.overall_misses::total 269604 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked
---
> system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits
> system.cpu1.icache.overall_hits::total 1711658 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses
> system.cpu1.icache.overall_misses::total 269479 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked
1538c1538
< system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked
1540c1540
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked
1542,1573c1542,1573
< system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks
< system.cpu1.icache.writebacks::total 256896 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency
---
> system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks
> system.cpu1.icache.writebacks::total 256867 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency
1586c1586
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
1589,1591c1589,1591
< system.iobus.trans_dist::WriteReq 54611 # Transaction distribution
< system.iobus.trans_dist::WriteResp 54611 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 54619 # Transaction distribution
> system.iobus.trans_dist::WriteResp 54619 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes)
1600c1600
< system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes)
1603,1604c1603,1604
< system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes)
1613c1613
< system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes)
1616,1617c1616,1617
< system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks)
1619c1619
< system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks)
1623c1623
< system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks)
1625c1625
< system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks)
1627c1627
< system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks)
1629c1629
< system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks)
1631c1631
< system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks)
1633c1633
< system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks)
1635c1635
< system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks)
1637c1637
< system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks)
1641c1641
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
1643c1643
< system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use
1647,1650c1647,1650
< system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy
1656c1656
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
1665,1672c1665,1672
< system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles
1689,1697c1689,1697
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked
1699c1699
< system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked
1701c1701
< system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked
1713,1720c1713,1720
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles
1729,1754c1729,1754
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 345941 # number of replacements
< system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use
< system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 345934 # number of replacements
> system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use
> system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy
1756,1760c1756,1760
< system.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id
---
> system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id
1762,1768c1762,1768
< system.l2c.tags.tag_accesses 38390429 # Number of tag accesses
< system.l2c.tags.data_accesses 38390429 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits
< system.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits
< system.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits
---
> system.l2c.tags.tag_accesses 38356372 # Number of tag accesses
> system.l2c.tags.data_accesses 38356372 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits
> system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits
> system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits
1770,1796c1770,1796
< system.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits
< system.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2120409 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 881644 # number of overall hits
< system.l2c.overall_hits::cpu0.data 868221 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 255533 # number of overall hits
< system.l2c.overall_hits::cpu1.data 115011 # number of overall hits
< system.l2c.overall_hits::total 2120409 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses
---
> system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits
> system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits
> system.l2c.overall_hits::cpu0.data 867710 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits
> system.l2c.overall_hits::cpu1.data 115068 # number of overall hits
> system.l2c.overall_hits::total 2117738 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses
1799,1914c1799,1914
< system.l2c.ReadExReq_misses::cpu0.data 109595 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 12065 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 121660 # number of ReadExReq misses
< system.l2c.ReadCleanReq_misses::cpu0.inst 13405 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu1.inst 1909 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::total 15314 # number of ReadCleanReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 272577 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 1964 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 274541 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.inst 13405 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 382172 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 1909 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 14029 # number of demand (read+write) misses
< system.l2c.demand_misses::total 411515 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 13405 # number of overall misses
< system.l2c.overall_misses::cpu0.data 382172 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 1909 # number of overall misses
< system.l2c.overall_misses::cpu1.data 14029 # number of overall misses
< system.l2c.overall_misses::total 411515 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 332000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 449000 # number of UpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 11349867000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1517430000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 12867297000 # number of ReadExReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1343054000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu1.inst 191509000 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::total 1534563000 # number of ReadCleanReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 22206710000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 230127000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 22436837000 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1343054000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 33556577000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 191509000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1747557000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 36838697000 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1343054000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 33556577000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 191509000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1747557000 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 36838697000 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 822340 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 822340 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackClean_accesses::writebacks 875169 # number of WritebackClean accesses(hits+misses)
< system.l2c.WritebackClean_accesses::total 875169 # number of WritebackClean accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2869 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 1499 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 4368 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 969 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 255583 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 43028 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 298611 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::cpu0.inst 895049 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::cpu1.inst 257442 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::total 1152491 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 994810 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 86012 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 1080822 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 895049 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1250393 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 257442 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 129040 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2531924 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 895049 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1250393 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 257442 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 129040 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2531924 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002091 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003336 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.002518 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.001032 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.428804 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.280399 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.407420 # miss rate for ReadExReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014977 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007415 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::total 0.013288 # miss rate for ReadCleanReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273999 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022834 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.254011 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.014977 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.305642 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.007415 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.108718 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.162531 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.014977 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.305642 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.007415 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.108718 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.162531 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55333.333333 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23400 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 40818.181818 # average UpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103561.905196 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125771.239121 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 105764.400789 # average ReadExReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100190.525923 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 100319.015191 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::total 100206.543033 # average ReadCleanReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81469.493024 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117172.606925 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 81724.904477 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 89519.694300 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 89519.694300 # average overall miss latency
---
> system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses
> system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses
> system.l2c.demand_misses::total 411506 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses
> system.l2c.overall_misses::cpu0.data 382165 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses
> system.l2c.overall_misses::cpu1.data 14030 # number of overall misses
> system.l2c.overall_misses::total 411506 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses)
> system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency
1921,1922c1921,1922
< system.l2c.writebacks::writebacks 82096 # number of writebacks
< system.l2c.writebacks::total 82096 # number of writebacks
---
> system.l2c.writebacks::writebacks 82080 # number of writebacks
> system.l2c.writebacks::total 82080 # number of writebacks
1932,1936c1932,1936
< system.l2c.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
---
> system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses
1939,1957c1939,1957
< system.l2c.ReadExReq_mshr_misses::cpu0.data 109595 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 12065 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 121660 # number of ReadExReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13404 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1892 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::total 15296 # number of ReadCleanReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272577 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1964 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 274541 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 13404 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 382172 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 1892 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 411497 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 13404 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 382172 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 1892 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 411497 # number of overall MSHR misses
---
> system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses
1961,1969c1961,1969
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 13059 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 20254 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 272000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 95500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 367500 # number of UpgradeReq MSHR miss cycles
---
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles
1972,1996c1972,1996
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10253916501 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1396780000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 11650696501 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1208926000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 171260500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::total 1380186500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19486691503 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 210487000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 19697178503 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1208926000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 29740608004 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 171260500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1607267000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 32728061504 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1208926000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 29740608004 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 171260500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1607267000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 32728061504 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469664500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39141500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1508806000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469664500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39141500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 1508806000 # number of overall MSHR uncacheable cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles
1999,2025c1999,2025
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002091 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003336 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.002518 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001032 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428804 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280399 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.407420 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013272 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273999 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022834 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254011 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.162523 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.162523 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19100 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909 # average UpgradeReq mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency
2028,2055c2028,2055
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2059c2059
< system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2061,2067c2061,2067
< system.membus.trans_dist::ReadResp 297167 # Transaction distribution
< system.membus.trans_dist::WriteReq 13059 # Transaction distribution
< system.membus.trans_dist::WriteResp 13059 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution
< system.membus.trans_dist::CleanEvict 263125 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 297263 # Transaction distribution
> system.membus.trans_dist::WriteReq 13067 # Transaction distribution
> system.membus.trans_dist::WriteResp 13067 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution
> system.membus.trans_dist::CleanEvict 263134 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution
2069,2072c2069,2072
< system.membus.trans_dist::ReadExReq 121953 # Transaction distribution
< system.membus.trans_dist::ReadExResp 121548 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution
< system.membus.trans_dist::BadAddressError 44 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 121851 # Transaction distribution
> system.membus.trans_dist::ReadExResp 121443 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution
> system.membus.trans_dist::BadAddressError 45 # Transaction distribution
2074,2077c2074,2078
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::InvalidateResp 134 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes)
2080,2083c2081,2084
< system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes)
2086,2087c2087,2088
< system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 12507 # Total snoops (count)
---
> system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 12662 # Total snoops (count)
2089,2091c2090,2092
< system.membus.snoop_fanout::samples 485548 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 485569 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram
2093,2094c2094,2095
< system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram
< system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram
> system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram
2099,2100c2100,2101
< system.membus.snoop_fanout::total 485548 # Request fanout histogram
< system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 485569 # Request fanout histogram
> system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks)
2102c2103
< system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks)
2104c2105
< system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks)
2106c2107
< system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks)
2108c2109
< system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks)
2110,2115c2111,2116
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2117c2118
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2119,2148c2120,2150
< system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution
< system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution
< system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 382362 # Total snoops (count)
< system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution
> system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution
> system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 382331 # Total snoops (count)
> system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram
2150,2153c2152,2155
< system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram
2158,2159c2160,2161
< system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks)
2161c2163
< system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks)
2163c2165
< system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks)
2165c2167
< system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks)
2167c2169
< system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks)
2169c2171
< system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks)
2171,2174c2173,2176
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2206,2228c2208,2230
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states
2230,2232c2232,2234
< system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl
---
> system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl
2234,2238c2236,2240
< system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl
---
> system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl
2240,2242c2242,2244
< system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl
---
> system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl
2244,2250c2246,2252
< system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl
2254,2255c2256,2257
< system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl
2257c2259
< system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed
---
> system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed
2261c2263
< system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed
---
> system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed
2263,2265c2265,2267
< system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed
< system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed
---
> system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed
> system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed
2268c2270
< system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed
---
> system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed
2270c2272
< system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed
---
> system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed
2273,2274c2275,2276
< system.cpu0.kern.callpal::total 163475 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches
---
> system.cpu0.kern.callpal::total 163481 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches
2280c2282
< system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches
2283,2285c2285,2287
< system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode
2287c2289
< system.cpu0.kern.swap_context 3350 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3352 # number of times the context was actually changed
2289,2306c2291,2308
< system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl
2309,2310c2311,2312
< system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl
2312c2314
< system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed
2315c2317
< system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed
---
> system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed
2318,2322c2320,2324
< system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed
< system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed
< system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed
---
> system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed
> system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed
> system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed
2324c2326
< system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed
---
> system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed
2328,2335c2330,2337
< system.cpu1.kern.callpal::total 54577 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 669 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 888
< system.cpu1.kern.mode_good::user 669
< system.cpu1.kern.mode_good::idle 219
< system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 54607 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 670 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 890
> system.cpu1.kern.mode_good::user 670
> system.cpu1.kern.mode_good::idle 220
> system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches
2337,2342c2339,2344
< system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1229 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1231 # number of times the context was actually changed