7,9c7,9
< host_inst_rate 158135 # Simulator instruction rate (inst/s)
< host_op_rate 158134 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5371969736 # Simulator tick rate (ticks/s)
---
> host_inst_rate 169237 # Simulator instruction rate (inst/s)
> host_op_rate 169237 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5749129790 # Simulator tick rate (ticks/s)
11c11
< host_seconds 359.10 # Real time elapsed on the host
---
> host_seconds 335.54 # Real time elapsed on the host
749,750d748
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
795,798c793,794
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles
825,829c821,822
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency
887,888d879
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
921d911
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1355,1356d1344
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1401,1404c1389,1390
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles
1431,1435c1417,1418
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency
1494,1495d1476
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1528d1508
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1613,1616c1593,1596
< system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
< system.iocache.demand_misses::total 175 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
< system.iocache.overall_misses::total 175 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
> system.iocache.overall_misses::total 41727 # number of overall misses
1621,1624c1601,1604
< system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles
1629,1632c1609,1612
< system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1645,1648c1625,1628
< system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency
1655,1656d1634
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1663,1666c1641,1644
< system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1671,1674c1649,1652
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles
1687,1691c1665,1668
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
1882,1883d1858
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
1959,1964c1934,1936
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2180387500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 660346500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2840734000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3651431000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 690497500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4341928500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles
2020,2026c1992,1994
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency
< host_inst_rate 158135 # Simulator instruction rate (inst/s)
< host_op_rate 158134 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5371969736 # Simulator tick rate (ticks/s)
---
> host_inst_rate 169237 # Simulator instruction rate (inst/s)
> host_op_rate 169237 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5749129790 # Simulator tick rate (ticks/s)
11c11
< host_seconds 359.10 # Real time elapsed on the host
---
> host_seconds 335.54 # Real time elapsed on the host
749,750d748
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
795,798c793,794
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles
825,829c821,822
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency
887,888d879
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
921d911
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1355,1356d1344
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1401,1404c1389,1390
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles
1431,1435c1417,1418
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency
1494,1495d1476
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1528d1508
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1613,1616c1593,1596
< system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
< system.iocache.demand_misses::total 175 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
< system.iocache.overall_misses::total 175 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
> system.iocache.overall_misses::total 41727 # number of overall misses
1621,1624c1601,1604
< system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles
1629,1632c1609,1612
< system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1645,1648c1625,1628
< system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency
1655,1656d1634
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1663,1666c1641,1644
< system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1671,1674c1649,1652
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles
1687,1691c1665,1668
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency
1882,1883d1858
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
1959,1964c1934,1936
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2180387500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 660346500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2840734000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3651431000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 690497500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4341928500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles
2020,2026c1992,1994
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency