3,5c3,5
< sim_seconds 1.907980 # Number of seconds simulated
< sim_ticks 1907980084000 # Number of ticks simulated
< final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.906957 # Number of seconds simulated
> sim_ticks 1906956794000 # Number of ticks simulated
> final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 144634 # Simulator instruction rate (inst/s)
< host_op_rate 144633 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4918211693 # Simulator tick rate (ticks/s)
< host_mem_usage 381420 # Number of bytes of host memory used
< host_seconds 387.94 # Real time elapsed on the host
< sim_insts 56109384 # Number of instructions simulated
< sim_ops 56109384 # Number of ops (including micro ops) simulated
---
> host_inst_rate 101212 # Simulator instruction rate (inst/s)
> host_op_rate 101212 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3411514986 # Simulator tick rate (ticks/s)
> host_mem_usage 375140 # Number of bytes of host memory used
> host_seconds 558.98 # Real time elapsed on the host
> sim_insts 56575230 # Number of instructions simulated
> sim_ops 56575230 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory
21,30c21,30
< system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory
32,38c32,38
< system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s)
40,50c40,50
< system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s)
52,62c52,62
< system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 411682 # Number of read requests accepted
< system.physmem.writeReqs 124264 # Number of write requests accepted
< system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 410454 # Number of read requests accepted
> system.physmem.writeReqs 122837 # Number of write requests accepted
> system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue
64,96c64,96
< system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25908 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25789 # Per bank write bursts
< system.physmem.perBankRdBursts::2 26010 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25614 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25643 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25797 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25922 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25550 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25897 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25701 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25484 # Per bank write bursts
< system.physmem.perBankRdBursts::11 25508 # Per bank write bursts
< system.physmem.perBankRdBursts::12 25696 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25817 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25547 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25690 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7970 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7556 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7711 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7606 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7633 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7951 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7934 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7815 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8060 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8044 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7565 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7446 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7634 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8000 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7754 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7564 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 26161 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25973 # Per bank write bursts
> system.physmem.perBankRdBursts::2 26108 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25765 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25066 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25574 # Per bank write bursts
> system.physmem.perBankRdBursts::6 25905 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25241 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25825 # Per bank write bursts
> system.physmem.perBankRdBursts::9 26325 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25290 # Per bank write bursts
> system.physmem.perBankRdBursts::11 25205 # Per bank write bursts
> system.physmem.perBankRdBursts::12 25472 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25390 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25632 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25396 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8442 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7958 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8052 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7723 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7027 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7199 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7428 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6815 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7536 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7897 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7294 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7366 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7733 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8096 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8387 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7862 # Per bank write bursts
98,99c98,99
< system.physmem.numWrRetry 18 # Number of times write queue was full causing retry
< system.physmem.totGap 1907975777500 # Total gap between requests
---
> system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
> system.physmem.totGap 1906952476500 # Total gap between requests
106c106
< system.physmem.readPktSize::6 411682 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 410454 # Read request sizes (log2)
113,120c113,120
< system.physmem.writePktSize::6 124264 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 122837 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
161,227c161,227
< system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes
231,282c231,265
< system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads
< system.physmem.totQLat 4128600500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads
> system.physmem.totQLat 4043689250 # Total ticks spent queuing
> system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst
284,288c267,271
< system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s
293,311c276,294
< system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing
< system.physmem.readRowHits 370844 # Number of row buffer hits during reads
< system.physmem.writeRowHits 99842 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes
< system.physmem.avgGap 3560014.96 # Average gap between requests
< system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.267627 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states
---
> system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing
> system.physmem.readRowHits 369741 # Number of row buffer hits during reads
> system.physmem.writeRowHits 98545 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes
> system.physmem.avgGap 3575819.72 # Average gap between requests
> system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.251160 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states
313c296
< system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states
315,325c298,308
< system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.276229 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states
---
> system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.278071 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states
327c310
< system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states
329,333c312,316
< system.cpu0.branchPred.lookups 11788808 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 16421216 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits
335,337c318,320
< system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions.
343,344c326,327
< system.cpu0.dtb.read_hits 7021210 # DTB read hits
< system.cpu0.dtb.read_misses 28922 # DTB read misses
---
> system.cpu0.dtb.read_hits 9282981 # DTB read hits
> system.cpu0.dtb.read_misses 32197 # DTB read misses
346,358c329,341
< system.cpu0.dtb.read_accesses 680178 # DTB read accesses
< system.cpu0.dtb.write_hits 4516223 # DTB write hits
< system.cpu0.dtb.write_misses 6969 # DTB write misses
< system.cpu0.dtb.write_acv 383 # DTB write access violations
< system.cpu0.dtb.write_accesses 234540 # DTB write accesses
< system.cpu0.dtb.data_hits 11537433 # DTB hits
< system.cpu0.dtb.data_misses 35891 # DTB misses
< system.cpu0.dtb.data_acv 932 # DTB access violations
< system.cpu0.dtb.data_accesses 914718 # DTB accesses
< system.cpu0.itb.fetch_hits 1192769 # ITB hits
< system.cpu0.itb.fetch_misses 29243 # ITB misses
< system.cpu0.itb.fetch_acv 632 # ITB acv
< system.cpu0.itb.fetch_accesses 1222012 # ITB accesses
---
> system.cpu0.dtb.read_accesses 681404 # DTB read accesses
> system.cpu0.dtb.write_hits 5956980 # DTB write hits
> system.cpu0.dtb.write_misses 7300 # DTB write misses
> system.cpu0.dtb.write_acv 382 # DTB write access violations
> system.cpu0.dtb.write_accesses 235779 # DTB write accesses
> system.cpu0.dtb.data_hits 15239961 # DTB hits
> system.cpu0.dtb.data_misses 39497 # DTB misses
> system.cpu0.dtb.data_acv 931 # DTB access violations
> system.cpu0.dtb.data_accesses 917183 # DTB accesses
> system.cpu0.itb.fetch_hits 1451467 # ITB hits
> system.cpu0.itb.fetch_misses 20802 # ITB misses
> system.cpu0.itb.fetch_acv 603 # ITB acv
> system.cpu0.itb.fetch_accesses 1472269 # ITB accesses
371c354
< system.cpu0.numCycles 94258709 # number of cpu cycles simulated
---
> system.cpu0.numCycles 115722397 # number of cpu cycles simulated
374,389c357,372
< system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total)
391,399c374,382
< system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total)
403,448c386,431
< system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle
450,458c433,441
< system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle
462c445
< system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle
464,494c447,477
< system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available
498,529c481,512
< system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued
531,543c514,526
< system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued
< system.cpu0.iq.rate 0.421350 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued
> system.cpu0.iq.rate 0.455897 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores
545,548c528,531
< system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed
551,552c534,535
< system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked
554,570c537,553
< system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute
572,580c555,563
< system.cpu0.iew.exec_nop 2437996 # number of nop insts executed
< system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 6171265 # Number of branches executed
< system.cpu0.iew.exec_stores 4532745 # Number of stores executed
< system.cpu0.iew.exec_rate 0.417390 # Inst execution rate
< system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 20149850 # num instructions producing a value
< system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 3417639 # number of nop insts executed
> system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 8298030 # Number of branches executed
> system.cpu0.iew.exec_stores 5978029 # Number of stores executed
> system.cpu0.iew.exec_rate 0.451498 # Inst execution rate
> system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 26562977 # num instructions producing a value
> system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value
582,583c565,566
< system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back
585,590c568,573
< system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle
592,600c575,583
< system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle
604,606c587,589
< system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 38919724 # Number of instructions committed
< system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 51918164 # Number of instructions committed
> system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed
608,647c591,630
< system.cpu0.commit.refs 10540382 # Number of memory references committed
< system.cpu0.commit.loads 6202306 # Number of loads committed
< system.cpu0.commit.membars 144405 # Number of memory barriers committed
< system.cpu0.commit.branches 5839773 # Number of branches committed
< system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 471449 # Number of function calls committed.
< system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction
< system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction
---
> system.cpu0.commit.refs 14033539 # Number of memory references committed
> system.cpu0.commit.loads 8292663 # Number of loads committed
> system.cpu0.commit.membars 202804 # Number of memory barriers committed
> system.cpu0.commit.branches 7846921 # Number of branches committed
> system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 666824 # Number of function calls committed.
> system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction
> system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction
649,676c632,659
< system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 132264444 # The number of ROB reads
< system.cpu0.rob.rob_writes 89122078 # The number of ROB writes
< system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 36785489 # Number of Instructions Simulated
< system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads
< system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 898491 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy
---
> system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 166079481 # The number of ROB reads
> system.cpu0.rob.rob_writes 118719518 # The number of ROB writes
> system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 48933669 # Number of Instructions Simulated
> system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads
> system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 1296864 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy
678,679c661,662
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
682,761c665,744
< system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits
< system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses
< system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked
---
> system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits
> system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked
764,841c747,824
< system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks
< system.cpu0.dcache.writebacks::total 426068 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks
> system.cpu0.dcache.writebacks::total 766891 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency
843,851c826,834
< system.cpu0.icache.tags.replacements 615978 # number of replacements
< system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 927295 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy
853,855c836,838
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id
857,895c840,878
< system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits
< system.cpu0.icache.overall_hits::total 5692804 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses
< system.cpu0.icache.overall_misses::total 650065 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked
---
> system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits
> system.cpu0.icache.overall_hits::total 7224199 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses
> system.cpu0.icache.overall_misses::total 974618 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked
897c880
< system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked
899c882
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked
903,932c886,915
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency
934,938c917,921
< system.cpu1.branchPred.lookups 7710185 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3314305 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits
940,942c923,925
< system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions.
947,962c930,945
< system.cpu1.dtb.read_hits 4026297 # DTB read hits
< system.cpu1.dtb.read_misses 14233 # DTB read misses
< system.cpu1.dtb.read_acv 6 # DTB read access violations
< system.cpu1.dtb.read_accesses 293572 # DTB read accesses
< system.cpu1.dtb.write_hits 2497972 # DTB write hits
< system.cpu1.dtb.write_misses 2408 # DTB write misses
< system.cpu1.dtb.write_acv 37 # DTB write access violations
< system.cpu1.dtb.write_accesses 109195 # DTB write accesses
< system.cpu1.dtb.data_hits 6524269 # DTB hits
< system.cpu1.dtb.data_misses 16641 # DTB misses
< system.cpu1.dtb.data_acv 43 # DTB access violations
< system.cpu1.dtb.data_accesses 402767 # DTB accesses
< system.cpu1.itb.fetch_hits 750930 # ITB hits
< system.cpu1.itb.fetch_misses 5383 # ITB misses
< system.cpu1.itb.fetch_acv 53 # ITB acv
< system.cpu1.itb.fetch_accesses 756313 # ITB accesses
---
> system.cpu1.dtb.read_hits 1755656 # DTB read hits
> system.cpu1.dtb.read_misses 9508 # DTB read misses
> system.cpu1.dtb.read_acv 5 # DTB read access violations
> system.cpu1.dtb.read_accesses 286377 # DTB read accesses
> system.cpu1.dtb.write_hits 1073642 # DTB write hits
> system.cpu1.dtb.write_misses 1995 # DTB write misses
> system.cpu1.dtb.write_acv 40 # DTB write access violations
> system.cpu1.dtb.write_accesses 108795 # DTB write accesses
> system.cpu1.dtb.data_hits 2829298 # DTB hits
> system.cpu1.dtb.data_misses 11503 # DTB misses
> system.cpu1.dtb.data_acv 45 # DTB access violations
> system.cpu1.dtb.data_accesses 395172 # DTB accesses
> system.cpu1.itb.fetch_hits 497795 # ITB hits
> system.cpu1.itb.fetch_misses 4809 # ITB misses
> system.cpu1.itb.fetch_acv 84 # ITB acv
> system.cpu1.itb.fetch_accesses 502604 # ITB accesses
975c958
< system.cpu1.numCycles 34369930 # number of cpu cycles simulated
---
> system.cpu1.numCycles 13378620 # number of cpu cycles simulated
978,993c961,975
< system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total)
995,1003c977,985
< system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total)
1007,1052c989,1034
< system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle
1054,1062c1036,1044
< system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle
1066c1048
< system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle
1068,1098c1050,1080
< system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available
1101,1133c1083,1115
< system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued
1135,1147c1117,1129
< system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued
< system.cpu1.iq.rate 0.619251 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued
> system.cpu1.iq.rate 0.628992 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores
1149,1152c1131,1134
< system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed
1155,1156c1137,1138
< system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked
1158,1174c1140,1156
< system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute
1176,1184c1158,1166
< system.cpu1.iew.exec_nop 1431237 # number of nop insts executed
< system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 3322997 # Number of branches executed
< system.cpu1.iew.exec_stores 2508398 # Number of stores executed
< system.cpu1.iew.exec_rate 0.611625 # Inst execution rate
< system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 10210202 # num instructions producing a value
< system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 464508 # number of nop insts executed
> system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1230259 # Number of branches executed
> system.cpu1.iew.exec_stores 1080816 # Number of stores executed
> system.cpu1.iew.exec_rate 0.621067 # Inst execution rate
> system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 3916216 # num instructions producing a value
> system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value
1186,1187c1168,1169
< system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back
1189,1194c1171,1176
< system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle
1196,1204c1178,1186
< system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle
1208,1210c1190,1192
< system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 20524993 # Number of instructions committed
< system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 8020551 # Number of instructions committed
> system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed
1212,1251c1194,1233
< system.cpu1.commit.refs 5937635 # Number of memory references committed
< system.cpu1.commit.loads 3555213 # Number of loads committed
< system.cpu1.commit.membars 92415 # Number of memory barriers committed
< system.cpu1.commit.branches 3082130 # Number of branches committed
< system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 318960 # Number of function calls committed.
< system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction
< system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction
---
> system.cpu1.commit.refs 2563717 # Number of memory references committed
> system.cpu1.commit.loads 1543225 # Number of loads committed
> system.cpu1.commit.membars 37500 # Number of memory barriers committed
> system.cpu1.commit.branches 1142801 # Number of branches committed
> system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 128494 # Number of function calls committed.
> system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction
> system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction
1253,1363c1235,1345
< system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 54833276 # The number of ROB reads
< system.cpu1.rob.rob_writes 48835744 # The number of ROB writes
< system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 19323895 # Number of Instructions Simulated
< system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads
< system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 561653 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits
< system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses
< system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked
---
> system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 21604416 # The number of ROB reads
> system.cpu1.rob.rob_writes 19248787 # The number of ROB writes
> system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 7641561 # Number of Instructions Simulated
> system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads
> system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 88757 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits
> system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses
> system.cpu1.dcache.overall_misses::total 341978 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked
1366,1443c1348,1425
< system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks
< system.cpu1.dcache.writebacks::total 435263 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks
> system.cpu1.dcache.writebacks::total 56462 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency
1445,1495c1427,1477
< system.cpu1.icache.tags.replacements 499853 # number of replacements
< system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
< system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits
< system.cpu1.icache.overall_hits::total 2783351 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses
< system.cpu1.icache.overall_misses::total 520843 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked
---
> system.cpu1.icache.tags.replacements 200477 # number of replacements
> system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
> system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits
> system.cpu1.icache.overall_hits::total 1230816 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses
> system.cpu1.icache.overall_misses::total 208101 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked
1497c1479
< system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked
1499c1481
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked
1503,1532c1485,1514
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency
1546,1551c1528,1533
< system.iobus.trans_dist::ReadReq 7377 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7377 # Transaction distribution
< system.iobus.trans_dist::WriteReq 53912 # Transaction distribution
< system.iobus.trans_dist::WriteResp 53912 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
> system.iobus.trans_dist::WriteReq 54460 # Transaction distribution
> system.iobus.trans_dist::WriteResp 54460 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes)
1557c1539
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1562,1567c1544,1549
< system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes)
1573c1555
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1578,1582c1560,1564
< system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks)
1584c1566
< system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks)
1596c1578
< system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1604c1586
< system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks)
1608c1590
< system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks)
1610c1592
< system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks)
1612,1613c1594,1595
< system.iocache.tags.replacements 41701 # number of replacements
< system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use
---
> system.iocache.tags.replacements 41698 # number of replacements
> system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use
1615c1597
< system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
1617,1620c1599,1602
< system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy
1624,1627c1606,1609
< system.iocache.tags.tag_accesses 375543 # Number of tag accesses
< system.iocache.tags.data_accesses 375543 # Number of data accesses
< system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 375570 # Number of tag accesses
> system.iocache.tags.data_accesses 375570 # Number of data accesses
> system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
1630,1643c1612,1625
< system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
< system.iocache.demand_misses::total 175 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
< system.iocache.overall_misses::total 175 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses
> system.iocache.demand_misses::total 178 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 178 # number of overall misses
> system.iocache.overall_misses::total 178 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
1646,1649c1628,1631
< system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses
1658,1665c1640,1647
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency
1674,1677c1656,1659
< system.iocache.writebacks::writebacks 41526 # number of writebacks
< system.iocache.writebacks::total 41526 # number of writebacks
< system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
---
> system.iocache.writebacks::writebacks 41520 # number of writebacks
> system.iocache.writebacks::total 41520 # number of writebacks
> system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
1680,1691c1662,1673
< system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13318883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13318883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829721346 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2829721346 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 13318883 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 13318883 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 13318883 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 13318883 # number of overall MSHR miss cycles
1700,1707c1682,1689
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 74825.185393 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.725501 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.725501 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74825.185393 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 74825.185393 # average overall mshr miss latency
1709,1888c1691,1870
< system.l2c.tags.replacements 346141 # number of replacements
< system.l2c.tags.tagsinuse 65297.340756 # Cycle average of tags in use
< system.l2c.tags.total_refs 4025883 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 411324 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 9.787620 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 7535768000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 53443.709143 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4213.616295 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 5688.285915 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1375.831057 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 575.898345 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.815486 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.064295 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.086796 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.020994 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.008788 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.996358 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 2225 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 5965 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 6968 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 49797 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 38794162 # Number of tag accesses
< system.l2c.tags.data_accesses 38794162 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 861331 # number of Writeback hits
< system.l2c.Writeback_hits::total 861331 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 36 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 115055 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 78240 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 193295 # number of ReadExReq hits
< system.l2c.ReadCleanReq_hits::cpu0.inst 604919 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::cpu1.inst 496677 # number of ReadCleanReq hits
< system.l2c.ReadCleanReq_hits::total 1101596 # number of ReadCleanReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 403562 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 443803 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 847365 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.inst 604919 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 518617 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 496677 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 522043 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2142256 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 604919 # number of overall hits
< system.l2c.overall_hits::cpu0.data 518617 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 496677 # number of overall hits
< system.l2c.overall_hits::cpu1.data 522043 # number of overall hits
< system.l2c.overall_hits::total 2142256 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 2583 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 538 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3121 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 69 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 169 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 105448 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 17488 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 122936 # number of ReadExReq misses
< system.l2c.ReadCleanReq_misses::cpu0.inst 11627 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::cpu1.inst 3714 # number of ReadCleanReq misses
< system.l2c.ReadCleanReq_misses::total 15341 # number of ReadCleanReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 272098 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 2179 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 274277 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.inst 11627 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 377546 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 3714 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 19667 # number of demand (read+write) misses
< system.l2c.demand_misses::total 412554 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 11627 # number of overall misses
< system.l2c.overall_misses::cpu0.data 377546 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 3714 # number of overall misses
< system.l2c.overall_misses::cpu1.data 19667 # number of overall misses
< system.l2c.overall_misses::total 412554 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1390000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1722000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 3112000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 341500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 556000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 9317536000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1807849000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 11125385000 # number of ReadExReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu0.inst 964295500 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::cpu1.inst 315495500 # number of ReadCleanReq miss cycles
< system.l2c.ReadCleanReq_miss_latency::total 1279791000 # number of ReadCleanReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 19840935500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 172644000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 20013579500 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 964295500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 29158471500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 315495500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1980493000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 32418755500 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 964295500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 29158471500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 315495500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1980493000 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 32418755500 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 861331 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 861331 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2724 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 618 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 3342 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 136 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 243 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 220503 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 95728 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 316231 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::cpu0.inst 616546 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::cpu1.inst 500391 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadCleanReq_accesses::total 1116937 # number of ReadCleanReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 675660 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 445982 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 1121642 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 616546 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 896163 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 500391 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 541710 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2554810 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 616546 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 896163 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 500391 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 541710 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2554810 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948238 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870550 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.933872 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.644860 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735294 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.695473 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.478216 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.182684 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.388754 # miss rate for ReadExReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018858 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007422 # miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_miss_rate::total 0.013735 # miss rate for ReadCleanReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.402714 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.004886 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.244532 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.018858 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.421292 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.007422 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.036305 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.161481 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.018858 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.421292 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.007422 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.036305 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.161481 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 538.133953 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3200.743494 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 997.116309 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4949.275362 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2145 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3289.940828 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88361.429330 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103376.543916 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 90497.372617 # average ReadExReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82935.881999 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84947.630587 # average ReadCleanReq miss latency
< system.l2c.ReadCleanReq_avg_miss_latency::total 83422.918975 # average ReadCleanReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72918.343758 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 79230.839835 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 72968.493530 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 78580.635505 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 78580.635505 # average overall miss latency
---
> system.l2c.tags.replacements 344930 # number of replacements
> system.l2c.tags.tagsinuse 65239.787598 # Cycle average of tags in use
> system.l2c.tags.total_refs 3999339 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 410104 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 9.752012 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 7535462000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 53414.062989 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5366.108277 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6187.949092 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 208.288223 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 63.379017 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.815034 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.081880 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.094421 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.003178 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000967 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.995480 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1024 65174 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 2299 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 6267 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 5773 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 50615 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1024 0.994476 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 38456225 # Number of tag accesses
> system.l2c.tags.data_accesses 38456225 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 823353 # number of Writeback hits
> system.l2c.Writeback_hits::total 823353 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 170 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 230 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 400 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 159888 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 19633 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 179521 # number of ReadExReq hits
> system.l2c.ReadCleanReq_hits::cpu0.inst 914307 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::cpu1.inst 199175 # number of ReadCleanReq hits
> system.l2c.ReadCleanReq_hits::total 1113482 # number of ReadCleanReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 746483 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 59707 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 806190 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.inst 914307 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 906371 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 199175 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 79340 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2099193 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 914307 # number of overall hits
> system.l2c.overall_hits::cpu0.data 906371 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 199175 # number of overall hits
> system.l2c.overall_hits::cpu1.data 79340 # number of overall hits
> system.l2c.overall_hits::total 2099193 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 2738 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1002 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 3740 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 352 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 366 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 718 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 114723 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7302 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 122025 # number of ReadExReq misses
> system.l2c.ReadCleanReq_misses::cpu0.inst 13477 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::cpu1.inst 1849 # number of ReadCleanReq misses
> system.l2c.ReadCleanReq_misses::total 15326 # number of ReadCleanReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 272988 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 841 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 273829 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.inst 13477 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 387711 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1849 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8143 # number of demand (read+write) misses
> system.l2c.demand_misses::total 411180 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13477 # number of overall misses
> system.l2c.overall_misses::cpu0.data 387711 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1849 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8143 # number of overall misses
> system.l2c.overall_misses::total 411180 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1902000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 5314000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 7216000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1240500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 123000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 1363500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 10174433000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 803053000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 10977486000 # number of ReadExReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1122774000 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::cpu1.inst 155099500 # number of ReadCleanReq miss cycles
> system.l2c.ReadCleanReq_miss_latency::total 1277873500 # number of ReadCleanReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 19926572000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 76887500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 20003459500 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1122774000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 30101005000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 155099500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 879940500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 32258819000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1122774000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 30101005000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 155099500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 879940500 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 32258819000 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 823353 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 823353 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2908 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 1232 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 4140 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 401 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 392 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 793 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 274611 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 26935 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 301546 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::cpu0.inst 927784 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::cpu1.inst 201024 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadCleanReq_accesses::total 1128808 # number of ReadCleanReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 1019471 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 60548 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 1080019 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 927784 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1294082 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 201024 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 87483 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2510373 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 927784 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1294082 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 201024 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 87483 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2510373 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941541 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.813312 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.903382 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.877805 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.933673 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.905422 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.417765 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.271097 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.404665 # miss rate for ReadExReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014526 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.009198 # miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_miss_rate::total 0.013577 # miss rate for ReadCleanReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.267774 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.013890 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.253541 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.014526 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.299603 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.009198 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.093081 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.163792 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.014526 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.299603 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.009198 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.093081 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.163792 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 694.667641 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5303.393214 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1929.411765 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3524.147727 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 336.065574 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1899.025070 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88686.950306 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109977.129554 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 89960.958820 # average ReadExReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 83310.380649 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83882.909681 # average ReadCleanReq miss latency
> system.l2c.ReadCleanReq_avg_miss_latency::total 83379.453217 # average ReadCleanReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72994.314768 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91423.900119 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 73050.916813 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 83310.380649 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 77637.737903 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 83882.909681 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 108060.972615 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 78454.251180 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 83310.380649 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 77637.737903 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 83882.909681 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 108060.972615 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 78454.251180 # average overall miss latency
1897,1898c1879,1880
< system.l2c.writebacks::writebacks 82738 # number of writebacks
< system.l2c.writebacks::total 82738 # number of writebacks
---
> system.l2c.writebacks::writebacks 81317 # number of writebacks
> system.l2c.writebacks::total 81317 # number of writebacks
1902,1903d1883
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1906,1907c1886
< system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
---
> system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
1910,1981c1889,1959
< system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 356 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 356 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2583 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 538 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3121 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 69 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 169 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 105448 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 17488 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 122936 # number of ReadExReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 11626 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 3697 # number of ReadCleanReq MSHR misses
< system.l2c.ReadCleanReq_mshr_misses::total 15323 # number of ReadCleanReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272098 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2178 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 274276 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 11626 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 377546 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 3697 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 19666 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 412535 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 11626 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 377546 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 3697 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 19666 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 412535 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 7202 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 12360 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 19562 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 53861495 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11082500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 64943995 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1433500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2068000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 3501500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8263056000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1632969000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 9896025000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 847954500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 277279000 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadCleanReq_mshr_miss_latency::total 1125233500 # number of ReadCleanReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17126346500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 197172000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 17323518500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 847954500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 25389402500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 277279000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1830141000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 28344777000 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 847954500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 25389402500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 277279000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1830141000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 28344777000 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 953578000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 469134500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1422712500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1615175500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 905955000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2521130500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2568753500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1375089500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 3943843000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 353 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 353 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2738 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1002 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 3740 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 352 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 366 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 718 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 114723 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7302 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 122025 # number of ReadExReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13476 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1832 # number of ReadCleanReq MSHR misses
> system.l2c.ReadCleanReq_mshr_misses::total 15308 # number of ReadCleanReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272988 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 841 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 273829 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13476 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 387711 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1832 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8143 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 411162 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13476 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 387711 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1832 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8143 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 411162 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 12908 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 20101 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 57077500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 20724000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 77801500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7323000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7608000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 14931000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9027203000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 730033000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9757236000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 987919000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 135556000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadCleanReq_mshr_miss_latency::total 1123475000 # number of ReadCleanReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17205778500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68477500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 17274256000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 987919000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 26232981500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 135556000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 798510500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 28154967000 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 987919000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 26232981500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 135556000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 798510500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 28154967000 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1392804000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27752000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1420556000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2037629000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 601171500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2638800500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3430433000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 628923500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4059356500 # number of overall MSHR uncacheable cycles
1984,2042c1962,2020
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948238 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870550 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.933872 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644860 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735294 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.695473 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.478216 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.182684 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.388754 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013719 # mshr miss rate for ReadCleanReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.402714 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.004884 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244531 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.161474 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.161474 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20680 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617 # average ReadExReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average ReadCleanReq mshr miss latency
< system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799 # average ReadCleanReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941541 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813312 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.903382 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.877805 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.933673 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905422 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.417765 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271097 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.404665 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013561 # mshr miss rate for ReadCleanReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267774 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.013890 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253541 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.163785 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.163785 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20846.420745 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20682.634731 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.540107 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.977273 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.885246 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20795.264624 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78686.950306 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99977.129554 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 79960.958820 # average ReadExReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average ReadCleanReq mshr miss latency
> system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73391.363993 # average ReadCleanReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63027.600114 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81423.900119 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63084.099931 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197982.089552 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175645.569620 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197491.450021 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203275.039904 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208450.589459 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204431.399132 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201092.268011 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 206746.712689 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 201947.987662 # average overall mshr uncacheable latency
2044,2056c2022,2034
< system.membus.trans_dist::ReadReq 7202 # Transaction distribution
< system.membus.trans_dist::ReadResp 296546 # Transaction distribution
< system.membus.trans_dist::WriteReq 12360 # Transaction distribution
< system.membus.trans_dist::WriteResp 12360 # Transaction distribution
< system.membus.trans_dist::Writeback 124264 # Transaction distribution
< system.membus.trans_dist::CleanEvict 262871 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution
< system.membus.trans_dist::ReadExReq 122900 # Transaction distribution
< system.membus.trans_dist::ReadExResp 122774 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution
< system.membus.trans_dist::BadAddressError 430 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 7193 # Transaction distribution
> system.membus.trans_dist::ReadResp 296434 # Transaction distribution
> system.membus.trans_dist::WriteReq 12908 # Transaction distribution
> system.membus.trans_dist::WriteResp 12908 # Transaction distribution
> system.membus.trans_dist::Writeback 122837 # Transaction distribution
> system.membus.trans_dist::CleanEvict 263082 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution
> system.membus.trans_dist::ReadExReq 122000 # Transaction distribution
> system.membus.trans_dist::ReadExResp 121659 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution
> system.membus.trans_dist::BadAddressError 74 # Transaction distribution
2059,2073c2037,2051
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 3872 # Total snoops (count)
< system.membus.snoop_fanout::samples 867863 # Request fanout histogram
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 10191 # Total snoops (count)
> system.membus.snoop_fanout::samples 873294 # Request fanout histogram
2078c2056
< system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram
2083,2084c2061,2062
< system.membus.snoop_fanout::total 867863 # Request fanout histogram
< system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 873294 # Request fanout histogram
> system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks)
2086c2064
< system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks)
2088c2066
< system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks)
2090c2068
< system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks)
2092c2070
< system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks)
2094,2107c2072,2085
< system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution
< system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution
< system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution
---
> system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution
> system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution
> system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution
2109,2122c2087,2100
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 464381 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 458492 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram
2127,2128c2105,2106
< system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram
< system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram
2132,2133c2110,2111
< system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks)
2135c2113
< system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
2137,2139c2115,2117
< system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks)
2141c2119
< system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks)
2143c2121
< system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks)
2177,2197c2155,2175
< system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl
2201,2202c2179,2180
< system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl
2234,2252c2212,2230
< system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed
< system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed
< system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed
< system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed
< system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 124254 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches
---
> system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed
> system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed
> system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed
> system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed
> system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 172559 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches
2254,2255c2232,2233
< system.cpu0.kern.mode_good::kernel 1341
< system.cpu0.kern.mode_good::user 1342
---
> system.cpu0.kern.mode_good::kernel 1342
> system.cpu0.kern.mode_good::user 1343
2257c2235
< system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches
2260,2262c2238,2240
< system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode
2264c2242
< system.cpu0.kern.swap_context 2294 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3604 # number of times the context was actually changed
2266,2283c2244,2261
< system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl
2286,2287c2264,2265
< system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl
2303,2316c2281,2294
< system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed
< system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed
< system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed
< system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed
< system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed
> system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed
> system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed
> system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed
> system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
2318,2319c2296,2297
< system.cpu1.kern.callpal::total 92064 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches
---
> system.cpu1.kern.callpal::total 45176 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches
2321,2322c2299,2300
< system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 461
---
> system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 568
2324,2325c2302,2303
< system.cpu1.kern.mode_good::idle 66
< system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches
---
> system.cpu1.kern.mode_good::idle 173
> system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches
2327,2332c2305,2310
< system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1950 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 912 # number of times the context was actually changed