3,5c3,5
< sim_seconds 1.901175 # Number of seconds simulated
< sim_ticks 1901175003500 # Number of ticks simulated
< final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.904438 # Number of seconds simulated
> sim_ticks 1904437574000 # Number of ticks simulated
> final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 154934 # Simulator instruction rate (inst/s)
< host_op_rate 154934 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5197600055 # Simulator tick rate (ticks/s)
< host_mem_usage 378544 # Number of bytes of host memory used
< host_seconds 365.78 # Real time elapsed on the host
< sim_insts 56671579 # Number of instructions simulated
< sim_ops 56671579 # Number of ops (including micro ops) simulated
---
> host_inst_rate 150033 # Simulator instruction rate (inst/s)
> host_op_rate 150033 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5049661741 # Simulator tick rate (ticks/s)
> host_mem_usage 379720 # Number of bytes of host memory used
> host_seconds 377.14 # Real time elapsed on the host
> sim_insts 56583768 # Number of instructions simulated
> sim_ops 56583768 # Number of ops (including micro ops) simulated
16,19c16,19
< system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory
21,30c21,30
< system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory
32,96c32,96
< system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 410534 # Number of read requests accepted
< system.physmem.writeReqs 164756 # Number of write requests accepted
< system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue
< system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25742 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25822 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25939 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25643 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25873 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25657 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25709 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25201 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25222 # Per bank write bursts
< system.physmem.perBankRdBursts::9 26115 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25677 # Per bank write bursts
< system.physmem.perBankRdBursts::11 25575 # Per bank write bursts
< system.physmem.perBankRdBursts::12 25800 # Per bank write bursts
< system.physmem.perBankRdBursts::13 26085 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25301 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25075 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10194 # Per bank write bursts
< system.physmem.perBankWrBursts::1 10103 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10030 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9736 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9490 # Per bank write bursts
< system.physmem.perBankWrBursts::5 10167 # Per bank write bursts
< system.physmem.perBankWrBursts::6 10200 # Per bank write bursts
< system.physmem.perBankWrBursts::7 9338 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9741 # Per bank write bursts
< system.physmem.perBankWrBursts::9 10459 # Per bank write bursts
< system.physmem.perBankWrBursts::10 10157 # Per bank write bursts
< system.physmem.perBankWrBursts::11 10688 # Per bank write bursts
< system.physmem.perBankWrBursts::12 11170 # Per bank write bursts
< system.physmem.perBankWrBursts::13 11200 # Per bank write bursts
< system.physmem.perBankWrBursts::14 10147 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9577 # Per bank write bursts
---
> system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 412410 # Number of read requests accepted
> system.physmem.writeReqs 166296 # Number of write requests accepted
> system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25681 # Per bank write bursts
> system.physmem.perBankRdBursts::1 26031 # Per bank write bursts
> system.physmem.perBankRdBursts::2 26262 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25929 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25778 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25597 # Per bank write bursts
> system.physmem.perBankRdBursts::6 26273 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25295 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25970 # Per bank write bursts
> system.physmem.perBankRdBursts::9 26150 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25721 # Per bank write bursts
> system.physmem.perBankRdBursts::11 25208 # Per bank write bursts
> system.physmem.perBankRdBursts::12 25640 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25768 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25547 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25457 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9358 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9077 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9200 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8756 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8419 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8251 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9072 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8046 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8692 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8978 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8574 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8968 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8555 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9260 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8896 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8762 # Per bank write bursts
98,99c98,99
< system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
< system.physmem.totGap 1901170614000 # Total gap between requests
---
> system.physmem.numWrRetry 50 # Number of times write queue was full causing retry
> system.physmem.totGap 1904433039500 # Total gap between requests
106c106
< system.physmem.readPktSize::6 410534 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 412410 # Read request sizes (log2)
113,120c113,120
< system.physmem.writePktSize::6 164756 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 166296 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
161,228c161,228
< system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
231,271c231,278
< system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads
< system.physmem.totQLat 3885054500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads
> system.physmem.totQLat 4111304500 # Total ticks spent queuing
> system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst
273,277c280,284
< system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s
282,300c289,307
< system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing
< system.physmem.readRowHits 370181 # Number of row buffer hits during reads
< system.physmem.writeRowHits 135448 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes
< system.physmem.avgGap 3304716.95 # Average gap between requests
< system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.322456 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states
---
> system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing
> system.physmem.readRowHits 371693 # Number of row buffer hits during reads
> system.physmem.writeRowHits 115102 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes
> system.physmem.avgGap 3290847.23 # Average gap between requests
> system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.325620 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states
> system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states
302c309
< system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states
304,314c311,321
< system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.329412 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states
---
> system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.317995 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states
> system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states
316c323
< system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states
318,322c325,329
< system.cpu0.branchPred.lookups 16131633 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 16050181 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits
324,326c331,333
< system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions.
332,347c339,354
< system.cpu0.dtb.read_hits 9231009 # DTB read hits
< system.cpu0.dtb.read_misses 34580 # DTB read misses
< system.cpu0.dtb.read_acv 535 # DTB read access violations
< system.cpu0.dtb.read_accesses 687791 # DTB read accesses
< system.cpu0.dtb.write_hits 5940395 # DTB write hits
< system.cpu0.dtb.write_misses 7538 # DTB write misses
< system.cpu0.dtb.write_acv 382 # DTB write access violations
< system.cpu0.dtb.write_accesses 237219 # DTB write accesses
< system.cpu0.dtb.data_hits 15171404 # DTB hits
< system.cpu0.dtb.data_misses 42118 # DTB misses
< system.cpu0.dtb.data_acv 917 # DTB access violations
< system.cpu0.dtb.data_accesses 925010 # DTB accesses
< system.cpu0.itb.fetch_hits 1435355 # ITB hits
< system.cpu0.itb.fetch_misses 29386 # ITB misses
< system.cpu0.itb.fetch_acv 625 # ITB acv
< system.cpu0.itb.fetch_accesses 1464741 # ITB accesses
---
> system.cpu0.dtb.read_hits 9185685 # DTB read hits
> system.cpu0.dtb.read_misses 31794 # DTB read misses
> system.cpu0.dtb.read_acv 464 # DTB read access violations
> system.cpu0.dtb.read_accesses 674724 # DTB read accesses
> system.cpu0.dtb.write_hits 5856177 # DTB write hits
> system.cpu0.dtb.write_misses 6642 # DTB write misses
> system.cpu0.dtb.write_acv 308 # DTB write access violations
> system.cpu0.dtb.write_accesses 220970 # DTB write accesses
> system.cpu0.dtb.data_hits 15041862 # DTB hits
> system.cpu0.dtb.data_misses 38436 # DTB misses
> system.cpu0.dtb.data_acv 772 # DTB access violations
> system.cpu0.dtb.data_accesses 895694 # DTB accesses
> system.cpu0.itb.fetch_hits 1413849 # ITB hits
> system.cpu0.itb.fetch_misses 27924 # ITB misses
> system.cpu0.itb.fetch_acv 522 # ITB acv
> system.cpu0.itb.fetch_accesses 1441773 # ITB accesses
360c367
< system.cpu0.numCycles 112944275 # number of cpu cycles simulated
---
> system.cpu0.numCycles 115311619 # number of cpu cycles simulated
363,378c370,386
< system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total)
380,388c388,396
< system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total)
392,437c400,445
< system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename
< system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename
> system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle
439,447c447,455
< system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle
451c459
< system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle
453,483c461,491
< system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available
486,518c494,526
< system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued
< system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued
> system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued
520,532c528,540
< system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued
< system.cpu0.iq.rate 0.465714 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued
> system.cpu0.iq.rate 0.453068 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores
534,537c542,545
< system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed
540,541c548,549
< system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked
543,559c551,567
< system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ
< system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch
< system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ
> system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch
> system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute
561,569c569,577
< system.cpu0.iew.exec_nop 3408998 # number of nop insts executed
< system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 8273174 # Number of branches executed
< system.cpu0.iew.exec_stores 5961648 # Number of stores executed
< system.cpu0.iew.exec_rate 0.461213 # Inst execution rate
< system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 26436063 # num instructions producing a value
< system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 3391780 # number of nop insts executed
> system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 8225133 # Number of branches executed
> system.cpu0.iew.exec_stores 5876205 # Number of stores executed
> system.cpu0.iew.exec_rate 0.448685 # Inst execution rate
> system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 26435135 # num instructions producing a value
> system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value
571,572c579,580
< system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back
574,579c582,587
< system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle
581,589c589,597
< system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle
593,595c601,603
< system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 51697359 # Number of instructions committed
< system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 51332073 # Number of instructions committed
> system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed
597,636c605,644
< system.cpu0.commit.refs 13959169 # Number of memory references committed
< system.cpu0.commit.loads 8256071 # Number of loads committed
< system.cpu0.commit.membars 200989 # Number of memory barriers committed
< system.cpu0.commit.branches 7816314 # Number of branches committed
< system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 663768 # Number of function calls committed.
< system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction
< system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction
---
> system.cpu0.commit.refs 13832347 # Number of memory references committed
> system.cpu0.commit.loads 8208434 # Number of loads committed
> system.cpu0.commit.membars 200823 # Number of memory barriers committed
> system.cpu0.commit.branches 7767218 # Number of branches committed
> system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 660195 # Number of function calls committed.
> system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction
> system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction
638,639c646,647
< system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached
---
> system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached
641,748c649,754
< system.cpu0.rob.rob_reads 163161097 # The number of ROB reads
< system.cpu0.rob.rob_writes 118660594 # The number of ROB writes
< system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 48729536 # Number of Instructions Simulated
< system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads
< system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes
< system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 1291740 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits
< system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses
< system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked
---
> system.cpu0.rob.rob_reads 165216916 # The number of ROB reads
> system.cpu0.rob.rob_writes 117798939 # The number of ROB writes
> system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 48375955 # Number of Instructions Simulated
> system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads
> system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes
> system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 1283357 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits
> system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses
> system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked
750,751c756,757
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked
---
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked
754,819c760,825
< system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks
< system.cpu0.dcache.writebacks::total 762456 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks
> system.cpu0.dcache.writebacks::total 752753 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
827,879c833,883
< system.cpu0.icache.tags.replacements 914535 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.589702 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 7236389 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 915045 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 7.908233 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 26485919250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.589702 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995292 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.995292 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id
< system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
< system.cpu0.icache.tags.tag_accesses 9110810 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 9110810 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 7236389 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 7236389 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 7236389 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 7236389 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 7236389 # number of overall hits
< system.cpu0.icache.overall_hits::total 7236389 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 959193 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 959193 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 959193 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 959193 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 959193 # number of overall misses
< system.cpu0.icache.overall_misses::total 959193 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13598697683 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 13598697683 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 13598697683 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 13598697683 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 13598697683 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 13598697683 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 8195582 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 8195582 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked
---
> system.cpu0.icache.tags.replacements 911417 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
> system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits
> system.cpu0.icache.overall_hits::total 7153262 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses
> system.cpu0.icache.overall_misses::total 957376 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked
881c885
< system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked
---
> system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked
883c887
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.177665 # average number of cycles each access was blocked
---
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked
887,916c891,920
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency
918,922c922,926
< system.cpu1.branchPred.lookups 3410499 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 3445639 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits
924,926c928,930
< system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions.
931,946c935,950
< system.cpu1.dtb.read_hits 1800297 # DTB read hits
< system.cpu1.dtb.read_misses 9623 # DTB read misses
< system.cpu1.dtb.read_acv 4 # DTB read access violations
< system.cpu1.dtb.read_accesses 290908 # DTB read accesses
< system.cpu1.dtb.write_hits 1120103 # DTB write hits
< system.cpu1.dtb.write_misses 2035 # DTB write misses
< system.cpu1.dtb.write_acv 37 # DTB write access violations
< system.cpu1.dtb.write_accesses 109629 # DTB write accesses
< system.cpu1.dtb.data_hits 2920400 # DTB hits
< system.cpu1.dtb.data_misses 11658 # DTB misses
< system.cpu1.dtb.data_acv 41 # DTB access violations
< system.cpu1.dtb.data_accesses 400537 # DTB accesses
< system.cpu1.itb.fetch_hits 513208 # ITB hits
< system.cpu1.itb.fetch_misses 5417 # ITB misses
< system.cpu1.itb.fetch_acv 59 # ITB acv
< system.cpu1.itb.fetch_accesses 518625 # ITB accesses
---
> system.cpu1.dtb.read_hits 1858276 # DTB read hits
> system.cpu1.dtb.read_misses 10905 # DTB read misses
> system.cpu1.dtb.read_acv 64 # DTB read access violations
> system.cpu1.dtb.read_accesses 300263 # DTB read accesses
> system.cpu1.dtb.write_hits 1193771 # DTB write hits
> system.cpu1.dtb.write_misses 2902 # DTB write misses
> system.cpu1.dtb.write_acv 104 # DTB write access violations
> system.cpu1.dtb.write_accesses 125157 # DTB write accesses
> system.cpu1.dtb.data_hits 3052047 # DTB hits
> system.cpu1.dtb.data_misses 13807 # DTB misses
> system.cpu1.dtb.data_acv 168 # DTB access violations
> system.cpu1.dtb.data_accesses 425420 # DTB accesses
> system.cpu1.itb.fetch_hits 529068 # ITB hits
> system.cpu1.itb.fetch_misses 7485 # ITB misses
> system.cpu1.itb.fetch_acv 158 # ITB acv
> system.cpu1.itb.fetch_accesses 536553 # ITB accesses
959c963
< system.cpu1.numCycles 13834996 # number of cpu cycles simulated
---
> system.cpu1.numCycles 14296923 # number of cpu cycles simulated
962,976c966,982
< system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total)
978,986c984,992
< system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total)
990,1035c996,1041
< system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename
< system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename
> system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle
1037,1045c1043,1051
< system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle
1049c1055
< system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle
1051,1081c1057,1087
< system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available
1084,1116c1090,1122
< system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued
< system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued
> system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued
1118,1130c1124,1136
< system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued
< system.cpu1.iq.rate 0.630763 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued
> system.cpu1.iq.rate 0.633233 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores
1132,1135c1138,1141
< system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed
1138,1139c1144,1145
< system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked
1141,1157c1147,1163
< system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ
< system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch
< system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ
> system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch
> system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute
1159,1167c1165,1173
< system.cpu1.iew.exec_nop 494140 # number of nop insts executed
< system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 1279494 # Number of branches executed
< system.cpu1.iew.exec_stores 1127581 # Number of stores executed
< system.cpu1.iew.exec_rate 0.622051 # Inst execution rate
< system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 4051784 # num instructions producing a value
< system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 503606 # number of nop insts executed
> system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 1318456 # Number of branches executed
> system.cpu1.iew.exec_stores 1202277 # Number of stores executed
> system.cpu1.iew.exec_rate 0.624860 # Inst execution rate
> system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 4148200 # num instructions producing a value
> system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value
1169,1170c1175,1176
< system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back
1172,1177c1178,1183
< system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle
1179,1187c1185,1193
< system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle
1191,1193c1197,1199
< system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 8342954 # Number of instructions committed
< system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 8615735 # Number of instructions committed
> system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed
1195,1234c1201,1240
< system.cpu1.commit.refs 2660112 # Number of memory references committed
< system.cpu1.commit.loads 1593766 # Number of loads committed
< system.cpu1.commit.membars 39768 # Number of memory barriers committed
< system.cpu1.commit.branches 1189273 # Number of branches committed
< system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 132492 # Number of function calls committed.
< system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction
< system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction
---
> system.cpu1.commit.refs 2763276 # Number of memory references committed
> system.cpu1.commit.loads 1626761 # Number of loads committed
> system.cpu1.commit.membars 39485 # Number of memory barriers committed
> system.cpu1.commit.branches 1225974 # Number of branches committed
> system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 135018 # Number of function calls committed.
> system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction
> system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction
1236,1237c1242,1243
< system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached
---
> system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached
1239,1347c1245,1355
< system.cpu1.rob.rob_reads 22401053 # The number of ROB reads
< system.cpu1.rob.rob_writes 19972727 # The number of ROB writes
< system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 7942043 # Number of Instructions Simulated
< system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads
< system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes
< system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 93396 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits
< system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses
< system.cpu1.dcache.overall_misses::total 362184 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked
---
> system.cpu1.rob.rob_reads 23176968 # The number of ROB reads
> system.cpu1.rob.rob_writes 20704388 # The number of ROB writes
> system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 8207813 # Number of Instructions Simulated
> system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads
> system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes
> system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 102439 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits
> system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses
> system.cpu1.dcache.overall_misses::total 425658 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked
1350,1415c1358,1423
< system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks
< system.cpu1.dcache.writebacks::total 60059 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks
> system.cpu1.dcache.writebacks::total 70134 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
1423,1474c1431,1484
< system.cpu1.icache.tags.replacements 205003 # number of replacements
< system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
< system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits
< system.cpu1.icache.overall_hits::total 1269898 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses
< system.cpu1.icache.overall_misses::total 212310 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked
---
> system.cpu1.icache.tags.replacements 211356 # number of replacements
> system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
> system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
> system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits
> system.cpu1.icache.overall_hits::total 1331062 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses
> system.cpu1.icache.overall_misses::total 219986 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked
1476c1486
< system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked
---
> system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked
1478c1488
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked
---
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked
1482,1511c1492,1521
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency
1525,1528c1535,1538
< system.iobus.trans_dist::ReadReq 7377 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7377 # Transaction distribution
< system.iobus.trans_dist::WriteReq 54536 # Transaction distribution
< system.iobus.trans_dist::WriteResp 12984 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 7375 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7375 # Transaction distribution
> system.iobus.trans_dist::WriteReq 54477 # Transaction distribution
> system.iobus.trans_dist::WriteResp 12925 # Transaction distribution
1530,1531c1540,1541
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
1534,1535c1544,1545
< system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes)
1537c1547
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
1542,1547c1552,1557
< system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
1550,1551c1560,1561
< system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes)
1553c1563
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
1558,1562c1568,1572
< system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks)
1564c1574
< system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
1570c1580
< system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks)
1572c1582
< system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks)
1576c1586
< system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
1584c1594
< system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks)
1588c1598
< system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks)
1590c1600
< system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks)
1592,1593c1602,1603
< system.iocache.tags.replacements 41701 # number of replacements
< system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use
---
> system.iocache.tags.replacements 41698 # number of replacements
> system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use
1595c1605
< system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
1597,1600c1607,1610
< system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy
1604,1607c1614,1617
< system.iocache.tags.tag_accesses 375597 # Number of tag accesses
< system.iocache.tags.data_accesses 375597 # Number of data accesses
< system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 181 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 375570 # Number of tag accesses
> system.iocache.tags.data_accesses 375570 # Number of data accesses
> system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
1610,1623c1620,1633
< system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses
< system.iocache.demand_misses::total 181 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 181 # number of overall misses
< system.iocache.overall_misses::total 181 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses
> system.iocache.demand_misses::total 178 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 178 # number of overall misses
> system.iocache.overall_misses::total 178 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
1626,1629c1636,1639
< system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses
1638,1646c1648,1656
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked
1648c1658
< system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked
1650c1660
< system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked
1656,1657c1666,1667
< system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
1660,1671c1670,1681
< system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles
1680,1687c1690,1697
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency
1689,1862c1699,1872
< system.l2c.tags.replacements 345072 # number of replacements
< system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use
< system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 27343076 # Number of tag accesses
< system.l2c.tags.data_accesses 27343076 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits
< system.l2c.Writeback_hits::total 822515 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 204045 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 84090 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2090069 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 901250 # number of overall hits
< system.l2c.overall_hits::cpu0.data 900684 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 204045 # number of overall hits
< system.l2c.overall_hits::cpu1.data 84090 # number of overall hits
< system.l2c.overall_hits::total 2090069 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 13855 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 273150 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 1501 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 784 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 289290 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2701 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1143 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3844 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 381 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 797 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 114840 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 7053 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 121893 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 13855 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 387990 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 1501 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 7837 # number of demand (read+write) misses
< system.l2c.demand_misses::total 411183 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 13855 # number of overall misses
< system.l2c.overall_misses::cpu0.data 387990 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 1501 # number of overall misses
< system.l2c.overall_misses::cpu1.data 7837 # number of overall misses
< system.l2c.overall_misses::total 411183 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 1053790500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17926629500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 116949250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 69771500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 19167140750 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1289954 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 4510297 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 5800251 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 801966 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70497 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 872463 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 9554653251 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 752768967 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 10307422218 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1053790500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 27481282751 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 116949250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 822540467 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 29474562968 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1053790500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 27481282751 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 116949250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 822540467 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 29474562968 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 915105 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 1016244 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 205546 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 63647 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2200542 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 822515 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 822515 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 1379 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 4254 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 431 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 444 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 875 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 272430 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 28280 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 300710 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 915105 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1288674 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 205546 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 91927 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2501252 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 915105 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1288674 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 205546 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 91927 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2501252 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.015140 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.268784 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.007303 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.012318 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.131463 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939478 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828861 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.903620 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.883991 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.936937 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.910857 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.421539 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.249399 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.405351 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.015140 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.301077 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.007303 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.085252 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.164391 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.015140 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.301077 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.007303 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.085252 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.164391 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76058.498737 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 65629.249497 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77914.223851 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 88994.260204 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 66255.801272 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 477.583858 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3946.016623 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1508.910250 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.897638 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 169.463942 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1094.683814 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83199.697414 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106730.322841 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 84561.231720 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 71682.348171 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 71682.348171 # average overall miss latency
---
> system.l2c.tags.replacements 346915 # number of replacements
> system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use
> system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 27379617 # Number of tag accesses
> system.l2c.tags.data_accesses 27379617 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits
> system.l2c.Writeback_hits::total 822887 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits
> system.l2c.overall_hits::cpu0.data 894803 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits
> system.l2c.overall_hits::cpu1.data 89043 # number of overall hits
> system.l2c.overall_hits::total 2092259 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 13731 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 273058 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 1686 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 819 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 289294 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2683 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1043 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 3726 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 349 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 386 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 735 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 112818 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 10944 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 123762 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 13731 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 385876 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 1686 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 11763 # number of demand (read+write) misses
> system.l2c.demand_misses::total 413056 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13731 # number of overall misses
> system.l2c.overall_misses::cpu0.data 385876 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 1686 # number of overall misses
> system.l2c.overall_misses::cpu1.data 11763 # number of overall misses
> system.l2c.overall_misses::total 413056 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 1146699750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 19948507750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 143666750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 75193250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 21314067500 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1596458 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 5835814 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 7432272 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1194963 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187494 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 1382457 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 9983790515 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1229173205 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 11212963720 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1146699750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 29932298265 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 143666750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1304366455 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 32527031220 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1146699750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 29932298265 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 143666750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1304366455 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 32527031220 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 911946 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 1015529 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 211884 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 64746 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2204105 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 822887 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 822887 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2859 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 1289 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 4148 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 402 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 416 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 818 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 265150 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 36060 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 301210 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 911946 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1280679 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 211884 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 100806 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2505315 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 911946 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1280679 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 211884 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 100806 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2505315 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.015057 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.268883 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.007957 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.012649 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.131252 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938440 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809154 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.898264 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.868159 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.927885 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.898533 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.425487 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.303494 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.410883 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.015057 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.301306 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.007957 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.116689 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.164872 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.015057 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.301306 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.007957 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.116689 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.164872 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 91811.050061 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 73676.147794 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 595.027208 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5595.219559 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1994.705314 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3423.962751 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 485.735751 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1880.893878 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88494.659673 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112314.803088 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 90601.022285 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 78747.267247 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 78747.267247 # average overall miss latency
1871,1989c1881,1999
< system.l2c.writebacks::writebacks 81684 # number of writebacks
< system.l2c.writebacks::total 81684 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits
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< system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.inst 13842 # number of ReadReq MSHR misses
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< system.l2c.ReadReq_mshr_misses::total 289272 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2701 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1143 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3844 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 381 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 416 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 797 # number of SCUpgradeReq MSHR misses
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< system.l2c.ReadExReq_mshr_misses::total 121893 # number of ReadExReq MSHR misses
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< system.l2c.overall_mshr_misses::cpu0.inst 13842 # number of overall MSHR misses
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< system.l2c.overall_mshr_misses::cpu1.inst 1497 # number of overall MSHR misses
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< system.l2c.overall_mshr_misses::total 411165 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 878413500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14522738500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 97828500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 60106500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 15559087000 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27191193 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11450632 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 38641825 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3833377 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4164911 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 7998288 # number of SCUpgradeReq MSHR miss cycles
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< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 665986031 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 8819400778 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 878413500 # number of demand (read+write) MSHR miss cycles
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< system.l2c.demand_mshr_miss_latency::cpu1.inst 97828500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 726092531 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 24378487778 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 878413500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 22676153247 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 97828500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 726092531 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 24378487778 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366462500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23156500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1389619000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2015759500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 582978000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2598737500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3382222000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606134500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 3988356500 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268783 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012318 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.131455 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939478 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828861 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.903620 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.883991 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.936937 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.910857 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421539 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249399 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.405351 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.164384 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency
---
> system.l2c.writebacks::writebacks 83224 # number of writebacks
> system.l2c.writebacks::total 83224 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.inst 13722 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 273058 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 1677 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 818 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 289275 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2683 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1043 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 3726 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 349 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 386 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 735 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 112818 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 10944 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 123762 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13722 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 385876 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6218348 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6847885 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 13066233 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8604034485 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1094197795 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9698232280 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 974652500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 25149140735 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 122062750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1159320045 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 27405176030 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 974652500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 25149140735 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 122062750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1159320045 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 27405176030 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1365620000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
2000,2004c2010,2014
< system.membus.trans_dist::ReadReq 296649 # Transaction distribution
< system.membus.trans_dist::ReadResp 296568 # Transaction distribution
< system.membus.trans_dist::WriteReq 12984 # Transaction distribution
< system.membus.trans_dist::WriteResp 12984 # Transaction distribution
< system.membus.trans_dist::Writeback 123204 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 296650 # Transaction distribution
> system.membus.trans_dist::ReadResp 296572 # Transaction distribution
> system.membus.trans_dist::WriteReq 12925 # Transaction distribution
> system.membus.trans_dist::WriteResp 12925 # Transaction distribution
> system.membus.trans_dist::Writeback 124744 # Transaction distribution
2007,2022c2017,2032
< system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution
< system.membus.trans_dist::ReadExReq 121989 # Transaction distribution
< system.membus.trans_dist::ReadExResp 121610 # Transaction distribution
< system.membus.trans_dist::BadAddressError 81 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution
> system.membus.trans_dist::ReadExReq 123808 # Transaction distribution
> system.membus.trans_dist::ReadExResp 123481 # Transaction distribution
> system.membus.trans_dist::BadAddressError 78 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes)
2025,2027c2035,2037
< system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 10884 # Total snoops (count)
< system.membus.snoop_fanout::samples 591178 # Request fanout histogram
---
> system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 10437 # Total snoops (count)
> system.membus.snoop_fanout::samples 594010 # Request fanout histogram
2032c2042
< system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram
2037,2038c2047,2048
< system.membus.snoop_fanout::total 591178 # Request fanout histogram
< system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 594010 # Request fanout histogram
> system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks)
2040c2050
< system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks)
2044,2046c2054,2056
< system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks)
2048,2073c2058,2083
< system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution
< system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 73699 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution
> system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 72565 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram
2078,2079c2088,2089
< system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram
< system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram
2083,2086c2093,2096
< system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks)
< system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
< system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks)
> system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
2088,2092c2098,2102
< system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks)
< system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
< system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks)
> system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks)
2094c2104
< system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks)
2128,2148c2138,2158
< system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl
2152,2183c2162,2194
< system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed
< system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed
< system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed
< system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed
< system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed
< system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed
< system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed
< system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed
< system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed
< system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed
< system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed
< system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed
< system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed
< system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed
< system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed
< system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed
< system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed
< system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed
< system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed
< system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed
< system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed
< system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed
< system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed
< system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed
< system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed
< system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed
< system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed
< system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed
< system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed
< system.cpu0.kern.syscall::total 232 # number of syscalls executed
---
> system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed
> system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed
> system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed
> system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed
> system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed
> system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed
> system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed
> system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed
> system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed
> system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed
> system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed
> system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed
> system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed
> system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed
> system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed
> system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed
> system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed
> system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed
> system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed
> system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed
> system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed
> system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed
> system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed
> system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed
> system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed
> system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed
> system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed
> system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed
> system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed
> system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed
> system.cpu0.kern.syscall::total 215 # number of syscalls executed
2185,2203c2196,2214
< system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed
< system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed
< system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed
< system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed
< system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 170980 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches
---
> system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed
> system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed
> system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed
> system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed
> system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 170714 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches
2205,2206c2216,2217
< system.cpu0.kern.mode_good::kernel 1354
< system.cpu0.kern.mode_good::user 1355
---
> system.cpu0.kern.mode_good::kernel 1181
> system.cpu0.kern.mode_good::user 1181
2208c2219
< system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches
2211,2213c2222,2224
< system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode
2215c2226
< system.cpu0.kern.swap_context 3574 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3503 # number of times the context was actually changed
2217,2234c2228,2245
< system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl
2237,2252c2248,2271
< system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed
< system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed
< system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed
< system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed
< system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed
< system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed
< system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed
< system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed
< system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed
< system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed
< system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed
< system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed
< system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed
< system.cpu1.kern.syscall::total 94 # number of syscalls executed
---
> system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed
> system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed
> system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed
> system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed
> system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed
> system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed
> system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed
> system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed
> system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed
> system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed
> system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed
> system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed
> system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed
> system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed
> system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed
> system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed
> system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed
> system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed
> system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed
> system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed
> system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed
> system.cpu1.kern.syscall::total 111 # number of syscalls executed
2254,2267c2273,2287
< system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed
< system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed
< system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed
< system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed
< system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed
> system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed
> system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed
> system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed
> system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed
> system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed
2269,2276c2289,2296
< system.cpu1.kern.callpal::total 46833 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 384 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 574
< system.cpu1.kern.mode_good::user 384
< system.cpu1.kern.mode_good::idle 190
< system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 46904 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 554 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 733
> system.cpu1.kern.mode_good::user 554
> system.cpu1.kern.mode_good::idle 179
> system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches
2278,2283c2298,2303
< system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 990 # number of times the context was actually changed
---
> system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1024 # number of times the context was actually changed