7,11c7,11
< host_inst_rate 133407 # Simulator instruction rate (inst/s)
< host_op_rate 133407 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4441980470 # Simulator tick rate (ticks/s)
< host_mem_usage 322876 # Number of bytes of host memory used
< host_seconds 428.88 # Real time elapsed on the host
---
> host_inst_rate 163944 # Simulator instruction rate (inst/s)
> host_op_rate 163944 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5458738398 # Simulator tick rate (ticks/s)
> host_mem_usage 318552 # Number of bytes of host memory used
> host_seconds 348.99 # Real time elapsed on the host
742,743d741
< system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
758,759d755
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses
766,767c762,763
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency