Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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stats.txt (11502:e273e86a873d)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.908652 # Number of seconds simulated 4sim_ticks 1908652088000 # Number of ticks simulated 5final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.908652 # Number of seconds simulated 4sim_ticks 1908652088000 # Number of ticks simulated 5final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 169428 # Simulator instruction rate (inst/s) 8host_op_rate 169428 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5757307258 # Simulator tick rate (ticks/s) 10host_mem_usage 336708 # Number of bytes of host memory used 11host_seconds 331.52 # Real time elapsed on the host	7host_inst_rate 205918 # Simulator instruction rate (inst/s) 8host_op_rate 205918 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6997264233 # Simulator tick rate (ticks/s) 10host_mem_usage 384940 # Number of bytes of host memory used 11host_seconds 272.77 # Real time elapsed on the host
12sim_insts 56168509 # Number of instructions simulated 13sim_ops 56168509 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 56168509 # Number of instructions simulated 13sim_ops 56168509 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 582976 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26208576 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 873216 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 103232 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 976448 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7849920 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7849920 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13644 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 385128 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 1613 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 9109 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 409509 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 122655 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 122655 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 457504 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12913926 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 54086 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 305439 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13731458 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 457504 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 54086 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 511590 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 4112808 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 4112808 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 4112808 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 457504 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12913926 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 54086 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 305439 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17844266 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 409509 # Number of read requests accepted 54system.physmem.writeReqs 122655 # Number of write requests accepted 55system.physmem.readBursts 409509 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 122655 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26200320 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7848512 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26208576 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7849920 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25687 # Per bank write bursts 66system.physmem.perBankRdBursts::1 26129 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25602 # Per bank write bursts 68system.physmem.perBankRdBursts::3 25363 # Per bank write bursts 69system.physmem.perBankRdBursts::4 24824 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25086 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25117 # Per bank write bursts 72system.physmem.perBankRdBursts::7 24738 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25651 # Per bank write bursts 74system.physmem.perBankRdBursts::9 26257 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25842 # Per bank write bursts 76system.physmem.perBankRdBursts::11 26258 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25994 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25940 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25679 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25213 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7897 # Per bank write bursts 82system.physmem.perBankWrBursts::1 8119 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8345 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7678 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7188 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7302 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7389 # Per bank write bursts 88system.physmem.perBankWrBursts::7 6798 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7376 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7907 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7738 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7709 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7797 # Per bank write bursts 94system.physmem.perBankWrBursts::13 7971 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7878 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7541 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 13 # Number of times write queue was full causing retry 99system.physmem.totGap 1908647739500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 409509 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 122655 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 317276 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 37774 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 29370 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 24859 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1609 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2843 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 3482 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4541 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 5973 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7803 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 8972 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7543 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 8151 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8864 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8361 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7558 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7964 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 8132 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6500 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6707 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 372 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 213 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 194 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 192 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 196 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 215 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 177 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 113 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 86 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 64693 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 526.314006 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 319.672506 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 416.720496 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 14759 22.81% 22.81% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11414 17.64% 40.46% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5700 8.81% 49.27% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2716 4.20% 53.47% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2485 3.84% 57.31% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1481 2.29% 59.60% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1583 2.45% 62.04% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1463 2.26% 64.31% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 23092 35.69% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 64693 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5538 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 73.921271 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2818.439252 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5535 99.95% 99.95% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5538 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5538 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.143915 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.892939 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 21.348287 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 4779 86.29% 86.29% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 158 2.85% 89.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 16 0.29% 89.44% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 27 0.49% 89.92% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 200 3.61% 93.54% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 23 0.42% 93.95% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 15 0.27% 94.22% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 7 0.13% 94.35% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 3 0.05% 94.40% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 6 0.11% 94.51% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 11 0.20% 94.71% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 7 0.13% 94.84% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 10 0.18% 95.02% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 4 0.07% 95.09% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 3 0.05% 95.14% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 1 0.02% 95.16% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 30 0.54% 95.70% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.04% 95.74% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 13 0.23% 95.97% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 1 0.02% 95.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 169 3.05% 99.04% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 3 0.05% 99.10% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 1 0.02% 99.12% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 2 0.04% 99.15% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 7 0.13% 99.28% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 1 0.02% 99.30% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::124-127 2 0.04% 99.33% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::140-143 1 0.02% 99.42% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 1 0.02% 99.44% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 1 0.02% 99.46% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::164-167 3 0.05% 99.51% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::168-171 1 0.02% 99.53% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 12 0.22% 99.75% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 1 0.02% 99.77% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::196-199 1 0.02% 99.78% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::212-215 1 0.02% 99.80% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::224-227 9 0.16% 99.96% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::248-251 1 0.02% 99.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::total 5538 # Writes before turning the bus around for reads 277system.physmem.totQLat 3969590750 # Total ticks spent queuing 278system.physmem.totMemAccLat 11645465750 # Total ticks spent from burst creation until serviced by the DRAM 279system.physmem.totBusLat 2046900000 # Total ticks spent in databus transfers 280system.physmem.avgQLat 9696.59 # Average queueing delay per DRAM burst 281system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 282system.physmem.avgMemAccLat 28446.59 # Average memory access latency per DRAM burst 283system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s 284system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s 285system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 286system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s 287system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 288system.physmem.busUtil 0.14 # Data bus utilization in percentage 289system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 290system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 291system.physmem.avgRdQLen 2.19 # Average read queue length when enqueuing 292system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing 293system.physmem.readRowHits 368832 # Number of row buffer hits during reads 294system.physmem.writeRowHits 98488 # Number of row buffer hits during writes 295system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads 296system.physmem.writeRowHitRate 80.30 # Row buffer hit rate for writes 297system.physmem.avgGap 3586578.08 # Average gap between requests 298system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined 299system.physmem_0.actEnergy 244233360 # Energy for activate commands per rank (pJ) 300system.physmem_0.preEnergy 133262250 # Energy for precharge commands per rank (pJ) 301system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) 302system.physmem_0.writeEnergy 393439680 # Energy for write commands per rank (pJ) 303system.physmem_0.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) 304system.physmem_0.actBackEnergy 57966073335 # Energy for active background per rank (pJ) 305system.physmem_0.preBackEnergy 1094343472500 # Energy for precharge background per rank (pJ) 306system.physmem_0.totalEnergy 1279324161285 # Total energy per rank (pJ) 307system.physmem_0.averagePower 670.276452 # Core power per rank (mW) 308system.physmem_0.memoryStateTime::IDLE 1820370973000 # Time in different power states 309system.physmem_0.memoryStateTime::REF 63734060000 # Time in different power states 310system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 311system.physmem_0.memoryStateTime::ACT 24546489500 # Time in different power states 312system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 313system.physmem_1.actEnergy 244845720 # Energy for activate commands per rank (pJ) 314system.physmem_1.preEnergy 133596375 # Energy for precharge commands per rank (pJ) 315system.physmem_1.readEnergy 1613305200 # Energy for read commands per rank (pJ) 316system.physmem_1.writeEnergy 401222160 # Energy for write commands per rank (pJ) 317system.physmem_1.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) 318system.physmem_1.actBackEnergy 57268583145 # Energy for active background per rank (pJ) 319system.physmem_1.preBackEnergy 1094955297750 # Energy for precharge background per rank (pJ) 320system.physmem_1.totalEnergy 1279280671710 # Total energy per rank (pJ) 321system.physmem_1.averagePower 670.253671 # Core power per rank (mW) 322system.physmem_1.memoryStateTime::IDLE 1821389841500 # Time in different power states 323system.physmem_1.memoryStateTime::REF 63734060000 # Time in different power states 324system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 325system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states 326system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 582976 # Number of bytes read from this memory 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 26208576 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 873216 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 103232 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 976448 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7849920 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7849920 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 13644 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 385128 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 1613 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 9109 # Number of read requests responded to by this memory 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 409509 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 122655 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 122655 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 457504 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12913926 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 54086 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 305439 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13731458 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 457504 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 54086 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 511590 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 4112808 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 4112808 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 4112808 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 457504 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12913926 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 54086 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 305439 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17844266 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 409509 # Number of read requests accepted 55system.physmem.writeReqs 122655 # Number of write requests accepted 56system.physmem.readBursts 409509 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 122655 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26200320 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7848512 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26208576 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7849920 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 25687 # Per bank write bursts 67system.physmem.perBankRdBursts::1 26129 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25602 # Per bank write bursts 69system.physmem.perBankRdBursts::3 25363 # Per bank write bursts 70system.physmem.perBankRdBursts::4 24824 # Per bank write bursts 71system.physmem.perBankRdBursts::5 25086 # Per bank write bursts 72system.physmem.perBankRdBursts::6 25117 # Per bank write bursts 73system.physmem.perBankRdBursts::7 24738 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25651 # Per bank write bursts 75system.physmem.perBankRdBursts::9 26257 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25842 # Per bank write bursts 77system.physmem.perBankRdBursts::11 26258 # Per bank write bursts 78system.physmem.perBankRdBursts::12 25994 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25940 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25679 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25213 # Per bank write bursts 82system.physmem.perBankWrBursts::0 7897 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8119 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8345 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7678 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7188 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7302 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7389 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6798 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7376 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7907 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7738 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7709 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7797 # Per bank write bursts 95system.physmem.perBankWrBursts::13 7971 # Per bank write bursts 96system.physmem.perBankWrBursts::14 7878 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7541 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 13 # Number of times write queue was full causing retry 100system.physmem.totGap 1908647739500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 409509 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 122655 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 317276 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 37774 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 29370 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 24859 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1609 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2843 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 3482 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 4541 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 5973 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7803 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8972 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7543 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8151 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8864 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8361 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7558 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7964 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 8132 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6500 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6707 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 372 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 213 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 194 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 192 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 196 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 215 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 177 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 113 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 117 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 86 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64693 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 526.314006 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 319.672506 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 416.720496 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 14759 22.81% 22.81% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 11414 17.64% 40.46% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5700 8.81% 49.27% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2716 4.20% 53.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2485 3.84% 57.31% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1481 2.29% 59.60% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1583 2.45% 62.04% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1463 2.26% 64.31% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 23092 35.69% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64693 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5538 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 73.921271 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2818.439252 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5535 99.95% 99.95% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 5538 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5538 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.143915 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.892939 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 21.348287 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 4779 86.29% 86.29% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 158 2.85% 89.15% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 16 0.29% 89.44% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 27 0.49% 89.92% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 200 3.61% 93.54% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 23 0.42% 93.95% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 15 0.27% 94.22% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 7 0.13% 94.35% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 3 0.05% 94.40% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 6 0.11% 94.51% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 11 0.20% 94.71% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 7 0.13% 94.84% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 10 0.18% 95.02% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 4 0.07% 95.09% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 3 0.05% 95.14% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 1 0.02% 95.16% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 30 0.54% 95.70% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.04% 95.74% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 13 0.23% 95.97% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 1 0.02% 95.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 169 3.05% 99.04% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 3 0.05% 99.10% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 1 0.02% 99.12% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 2 0.04% 99.15% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::116-119 7 0.13% 99.28% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 1 0.02% 99.30% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 2 0.04% 99.33% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 1 0.02% 99.42% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::148-151 1 0.02% 99.44% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 1 0.02% 99.46% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 3 0.05% 99.51% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::168-171 1 0.02% 99.53% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::172-175 12 0.22% 99.75% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::176-179 1 0.02% 99.77% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::196-199 1 0.02% 99.78% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::212-215 1 0.02% 99.80% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::224-227 9 0.16% 99.96% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::248-251 1 0.02% 99.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::total 5538 # Writes before turning the bus around for reads 278system.physmem.totQLat 3969590750 # Total ticks spent queuing 279system.physmem.totMemAccLat 11645465750 # Total ticks spent from burst creation until serviced by the DRAM 280system.physmem.totBusLat 2046900000 # Total ticks spent in databus transfers 281system.physmem.avgQLat 9696.59 # Average queueing delay per DRAM burst 282system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 283system.physmem.avgMemAccLat 28446.59 # Average memory access latency per DRAM burst 284system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s 285system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s 286system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s 287system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s 288system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 289system.physmem.busUtil 0.14 # Data bus utilization in percentage 290system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 291system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 292system.physmem.avgRdQLen 2.19 # Average read queue length when enqueuing 293system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing 294system.physmem.readRowHits 368832 # Number of row buffer hits during reads 295system.physmem.writeRowHits 98488 # Number of row buffer hits during writes 296system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads 297system.physmem.writeRowHitRate 80.30 # Row buffer hit rate for writes 298system.physmem.avgGap 3586578.08 # Average gap between requests 299system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined 300system.physmem_0.actEnergy 244233360 # Energy for activate commands per rank (pJ) 301system.physmem_0.preEnergy 133262250 # Energy for precharge commands per rank (pJ) 302system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) 303system.physmem_0.writeEnergy 393439680 # Energy for write commands per rank (pJ) 304system.physmem_0.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) 305system.physmem_0.actBackEnergy 57966073335 # Energy for active background per rank (pJ) 306system.physmem_0.preBackEnergy 1094343472500 # Energy for precharge background per rank (pJ) 307system.physmem_0.totalEnergy 1279324161285 # Total energy per rank (pJ) 308system.physmem_0.averagePower 670.276452 # Core power per rank (mW) 309system.physmem_0.memoryStateTime::IDLE 1820370973000 # Time in different power states 310system.physmem_0.memoryStateTime::REF 63734060000 # Time in different power states 311system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_0.memoryStateTime::ACT 24546489500 # Time in different power states 313system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 314system.physmem_1.actEnergy 244845720 # Energy for activate commands per rank (pJ) 315system.physmem_1.preEnergy 133596375 # Energy for precharge commands per rank (pJ) 316system.physmem_1.readEnergy 1613305200 # Energy for read commands per rank (pJ) 317system.physmem_1.writeEnergy 401222160 # Energy for write commands per rank (pJ) 318system.physmem_1.refreshEnergy 124663821360 # Energy for refresh commands per rank (pJ) 319system.physmem_1.actBackEnergy 57268583145 # Energy for active background per rank (pJ) 320system.physmem_1.preBackEnergy 1094955297750 # Energy for precharge background per rank (pJ) 321system.physmem_1.totalEnergy 1279280671710 # Total energy per rank (pJ) 322system.physmem_1.averagePower 670.253671 # Core power per rank (mW) 323system.physmem_1.memoryStateTime::IDLE 1821389841500 # Time in different power states 324system.physmem_1.memoryStateTime::REF 63734060000 # Time in different power states 325system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 326system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states 327system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	328system.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 329system.bridge.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
327system.cpu0.branchPred.lookups 18555851 # Number of BP lookups 328system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted 329system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect 330system.cpu0.branchPred.BTBLookups 11677993 # Number of BTB lookups 331system.cpu0.branchPred.BTBHits 5178603 # Number of BTB hits 332system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 333system.cpu0.branchPred.BTBHitPct 44.344974 # BTB Hit Percentage 334system.cpu0.branchPred.usedRAS 1050126 # Number of times the RAS was used to get a target. 335system.cpu0.branchPred.RASInCorrect 41449 # Number of incorrect RAS predictions. 336system.cpu0.branchPred.indirectLookups 5562960 # Number of indirect predictor lookups. 337system.cpu0.branchPred.indirectHits 527221 # Number of indirect target hits. 338system.cpu0.branchPred.indirectMisses 5035739 # Number of indirect misses. 339system.cpu0.branchPredindirectMispredicted 249629 # Number of mispredicted indirect branches. 340system.cpu_clk_domain.clock 500 # Clock period in ticks 341system.cpu0.dtb.fetch_hits 0 # ITB hits 342system.cpu0.dtb.fetch_misses 0 # ITB misses 343system.cpu0.dtb.fetch_acv 0 # ITB acv 344system.cpu0.dtb.fetch_accesses 0 # ITB accesses 345system.cpu0.dtb.read_hits 10426157 # DTB read hits 346system.cpu0.dtb.read_misses 39598 # DTB read misses 347system.cpu0.dtb.read_acv 591 # DTB read access violations 348system.cpu0.dtb.read_accesses 665311 # DTB read accesses 349system.cpu0.dtb.write_hits 6323119 # DTB write hits 350system.cpu0.dtb.write_misses 9829 # DTB write misses 351system.cpu0.dtb.write_acv 421 # DTB write access violations 352system.cpu0.dtb.write_accesses 221072 # DTB write accesses 353system.cpu0.dtb.data_hits 16749276 # DTB hits 354system.cpu0.dtb.data_misses 49427 # DTB misses 355system.cpu0.dtb.data_acv 1012 # DTB access violations 356system.cpu0.dtb.data_accesses 886383 # DTB accesses 357system.cpu0.itb.fetch_hits 1503637 # ITB hits 358system.cpu0.itb.fetch_misses 7915 # ITB misses 359system.cpu0.itb.fetch_acv 722 # ITB acv 360system.cpu0.itb.fetch_accesses 1511552 # ITB accesses 361system.cpu0.itb.read_hits 0 # DTB read hits 362system.cpu0.itb.read_misses 0 # DTB read misses 363system.cpu0.itb.read_acv 0 # DTB read access violations 364system.cpu0.itb.read_accesses 0 # DTB read accesses 365system.cpu0.itb.write_hits 0 # DTB write hits 366system.cpu0.itb.write_misses 0 # DTB write misses 367system.cpu0.itb.write_acv 0 # DTB write access violations 368system.cpu0.itb.write_accesses 0 # DTB write accesses 369system.cpu0.itb.data_hits 0 # DTB hits 370system.cpu0.itb.data_misses 0 # DTB misses 371system.cpu0.itb.data_acv 0 # DTB access violations 372system.cpu0.itb.data_accesses 0 # DTB accesses	330system.cpu0.branchPred.lookups 18555851 # Number of BP lookups 331system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted 332system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect 333system.cpu0.branchPred.BTBLookups 11677993 # Number of BTB lookups 334system.cpu0.branchPred.BTBHits 5178603 # Number of BTB hits 335system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 336system.cpu0.branchPred.BTBHitPct 44.344974 # BTB Hit Percentage 337system.cpu0.branchPred.usedRAS 1050126 # Number of times the RAS was used to get a target. 338system.cpu0.branchPred.RASInCorrect 41449 # Number of incorrect RAS predictions. 339system.cpu0.branchPred.indirectLookups 5562960 # Number of indirect predictor lookups. 340system.cpu0.branchPred.indirectHits 527221 # Number of indirect target hits. 341system.cpu0.branchPred.indirectMisses 5035739 # Number of indirect misses. 342system.cpu0.branchPredindirectMispredicted 249629 # Number of mispredicted indirect branches. 343system.cpu_clk_domain.clock 500 # Clock period in ticks 344system.cpu0.dtb.fetch_hits 0 # ITB hits 345system.cpu0.dtb.fetch_misses 0 # ITB misses 346system.cpu0.dtb.fetch_acv 0 # ITB acv 347system.cpu0.dtb.fetch_accesses 0 # ITB accesses 348system.cpu0.dtb.read_hits 10426157 # DTB read hits 349system.cpu0.dtb.read_misses 39598 # DTB read misses 350system.cpu0.dtb.read_acv 591 # DTB read access violations 351system.cpu0.dtb.read_accesses 665311 # DTB read accesses 352system.cpu0.dtb.write_hits 6323119 # DTB write hits 353system.cpu0.dtb.write_misses 9829 # DTB write misses 354system.cpu0.dtb.write_acv 421 # DTB write access violations 355system.cpu0.dtb.write_accesses 221072 # DTB write accesses 356system.cpu0.dtb.data_hits 16749276 # DTB hits 357system.cpu0.dtb.data_misses 49427 # DTB misses 358system.cpu0.dtb.data_acv 1012 # DTB access violations 359system.cpu0.dtb.data_accesses 886383 # DTB accesses 360system.cpu0.itb.fetch_hits 1503637 # ITB hits 361system.cpu0.itb.fetch_misses 7915 # ITB misses 362system.cpu0.itb.fetch_acv 722 # ITB acv 363system.cpu0.itb.fetch_accesses 1511552 # ITB accesses 364system.cpu0.itb.read_hits 0 # DTB read hits 365system.cpu0.itb.read_misses 0 # DTB read misses 366system.cpu0.itb.read_acv 0 # DTB read access violations 367system.cpu0.itb.read_accesses 0 # DTB read accesses 368system.cpu0.itb.write_hits 0 # DTB write hits 369system.cpu0.itb.write_misses 0 # DTB write misses 370system.cpu0.itb.write_acv 0 # DTB write access violations 371system.cpu0.itb.write_accesses 0 # DTB write accesses 372system.cpu0.itb.data_hits 0 # DTB hits 373system.cpu0.itb.data_misses 0 # DTB misses 374system.cpu0.itb.data_acv 0 # DTB access violations 375system.cpu0.itb.data_accesses 0 # DTB accesses
	376system.cpu0.numPwrStateTransitions 12751 # Number of power state transitions 377system.cpu0.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state 378system.cpu0.pwrStateClkGateDist::mean 289891468.868256 # Distribution of time spent in the clock gated state 379system.cpu0.pwrStateClkGateDist::stdev 443092480.248663 # Distribution of time spent in the clock gated state 380system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state 381system.cpu0.pwrStateClkGateDist::1000-5e+10 6372 99.94% 100.00% # Distribution of time spent in the clock gated state 382system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 383system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 384system.cpu0.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state 385system.cpu0.pwrStateResidencyTicks::ON 60304082496 # Cumulative time (in ticks) in various power states 386system.cpu0.pwrStateResidencyTicks::CLK_GATED 1848348005504 # Cumulative time (in ticks) in various power states
373system.cpu0.numCycles 120614537 # number of cpu cycles simulated 374system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 376system.cpu0.fetch.icacheStallCycles 28910287 # Number of cycles fetch is stalled on an Icache miss 377system.cpu0.fetch.Insts 80847463 # Number of instructions fetch has processed 378system.cpu0.fetch.Branches 18555851 # Number of branches that fetch encountered 379system.cpu0.fetch.predictedBranches 6755950 # Number of branches that fetch has predicted taken 380system.cpu0.fetch.Cycles 84571652 # Number of cycles fetch has run and was not squashing or blocked 381system.cpu0.fetch.SquashCycles 1544806 # Number of cycles fetch has spent squashing 382system.cpu0.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb 383system.cpu0.fetch.MiscStallCycles 27521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 384system.cpu0.fetch.PendingTrapStallCycles 158722 # Number of stall cycles due to pending traps 385system.cpu0.fetch.PendingQuiesceStallCycles 425179 # Number of stall cycles due to pending quiesce instructions 386system.cpu0.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR 387system.cpu0.fetch.CacheLines 9281945 # Number of cache lines fetched 388system.cpu0.fetch.IcacheSquashes 366954 # Number of outstanding Icache misses that were squashed 389system.cpu0.fetch.rateDist::samples 114866072 # Number of instructions fetched each cycle (Total) 390system.cpu0.fetch.rateDist::mean 0.703841 # Number of instructions fetched each cycle (Total) 391system.cpu0.fetch.rateDist::stdev 2.035887 # Number of instructions fetched each cycle (Total) 392system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 393system.cpu0.fetch.rateDist::0 99921621 86.99% 86.99% # Number of instructions fetched each cycle (Total) 394system.cpu0.fetch.rateDist::1 978753 0.85% 87.84% # Number of instructions fetched each cycle (Total) 395system.cpu0.fetch.rateDist::2 2003703 1.74% 89.59% # Number of instructions fetched each cycle (Total) 396system.cpu0.fetch.rateDist::3 871619 0.76% 90.34% # Number of instructions fetched each cycle (Total) 397system.cpu0.fetch.rateDist::4 2763119 2.41% 92.75% # Number of instructions fetched each cycle (Total) 398system.cpu0.fetch.rateDist::5 643273 0.56% 93.31% # Number of instructions fetched each cycle (Total) 399system.cpu0.fetch.rateDist::6 756873 0.66% 93.97% # Number of instructions fetched each cycle (Total) 400system.cpu0.fetch.rateDist::7 980520 0.85% 94.82% # Number of instructions fetched each cycle (Total) 401system.cpu0.fetch.rateDist::8 5946591 5.18% 100.00% # Number of instructions fetched each cycle (Total) 402system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 403system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 404system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 405system.cpu0.fetch.rateDist::total 114866072 # Number of instructions fetched each cycle (Total) 406system.cpu0.fetch.branchRate 0.153844 # Number of branch fetches per cycle 407system.cpu0.fetch.rate 0.670296 # Number of inst fetches per cycle 408system.cpu0.decode.IdleCycles 23249023 # Number of cycles decode is idle 409system.cpu0.decode.BlockedCycles 79273649 # Number of cycles decode is blocked 410system.cpu0.decode.RunCycles 9681952 # Number of cycles decode is running 411system.cpu0.decode.UnblockCycles 1921768 # Number of cycles decode is unblocking 412system.cpu0.decode.SquashCycles 739679 # Number of cycles decode is squashing 413system.cpu0.decode.BranchResolved 692177 # Number of times decode resolved a branch 414system.cpu0.decode.BranchMispred 33362 # Number of times decode detected a branch misprediction 415system.cpu0.decode.DecodedInsts 69931495 # Number of instructions handled by decode 416system.cpu0.decode.SquashedInsts 102843 # Number of squashed instructions handled by decode 417system.cpu0.rename.SquashCycles 739679 # Number of cycles rename is squashing 418system.cpu0.rename.IdleCycles 24188488 # Number of cycles rename is idle 419system.cpu0.rename.BlockCycles 52133494 # Number of cycles rename is blocking 420system.cpu0.rename.serializeStallCycles 18507080 # count of cycles rename stalled for serializing inst 421system.cpu0.rename.RunCycles 10598824 # Number of cycles rename is running 422system.cpu0.rename.UnblockCycles 8698505 # Number of cycles rename is unblocking 423system.cpu0.rename.RenamedInsts 67143844 # Number of instructions processed by rename 424system.cpu0.rename.ROBFullEvents 198929 # Number of times rename has blocked due to ROB full 425system.cpu0.rename.IQFullEvents 2037542 # Number of times rename has blocked due to IQ full 426system.cpu0.rename.LQFullEvents 235156 # Number of times rename has blocked due to LQ full 427system.cpu0.rename.SQFullEvents 4634826 # Number of times rename has blocked due to SQ full 428system.cpu0.rename.RenamedOperands 45210033 # Number of destination operands rename has renamed 429system.cpu0.rename.RenameLookups 80787031 # Number of register rename lookups that rename has made 430system.cpu0.rename.int_rename_lookups 80633489 # Number of integer rename lookups 431system.cpu0.rename.fp_rename_lookups 143553 # Number of floating rename lookups 432system.cpu0.rename.CommittedMaps 36399823 # Number of HB maps that are committed 433system.cpu0.rename.UndoneMaps 8810210 # Number of HB maps that are undone due to squashing 434system.cpu0.rename.serializingInsts 1599007 # count of serializing insts renamed 435system.cpu0.rename.tempSerializingInsts 262557 # count of temporary serializing insts renamed 436system.cpu0.rename.skidInsts 13124305 # count of insts added to the skid buffer 437system.cpu0.memDep0.insertedLoads 10911287 # Number of loads inserted to the mem dependence unit. 438system.cpu0.memDep0.insertedStores 6742479 # Number of stores inserted to the mem dependence unit. 439system.cpu0.memDep0.conflictingLoads 1608349 # Number of conflicting loads. 440system.cpu0.memDep0.conflictingStores 1040811 # Number of conflicting stores. 441system.cpu0.iq.iqInstsAdded 59252141 # Number of instructions added to the IQ (excludes non-spec) 442system.cpu0.iq.iqNonSpecInstsAdded 2087306 # Number of non-speculative instructions added to the IQ 443system.cpu0.iq.iqInstsIssued 57311786 # Number of instructions issued 444system.cpu0.iq.iqSquashedInstsIssued 84500 # Number of squashed instructions issued 445system.cpu0.iq.iqSquashedInstsExamined 10900957 # Number of squashed instructions iterated over during squash; mainly for profiling 446system.cpu0.iq.iqSquashedOperandsExamined 4754694 # Number of squashed operands that are examined and possibly removed from graph 447system.cpu0.iq.iqSquashedNonSpecRemoved 1456877 # Number of squashed non-spec instructions that were removed 448system.cpu0.iq.issued_per_cycle::samples 114866072 # Number of insts issued each cycle 449system.cpu0.iq.issued_per_cycle::mean 0.498944 # Number of insts issued each cycle 450system.cpu0.iq.issued_per_cycle::stdev 1.243932 # Number of insts issued each cycle 451system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 452system.cpu0.iq.issued_per_cycle::0 91593251 79.74% 79.74% # Number of insts issued each cycle 453system.cpu0.iq.issued_per_cycle::1 9917884 8.63% 88.37% # Number of insts issued each cycle 454system.cpu0.iq.issued_per_cycle::2 4171968 3.63% 92.01% # Number of insts issued each cycle 455system.cpu0.iq.issued_per_cycle::3 2987675 2.60% 94.61% # Number of insts issued each cycle 456system.cpu0.iq.issued_per_cycle::4 3091850 2.69% 97.30% # Number of insts issued each cycle 457system.cpu0.iq.issued_per_cycle::5 1551239 1.35% 98.65% # Number of insts issued each cycle 458system.cpu0.iq.issued_per_cycle::6 1031605 0.90% 99.55% # Number of insts issued each cycle 459system.cpu0.iq.issued_per_cycle::7 391084 0.34% 99.89% # Number of insts issued each cycle 460system.cpu0.iq.issued_per_cycle::8 129516 0.11% 100.00% # Number of insts issued each cycle 461system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 462system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 463system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 464system.cpu0.iq.issued_per_cycle::total 114866072 # Number of insts issued each cycle 465system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 466system.cpu0.iq.fu_full::IntAlu 177618 15.88% 15.88% # attempts to use FU when none available 467system.cpu0.iq.fu_full::IntMult 0 0.00% 15.88% # attempts to use FU when none available 468system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.88% # attempts to use FU when none available 469system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.88% # attempts to use FU when none available 470system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.88% # attempts to use FU when none available 471system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.88% # attempts to use FU when none available 472system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.88% # attempts to use FU when none available 473system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.88% # attempts to use FU when none available 474system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.88% # attempts to use FU when none available 475system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.88% # attempts to use FU when none available 476system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.88% # attempts to use FU when none available 477system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.88% # attempts to use FU when none available 478system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.88% # attempts to use FU when none available 479system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.88% # attempts to use FU when none available 480system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.88% # attempts to use FU when none available 481system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.88% # attempts to use FU when none available 482system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.88% # attempts to use FU when none available 483system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.88% # attempts to use FU when none available 484system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.88% # attempts to use FU when none available 485system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.88% # attempts to use FU when none available 486system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.88% # attempts to use FU when none available 487system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.88% # attempts to use FU when none available 488system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.88% # attempts to use FU when none available 489system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.88% # attempts to use FU when none available 490system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.88% # attempts to use FU when none available 491system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.88% # attempts to use FU when none available 492system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.88% # attempts to use FU when none available 493system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.88% # attempts to use FU when none available 494system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.88% # attempts to use FU when none available 495system.cpu0.iq.fu_full::MemRead 580154 51.88% 67.76% # attempts to use FU when none available 496system.cpu0.iq.fu_full::MemWrite 360585 32.24% 100.00% # attempts to use FU when none available 497system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 498system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 499system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued 500system.cpu0.iq.FU_type_0::IntAlu 38999657 68.05% 68.05% # Type of FU issued 501system.cpu0.iq.FU_type_0::IntMult 59968 0.10% 68.16% # Type of FU issued 502system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.16% # Type of FU issued 503system.cpu0.iq.FU_type_0::FloatAdd 28473 0.05% 68.21% # Type of FU issued 504system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 505system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 506system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 507system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.21% # Type of FU issued 508system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 509system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 510system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 511system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 512system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 513system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 514system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued 515system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 516system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 517system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued 518system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 519system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 520system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued 521system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 522system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued 523system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued 524system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued 525system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued 526system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued 527system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued 528system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued 529system.cpu0.iq.FU_type_0::MemRead 10921462 19.06% 87.27% # Type of FU issued 530system.cpu0.iq.FU_type_0::MemWrite 6423481 11.21% 98.48% # Type of FU issued 531system.cpu0.iq.FU_type_0::IprAccess 873773 1.52% 100.00% # Type of FU issued 532system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 533system.cpu0.iq.FU_type_0::total 57311786 # Type of FU issued 534system.cpu0.iq.rate 0.475165 # Inst issue rate 535system.cpu0.iq.fu_busy_cnt 1118357 # FU busy when requested 536system.cpu0.iq.fu_busy_rate 0.019514 # FU busy rate (busy events/executed inst) 537system.cpu0.iq.int_inst_queue_reads 230030260 # Number of integer instruction queue reads 538system.cpu0.iq.int_inst_queue_writes 71938879 # Number of integer instruction queue writes 539system.cpu0.iq.int_inst_queue_wakeup_accesses 55311420 # Number of integer instruction queue wakeup accesses 540system.cpu0.iq.fp_inst_queue_reads 662241 # Number of floating instruction queue reads 541system.cpu0.iq.fp_inst_queue_writes 320414 # Number of floating instruction queue writes 542system.cpu0.iq.fp_inst_queue_wakeup_accesses 300136 # Number of floating instruction queue wakeup accesses 543system.cpu0.iq.int_alu_accesses 58069335 # Number of integer alu accesses 544system.cpu0.iq.fp_alu_accesses 357492 # Number of floating point alu accesses 545system.cpu0.iew.lsq.thread0.forwLoads 651404 # Number of loads that had data forwarded from stores 546system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 547system.cpu0.iew.lsq.thread0.squashedLoads 2319887 # Number of loads squashed 548system.cpu0.iew.lsq.thread0.ignoredResponses 3968 # Number of memory responses ignored because the instruction is squashed 549system.cpu0.iew.lsq.thread0.memOrderViolation 19302 # Number of memory ordering violations 550system.cpu0.iew.lsq.thread0.squashedStores 772094 # Number of stores squashed 551system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 552system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 553system.cpu0.iew.lsq.thread0.rescheduledLoads 18487 # Number of loads that were rescheduled 554system.cpu0.iew.lsq.thread0.cacheBlocked 403076 # Number of times an access to memory failed due to the cache being blocked 555system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 556system.cpu0.iew.iewSquashCycles 739679 # Number of cycles IEW is squashing 557system.cpu0.iew.iewBlockCycles 48919856 # Number of cycles IEW is blocking 558system.cpu0.iew.iewUnblockCycles 836899 # Number of cycles IEW is unblocking 559system.cpu0.iew.iewDispatchedInsts 65195890 # Number of instructions dispatched to IQ 560system.cpu0.iew.iewDispSquashedInsts 175652 # Number of squashed instructions skipped by dispatch 561system.cpu0.iew.iewDispLoadInsts 10911287 # Number of dispatched load instructions 562system.cpu0.iew.iewDispStoreInsts 6742479 # Number of dispatched store instructions 563system.cpu0.iew.iewDispNonSpecInsts 1850250 # Number of dispatched non-speculative instructions 564system.cpu0.iew.iewIQFullEvents 42611 # Number of times the IQ has become full, causing a stall 565system.cpu0.iew.iewLSQFullEvents 592619 # Number of times the LSQ has become full, causing a stall 566system.cpu0.iew.memOrderViolationEvents 19302 # Number of memory order violations 567system.cpu0.iew.predictedTakenIncorrect 209624 # Number of branches that were predicted taken incorrectly 568system.cpu0.iew.predictedNotTakenIncorrect 584555 # Number of branches that were predicted not taken incorrectly 569system.cpu0.iew.branchMispredicts 794179 # Number of branch mispredicts detected at execute 570system.cpu0.iew.iewExecutedInsts 56526207 # Number of executed instructions 571system.cpu0.iew.iewExecLoadInsts 10495265 # Number of load instructions executed 572system.cpu0.iew.iewExecSquashedInsts 785579 # Number of squashed instructions skipped in execute 573system.cpu0.iew.exec_swp 0 # number of swp insts executed 574system.cpu0.iew.exec_nop 3856443 # number of nop insts executed 575system.cpu0.iew.exec_refs 16847340 # number of memory reference insts executed 576system.cpu0.iew.exec_branches 8962761 # Number of branches executed 577system.cpu0.iew.exec_stores 6352075 # Number of stores executed 578system.cpu0.iew.exec_rate 0.468652 # Inst execution rate 579system.cpu0.iew.wb_sent 55828896 # cumulative count of insts sent to commit 580system.cpu0.iew.wb_count 55611556 # cumulative count of insts written-back 581system.cpu0.iew.wb_producers 28259375 # num instructions producing a value 582system.cpu0.iew.wb_consumers 39130384 # num instructions consuming a value 583system.cpu0.iew.wb_rate 0.461068 # insts written-back per cycle 584system.cpu0.iew.wb_fanout 0.722185 # average fanout of values written-back 585system.cpu0.commit.commitSquashedInsts 11491140 # The number of squashed insts skipped by commit 586system.cpu0.commit.commitNonSpecStalls 630429 # The number of times commit has been forced to stall to communicate backwards 587system.cpu0.commit.branchMispredicts 709660 # The number of times a branch was mispredicted 588system.cpu0.commit.committed_per_cycle::samples 112872616 # Number of insts commited each cycle 589system.cpu0.commit.committed_per_cycle::mean 0.474349 # Number of insts commited each cycle 590system.cpu0.commit.committed_per_cycle::stdev 1.409733 # Number of insts commited each cycle 591system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 592system.cpu0.commit.committed_per_cycle::0 93942624 83.23% 83.23% # Number of insts commited each cycle 593system.cpu0.commit.committed_per_cycle::1 7580066 6.72% 89.94% # Number of insts commited each cycle 594system.cpu0.commit.committed_per_cycle::2 4021065 3.56% 93.51% # Number of insts commited each cycle 595system.cpu0.commit.committed_per_cycle::3 2150933 1.91% 95.41% # Number of insts commited each cycle 596system.cpu0.commit.committed_per_cycle::4 1669707 1.48% 96.89% # Number of insts commited each cycle 597system.cpu0.commit.committed_per_cycle::5 619428 0.55% 97.44% # Number of insts commited each cycle 598system.cpu0.commit.committed_per_cycle::6 456360 0.40% 97.84% # Number of insts commited each cycle 599system.cpu0.commit.committed_per_cycle::7 507616 0.45% 98.29% # Number of insts commited each cycle 600system.cpu0.commit.committed_per_cycle::8 1924817 1.71% 100.00% # Number of insts commited each cycle 601system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 602system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 603system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 604system.cpu0.commit.committed_per_cycle::total 112872616 # Number of insts commited each cycle 605system.cpu0.commit.committedInsts 53540971 # Number of instructions committed 606system.cpu0.commit.committedOps 53540971 # Number of ops (including micro ops) committed 607system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 608system.cpu0.commit.refs 14561785 # Number of memory references committed 609system.cpu0.commit.loads 8591400 # Number of loads committed 610system.cpu0.commit.membars 215482 # Number of memory barriers committed 611system.cpu0.commit.branches 8090306 # Number of branches committed 612system.cpu0.commit.fp_insts 289534 # Number of committed floating point instructions. 613system.cpu0.commit.int_insts 49542263 # Number of committed integer instructions. 614system.cpu0.commit.function_calls 699437 # Number of function calls committed. 615system.cpu0.commit.op_class_0::No_OpClass 3105795 5.80% 5.80% # Class of committed instruction 616system.cpu0.commit.op_class_0::IntAlu 34689949 64.79% 70.59% # Class of committed instruction 617system.cpu0.commit.op_class_0::IntMult 58544 0.11% 70.70% # Class of committed instruction 618system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.70% # Class of committed instruction 619system.cpu0.commit.op_class_0::FloatAdd 28001 0.05% 70.75% # Class of committed instruction 620system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction 621system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction 622system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction 623system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.76% # Class of committed instruction 624system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction 625system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction 626system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction 627system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction 628system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction 629system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction 630system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction 631system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction 632system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction 633system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction 634system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction 635system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction 636system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction 637system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction 638system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction 639system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction 640system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction 642system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction 643system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction 644system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction 645system.cpu0.commit.op_class_0::MemRead 8806882 16.45% 87.21% # Class of committed instruction 646system.cpu0.commit.op_class_0::MemWrite 5976371 11.16% 98.37% # Class of committed instruction 647system.cpu0.commit.op_class_0::IprAccess 873773 1.63% 100.00% # Class of committed instruction 648system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 649system.cpu0.commit.op_class_0::total 53540971 # Class of committed instruction 650system.cpu0.commit.bw_lim_events 1924817 # number cycles where commit BW limit reached 651system.cpu0.rob.rob_reads 175788251 # The number of ROB reads 652system.cpu0.rob.rob_writes 132059822 # The number of ROB writes 653system.cpu0.timesIdled 545123 # Number of times that the entire CPU went into an idle state and unscheduled itself 654system.cpu0.idleCycles 5748465 # Total number of cycles that the CPU has spent unscheduled due to idling 655system.cpu0.quiesceCycles 3696064399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 656system.cpu0.committedInsts 50438489 # Number of Instructions Simulated 657system.cpu0.committedOps 50438489 # Number of Ops (including micro ops) Simulated 658system.cpu0.cpi 2.391319 # CPI: Cycles Per Instruction 659system.cpu0.cpi_total 2.391319 # CPI: Total CPI of All Threads 660system.cpu0.ipc 0.418179 # IPC: Instructions Per Cycle 661system.cpu0.ipc_total 0.418179 # IPC: Total IPC of All Threads 662system.cpu0.int_regfile_reads 73773620 # number of integer regfile reads 663system.cpu0.int_regfile_writes 40428970 # number of integer regfile writes 664system.cpu0.fp_regfile_reads 142673 # number of floating regfile reads 665system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes 666system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads 667system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes	387system.cpu0.numCycles 120614537 # number of cpu cycles simulated 388system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 389system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 390system.cpu0.fetch.icacheStallCycles 28910287 # Number of cycles fetch is stalled on an Icache miss 391system.cpu0.fetch.Insts 80847463 # Number of instructions fetch has processed 392system.cpu0.fetch.Branches 18555851 # Number of branches that fetch encountered 393system.cpu0.fetch.predictedBranches 6755950 # Number of branches that fetch has predicted taken 394system.cpu0.fetch.Cycles 84571652 # Number of cycles fetch has run and was not squashing or blocked 395system.cpu0.fetch.SquashCycles 1544806 # Number of cycles fetch has spent squashing 396system.cpu0.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb 397system.cpu0.fetch.MiscStallCycles 27521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 398system.cpu0.fetch.PendingTrapStallCycles 158722 # Number of stall cycles due to pending traps 399system.cpu0.fetch.PendingQuiesceStallCycles 425179 # Number of stall cycles due to pending quiesce instructions 400system.cpu0.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR 401system.cpu0.fetch.CacheLines 9281945 # Number of cache lines fetched 402system.cpu0.fetch.IcacheSquashes 366954 # Number of outstanding Icache misses that were squashed 403system.cpu0.fetch.rateDist::samples 114866072 # Number of instructions fetched each cycle (Total) 404system.cpu0.fetch.rateDist::mean 0.703841 # Number of instructions fetched each cycle (Total) 405system.cpu0.fetch.rateDist::stdev 2.035887 # Number of instructions fetched each cycle (Total) 406system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 407system.cpu0.fetch.rateDist::0 99921621 86.99% 86.99% # Number of instructions fetched each cycle (Total) 408system.cpu0.fetch.rateDist::1 978753 0.85% 87.84% # Number of instructions fetched each cycle (Total) 409system.cpu0.fetch.rateDist::2 2003703 1.74% 89.59% # Number of instructions fetched each cycle (Total) 410system.cpu0.fetch.rateDist::3 871619 0.76% 90.34% # Number of instructions fetched each cycle (Total) 411system.cpu0.fetch.rateDist::4 2763119 2.41% 92.75% # Number of instructions fetched each cycle (Total) 412system.cpu0.fetch.rateDist::5 643273 0.56% 93.31% # Number of instructions fetched each cycle (Total) 413system.cpu0.fetch.rateDist::6 756873 0.66% 93.97% # Number of instructions fetched each cycle (Total) 414system.cpu0.fetch.rateDist::7 980520 0.85% 94.82% # Number of instructions fetched each cycle (Total) 415system.cpu0.fetch.rateDist::8 5946591 5.18% 100.00% # Number of instructions fetched each cycle (Total) 416system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 417system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 418system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 419system.cpu0.fetch.rateDist::total 114866072 # Number of instructions fetched each cycle (Total) 420system.cpu0.fetch.branchRate 0.153844 # Number of branch fetches per cycle 421system.cpu0.fetch.rate 0.670296 # Number of inst fetches per cycle 422system.cpu0.decode.IdleCycles 23249023 # Number of cycles decode is idle 423system.cpu0.decode.BlockedCycles 79273649 # Number of cycles decode is blocked 424system.cpu0.decode.RunCycles 9681952 # Number of cycles decode is running 425system.cpu0.decode.UnblockCycles 1921768 # Number of cycles decode is unblocking 426system.cpu0.decode.SquashCycles 739679 # Number of cycles decode is squashing 427system.cpu0.decode.BranchResolved 692177 # Number of times decode resolved a branch 428system.cpu0.decode.BranchMispred 33362 # Number of times decode detected a branch misprediction 429system.cpu0.decode.DecodedInsts 69931495 # Number of instructions handled by decode 430system.cpu0.decode.SquashedInsts 102843 # Number of squashed instructions handled by decode 431system.cpu0.rename.SquashCycles 739679 # Number of cycles rename is squashing 432system.cpu0.rename.IdleCycles 24188488 # Number of cycles rename is idle 433system.cpu0.rename.BlockCycles 52133494 # Number of cycles rename is blocking 434system.cpu0.rename.serializeStallCycles 18507080 # count of cycles rename stalled for serializing inst 435system.cpu0.rename.RunCycles 10598824 # Number of cycles rename is running 436system.cpu0.rename.UnblockCycles 8698505 # Number of cycles rename is unblocking 437system.cpu0.rename.RenamedInsts 67143844 # Number of instructions processed by rename 438system.cpu0.rename.ROBFullEvents 198929 # Number of times rename has blocked due to ROB full 439system.cpu0.rename.IQFullEvents 2037542 # Number of times rename has blocked due to IQ full 440system.cpu0.rename.LQFullEvents 235156 # Number of times rename has blocked due to LQ full 441system.cpu0.rename.SQFullEvents 4634826 # Number of times rename has blocked due to SQ full 442system.cpu0.rename.RenamedOperands 45210033 # Number of destination operands rename has renamed 443system.cpu0.rename.RenameLookups 80787031 # Number of register rename lookups that rename has made 444system.cpu0.rename.int_rename_lookups 80633489 # Number of integer rename lookups 445system.cpu0.rename.fp_rename_lookups 143553 # Number of floating rename lookups 446system.cpu0.rename.CommittedMaps 36399823 # Number of HB maps that are committed 447system.cpu0.rename.UndoneMaps 8810210 # Number of HB maps that are undone due to squashing 448system.cpu0.rename.serializingInsts 1599007 # count of serializing insts renamed 449system.cpu0.rename.tempSerializingInsts 262557 # count of temporary serializing insts renamed 450system.cpu0.rename.skidInsts 13124305 # count of insts added to the skid buffer 451system.cpu0.memDep0.insertedLoads 10911287 # Number of loads inserted to the mem dependence unit. 452system.cpu0.memDep0.insertedStores 6742479 # Number of stores inserted to the mem dependence unit. 453system.cpu0.memDep0.conflictingLoads 1608349 # Number of conflicting loads. 454system.cpu0.memDep0.conflictingStores 1040811 # Number of conflicting stores. 455system.cpu0.iq.iqInstsAdded 59252141 # Number of instructions added to the IQ (excludes non-spec) 456system.cpu0.iq.iqNonSpecInstsAdded 2087306 # Number of non-speculative instructions added to the IQ 457system.cpu0.iq.iqInstsIssued 57311786 # Number of instructions issued 458system.cpu0.iq.iqSquashedInstsIssued 84500 # Number of squashed instructions issued 459system.cpu0.iq.iqSquashedInstsExamined 10900957 # Number of squashed instructions iterated over during squash; mainly for profiling 460system.cpu0.iq.iqSquashedOperandsExamined 4754694 # Number of squashed operands that are examined and possibly removed from graph 461system.cpu0.iq.iqSquashedNonSpecRemoved 1456877 # Number of squashed non-spec instructions that were removed 462system.cpu0.iq.issued_per_cycle::samples 114866072 # Number of insts issued each cycle 463system.cpu0.iq.issued_per_cycle::mean 0.498944 # Number of insts issued each cycle 464system.cpu0.iq.issued_per_cycle::stdev 1.243932 # Number of insts issued each cycle 465system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 466system.cpu0.iq.issued_per_cycle::0 91593251 79.74% 79.74% # Number of insts issued each cycle 467system.cpu0.iq.issued_per_cycle::1 9917884 8.63% 88.37% # Number of insts issued each cycle 468system.cpu0.iq.issued_per_cycle::2 4171968 3.63% 92.01% # Number of insts issued each cycle 469system.cpu0.iq.issued_per_cycle::3 2987675 2.60% 94.61% # Number of insts issued each cycle 470system.cpu0.iq.issued_per_cycle::4 3091850 2.69% 97.30% # Number of insts issued each cycle 471system.cpu0.iq.issued_per_cycle::5 1551239 1.35% 98.65% # Number of insts issued each cycle 472system.cpu0.iq.issued_per_cycle::6 1031605 0.90% 99.55% # Number of insts issued each cycle 473system.cpu0.iq.issued_per_cycle::7 391084 0.34% 99.89% # Number of insts issued each cycle 474system.cpu0.iq.issued_per_cycle::8 129516 0.11% 100.00% # Number of insts issued each cycle 475system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 476system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 477system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 478system.cpu0.iq.issued_per_cycle::total 114866072 # Number of insts issued each cycle 479system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 480system.cpu0.iq.fu_full::IntAlu 177618 15.88% 15.88% # attempts to use FU when none available 481system.cpu0.iq.fu_full::IntMult 0 0.00% 15.88% # attempts to use FU when none available 482system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.88% # attempts to use FU when none available 483system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.88% # attempts to use FU when none available 484system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.88% # attempts to use FU when none available 485system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.88% # attempts to use FU when none available 486system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.88% # attempts to use FU when none available 487system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.88% # attempts to use FU when none available 488system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.88% # attempts to use FU when none available 489system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.88% # attempts to use FU when none available 490system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.88% # attempts to use FU when none available 491system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.88% # attempts to use FU when none available 492system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.88% # attempts to use FU when none available 493system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.88% # attempts to use FU when none available 494system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.88% # attempts to use FU when none available 495system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.88% # attempts to use FU when none available 496system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.88% # attempts to use FU when none available 497system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.88% # attempts to use FU when none available 498system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.88% # attempts to use FU when none available 499system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.88% # attempts to use FU when none available 500system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.88% # attempts to use FU when none available 501system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.88% # attempts to use FU when none available 502system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.88% # attempts to use FU when none available 503system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.88% # attempts to use FU when none available 504system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.88% # attempts to use FU when none available 505system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.88% # attempts to use FU when none available 506system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.88% # attempts to use FU when none available 507system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.88% # attempts to use FU when none available 508system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.88% # attempts to use FU when none available 509system.cpu0.iq.fu_full::MemRead 580154 51.88% 67.76% # attempts to use FU when none available 510system.cpu0.iq.fu_full::MemWrite 360585 32.24% 100.00% # attempts to use FU when none available 511system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 512system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 513system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued 514system.cpu0.iq.FU_type_0::IntAlu 38999657 68.05% 68.05% # Type of FU issued 515system.cpu0.iq.FU_type_0::IntMult 59968 0.10% 68.16% # Type of FU issued 516system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.16% # Type of FU issued 517system.cpu0.iq.FU_type_0::FloatAdd 28473 0.05% 68.21% # Type of FU issued 518system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 519system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 520system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 521system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.21% # Type of FU issued 522system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 523system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 524system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 525system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 526system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 527system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 528system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued 529system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 530system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 531system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued 532system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 533system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 534system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued 535system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 536system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued 537system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued 538system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued 539system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued 540system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued 541system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued 542system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued 543system.cpu0.iq.FU_type_0::MemRead 10921462 19.06% 87.27% # Type of FU issued 544system.cpu0.iq.FU_type_0::MemWrite 6423481 11.21% 98.48% # Type of FU issued 545system.cpu0.iq.FU_type_0::IprAccess 873773 1.52% 100.00% # Type of FU issued 546system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 547system.cpu0.iq.FU_type_0::total 57311786 # Type of FU issued 548system.cpu0.iq.rate 0.475165 # Inst issue rate 549system.cpu0.iq.fu_busy_cnt 1118357 # FU busy when requested 550system.cpu0.iq.fu_busy_rate 0.019514 # FU busy rate (busy events/executed inst) 551system.cpu0.iq.int_inst_queue_reads 230030260 # Number of integer instruction queue reads 552system.cpu0.iq.int_inst_queue_writes 71938879 # Number of integer instruction queue writes 553system.cpu0.iq.int_inst_queue_wakeup_accesses 55311420 # Number of integer instruction queue wakeup accesses 554system.cpu0.iq.fp_inst_queue_reads 662241 # Number of floating instruction queue reads 555system.cpu0.iq.fp_inst_queue_writes 320414 # Number of floating instruction queue writes 556system.cpu0.iq.fp_inst_queue_wakeup_accesses 300136 # Number of floating instruction queue wakeup accesses 557system.cpu0.iq.int_alu_accesses 58069335 # Number of integer alu accesses 558system.cpu0.iq.fp_alu_accesses 357492 # Number of floating point alu accesses 559system.cpu0.iew.lsq.thread0.forwLoads 651404 # Number of loads that had data forwarded from stores 560system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 561system.cpu0.iew.lsq.thread0.squashedLoads 2319887 # Number of loads squashed 562system.cpu0.iew.lsq.thread0.ignoredResponses 3968 # Number of memory responses ignored because the instruction is squashed 563system.cpu0.iew.lsq.thread0.memOrderViolation 19302 # Number of memory ordering violations 564system.cpu0.iew.lsq.thread0.squashedStores 772094 # Number of stores squashed 565system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 566system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 567system.cpu0.iew.lsq.thread0.rescheduledLoads 18487 # Number of loads that were rescheduled 568system.cpu0.iew.lsq.thread0.cacheBlocked 403076 # Number of times an access to memory failed due to the cache being blocked 569system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 570system.cpu0.iew.iewSquashCycles 739679 # Number of cycles IEW is squashing 571system.cpu0.iew.iewBlockCycles 48919856 # Number of cycles IEW is blocking 572system.cpu0.iew.iewUnblockCycles 836899 # Number of cycles IEW is unblocking 573system.cpu0.iew.iewDispatchedInsts 65195890 # Number of instructions dispatched to IQ 574system.cpu0.iew.iewDispSquashedInsts 175652 # Number of squashed instructions skipped by dispatch 575system.cpu0.iew.iewDispLoadInsts 10911287 # Number of dispatched load instructions 576system.cpu0.iew.iewDispStoreInsts 6742479 # Number of dispatched store instructions 577system.cpu0.iew.iewDispNonSpecInsts 1850250 # Number of dispatched non-speculative instructions 578system.cpu0.iew.iewIQFullEvents 42611 # Number of times the IQ has become full, causing a stall 579system.cpu0.iew.iewLSQFullEvents 592619 # Number of times the LSQ has become full, causing a stall 580system.cpu0.iew.memOrderViolationEvents 19302 # Number of memory order violations 581system.cpu0.iew.predictedTakenIncorrect 209624 # Number of branches that were predicted taken incorrectly 582system.cpu0.iew.predictedNotTakenIncorrect 584555 # Number of branches that were predicted not taken incorrectly 583system.cpu0.iew.branchMispredicts 794179 # Number of branch mispredicts detected at execute 584system.cpu0.iew.iewExecutedInsts 56526207 # Number of executed instructions 585system.cpu0.iew.iewExecLoadInsts 10495265 # Number of load instructions executed 586system.cpu0.iew.iewExecSquashedInsts 785579 # Number of squashed instructions skipped in execute 587system.cpu0.iew.exec_swp 0 # number of swp insts executed 588system.cpu0.iew.exec_nop 3856443 # number of nop insts executed 589system.cpu0.iew.exec_refs 16847340 # number of memory reference insts executed 590system.cpu0.iew.exec_branches 8962761 # Number of branches executed 591system.cpu0.iew.exec_stores 6352075 # Number of stores executed 592system.cpu0.iew.exec_rate 0.468652 # Inst execution rate 593system.cpu0.iew.wb_sent 55828896 # cumulative count of insts sent to commit 594system.cpu0.iew.wb_count 55611556 # cumulative count of insts written-back 595system.cpu0.iew.wb_producers 28259375 # num instructions producing a value 596system.cpu0.iew.wb_consumers 39130384 # num instructions consuming a value 597system.cpu0.iew.wb_rate 0.461068 # insts written-back per cycle 598system.cpu0.iew.wb_fanout 0.722185 # average fanout of values written-back 599system.cpu0.commit.commitSquashedInsts 11491140 # The number of squashed insts skipped by commit 600system.cpu0.commit.commitNonSpecStalls 630429 # The number of times commit has been forced to stall to communicate backwards 601system.cpu0.commit.branchMispredicts 709660 # The number of times a branch was mispredicted 602system.cpu0.commit.committed_per_cycle::samples 112872616 # Number of insts commited each cycle 603system.cpu0.commit.committed_per_cycle::mean 0.474349 # Number of insts commited each cycle 604system.cpu0.commit.committed_per_cycle::stdev 1.409733 # Number of insts commited each cycle 605system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 606system.cpu0.commit.committed_per_cycle::0 93942624 83.23% 83.23% # Number of insts commited each cycle 607system.cpu0.commit.committed_per_cycle::1 7580066 6.72% 89.94% # Number of insts commited each cycle 608system.cpu0.commit.committed_per_cycle::2 4021065 3.56% 93.51% # Number of insts commited each cycle 609system.cpu0.commit.committed_per_cycle::3 2150933 1.91% 95.41% # Number of insts commited each cycle 610system.cpu0.commit.committed_per_cycle::4 1669707 1.48% 96.89% # Number of insts commited each cycle 611system.cpu0.commit.committed_per_cycle::5 619428 0.55% 97.44% # Number of insts commited each cycle 612system.cpu0.commit.committed_per_cycle::6 456360 0.40% 97.84% # Number of insts commited each cycle 613system.cpu0.commit.committed_per_cycle::7 507616 0.45% 98.29% # Number of insts commited each cycle 614system.cpu0.commit.committed_per_cycle::8 1924817 1.71% 100.00% # Number of insts commited each cycle 615system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 616system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 617system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 618system.cpu0.commit.committed_per_cycle::total 112872616 # Number of insts commited each cycle 619system.cpu0.commit.committedInsts 53540971 # Number of instructions committed 620system.cpu0.commit.committedOps 53540971 # Number of ops (including micro ops) committed 621system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 622system.cpu0.commit.refs 14561785 # Number of memory references committed 623system.cpu0.commit.loads 8591400 # Number of loads committed 624system.cpu0.commit.membars 215482 # Number of memory barriers committed 625system.cpu0.commit.branches 8090306 # Number of branches committed 626system.cpu0.commit.fp_insts 289534 # Number of committed floating point instructions. 627system.cpu0.commit.int_insts 49542263 # Number of committed integer instructions. 628system.cpu0.commit.function_calls 699437 # Number of function calls committed. 629system.cpu0.commit.op_class_0::No_OpClass 3105795 5.80% 5.80% # Class of committed instruction 630system.cpu0.commit.op_class_0::IntAlu 34689949 64.79% 70.59% # Class of committed instruction 631system.cpu0.commit.op_class_0::IntMult 58544 0.11% 70.70% # Class of committed instruction 632system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.70% # Class of committed instruction 633system.cpu0.commit.op_class_0::FloatAdd 28001 0.05% 70.75% # Class of committed instruction 634system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction 635system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction 636system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction 637system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.76% # Class of committed instruction 638system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction 639system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction 640system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction 641system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction 642system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction 643system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction 644system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction 645system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction 646system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction 647system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction 648system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction 649system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction 650system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction 651system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction 652system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction 653system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction 654system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction 655system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction 656system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction 657system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction 658system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction 659system.cpu0.commit.op_class_0::MemRead 8806882 16.45% 87.21% # Class of committed instruction 660system.cpu0.commit.op_class_0::MemWrite 5976371 11.16% 98.37% # Class of committed instruction 661system.cpu0.commit.op_class_0::IprAccess 873773 1.63% 100.00% # Class of committed instruction 662system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 663system.cpu0.commit.op_class_0::total 53540971 # Class of committed instruction 664system.cpu0.commit.bw_lim_events 1924817 # number cycles where commit BW limit reached 665system.cpu0.rob.rob_reads 175788251 # The number of ROB reads 666system.cpu0.rob.rob_writes 132059822 # The number of ROB writes 667system.cpu0.timesIdled 545123 # Number of times that the entire CPU went into an idle state and unscheduled itself 668system.cpu0.idleCycles 5748465 # Total number of cycles that the CPU has spent unscheduled due to idling 669system.cpu0.quiesceCycles 3696064399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 670system.cpu0.committedInsts 50438489 # Number of Instructions Simulated 671system.cpu0.committedOps 50438489 # Number of Ops (including micro ops) Simulated 672system.cpu0.cpi 2.391319 # CPI: Cycles Per Instruction 673system.cpu0.cpi_total 2.391319 # CPI: Total CPI of All Threads 674system.cpu0.ipc 0.418179 # IPC: Instructions Per Cycle 675system.cpu0.ipc_total 0.418179 # IPC: Total IPC of All Threads 676system.cpu0.int_regfile_reads 73773620 # number of integer regfile reads 677system.cpu0.int_regfile_writes 40428970 # number of integer regfile writes 678system.cpu0.fp_regfile_reads 142673 # number of floating regfile reads 679system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes 680system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads 681system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes
	682system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
668system.cpu0.dcache.tags.replacements 1337856 # number of replacements 669system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use 670system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. 671system.cpu0.dcache.tags.sampled_refs 1338256 # Sample count of references to valid blocks. 672system.cpu0.dcache.tags.avg_refs 8.858896 # Average number of references to valid blocks. 673system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. 674system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.906059 # Average occupied blocks per requestor 675system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988098 # Average percentage of cache occupancy 676system.cpu0.dcache.tags.occ_percent::total 0.988098 # Average percentage of cache occupancy 677system.cpu0.dcache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id 678system.cpu0.dcache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id 679system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 680system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id 681system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses 682system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses	683system.cpu0.dcache.tags.replacements 1337856 # number of replacements 684system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use 685system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. 686system.cpu0.dcache.tags.sampled_refs 1338256 # Sample count of references to valid blocks. 687system.cpu0.dcache.tags.avg_refs 8.858896 # Average number of references to valid blocks. 688system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. 689system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.906059 # Average occupied blocks per requestor 690system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988098 # Average percentage of cache occupancy 691system.cpu0.dcache.tags.occ_percent::total 0.988098 # Average percentage of cache occupancy 692system.cpu0.dcache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id 693system.cpu0.dcache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id 694system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 695system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id 696system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses 697system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses
	698system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
683system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits 684system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits 685system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits 686system.cpu0.dcache.WriteReq_hits::total 3919891 # number of WriteReq hits 687system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 201495 # number of LoadLockedReq hits 688system.cpu0.dcache.LoadLockedReq_hits::total 201495 # number of LoadLockedReq hits 689system.cpu0.dcache.StoreCondReq_hits::cpu0.data 204000 # number of StoreCondReq hits 690system.cpu0.dcache.StoreCondReq_hits::total 204000 # number of StoreCondReq hits 691system.cpu0.dcache.demand_hits::cpu0.data 11448777 # number of demand (read+write) hits 692system.cpu0.dcache.demand_hits::total 11448777 # number of demand (read+write) hits 693system.cpu0.dcache.overall_hits::cpu0.data 11448777 # number of overall hits 694system.cpu0.dcache.overall_hits::total 11448777 # number of overall hits 695system.cpu0.dcache.ReadReq_misses::cpu0.data 1699683 # number of ReadReq misses 696system.cpu0.dcache.ReadReq_misses::total 1699683 # number of ReadReq misses 697system.cpu0.dcache.WriteReq_misses::cpu0.data 1831149 # number of WriteReq misses 698system.cpu0.dcache.WriteReq_misses::total 1831149 # number of WriteReq misses 699system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21973 # number of LoadLockedReq misses 700system.cpu0.dcache.LoadLockedReq_misses::total 21973 # number of LoadLockedReq misses 701system.cpu0.dcache.StoreCondReq_misses::cpu0.data 873 # number of StoreCondReq misses 702system.cpu0.dcache.StoreCondReq_misses::total 873 # number of StoreCondReq misses 703system.cpu0.dcache.demand_misses::cpu0.data 3530832 # number of demand (read+write) misses 704system.cpu0.dcache.demand_misses::total 3530832 # number of demand (read+write) misses 705system.cpu0.dcache.overall_misses::cpu0.data 3530832 # number of overall misses 706system.cpu0.dcache.overall_misses::total 3530832 # number of overall misses 707system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40671315500 # number of ReadReq miss cycles 708system.cpu0.dcache.ReadReq_miss_latency::total 40671315500 # number of ReadReq miss cycles 709system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77312811875 # number of WriteReq miss cycles 710system.cpu0.dcache.WriteReq_miss_latency::total 77312811875 # number of WriteReq miss cycles 711system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331728000 # number of LoadLockedReq miss cycles 712system.cpu0.dcache.LoadLockedReq_miss_latency::total 331728000 # number of LoadLockedReq miss cycles 713system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6457500 # number of StoreCondReq miss cycles 714system.cpu0.dcache.StoreCondReq_miss_latency::total 6457500 # number of StoreCondReq miss cycles 715system.cpu0.dcache.demand_miss_latency::cpu0.data 117984127375 # number of demand (read+write) miss cycles 716system.cpu0.dcache.demand_miss_latency::total 117984127375 # number of demand (read+write) miss cycles 717system.cpu0.dcache.overall_miss_latency::cpu0.data 117984127375 # number of overall miss cycles 718system.cpu0.dcache.overall_miss_latency::total 117984127375 # number of overall miss cycles 719system.cpu0.dcache.ReadReq_accesses::cpu0.data 9228569 # number of ReadReq accesses(hits+misses) 720system.cpu0.dcache.ReadReq_accesses::total 9228569 # number of ReadReq accesses(hits+misses) 721system.cpu0.dcache.WriteReq_accesses::cpu0.data 5751040 # number of WriteReq accesses(hits+misses) 722system.cpu0.dcache.WriteReq_accesses::total 5751040 # number of WriteReq accesses(hits+misses) 723system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223468 # number of LoadLockedReq accesses(hits+misses) 724system.cpu0.dcache.LoadLockedReq_accesses::total 223468 # number of LoadLockedReq accesses(hits+misses) 725system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 204873 # number of StoreCondReq accesses(hits+misses) 726system.cpu0.dcache.StoreCondReq_accesses::total 204873 # number of StoreCondReq accesses(hits+misses) 727system.cpu0.dcache.demand_accesses::cpu0.data 14979609 # number of demand (read+write) accesses 728system.cpu0.dcache.demand_accesses::total 14979609 # number of demand (read+write) accesses 729system.cpu0.dcache.overall_accesses::cpu0.data 14979609 # number of overall (read+write) accesses 730system.cpu0.dcache.overall_accesses::total 14979609 # number of overall (read+write) accesses 731system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184176 # miss rate for ReadReq accesses 732system.cpu0.dcache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses 733system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318403 # miss rate for WriteReq accesses 734system.cpu0.dcache.WriteReq_miss_rate::total 0.318403 # miss rate for WriteReq accesses 735system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098327 # miss rate for LoadLockedReq accesses 736system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098327 # miss rate for LoadLockedReq accesses 737system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004261 # miss rate for StoreCondReq accesses 738system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004261 # miss rate for StoreCondReq accesses 739system.cpu0.dcache.demand_miss_rate::cpu0.data 0.235709 # miss rate for demand accesses 740system.cpu0.dcache.demand_miss_rate::total 0.235709 # miss rate for demand accesses 741system.cpu0.dcache.overall_miss_rate::cpu0.data 0.235709 # miss rate for overall accesses 742system.cpu0.dcache.overall_miss_rate::total 0.235709 # miss rate for overall accesses 743system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23928.765246 # average ReadReq miss latency 744system.cpu0.dcache.ReadReq_avg_miss_latency::total 23928.765246 # average ReadReq miss latency 745system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.928977 # average WriteReq miss latency 746system.cpu0.dcache.WriteReq_avg_miss_latency::total 42220.928977 # average WriteReq miss latency 747system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15097.073681 # average LoadLockedReq miss latency 748system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15097.073681 # average LoadLockedReq miss latency 749system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7396.907216 # average StoreCondReq miss latency 750system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7396.907216 # average StoreCondReq miss latency 751system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency 752system.cpu0.dcache.demand_avg_miss_latency::total 33415.389737 # average overall miss latency 753system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency 754system.cpu0.dcache.overall_avg_miss_latency::total 33415.389737 # average overall miss latency 755system.cpu0.dcache.blocked_cycles::no_mshrs 4312836 # number of cycles access was blocked 756system.cpu0.dcache.blocked_cycles::no_targets 8080 # number of cycles access was blocked 757system.cpu0.dcache.blocked::no_mshrs 119422 # number of cycles access was blocked 758system.cpu0.dcache.blocked::no_targets 127 # number of cycles access was blocked 759system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.114250 # average number of cycles each access was blocked 760system.cpu0.dcache.avg_blocked_cycles::no_targets 63.622047 # average number of cycles each access was blocked 761system.cpu0.dcache.writebacks::writebacks 792748 # number of writebacks 762system.cpu0.dcache.writebacks::total 792748 # number of writebacks 763system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 643460 # number of ReadReq MSHR hits 764system.cpu0.dcache.ReadReq_mshr_hits::total 643460 # number of ReadReq MSHR hits 765system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1557660 # number of WriteReq MSHR hits 766system.cpu0.dcache.WriteReq_mshr_hits::total 1557660 # number of WriteReq MSHR hits 767system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6525 # number of LoadLockedReq MSHR hits 768system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6525 # number of LoadLockedReq MSHR hits 769system.cpu0.dcache.demand_mshr_hits::cpu0.data 2201120 # number of demand (read+write) MSHR hits 770system.cpu0.dcache.demand_mshr_hits::total 2201120 # number of demand (read+write) MSHR hits 771system.cpu0.dcache.overall_mshr_hits::cpu0.data 2201120 # number of overall MSHR hits 772system.cpu0.dcache.overall_mshr_hits::total 2201120 # number of overall MSHR hits 773system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1056223 # number of ReadReq MSHR misses 774system.cpu0.dcache.ReadReq_mshr_misses::total 1056223 # number of ReadReq MSHR misses 775system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273489 # number of WriteReq MSHR misses 776system.cpu0.dcache.WriteReq_mshr_misses::total 273489 # number of WriteReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15448 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15448 # number of LoadLockedReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 873 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.StoreCondReq_mshr_misses::total 873 # number of StoreCondReq MSHR misses 781system.cpu0.dcache.demand_mshr_misses::cpu0.data 1329712 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.demand_mshr_misses::total 1329712 # number of demand (read+write) MSHR misses 783system.cpu0.dcache.overall_mshr_misses::cpu0.data 1329712 # number of overall MSHR misses 784system.cpu0.dcache.overall_mshr_misses::total 1329712 # number of overall MSHR misses 785system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable 786system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7053 # number of ReadReq MSHR uncacheable 787system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable 788system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9807 # number of WriteReq MSHR uncacheable 789system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses 790system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16860 # number of overall MSHR uncacheable misses 791system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30297527500 # number of ReadReq MSHR miss cycles 792system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30297527500 # number of ReadReq MSHR miss cycles 793system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12178891856 # number of WriteReq MSHR miss cycles 794system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12178891856 # number of WriteReq MSHR miss cycles 795system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 190480500 # number of LoadLockedReq MSHR miss cycles 796system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 190480500 # number of LoadLockedReq MSHR miss cycles 797system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5584500 # number of StoreCondReq MSHR miss cycles 798system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5584500 # number of StoreCondReq MSHR miss cycles 799system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42476419356 # number of demand (read+write) MSHR miss cycles 800system.cpu0.dcache.demand_mshr_miss_latency::total 42476419356 # number of demand (read+write) MSHR miss cycles 801system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42476419356 # number of overall MSHR miss cycles 802system.cpu0.dcache.overall_mshr_miss_latency::total 42476419356 # number of overall MSHR miss cycles 803system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1570178500 # number of ReadReq MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1570178500 # number of ReadReq MSHR uncacheable cycles 805system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1570178500 # number of overall MSHR uncacheable cycles 806system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1570178500 # number of overall MSHR uncacheable cycles 807system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114451 # mshr miss rate for ReadReq accesses 808system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114451 # mshr miss rate for ReadReq accesses 809system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047555 # mshr miss rate for WriteReq accesses 810system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047555 # mshr miss rate for WriteReq accesses 811system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069128 # mshr miss rate for LoadLockedReq accesses 812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.069128 # mshr miss rate for LoadLockedReq accesses 813system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004261 # mshr miss rate for StoreCondReq accesses 814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004261 # mshr miss rate for StoreCondReq accesses 815system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for demand accesses 816system.cpu0.dcache.demand_mshr_miss_rate::total 0.088768 # mshr miss rate for demand accesses 817system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for overall accesses 818system.cpu0.dcache.overall_mshr_miss_rate::total 0.088768 # mshr miss rate for overall accesses 819system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28684.782948 # average ReadReq mshr miss latency 820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28684.782948 # average ReadReq mshr miss latency 821system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44531.560158 # average WriteReq mshr miss latency 822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44531.560158 # average WriteReq mshr miss latency 823system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12330.431124 # average LoadLockedReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.431124 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6396.907216 # average StoreCondReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6396.907216 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency 828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency 830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency 833system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency 834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency	699system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits 700system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits 701system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits 702system.cpu0.dcache.WriteReq_hits::total 3919891 # number of WriteReq hits 703system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 201495 # number of LoadLockedReq hits 704system.cpu0.dcache.LoadLockedReq_hits::total 201495 # number of LoadLockedReq hits 705system.cpu0.dcache.StoreCondReq_hits::cpu0.data 204000 # number of StoreCondReq hits 706system.cpu0.dcache.StoreCondReq_hits::total 204000 # number of StoreCondReq hits 707system.cpu0.dcache.demand_hits::cpu0.data 11448777 # number of demand (read+write) hits 708system.cpu0.dcache.demand_hits::total 11448777 # number of demand (read+write) hits 709system.cpu0.dcache.overall_hits::cpu0.data 11448777 # number of overall hits 710system.cpu0.dcache.overall_hits::total 11448777 # number of overall hits 711system.cpu0.dcache.ReadReq_misses::cpu0.data 1699683 # number of ReadReq misses 712system.cpu0.dcache.ReadReq_misses::total 1699683 # number of ReadReq misses 713system.cpu0.dcache.WriteReq_misses::cpu0.data 1831149 # number of WriteReq misses 714system.cpu0.dcache.WriteReq_misses::total 1831149 # number of WriteReq misses 715system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21973 # number of LoadLockedReq misses 716system.cpu0.dcache.LoadLockedReq_misses::total 21973 # number of LoadLockedReq misses 717system.cpu0.dcache.StoreCondReq_misses::cpu0.data 873 # number of StoreCondReq misses 718system.cpu0.dcache.StoreCondReq_misses::total 873 # number of StoreCondReq misses 719system.cpu0.dcache.demand_misses::cpu0.data 3530832 # number of demand (read+write) misses 720system.cpu0.dcache.demand_misses::total 3530832 # number of demand (read+write) misses 721system.cpu0.dcache.overall_misses::cpu0.data 3530832 # number of overall misses 722system.cpu0.dcache.overall_misses::total 3530832 # number of overall misses 723system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40671315500 # number of ReadReq miss cycles 724system.cpu0.dcache.ReadReq_miss_latency::total 40671315500 # number of ReadReq miss cycles 725system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77312811875 # number of WriteReq miss cycles 726system.cpu0.dcache.WriteReq_miss_latency::total 77312811875 # number of WriteReq miss cycles 727system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331728000 # number of LoadLockedReq miss cycles 728system.cpu0.dcache.LoadLockedReq_miss_latency::total 331728000 # number of LoadLockedReq miss cycles 729system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6457500 # number of StoreCondReq miss cycles 730system.cpu0.dcache.StoreCondReq_miss_latency::total 6457500 # number of StoreCondReq miss cycles 731system.cpu0.dcache.demand_miss_latency::cpu0.data 117984127375 # number of demand (read+write) miss cycles 732system.cpu0.dcache.demand_miss_latency::total 117984127375 # number of demand (read+write) miss cycles 733system.cpu0.dcache.overall_miss_latency::cpu0.data 117984127375 # number of overall miss cycles 734system.cpu0.dcache.overall_miss_latency::total 117984127375 # number of overall miss cycles 735system.cpu0.dcache.ReadReq_accesses::cpu0.data 9228569 # number of ReadReq accesses(hits+misses) 736system.cpu0.dcache.ReadReq_accesses::total 9228569 # number of ReadReq accesses(hits+misses) 737system.cpu0.dcache.WriteReq_accesses::cpu0.data 5751040 # number of WriteReq accesses(hits+misses) 738system.cpu0.dcache.WriteReq_accesses::total 5751040 # number of WriteReq accesses(hits+misses) 739system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223468 # number of LoadLockedReq accesses(hits+misses) 740system.cpu0.dcache.LoadLockedReq_accesses::total 223468 # number of LoadLockedReq accesses(hits+misses) 741system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 204873 # number of StoreCondReq accesses(hits+misses) 742system.cpu0.dcache.StoreCondReq_accesses::total 204873 # number of StoreCondReq accesses(hits+misses) 743system.cpu0.dcache.demand_accesses::cpu0.data 14979609 # number of demand (read+write) accesses 744system.cpu0.dcache.demand_accesses::total 14979609 # number of demand (read+write) accesses 745system.cpu0.dcache.overall_accesses::cpu0.data 14979609 # number of overall (read+write) accesses 746system.cpu0.dcache.overall_accesses::total 14979609 # number of overall (read+write) accesses 747system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184176 # miss rate for ReadReq accesses 748system.cpu0.dcache.ReadReq_miss_rate::total 0.184176 # miss rate for ReadReq accesses 749system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.318403 # miss rate for WriteReq accesses 750system.cpu0.dcache.WriteReq_miss_rate::total 0.318403 # miss rate for WriteReq accesses 751system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098327 # miss rate for LoadLockedReq accesses 752system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098327 # miss rate for LoadLockedReq accesses 753system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004261 # miss rate for StoreCondReq accesses 754system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004261 # miss rate for StoreCondReq accesses 755system.cpu0.dcache.demand_miss_rate::cpu0.data 0.235709 # miss rate for demand accesses 756system.cpu0.dcache.demand_miss_rate::total 0.235709 # miss rate for demand accesses 757system.cpu0.dcache.overall_miss_rate::cpu0.data 0.235709 # miss rate for overall accesses 758system.cpu0.dcache.overall_miss_rate::total 0.235709 # miss rate for overall accesses 759system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23928.765246 # average ReadReq miss latency 760system.cpu0.dcache.ReadReq_avg_miss_latency::total 23928.765246 # average ReadReq miss latency 761system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.928977 # average WriteReq miss latency 762system.cpu0.dcache.WriteReq_avg_miss_latency::total 42220.928977 # average WriteReq miss latency 763system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15097.073681 # average LoadLockedReq miss latency 764system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15097.073681 # average LoadLockedReq miss latency 765system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7396.907216 # average StoreCondReq miss latency 766system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7396.907216 # average StoreCondReq miss latency 767system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency 768system.cpu0.dcache.demand_avg_miss_latency::total 33415.389737 # average overall miss latency 769system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33415.389737 # average overall miss latency 770system.cpu0.dcache.overall_avg_miss_latency::total 33415.389737 # average overall miss latency 771system.cpu0.dcache.blocked_cycles::no_mshrs 4312836 # number of cycles access was blocked 772system.cpu0.dcache.blocked_cycles::no_targets 8080 # number of cycles access was blocked 773system.cpu0.dcache.blocked::no_mshrs 119422 # number of cycles access was blocked 774system.cpu0.dcache.blocked::no_targets 127 # number of cycles access was blocked 775system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.114250 # average number of cycles each access was blocked 776system.cpu0.dcache.avg_blocked_cycles::no_targets 63.622047 # average number of cycles each access was blocked 777system.cpu0.dcache.writebacks::writebacks 792748 # number of writebacks 778system.cpu0.dcache.writebacks::total 792748 # number of writebacks 779system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 643460 # number of ReadReq MSHR hits 780system.cpu0.dcache.ReadReq_mshr_hits::total 643460 # number of ReadReq MSHR hits 781system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1557660 # number of WriteReq MSHR hits 782system.cpu0.dcache.WriteReq_mshr_hits::total 1557660 # number of WriteReq MSHR hits 783system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6525 # number of LoadLockedReq MSHR hits 784system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6525 # number of LoadLockedReq MSHR hits 785system.cpu0.dcache.demand_mshr_hits::cpu0.data 2201120 # number of demand (read+write) MSHR hits 786system.cpu0.dcache.demand_mshr_hits::total 2201120 # number of demand (read+write) MSHR hits 787system.cpu0.dcache.overall_mshr_hits::cpu0.data 2201120 # number of overall MSHR hits 788system.cpu0.dcache.overall_mshr_hits::total 2201120 # number of overall MSHR hits 789system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1056223 # number of ReadReq MSHR misses 790system.cpu0.dcache.ReadReq_mshr_misses::total 1056223 # number of ReadReq MSHR misses 791system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273489 # number of WriteReq MSHR misses 792system.cpu0.dcache.WriteReq_mshr_misses::total 273489 # number of WriteReq MSHR misses 793system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15448 # number of LoadLockedReq MSHR misses 794system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15448 # number of LoadLockedReq MSHR misses 795system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 873 # number of StoreCondReq MSHR misses 796system.cpu0.dcache.StoreCondReq_mshr_misses::total 873 # number of StoreCondReq MSHR misses 797system.cpu0.dcache.demand_mshr_misses::cpu0.data 1329712 # number of demand (read+write) MSHR misses 798system.cpu0.dcache.demand_mshr_misses::total 1329712 # number of demand (read+write) MSHR misses 799system.cpu0.dcache.overall_mshr_misses::cpu0.data 1329712 # number of overall MSHR misses 800system.cpu0.dcache.overall_mshr_misses::total 1329712 # number of overall MSHR misses 801system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable 802system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7053 # number of ReadReq MSHR uncacheable 803system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable 804system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9807 # number of WriteReq MSHR uncacheable 805system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses 806system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16860 # number of overall MSHR uncacheable misses 807system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30297527500 # number of ReadReq MSHR miss cycles 808system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30297527500 # number of ReadReq MSHR miss cycles 809system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12178891856 # number of WriteReq MSHR miss cycles 810system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12178891856 # number of WriteReq MSHR miss cycles 811system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 190480500 # number of LoadLockedReq MSHR miss cycles 812system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 190480500 # number of LoadLockedReq MSHR miss cycles 813system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5584500 # number of StoreCondReq MSHR miss cycles 814system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5584500 # number of StoreCondReq MSHR miss cycles 815system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42476419356 # number of demand (read+write) MSHR miss cycles 816system.cpu0.dcache.demand_mshr_miss_latency::total 42476419356 # number of demand (read+write) MSHR miss cycles 817system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42476419356 # number of overall MSHR miss cycles 818system.cpu0.dcache.overall_mshr_miss_latency::total 42476419356 # number of overall MSHR miss cycles 819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1570178500 # number of ReadReq MSHR uncacheable cycles 820system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1570178500 # number of ReadReq MSHR uncacheable cycles 821system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1570178500 # number of overall MSHR uncacheable cycles 822system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1570178500 # number of overall MSHR uncacheable cycles 823system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114451 # mshr miss rate for ReadReq accesses 824system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114451 # mshr miss rate for ReadReq accesses 825system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047555 # mshr miss rate for WriteReq accesses 826system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047555 # mshr miss rate for WriteReq accesses 827system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069128 # mshr miss rate for LoadLockedReq accesses 828system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.069128 # mshr miss rate for LoadLockedReq accesses 829system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004261 # mshr miss rate for StoreCondReq accesses 830system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004261 # mshr miss rate for StoreCondReq accesses 831system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for demand accesses 832system.cpu0.dcache.demand_mshr_miss_rate::total 0.088768 # mshr miss rate for demand accesses 833system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088768 # mshr miss rate for overall accesses 834system.cpu0.dcache.overall_mshr_miss_rate::total 0.088768 # mshr miss rate for overall accesses 835system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28684.782948 # average ReadReq mshr miss latency 836system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28684.782948 # average ReadReq mshr miss latency 837system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44531.560158 # average WriteReq mshr miss latency 838system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44531.560158 # average WriteReq mshr miss latency 839system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12330.431124 # average LoadLockedReq mshr miss latency 840system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.431124 # average LoadLockedReq mshr miss latency 841system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6396.907216 # average StoreCondReq mshr miss latency 842system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6396.907216 # average StoreCondReq mshr miss latency 843system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency 844system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency 845system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31944.074624 # average overall mshr miss latency 846system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31944.074624 # average overall mshr miss latency 847system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 # average ReadReq mshr uncacheable latency 848system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency 849system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency 850system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency
	851system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
835system.cpu0.icache.tags.replacements 1021310 # number of replacements 836system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use 837system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. 838system.cpu0.icache.tags.sampled_refs 1021822 # Sample count of references to valid blocks. 839system.cpu0.icache.tags.avg_refs 8.022646 # Average number of references to valid blocks. 840system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. 841system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.519684 # Average occupied blocks per requestor 842system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995156 # Average percentage of cache occupancy 843system.cpu0.icache.tags.occ_percent::total 0.995156 # Average percentage of cache occupancy 844system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 845system.cpu0.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id 846system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 847system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 848system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses 849system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses	852system.cpu0.icache.tags.replacements 1021310 # number of replacements 853system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use 854system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. 855system.cpu0.icache.tags.sampled_refs 1021822 # Sample count of references to valid blocks. 856system.cpu0.icache.tags.avg_refs 8.022646 # Average number of references to valid blocks. 857system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. 858system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.519684 # Average occupied blocks per requestor 859system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995156 # Average percentage of cache occupancy 860system.cpu0.icache.tags.occ_percent::total 0.995156 # Average percentage of cache occupancy 861system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 862system.cpu0.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id 863system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id 864system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 865system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses 866system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses
	867system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
850system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits 851system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits 852system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits 853system.cpu0.icache.demand_hits::total 8197716 # number of demand (read+write) hits 854system.cpu0.icache.overall_hits::cpu0.inst 8197716 # number of overall hits 855system.cpu0.icache.overall_hits::total 8197716 # number of overall hits 856system.cpu0.icache.ReadReq_misses::cpu0.inst 1084226 # number of ReadReq misses 857system.cpu0.icache.ReadReq_misses::total 1084226 # number of ReadReq misses 858system.cpu0.icache.demand_misses::cpu0.inst 1084226 # number of demand (read+write) misses 859system.cpu0.icache.demand_misses::total 1084226 # number of demand (read+write) misses 860system.cpu0.icache.overall_misses::cpu0.inst 1084226 # number of overall misses 861system.cpu0.icache.overall_misses::total 1084226 # number of overall misses 862system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15369093993 # number of ReadReq miss cycles 863system.cpu0.icache.ReadReq_miss_latency::total 15369093993 # number of ReadReq miss cycles 864system.cpu0.icache.demand_miss_latency::cpu0.inst 15369093993 # number of demand (read+write) miss cycles 865system.cpu0.icache.demand_miss_latency::total 15369093993 # number of demand (read+write) miss cycles 866system.cpu0.icache.overall_miss_latency::cpu0.inst 15369093993 # number of overall miss cycles 867system.cpu0.icache.overall_miss_latency::total 15369093993 # number of overall miss cycles 868system.cpu0.icache.ReadReq_accesses::cpu0.inst 9281942 # number of ReadReq accesses(hits+misses) 869system.cpu0.icache.ReadReq_accesses::total 9281942 # number of ReadReq accesses(hits+misses) 870system.cpu0.icache.demand_accesses::cpu0.inst 9281942 # number of demand (read+write) accesses 871system.cpu0.icache.demand_accesses::total 9281942 # number of demand (read+write) accesses 872system.cpu0.icache.overall_accesses::cpu0.inst 9281942 # number of overall (read+write) accesses 873system.cpu0.icache.overall_accesses::total 9281942 # number of overall (read+write) accesses 874system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116810 # miss rate for ReadReq accesses 875system.cpu0.icache.ReadReq_miss_rate::total 0.116810 # miss rate for ReadReq accesses 876system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116810 # miss rate for demand accesses 877system.cpu0.icache.demand_miss_rate::total 0.116810 # miss rate for demand accesses 878system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116810 # miss rate for overall accesses 879system.cpu0.icache.overall_miss_rate::total 0.116810 # miss rate for overall accesses 880system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.175649 # average ReadReq miss latency 881system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.175649 # average ReadReq miss latency 882system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency 883system.cpu0.icache.demand_avg_miss_latency::total 14175.175649 # average overall miss latency 884system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency 885system.cpu0.icache.overall_avg_miss_latency::total 14175.175649 # average overall miss latency 886system.cpu0.icache.blocked_cycles::no_mshrs 5565 # number of cycles access was blocked 887system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu0.icache.blocked::no_mshrs 223 # number of cycles access was blocked 889system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.955157 # average number of cycles each access was blocked 891system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu0.icache.writebacks::writebacks 1021310 # number of writebacks 893system.cpu0.icache.writebacks::total 1021310 # number of writebacks 894system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 62188 # number of ReadReq MSHR hits 895system.cpu0.icache.ReadReq_mshr_hits::total 62188 # number of ReadReq MSHR hits 896system.cpu0.icache.demand_mshr_hits::cpu0.inst 62188 # number of demand (read+write) MSHR hits 897system.cpu0.icache.demand_mshr_hits::total 62188 # number of demand (read+write) MSHR hits 898system.cpu0.icache.overall_mshr_hits::cpu0.inst 62188 # number of overall MSHR hits 899system.cpu0.icache.overall_mshr_hits::total 62188 # number of overall MSHR hits 900system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1022038 # number of ReadReq MSHR misses 901system.cpu0.icache.ReadReq_mshr_misses::total 1022038 # number of ReadReq MSHR misses 902system.cpu0.icache.demand_mshr_misses::cpu0.inst 1022038 # number of demand (read+write) MSHR misses 903system.cpu0.icache.demand_mshr_misses::total 1022038 # number of demand (read+write) MSHR misses 904system.cpu0.icache.overall_mshr_misses::cpu0.inst 1022038 # number of overall MSHR misses 905system.cpu0.icache.overall_mshr_misses::total 1022038 # number of overall MSHR misses 906system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13659780995 # number of ReadReq MSHR miss cycles 907system.cpu0.icache.ReadReq_mshr_miss_latency::total 13659780995 # number of ReadReq MSHR miss cycles 908system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13659780995 # number of demand (read+write) MSHR miss cycles 909system.cpu0.icache.demand_mshr_miss_latency::total 13659780995 # number of demand (read+write) MSHR miss cycles 910system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13659780995 # number of overall MSHR miss cycles 911system.cpu0.icache.overall_mshr_miss_latency::total 13659780995 # number of overall MSHR miss cycles 912system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for ReadReq accesses 913system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110110 # mshr miss rate for ReadReq accesses 914system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for demand accesses 915system.cpu0.icache.demand_mshr_miss_rate::total 0.110110 # mshr miss rate for demand accesses 916system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for overall accesses 917system.cpu0.icache.overall_mshr_miss_rate::total 0.110110 # mshr miss rate for overall accesses 918system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average ReadReq mshr miss latency 919system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13365.237883 # average ReadReq mshr miss latency 920system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency 921system.cpu0.icache.demand_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency 922system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency 923system.cpu0.icache.overall_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency 924system.cpu1.branchPred.lookups 2642221 # Number of BP lookups 925system.cpu1.branchPred.condPredicted 2286827 # Number of conditional branches predicted 926system.cpu1.branchPred.condIncorrect 62241 # Number of conditional branches incorrect 927system.cpu1.branchPred.BTBLookups 1292185 # Number of BTB lookups 928system.cpu1.branchPred.BTBHits 477042 # Number of BTB hits 929system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 930system.cpu1.branchPred.BTBHitPct 36.917469 # BTB Hit Percentage 931system.cpu1.branchPred.usedRAS 126491 # Number of times the RAS was used to get a target. 932system.cpu1.branchPred.RASInCorrect 4205 # Number of incorrect RAS predictions. 933system.cpu1.branchPred.indirectLookups 709163 # Number of indirect predictor lookups. 934system.cpu1.branchPred.indirectHits 105030 # Number of indirect target hits. 935system.cpu1.branchPred.indirectMisses 604133 # Number of indirect misses. 936system.cpu1.branchPredindirectMispredicted 17634 # Number of mispredicted indirect branches. 937system.cpu1.dtb.fetch_hits 0 # ITB hits 938system.cpu1.dtb.fetch_misses 0 # ITB misses 939system.cpu1.dtb.fetch_acv 0 # ITB acv 940system.cpu1.dtb.fetch_accesses 0 # ITB accesses 941system.cpu1.dtb.read_hits 1454361 # DTB read hits 942system.cpu1.dtb.read_misses 11674 # DTB read misses 943system.cpu1.dtb.read_acv 55 # DTB read access violations 944system.cpu1.dtb.read_accesses 336696 # DTB read accesses 945system.cpu1.dtb.write_hits 804644 # DTB write hits 946system.cpu1.dtb.write_misses 2787 # DTB write misses 947system.cpu1.dtb.write_acv 46 # DTB write access violations 948system.cpu1.dtb.write_accesses 125975 # DTB write accesses 949system.cpu1.dtb.data_hits 2259005 # DTB hits 950system.cpu1.dtb.data_misses 14461 # DTB misses 951system.cpu1.dtb.data_acv 101 # DTB access violations 952system.cpu1.dtb.data_accesses 462671 # DTB accesses 953system.cpu1.itb.fetch_hits 472443 # ITB hits 954system.cpu1.itb.fetch_misses 2661 # ITB misses 955system.cpu1.itb.fetch_acv 95 # ITB acv 956system.cpu1.itb.fetch_accesses 475104 # ITB accesses 957system.cpu1.itb.read_hits 0 # DTB read hits 958system.cpu1.itb.read_misses 0 # DTB read misses 959system.cpu1.itb.read_acv 0 # DTB read access violations 960system.cpu1.itb.read_accesses 0 # DTB read accesses 961system.cpu1.itb.write_hits 0 # DTB write hits 962system.cpu1.itb.write_misses 0 # DTB write misses 963system.cpu1.itb.write_acv 0 # DTB write access violations 964system.cpu1.itb.write_accesses 0 # DTB write accesses 965system.cpu1.itb.data_hits 0 # DTB hits 966system.cpu1.itb.data_misses 0 # DTB misses 967system.cpu1.itb.data_acv 0 # DTB access violations 968system.cpu1.itb.data_accesses 0 # DTB accesses	868system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits 869system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits 870system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits 871system.cpu0.icache.demand_hits::total 8197716 # number of demand (read+write) hits 872system.cpu0.icache.overall_hits::cpu0.inst 8197716 # number of overall hits 873system.cpu0.icache.overall_hits::total 8197716 # number of overall hits 874system.cpu0.icache.ReadReq_misses::cpu0.inst 1084226 # number of ReadReq misses 875system.cpu0.icache.ReadReq_misses::total 1084226 # number of ReadReq misses 876system.cpu0.icache.demand_misses::cpu0.inst 1084226 # number of demand (read+write) misses 877system.cpu0.icache.demand_misses::total 1084226 # number of demand (read+write) misses 878system.cpu0.icache.overall_misses::cpu0.inst 1084226 # number of overall misses 879system.cpu0.icache.overall_misses::total 1084226 # number of overall misses 880system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15369093993 # number of ReadReq miss cycles 881system.cpu0.icache.ReadReq_miss_latency::total 15369093993 # number of ReadReq miss cycles 882system.cpu0.icache.demand_miss_latency::cpu0.inst 15369093993 # number of demand (read+write) miss cycles 883system.cpu0.icache.demand_miss_latency::total 15369093993 # number of demand (read+write) miss cycles 884system.cpu0.icache.overall_miss_latency::cpu0.inst 15369093993 # number of overall miss cycles 885system.cpu0.icache.overall_miss_latency::total 15369093993 # number of overall miss cycles 886system.cpu0.icache.ReadReq_accesses::cpu0.inst 9281942 # number of ReadReq accesses(hits+misses) 887system.cpu0.icache.ReadReq_accesses::total 9281942 # number of ReadReq accesses(hits+misses) 888system.cpu0.icache.demand_accesses::cpu0.inst 9281942 # number of demand (read+write) accesses 889system.cpu0.icache.demand_accesses::total 9281942 # number of demand (read+write) accesses 890system.cpu0.icache.overall_accesses::cpu0.inst 9281942 # number of overall (read+write) accesses 891system.cpu0.icache.overall_accesses::total 9281942 # number of overall (read+write) accesses 892system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116810 # miss rate for ReadReq accesses 893system.cpu0.icache.ReadReq_miss_rate::total 0.116810 # miss rate for ReadReq accesses 894system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116810 # miss rate for demand accesses 895system.cpu0.icache.demand_miss_rate::total 0.116810 # miss rate for demand accesses 896system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116810 # miss rate for overall accesses 897system.cpu0.icache.overall_miss_rate::total 0.116810 # miss rate for overall accesses 898system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.175649 # average ReadReq miss latency 899system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.175649 # average ReadReq miss latency 900system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency 901system.cpu0.icache.demand_avg_miss_latency::total 14175.175649 # average overall miss latency 902system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.175649 # average overall miss latency 903system.cpu0.icache.overall_avg_miss_latency::total 14175.175649 # average overall miss latency 904system.cpu0.icache.blocked_cycles::no_mshrs 5565 # number of cycles access was blocked 905system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 906system.cpu0.icache.blocked::no_mshrs 223 # number of cycles access was blocked 907system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 908system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.955157 # average number of cycles each access was blocked 909system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 910system.cpu0.icache.writebacks::writebacks 1021310 # number of writebacks 911system.cpu0.icache.writebacks::total 1021310 # number of writebacks 912system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 62188 # number of ReadReq MSHR hits 913system.cpu0.icache.ReadReq_mshr_hits::total 62188 # number of ReadReq MSHR hits 914system.cpu0.icache.demand_mshr_hits::cpu0.inst 62188 # number of demand (read+write) MSHR hits 915system.cpu0.icache.demand_mshr_hits::total 62188 # number of demand (read+write) MSHR hits 916system.cpu0.icache.overall_mshr_hits::cpu0.inst 62188 # number of overall MSHR hits 917system.cpu0.icache.overall_mshr_hits::total 62188 # number of overall MSHR hits 918system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1022038 # number of ReadReq MSHR misses 919system.cpu0.icache.ReadReq_mshr_misses::total 1022038 # number of ReadReq MSHR misses 920system.cpu0.icache.demand_mshr_misses::cpu0.inst 1022038 # number of demand (read+write) MSHR misses 921system.cpu0.icache.demand_mshr_misses::total 1022038 # number of demand (read+write) MSHR misses 922system.cpu0.icache.overall_mshr_misses::cpu0.inst 1022038 # number of overall MSHR misses 923system.cpu0.icache.overall_mshr_misses::total 1022038 # number of overall MSHR misses 924system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13659780995 # number of ReadReq MSHR miss cycles 925system.cpu0.icache.ReadReq_mshr_miss_latency::total 13659780995 # number of ReadReq MSHR miss cycles 926system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13659780995 # number of demand (read+write) MSHR miss cycles 927system.cpu0.icache.demand_mshr_miss_latency::total 13659780995 # number of demand (read+write) MSHR miss cycles 928system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13659780995 # number of overall MSHR miss cycles 929system.cpu0.icache.overall_mshr_miss_latency::total 13659780995 # number of overall MSHR miss cycles 930system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for ReadReq accesses 931system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110110 # mshr miss rate for ReadReq accesses 932system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for demand accesses 933system.cpu0.icache.demand_mshr_miss_rate::total 0.110110 # mshr miss rate for demand accesses 934system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110110 # mshr miss rate for overall accesses 935system.cpu0.icache.overall_mshr_miss_rate::total 0.110110 # mshr miss rate for overall accesses 936system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average ReadReq mshr miss latency 937system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13365.237883 # average ReadReq mshr miss latency 938system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency 939system.cpu0.icache.demand_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency 940system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13365.237883 # average overall mshr miss latency 941system.cpu0.icache.overall_avg_mshr_miss_latency::total 13365.237883 # average overall mshr miss latency 942system.cpu1.branchPred.lookups 2642221 # Number of BP lookups 943system.cpu1.branchPred.condPredicted 2286827 # Number of conditional branches predicted 944system.cpu1.branchPred.condIncorrect 62241 # Number of conditional branches incorrect 945system.cpu1.branchPred.BTBLookups 1292185 # Number of BTB lookups 946system.cpu1.branchPred.BTBHits 477042 # Number of BTB hits 947system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 948system.cpu1.branchPred.BTBHitPct 36.917469 # BTB Hit Percentage 949system.cpu1.branchPred.usedRAS 126491 # Number of times the RAS was used to get a target. 950system.cpu1.branchPred.RASInCorrect 4205 # Number of incorrect RAS predictions. 951system.cpu1.branchPred.indirectLookups 709163 # Number of indirect predictor lookups. 952system.cpu1.branchPred.indirectHits 105030 # Number of indirect target hits. 953system.cpu1.branchPred.indirectMisses 604133 # Number of indirect misses. 954system.cpu1.branchPredindirectMispredicted 17634 # Number of mispredicted indirect branches. 955system.cpu1.dtb.fetch_hits 0 # ITB hits 956system.cpu1.dtb.fetch_misses 0 # ITB misses 957system.cpu1.dtb.fetch_acv 0 # ITB acv 958system.cpu1.dtb.fetch_accesses 0 # ITB accesses 959system.cpu1.dtb.read_hits 1454361 # DTB read hits 960system.cpu1.dtb.read_misses 11674 # DTB read misses 961system.cpu1.dtb.read_acv 55 # DTB read access violations 962system.cpu1.dtb.read_accesses 336696 # DTB read accesses 963system.cpu1.dtb.write_hits 804644 # DTB write hits 964system.cpu1.dtb.write_misses 2787 # DTB write misses 965system.cpu1.dtb.write_acv 46 # DTB write access violations 966system.cpu1.dtb.write_accesses 125975 # DTB write accesses 967system.cpu1.dtb.data_hits 2259005 # DTB hits 968system.cpu1.dtb.data_misses 14461 # DTB misses 969system.cpu1.dtb.data_acv 101 # DTB access violations 970system.cpu1.dtb.data_accesses 462671 # DTB accesses 971system.cpu1.itb.fetch_hits 472443 # ITB hits 972system.cpu1.itb.fetch_misses 2661 # ITB misses 973system.cpu1.itb.fetch_acv 95 # ITB acv 974system.cpu1.itb.fetch_accesses 475104 # ITB accesses 975system.cpu1.itb.read_hits 0 # DTB read hits 976system.cpu1.itb.read_misses 0 # DTB read misses 977system.cpu1.itb.read_acv 0 # DTB read access violations 978system.cpu1.itb.read_accesses 0 # DTB read accesses 979system.cpu1.itb.write_hits 0 # DTB write hits 980system.cpu1.itb.write_misses 0 # DTB write misses 981system.cpu1.itb.write_acv 0 # DTB write access violations 982system.cpu1.itb.write_accesses 0 # DTB write accesses 983system.cpu1.itb.data_hits 0 # DTB hits 984system.cpu1.itb.data_misses 0 # DTB misses 985system.cpu1.itb.data_acv 0 # DTB access violations 986system.cpu1.itb.data_accesses 0 # DTB accesses
	987system.cpu1.numPwrStateTransitions 4618 # Number of power state transitions 988system.cpu1.pwrStateClkGateDist::samples 2309 # Distribution of time spent in the clock gated state 989system.cpu1.pwrStateClkGateDist::mean 824384353.183196 # Distribution of time spent in the clock gated state 990system.cpu1.pwrStateClkGateDist::stdev 333980461.680684 # Distribution of time spent in the clock gated state 991system.cpu1.pwrStateClkGateDist::1000-5e+10 2309 100.00% 100.00% # Distribution of time spent in the clock gated state 992system.cpu1.pwrStateClkGateDist::min_value 88500 # Distribution of time spent in the clock gated state 993system.cpu1.pwrStateClkGateDist::max_value 975572500 # Distribution of time spent in the clock gated state 994system.cpu1.pwrStateClkGateDist::total 2309 # Distribution of time spent in the clock gated state 995system.cpu1.pwrStateResidencyTicks::ON 5148616500 # Cumulative time (in ticks) in various power states 996system.cpu1.pwrStateResidencyTicks::CLK_GATED 1903503471500 # Cumulative time (in ticks) in various power states
969system.cpu1.numCycles 10299543 # number of cpu cycles simulated 970system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 971system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 972system.cpu1.fetch.icacheStallCycles 3708105 # Number of cycles fetch is stalled on an Icache miss 973system.cpu1.fetch.Insts 10416725 # Number of instructions fetch has processed 974system.cpu1.fetch.Branches 2642221 # Number of branches that fetch encountered 975system.cpu1.fetch.predictedBranches 708563 # Number of branches that fetch has predicted taken 976system.cpu1.fetch.Cycles 5867887 # Number of cycles fetch has run and was not squashing or blocked 977system.cpu1.fetch.SquashCycles 223660 # Number of cycles fetch has spent squashing 978system.cpu1.fetch.MiscStallCycles 23709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 979system.cpu1.fetch.PendingTrapStallCycles 51632 # Number of stall cycles due to pending traps 980system.cpu1.fetch.PendingQuiesceStallCycles 40219 # Number of stall cycles due to pending quiesce instructions 981system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR 982system.cpu1.fetch.CacheLines 1189367 # Number of cache lines fetched 983system.cpu1.fetch.IcacheSquashes 46143 # Number of outstanding Icache misses that were squashed 984system.cpu1.fetch.rateDist::samples 9803421 # Number of instructions fetched each cycle (Total) 985system.cpu1.fetch.rateDist::mean 1.062560 # Number of instructions fetched each cycle (Total) 986system.cpu1.fetch.rateDist::stdev 2.469546 # Number of instructions fetched each cycle (Total) 987system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 988system.cpu1.fetch.rateDist::0 7976409 81.36% 81.36% # Number of instructions fetched each cycle (Total) 989system.cpu1.fetch.rateDist::1 98791 1.01% 82.37% # Number of instructions fetched each cycle (Total) 990system.cpu1.fetch.rateDist::2 205509 2.10% 84.47% # Number of instructions fetched each cycle (Total) 991system.cpu1.fetch.rateDist::3 143569 1.46% 85.93% # Number of instructions fetched each cycle (Total) 992system.cpu1.fetch.rateDist::4 244577 2.49% 88.43% # Number of instructions fetched each cycle (Total) 993system.cpu1.fetch.rateDist::5 96035 0.98% 89.41% # Number of instructions fetched each cycle (Total) 994system.cpu1.fetch.rateDist::6 110446 1.13% 90.53% # Number of instructions fetched each cycle (Total) 995system.cpu1.fetch.rateDist::7 69630 0.71% 91.24% # Number of instructions fetched each cycle (Total) 996system.cpu1.fetch.rateDist::8 858455 8.76% 100.00% # Number of instructions fetched each cycle (Total) 997system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 998system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 999system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1000system.cpu1.fetch.rateDist::total 9803421 # Number of instructions fetched each cycle (Total) 1001system.cpu1.fetch.branchRate 0.256538 # Number of branch fetches per cycle 1002system.cpu1.fetch.rate 1.011377 # Number of inst fetches per cycle 1003system.cpu1.decode.IdleCycles 3120035 # Number of cycles decode is idle 1004system.cpu1.decode.BlockedCycles 5128574 # Number of cycles decode is blocked 1005system.cpu1.decode.RunCycles 1274002 # Number of cycles decode is running 1006system.cpu1.decode.UnblockCycles 173173 # Number of cycles decode is unblocking 1007system.cpu1.decode.SquashCycles 107636 # Number of cycles decode is squashing 1008system.cpu1.decode.BranchResolved 84669 # Number of times decode resolved a branch 1009system.cpu1.decode.BranchMispred 4317 # Number of times decode detected a branch misprediction 1010system.cpu1.decode.DecodedInsts 8395667 # Number of instructions handled by decode 1011system.cpu1.decode.SquashedInsts 13790 # Number of squashed instructions handled by decode 1012system.cpu1.rename.SquashCycles 107636 # Number of cycles rename is squashing 1013system.cpu1.rename.IdleCycles 3236399 # Number of cycles rename is idle 1014system.cpu1.rename.BlockCycles 505262 # Number of cycles rename is blocking 1015system.cpu1.rename.serializeStallCycles 3781107 # count of cycles rename stalled for serializing inst 1016system.cpu1.rename.RunCycles 1330090 # Number of cycles rename is running 1017system.cpu1.rename.UnblockCycles 842925 # Number of cycles rename is unblocking 1018system.cpu1.rename.RenamedInsts 7927045 # Number of instructions processed by rename 1019system.cpu1.rename.ROBFullEvents 866 # Number of times rename has blocked due to ROB full 1020system.cpu1.rename.IQFullEvents 80988 # Number of times rename has blocked due to IQ full 1021system.cpu1.rename.LQFullEvents 18891 # Number of times rename has blocked due to LQ full 1022system.cpu1.rename.SQFullEvents 445625 # Number of times rename has blocked due to SQ full 1023system.cpu1.rename.RenamedOperands 5308652 # Number of destination operands rename has renamed 1024system.cpu1.rename.RenameLookups 9558760 # Number of register rename lookups that rename has made 1025system.cpu1.rename.int_rename_lookups 9526496 # Number of integer rename lookups 1026system.cpu1.rename.fp_rename_lookups 27580 # Number of floating rename lookups 1027system.cpu1.rename.CommittedMaps 4111841 # Number of HB maps that are committed 1028system.cpu1.rename.UndoneMaps 1196803 # Number of HB maps that are undone due to squashing 1029system.cpu1.rename.serializingInsts 316905 # count of serializing insts renamed 1030system.cpu1.rename.tempSerializingInsts 22710 # count of temporary serializing insts renamed 1031system.cpu1.rename.skidInsts 1429971 # count of insts added to the skid buffer 1032system.cpu1.memDep0.insertedLoads 1508631 # Number of loads inserted to the mem dependence unit. 1033system.cpu1.memDep0.insertedStores 873340 # Number of stores inserted to the mem dependence unit. 1034system.cpu1.memDep0.conflictingLoads 185286 # Number of conflicting loads. 1035system.cpu1.memDep0.conflictingStores 107493 # Number of conflicting stores. 1036system.cpu1.iq.iqInstsAdded 6977977 # Number of instructions added to the IQ (excludes non-spec) 1037system.cpu1.iq.iqNonSpecInstsAdded 344578 # Number of non-speculative instructions added to the IQ 1038system.cpu1.iq.iqInstsIssued 6652421 # Number of instructions issued 1039system.cpu1.iq.iqSquashedInstsIssued 19333 # Number of squashed instructions issued 1040system.cpu1.iq.iqSquashedInstsExamined 1592530 # Number of squashed instructions iterated over during squash; mainly for profiling 1041system.cpu1.iq.iqSquashedOperandsExamined 796148 # Number of squashed operands that are examined and possibly removed from graph 1042system.cpu1.iq.iqSquashedNonSpecRemoved 266679 # Number of squashed non-spec instructions that were removed 1043system.cpu1.iq.issued_per_cycle::samples 9803421 # Number of insts issued each cycle 1044system.cpu1.iq.issued_per_cycle::mean 0.678582 # Number of insts issued each cycle 1045system.cpu1.iq.issued_per_cycle::stdev 1.403550 # Number of insts issued each cycle 1046system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1047system.cpu1.iq.issued_per_cycle::0 7053571 71.95% 71.95% # Number of insts issued each cycle 1048system.cpu1.iq.issued_per_cycle::1 1194265 12.18% 84.13% # Number of insts issued each cycle 1049system.cpu1.iq.issued_per_cycle::2 509519 5.20% 89.33% # Number of insts issued each cycle 1050system.cpu1.iq.issued_per_cycle::3 375157 3.83% 93.16% # Number of insts issued each cycle 1051system.cpu1.iq.issued_per_cycle::4 322481 3.29% 96.45% # Number of insts issued each cycle 1052system.cpu1.iq.issued_per_cycle::5 169260 1.73% 98.17% # Number of insts issued each cycle 1053system.cpu1.iq.issued_per_cycle::6 99294 1.01% 99.19% # Number of insts issued each cycle 1054system.cpu1.iq.issued_per_cycle::7 57333 0.58% 99.77% # Number of insts issued each cycle 1055system.cpu1.iq.issued_per_cycle::8 22541 0.23% 100.00% # Number of insts issued each cycle 1056system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1057system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1058system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1059system.cpu1.iq.issued_per_cycle::total 9803421 # Number of insts issued each cycle 1060system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1061system.cpu1.iq.fu_full::IntAlu 24978 11.96% 11.96% # attempts to use FU when none available 1062system.cpu1.iq.fu_full::IntMult 0 0.00% 11.96% # attempts to use FU when none available 1063system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.96% # attempts to use FU when none available 1064system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.96% # attempts to use FU when none available 1065system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.96% # attempts to use FU when none available 1066system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.96% # attempts to use FU when none available 1067system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.96% # attempts to use FU when none available 1068system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.96% # attempts to use FU when none available 1069system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.96% # attempts to use FU when none available 1070system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.96% # attempts to use FU when none available 1071system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.96% # attempts to use FU when none available 1072system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.96% # attempts to use FU when none available 1073system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.96% # attempts to use FU when none available 1074system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.96% # attempts to use FU when none available 1075system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.96% # attempts to use FU when none available 1076system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.96% # attempts to use FU when none available 1077system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.96% # attempts to use FU when none available 1078system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.96% # attempts to use FU when none available 1079system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.96% # attempts to use FU when none available 1080system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.96% # attempts to use FU when none available 1081system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.96% # attempts to use FU when none available 1082system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.96% # attempts to use FU when none available 1083system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.96% # attempts to use FU when none available 1084system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.96% # attempts to use FU when none available 1085system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.96% # attempts to use FU when none available 1086system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.96% # attempts to use FU when none available 1087system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.96% # attempts to use FU when none available 1088system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.96% # attempts to use FU when none available 1089system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.96% # attempts to use FU when none available 1090system.cpu1.iq.fu_full::MemRead 116023 55.55% 67.51% # attempts to use FU when none available 1091system.cpu1.iq.fu_full::MemWrite 67859 32.49% 100.00% # attempts to use FU when none available 1092system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1093system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1094system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued 1095system.cpu1.iq.FU_type_0::IntAlu 4085085 61.41% 61.47% # Type of FU issued 1096system.cpu1.iq.FU_type_0::IntMult 10572 0.16% 61.63% # Type of FU issued 1097system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.63% # Type of FU issued 1098system.cpu1.iq.FU_type_0::FloatAdd 10292 0.15% 61.78% # Type of FU issued 1099system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued 1100system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued 1101system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued 1102system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.81% # Type of FU issued 1103system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.81% # Type of FU issued 1104system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.81% # Type of FU issued 1105system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.81% # Type of FU issued 1106system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.81% # Type of FU issued 1107system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.81% # Type of FU issued 1108system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.81% # Type of FU issued 1109system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.81% # Type of FU issued 1110system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.81% # Type of FU issued 1111system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.81% # Type of FU issued 1112system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.81% # Type of FU issued 1113system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.81% # Type of FU issued 1114system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.81% # Type of FU issued 1115system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.81% # Type of FU issued 1116system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.81% # Type of FU issued 1117system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.81% # Type of FU issued 1118system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.81% # Type of FU issued 1119system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.81% # Type of FU issued 1120system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.81% # Type of FU issued 1121system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued 1122system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued 1123system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued 1124system.cpu1.iq.FU_type_0::MemRead 1521104 22.87% 84.68% # Type of FU issued 1125system.cpu1.iq.FU_type_0::MemWrite 824727 12.40% 97.07% # Type of FU issued 1126system.cpu1.iq.FU_type_0::IprAccess 194682 2.93% 100.00% # Type of FU issued 1127system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1128system.cpu1.iq.FU_type_0::total 6652421 # Type of FU issued 1129system.cpu1.iq.rate 0.645895 # Inst issue rate 1130system.cpu1.iq.fu_busy_cnt 208860 # FU busy when requested 1131system.cpu1.iq.fu_busy_rate 0.031396 # FU busy rate (busy events/executed inst) 1132system.cpu1.iq.int_inst_queue_reads 23247701 # Number of integer instruction queue reads 1133system.cpu1.iq.int_inst_queue_writes 8874149 # Number of integer instruction queue writes 1134system.cpu1.iq.int_inst_queue_wakeup_accesses 6353252 # Number of integer instruction queue wakeup accesses 1135system.cpu1.iq.fp_inst_queue_reads 88754 # Number of floating instruction queue reads 1136system.cpu1.iq.fp_inst_queue_writes 44866 # Number of floating instruction queue writes 1137system.cpu1.iq.fp_inst_queue_wakeup_accesses 42405 # Number of floating instruction queue wakeup accesses 1138system.cpu1.iq.int_alu_accesses 6811194 # Number of integer alu accesses 1139system.cpu1.iq.fp_alu_accesses 46114 # Number of floating point alu accesses 1140system.cpu1.iew.lsq.thread0.forwLoads 75849 # Number of loads that had data forwarded from stores 1141system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1142system.cpu1.iew.lsq.thread0.squashedLoads 328260 # Number of loads squashed 1143system.cpu1.iew.lsq.thread0.ignoredResponses 949 # Number of memory responses ignored because the instruction is squashed 1144system.cpu1.iew.lsq.thread0.memOrderViolation 4058 # Number of memory ordering violations 1145system.cpu1.iew.lsq.thread0.squashedStores 119869 # Number of stores squashed 1146system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1147system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1148system.cpu1.iew.lsq.thread0.rescheduledLoads 415 # Number of loads that were rescheduled 1149system.cpu1.iew.lsq.thread0.cacheBlocked 72546 # Number of times an access to memory failed due to the cache being blocked 1150system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1151system.cpu1.iew.iewSquashCycles 107636 # Number of cycles IEW is squashing 1152system.cpu1.iew.iewBlockCycles 325014 # Number of cycles IEW is blocking 1153system.cpu1.iew.iewUnblockCycles 147509 # Number of cycles IEW is unblocking 1154system.cpu1.iew.iewDispatchedInsts 7654698 # Number of instructions dispatched to IQ 1155system.cpu1.iew.iewDispSquashedInsts 36160 # Number of squashed instructions skipped by dispatch 1156system.cpu1.iew.iewDispLoadInsts 1508631 # Number of dispatched load instructions 1157system.cpu1.iew.iewDispStoreInsts 873340 # Number of dispatched store instructions 1158system.cpu1.iew.iewDispNonSpecInsts 319432 # Number of dispatched non-speculative instructions 1159system.cpu1.iew.iewIQFullEvents 4857 # Number of times the IQ has become full, causing a stall 1160system.cpu1.iew.iewLSQFullEvents 141756 # Number of times the LSQ has become full, causing a stall 1161system.cpu1.iew.memOrderViolationEvents 4058 # Number of memory order violations 1162system.cpu1.iew.predictedTakenIncorrect 24786 # Number of branches that were predicted taken incorrectly 1163system.cpu1.iew.predictedNotTakenIncorrect 89639 # Number of branches that were predicted not taken incorrectly 1164system.cpu1.iew.branchMispredicts 114425 # Number of branch mispredicts detected at execute 1165system.cpu1.iew.iewExecutedInsts 6540293 # Number of executed instructions 1166system.cpu1.iew.iewExecLoadInsts 1470121 # Number of load instructions executed 1167system.cpu1.iew.iewExecSquashedInsts 112127 # Number of squashed instructions skipped in execute 1168system.cpu1.iew.exec_swp 0 # number of swp insts executed 1169system.cpu1.iew.exec_nop 332143 # number of nop insts executed 1170system.cpu1.iew.exec_refs 2281164 # number of memory reference insts executed 1171system.cpu1.iew.exec_branches 956130 # Number of branches executed 1172system.cpu1.iew.exec_stores 811043 # Number of stores executed 1173system.cpu1.iew.exec_rate 0.635008 # Inst execution rate 1174system.cpu1.iew.wb_sent 6430736 # cumulative count of insts sent to commit 1175system.cpu1.iew.wb_count 6395657 # cumulative count of insts written-back 1176system.cpu1.iew.wb_producers 3121788 # num instructions producing a value 1177system.cpu1.iew.wb_consumers 4363189 # num instructions consuming a value 1178system.cpu1.iew.wb_rate 0.620965 # insts written-back per cycle 1179system.cpu1.iew.wb_fanout 0.715483 # average fanout of values written-back 1180system.cpu1.commit.commitSquashedInsts 1558734 # The number of squashed insts skipped by commit 1181system.cpu1.commit.commitNonSpecStalls 77899 # The number of times commit has been forced to stall to communicate backwards 1182system.cpu1.commit.branchMispredicts 97361 # The number of times a branch was mispredicted 1183system.cpu1.commit.committed_per_cycle::samples 9525282 # Number of insts commited each cycle 1184system.cpu1.commit.committed_per_cycle::mean 0.626287 # Number of insts commited each cycle 1185system.cpu1.commit.committed_per_cycle::stdev 1.584809 # Number of insts commited each cycle 1186system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1187system.cpu1.commit.committed_per_cycle::0 7314942 76.80% 76.80% # Number of insts commited each cycle 1188system.cpu1.commit.committed_per_cycle::1 1051446 11.04% 87.83% # Number of insts commited each cycle 1189system.cpu1.commit.committed_per_cycle::2 355573 3.73% 91.57% # Number of insts commited each cycle 1190system.cpu1.commit.committed_per_cycle::3 228997 2.40% 93.97% # Number of insts commited each cycle 1191system.cpu1.commit.committed_per_cycle::4 163534 1.72% 95.69% # Number of insts commited each cycle 1192system.cpu1.commit.committed_per_cycle::5 72316 0.76% 96.45% # Number of insts commited each cycle 1193system.cpu1.commit.committed_per_cycle::6 75781 0.80% 97.24% # Number of insts commited each cycle 1194system.cpu1.commit.committed_per_cycle::7 55973 0.59% 97.83% # Number of insts commited each cycle 1195system.cpu1.commit.committed_per_cycle::8 206720 2.17% 100.00% # Number of insts commited each cycle 1196system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1197system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1198system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1199system.cpu1.commit.committed_per_cycle::total 9525282 # Number of insts commited each cycle 1200system.cpu1.commit.committedInsts 5965556 # Number of instructions committed 1201system.cpu1.commit.committedOps 5965556 # Number of ops (including micro ops) committed 1202system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1203system.cpu1.commit.refs 1933842 # Number of memory references committed 1204system.cpu1.commit.loads 1180371 # Number of loads committed 1205system.cpu1.commit.membars 21608 # Number of memory barriers committed 1206system.cpu1.commit.branches 842250 # Number of branches committed 1207system.cpu1.commit.fp_insts 40666 # Number of committed floating point instructions. 1208system.cpu1.commit.int_insts 5575941 # Number of committed integer instructions. 1209system.cpu1.commit.function_calls 91630 # Number of function calls committed. 1210system.cpu1.commit.op_class_0::No_OpClass 239508 4.01% 4.01% # Class of committed instruction 1211system.cpu1.commit.op_class_0::IntAlu 3553035 59.56% 63.57% # Class of committed instruction 1212system.cpu1.commit.op_class_0::IntMult 10403 0.17% 63.75% # Class of committed instruction 1213system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.75% # Class of committed instruction 1214system.cpu1.commit.op_class_0::FloatAdd 10285 0.17% 63.92% # Class of committed instruction 1215system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.92% # Class of committed instruction 1216system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.92% # Class of committed instruction 1217system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.92% # Class of committed instruction 1218system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.95% # Class of committed instruction 1219system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.95% # Class of committed instruction 1220system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.95% # Class of committed instruction 1221system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.95% # Class of committed instruction 1222system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.95% # Class of committed instruction 1223system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.95% # Class of committed instruction 1224system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.95% # Class of committed instruction 1225system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.95% # Class of committed instruction 1226system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.95% # Class of committed instruction 1227system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.95% # Class of committed instruction 1228system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.95% # Class of committed instruction 1229system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.95% # Class of committed instruction 1230system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.95% # Class of committed instruction 1231system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.95% # Class of committed instruction 1232system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.95% # Class of committed instruction 1233system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.95% # Class of committed instruction 1234system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.95% # Class of committed instruction 1235system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.95% # Class of committed instruction 1236system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.95% # Class of committed instruction 1237system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.95% # Class of committed instruction 1238system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.95% # Class of committed instruction 1239system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.95% # Class of committed instruction 1240system.cpu1.commit.op_class_0::MemRead 1201979 20.15% 84.10% # Class of committed instruction 1241system.cpu1.commit.op_class_0::MemWrite 753678 12.63% 96.74% # Class of committed instruction 1242system.cpu1.commit.op_class_0::IprAccess 194682 3.26% 100.00% # Class of committed instruction 1243system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1244system.cpu1.commit.op_class_0::total 5965556 # Class of committed instruction 1245system.cpu1.commit.bw_lim_events 206720 # number cycles where commit BW limit reached 1246system.cpu1.rob.rob_reads 16752551 # The number of ROB reads 1247system.cpu1.rob.rob_writes 15324043 # The number of ROB writes 1248system.cpu1.timesIdled 69166 # Number of times that the entire CPU went into an idle state and unscheduled itself 1249system.cpu1.idleCycles 496122 # Total number of cycles that the CPU has spent unscheduled due to idling 1250system.cpu1.quiesceCycles 3807004634 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1251system.cpu1.committedInsts 5730020 # Number of Instructions Simulated 1252system.cpu1.committedOps 5730020 # Number of Ops (including micro ops) Simulated 1253system.cpu1.cpi 1.797471 # CPI: Cycles Per Instruction 1254system.cpu1.cpi_total 1.797471 # CPI: Total CPI of All Threads 1255system.cpu1.ipc 0.556337 # IPC: Instructions Per Cycle 1256system.cpu1.ipc_total 0.556337 # IPC: Total IPC of All Threads 1257system.cpu1.int_regfile_reads 8470716 # number of integer regfile reads 1258system.cpu1.int_regfile_writes 4619691 # number of integer regfile writes 1259system.cpu1.fp_regfile_reads 26922 # number of floating regfile reads 1260system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes 1261system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads 1262system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes	997system.cpu1.numCycles 10299543 # number of cpu cycles simulated 998system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 999system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1000system.cpu1.fetch.icacheStallCycles 3708105 # Number of cycles fetch is stalled on an Icache miss 1001system.cpu1.fetch.Insts 10416725 # Number of instructions fetch has processed 1002system.cpu1.fetch.Branches 2642221 # Number of branches that fetch encountered 1003system.cpu1.fetch.predictedBranches 708563 # Number of branches that fetch has predicted taken 1004system.cpu1.fetch.Cycles 5867887 # Number of cycles fetch has run and was not squashing or blocked 1005system.cpu1.fetch.SquashCycles 223660 # Number of cycles fetch has spent squashing 1006system.cpu1.fetch.MiscStallCycles 23709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1007system.cpu1.fetch.PendingTrapStallCycles 51632 # Number of stall cycles due to pending traps 1008system.cpu1.fetch.PendingQuiesceStallCycles 40219 # Number of stall cycles due to pending quiesce instructions 1009system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR 1010system.cpu1.fetch.CacheLines 1189367 # Number of cache lines fetched 1011system.cpu1.fetch.IcacheSquashes 46143 # Number of outstanding Icache misses that were squashed 1012system.cpu1.fetch.rateDist::samples 9803421 # Number of instructions fetched each cycle (Total) 1013system.cpu1.fetch.rateDist::mean 1.062560 # Number of instructions fetched each cycle (Total) 1014system.cpu1.fetch.rateDist::stdev 2.469546 # Number of instructions fetched each cycle (Total) 1015system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1016system.cpu1.fetch.rateDist::0 7976409 81.36% 81.36% # Number of instructions fetched each cycle (Total) 1017system.cpu1.fetch.rateDist::1 98791 1.01% 82.37% # Number of instructions fetched each cycle (Total) 1018system.cpu1.fetch.rateDist::2 205509 2.10% 84.47% # Number of instructions fetched each cycle (Total) 1019system.cpu1.fetch.rateDist::3 143569 1.46% 85.93% # Number of instructions fetched each cycle (Total) 1020system.cpu1.fetch.rateDist::4 244577 2.49% 88.43% # Number of instructions fetched each cycle (Total) 1021system.cpu1.fetch.rateDist::5 96035 0.98% 89.41% # Number of instructions fetched each cycle (Total) 1022system.cpu1.fetch.rateDist::6 110446 1.13% 90.53% # Number of instructions fetched each cycle (Total) 1023system.cpu1.fetch.rateDist::7 69630 0.71% 91.24% # Number of instructions fetched each cycle (Total) 1024system.cpu1.fetch.rateDist::8 858455 8.76% 100.00% # Number of instructions fetched each cycle (Total) 1025system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1026system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1027system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1028system.cpu1.fetch.rateDist::total 9803421 # Number of instructions fetched each cycle (Total) 1029system.cpu1.fetch.branchRate 0.256538 # Number of branch fetches per cycle 1030system.cpu1.fetch.rate 1.011377 # Number of inst fetches per cycle 1031system.cpu1.decode.IdleCycles 3120035 # Number of cycles decode is idle 1032system.cpu1.decode.BlockedCycles 5128574 # Number of cycles decode is blocked 1033system.cpu1.decode.RunCycles 1274002 # Number of cycles decode is running 1034system.cpu1.decode.UnblockCycles 173173 # Number of cycles decode is unblocking 1035system.cpu1.decode.SquashCycles 107636 # Number of cycles decode is squashing 1036system.cpu1.decode.BranchResolved 84669 # Number of times decode resolved a branch 1037system.cpu1.decode.BranchMispred 4317 # Number of times decode detected a branch misprediction 1038system.cpu1.decode.DecodedInsts 8395667 # Number of instructions handled by decode 1039system.cpu1.decode.SquashedInsts 13790 # Number of squashed instructions handled by decode 1040system.cpu1.rename.SquashCycles 107636 # Number of cycles rename is squashing 1041system.cpu1.rename.IdleCycles 3236399 # Number of cycles rename is idle 1042system.cpu1.rename.BlockCycles 505262 # Number of cycles rename is blocking 1043system.cpu1.rename.serializeStallCycles 3781107 # count of cycles rename stalled for serializing inst 1044system.cpu1.rename.RunCycles 1330090 # Number of cycles rename is running 1045system.cpu1.rename.UnblockCycles 842925 # Number of cycles rename is unblocking 1046system.cpu1.rename.RenamedInsts 7927045 # Number of instructions processed by rename 1047system.cpu1.rename.ROBFullEvents 866 # Number of times rename has blocked due to ROB full 1048system.cpu1.rename.IQFullEvents 80988 # Number of times rename has blocked due to IQ full 1049system.cpu1.rename.LQFullEvents 18891 # Number of times rename has blocked due to LQ full 1050system.cpu1.rename.SQFullEvents 445625 # Number of times rename has blocked due to SQ full 1051system.cpu1.rename.RenamedOperands 5308652 # Number of destination operands rename has renamed 1052system.cpu1.rename.RenameLookups 9558760 # Number of register rename lookups that rename has made 1053system.cpu1.rename.int_rename_lookups 9526496 # Number of integer rename lookups 1054system.cpu1.rename.fp_rename_lookups 27580 # Number of floating rename lookups 1055system.cpu1.rename.CommittedMaps 4111841 # Number of HB maps that are committed 1056system.cpu1.rename.UndoneMaps 1196803 # Number of HB maps that are undone due to squashing 1057system.cpu1.rename.serializingInsts 316905 # count of serializing insts renamed 1058system.cpu1.rename.tempSerializingInsts 22710 # count of temporary serializing insts renamed 1059system.cpu1.rename.skidInsts 1429971 # count of insts added to the skid buffer 1060system.cpu1.memDep0.insertedLoads 1508631 # Number of loads inserted to the mem dependence unit. 1061system.cpu1.memDep0.insertedStores 873340 # Number of stores inserted to the mem dependence unit. 1062system.cpu1.memDep0.conflictingLoads 185286 # Number of conflicting loads. 1063system.cpu1.memDep0.conflictingStores 107493 # Number of conflicting stores. 1064system.cpu1.iq.iqInstsAdded 6977977 # Number of instructions added to the IQ (excludes non-spec) 1065system.cpu1.iq.iqNonSpecInstsAdded 344578 # Number of non-speculative instructions added to the IQ 1066system.cpu1.iq.iqInstsIssued 6652421 # Number of instructions issued 1067system.cpu1.iq.iqSquashedInstsIssued 19333 # Number of squashed instructions issued 1068system.cpu1.iq.iqSquashedInstsExamined 1592530 # Number of squashed instructions iterated over during squash; mainly for profiling 1069system.cpu1.iq.iqSquashedOperandsExamined 796148 # Number of squashed operands that are examined and possibly removed from graph 1070system.cpu1.iq.iqSquashedNonSpecRemoved 266679 # Number of squashed non-spec instructions that were removed 1071system.cpu1.iq.issued_per_cycle::samples 9803421 # Number of insts issued each cycle 1072system.cpu1.iq.issued_per_cycle::mean 0.678582 # Number of insts issued each cycle 1073system.cpu1.iq.issued_per_cycle::stdev 1.403550 # Number of insts issued each cycle 1074system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1075system.cpu1.iq.issued_per_cycle::0 7053571 71.95% 71.95% # Number of insts issued each cycle 1076system.cpu1.iq.issued_per_cycle::1 1194265 12.18% 84.13% # Number of insts issued each cycle 1077system.cpu1.iq.issued_per_cycle::2 509519 5.20% 89.33% # Number of insts issued each cycle 1078system.cpu1.iq.issued_per_cycle::3 375157 3.83% 93.16% # Number of insts issued each cycle 1079system.cpu1.iq.issued_per_cycle::4 322481 3.29% 96.45% # Number of insts issued each cycle 1080system.cpu1.iq.issued_per_cycle::5 169260 1.73% 98.17% # Number of insts issued each cycle 1081system.cpu1.iq.issued_per_cycle::6 99294 1.01% 99.19% # Number of insts issued each cycle 1082system.cpu1.iq.issued_per_cycle::7 57333 0.58% 99.77% # Number of insts issued each cycle 1083system.cpu1.iq.issued_per_cycle::8 22541 0.23% 100.00% # Number of insts issued each cycle 1084system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1085system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1086system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1087system.cpu1.iq.issued_per_cycle::total 9803421 # Number of insts issued each cycle 1088system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1089system.cpu1.iq.fu_full::IntAlu 24978 11.96% 11.96% # attempts to use FU when none available 1090system.cpu1.iq.fu_full::IntMult 0 0.00% 11.96% # attempts to use FU when none available 1091system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.96% # attempts to use FU when none available 1092system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.96% # attempts to use FU when none available 1093system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.96% # attempts to use FU when none available 1094system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.96% # attempts to use FU when none available 1095system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.96% # attempts to use FU when none available 1096system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.96% # attempts to use FU when none available 1097system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.96% # attempts to use FU when none available 1098system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.96% # attempts to use FU when none available 1099system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.96% # attempts to use FU when none available 1100system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.96% # attempts to use FU when none available 1101system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.96% # attempts to use FU when none available 1102system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.96% # attempts to use FU when none available 1103system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.96% # attempts to use FU when none available 1104system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.96% # attempts to use FU when none available 1105system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.96% # attempts to use FU when none available 1106system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.96% # attempts to use FU when none available 1107system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.96% # attempts to use FU when none available 1108system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.96% # attempts to use FU when none available 1109system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.96% # attempts to use FU when none available 1110system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.96% # attempts to use FU when none available 1111system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.96% # attempts to use FU when none available 1112system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.96% # attempts to use FU when none available 1113system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.96% # attempts to use FU when none available 1114system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.96% # attempts to use FU when none available 1115system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.96% # attempts to use FU when none available 1116system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.96% # attempts to use FU when none available 1117system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.96% # attempts to use FU when none available 1118system.cpu1.iq.fu_full::MemRead 116023 55.55% 67.51% # attempts to use FU when none available 1119system.cpu1.iq.fu_full::MemWrite 67859 32.49% 100.00% # attempts to use FU when none available 1120system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1121system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1122system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued 1123system.cpu1.iq.FU_type_0::IntAlu 4085085 61.41% 61.47% # Type of FU issued 1124system.cpu1.iq.FU_type_0::IntMult 10572 0.16% 61.63% # Type of FU issued 1125system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.63% # Type of FU issued 1126system.cpu1.iq.FU_type_0::FloatAdd 10292 0.15% 61.78% # Type of FU issued 1127system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued 1128system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued 1129system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued 1130system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.81% # Type of FU issued 1131system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.81% # Type of FU issued 1132system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.81% # Type of FU issued 1133system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.81% # Type of FU issued 1134system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.81% # Type of FU issued 1135system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.81% # Type of FU issued 1136system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.81% # Type of FU issued 1137system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.81% # Type of FU issued 1138system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.81% # Type of FU issued 1139system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.81% # Type of FU issued 1140system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.81% # Type of FU issued 1141system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.81% # Type of FU issued 1142system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.81% # Type of FU issued 1143system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.81% # Type of FU issued 1144system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.81% # Type of FU issued 1145system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.81% # Type of FU issued 1146system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.81% # Type of FU issued 1147system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.81% # Type of FU issued 1148system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.81% # Type of FU issued 1149system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued 1150system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued 1151system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued 1152system.cpu1.iq.FU_type_0::MemRead 1521104 22.87% 84.68% # Type of FU issued 1153system.cpu1.iq.FU_type_0::MemWrite 824727 12.40% 97.07% # Type of FU issued 1154system.cpu1.iq.FU_type_0::IprAccess 194682 2.93% 100.00% # Type of FU issued 1155system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1156system.cpu1.iq.FU_type_0::total 6652421 # Type of FU issued 1157system.cpu1.iq.rate 0.645895 # Inst issue rate 1158system.cpu1.iq.fu_busy_cnt 208860 # FU busy when requested 1159system.cpu1.iq.fu_busy_rate 0.031396 # FU busy rate (busy events/executed inst) 1160system.cpu1.iq.int_inst_queue_reads 23247701 # Number of integer instruction queue reads 1161system.cpu1.iq.int_inst_queue_writes 8874149 # Number of integer instruction queue writes 1162system.cpu1.iq.int_inst_queue_wakeup_accesses 6353252 # Number of integer instruction queue wakeup accesses 1163system.cpu1.iq.fp_inst_queue_reads 88754 # Number of floating instruction queue reads 1164system.cpu1.iq.fp_inst_queue_writes 44866 # Number of floating instruction queue writes 1165system.cpu1.iq.fp_inst_queue_wakeup_accesses 42405 # Number of floating instruction queue wakeup accesses 1166system.cpu1.iq.int_alu_accesses 6811194 # Number of integer alu accesses 1167system.cpu1.iq.fp_alu_accesses 46114 # Number of floating point alu accesses 1168system.cpu1.iew.lsq.thread0.forwLoads 75849 # Number of loads that had data forwarded from stores 1169system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1170system.cpu1.iew.lsq.thread0.squashedLoads 328260 # Number of loads squashed 1171system.cpu1.iew.lsq.thread0.ignoredResponses 949 # Number of memory responses ignored because the instruction is squashed 1172system.cpu1.iew.lsq.thread0.memOrderViolation 4058 # Number of memory ordering violations 1173system.cpu1.iew.lsq.thread0.squashedStores 119869 # Number of stores squashed 1174system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1175system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1176system.cpu1.iew.lsq.thread0.rescheduledLoads 415 # Number of loads that were rescheduled 1177system.cpu1.iew.lsq.thread0.cacheBlocked 72546 # Number of times an access to memory failed due to the cache being blocked 1178system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1179system.cpu1.iew.iewSquashCycles 107636 # Number of cycles IEW is squashing 1180system.cpu1.iew.iewBlockCycles 325014 # Number of cycles IEW is blocking 1181system.cpu1.iew.iewUnblockCycles 147509 # Number of cycles IEW is unblocking 1182system.cpu1.iew.iewDispatchedInsts 7654698 # Number of instructions dispatched to IQ 1183system.cpu1.iew.iewDispSquashedInsts 36160 # Number of squashed instructions skipped by dispatch 1184system.cpu1.iew.iewDispLoadInsts 1508631 # Number of dispatched load instructions 1185system.cpu1.iew.iewDispStoreInsts 873340 # Number of dispatched store instructions 1186system.cpu1.iew.iewDispNonSpecInsts 319432 # Number of dispatched non-speculative instructions 1187system.cpu1.iew.iewIQFullEvents 4857 # Number of times the IQ has become full, causing a stall 1188system.cpu1.iew.iewLSQFullEvents 141756 # Number of times the LSQ has become full, causing a stall 1189system.cpu1.iew.memOrderViolationEvents 4058 # Number of memory order violations 1190system.cpu1.iew.predictedTakenIncorrect 24786 # Number of branches that were predicted taken incorrectly 1191system.cpu1.iew.predictedNotTakenIncorrect 89639 # Number of branches that were predicted not taken incorrectly 1192system.cpu1.iew.branchMispredicts 114425 # Number of branch mispredicts detected at execute 1193system.cpu1.iew.iewExecutedInsts 6540293 # Number of executed instructions 1194system.cpu1.iew.iewExecLoadInsts 1470121 # Number of load instructions executed 1195system.cpu1.iew.iewExecSquashedInsts 112127 # Number of squashed instructions skipped in execute 1196system.cpu1.iew.exec_swp 0 # number of swp insts executed 1197system.cpu1.iew.exec_nop 332143 # number of nop insts executed 1198system.cpu1.iew.exec_refs 2281164 # number of memory reference insts executed 1199system.cpu1.iew.exec_branches 956130 # Number of branches executed 1200system.cpu1.iew.exec_stores 811043 # Number of stores executed 1201system.cpu1.iew.exec_rate 0.635008 # Inst execution rate 1202system.cpu1.iew.wb_sent 6430736 # cumulative count of insts sent to commit 1203system.cpu1.iew.wb_count 6395657 # cumulative count of insts written-back 1204system.cpu1.iew.wb_producers 3121788 # num instructions producing a value 1205system.cpu1.iew.wb_consumers 4363189 # num instructions consuming a value 1206system.cpu1.iew.wb_rate 0.620965 # insts written-back per cycle 1207system.cpu1.iew.wb_fanout 0.715483 # average fanout of values written-back 1208system.cpu1.commit.commitSquashedInsts 1558734 # The number of squashed insts skipped by commit 1209system.cpu1.commit.commitNonSpecStalls 77899 # The number of times commit has been forced to stall to communicate backwards 1210system.cpu1.commit.branchMispredicts 97361 # The number of times a branch was mispredicted 1211system.cpu1.commit.committed_per_cycle::samples 9525282 # Number of insts commited each cycle 1212system.cpu1.commit.committed_per_cycle::mean 0.626287 # Number of insts commited each cycle 1213system.cpu1.commit.committed_per_cycle::stdev 1.584809 # Number of insts commited each cycle 1214system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1215system.cpu1.commit.committed_per_cycle::0 7314942 76.80% 76.80% # Number of insts commited each cycle 1216system.cpu1.commit.committed_per_cycle::1 1051446 11.04% 87.83% # Number of insts commited each cycle 1217system.cpu1.commit.committed_per_cycle::2 355573 3.73% 91.57% # Number of insts commited each cycle 1218system.cpu1.commit.committed_per_cycle::3 228997 2.40% 93.97% # Number of insts commited each cycle 1219system.cpu1.commit.committed_per_cycle::4 163534 1.72% 95.69% # Number of insts commited each cycle 1220system.cpu1.commit.committed_per_cycle::5 72316 0.76% 96.45% # Number of insts commited each cycle 1221system.cpu1.commit.committed_per_cycle::6 75781 0.80% 97.24% # Number of insts commited each cycle 1222system.cpu1.commit.committed_per_cycle::7 55973 0.59% 97.83% # Number of insts commited each cycle 1223system.cpu1.commit.committed_per_cycle::8 206720 2.17% 100.00% # Number of insts commited each cycle 1224system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1225system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1226system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1227system.cpu1.commit.committed_per_cycle::total 9525282 # Number of insts commited each cycle 1228system.cpu1.commit.committedInsts 5965556 # Number of instructions committed 1229system.cpu1.commit.committedOps 5965556 # Number of ops (including micro ops) committed 1230system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1231system.cpu1.commit.refs 1933842 # Number of memory references committed 1232system.cpu1.commit.loads 1180371 # Number of loads committed 1233system.cpu1.commit.membars 21608 # Number of memory barriers committed 1234system.cpu1.commit.branches 842250 # Number of branches committed 1235system.cpu1.commit.fp_insts 40666 # Number of committed floating point instructions. 1236system.cpu1.commit.int_insts 5575941 # Number of committed integer instructions. 1237system.cpu1.commit.function_calls 91630 # Number of function calls committed. 1238system.cpu1.commit.op_class_0::No_OpClass 239508 4.01% 4.01% # Class of committed instruction 1239system.cpu1.commit.op_class_0::IntAlu 3553035 59.56% 63.57% # Class of committed instruction 1240system.cpu1.commit.op_class_0::IntMult 10403 0.17% 63.75% # Class of committed instruction 1241system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.75% # Class of committed instruction 1242system.cpu1.commit.op_class_0::FloatAdd 10285 0.17% 63.92% # Class of committed instruction 1243system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.92% # Class of committed instruction 1244system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.92% # Class of committed instruction 1245system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.92% # Class of committed instruction 1246system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.95% # Class of committed instruction 1247system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.95% # Class of committed instruction 1248system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.95% # Class of committed instruction 1249system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.95% # Class of committed instruction 1250system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.95% # Class of committed instruction 1251system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.95% # Class of committed instruction 1252system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.95% # Class of committed instruction 1253system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.95% # Class of committed instruction 1254system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.95% # Class of committed instruction 1255system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.95% # Class of committed instruction 1256system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.95% # Class of committed instruction 1257system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.95% # Class of committed instruction 1258system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.95% # Class of committed instruction 1259system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.95% # Class of committed instruction 1260system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.95% # Class of committed instruction 1261system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.95% # Class of committed instruction 1262system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.95% # Class of committed instruction 1263system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.95% # Class of committed instruction 1264system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.95% # Class of committed instruction 1265system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.95% # Class of committed instruction 1266system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.95% # Class of committed instruction 1267system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.95% # Class of committed instruction 1268system.cpu1.commit.op_class_0::MemRead 1201979 20.15% 84.10% # Class of committed instruction 1269system.cpu1.commit.op_class_0::MemWrite 753678 12.63% 96.74% # Class of committed instruction 1270system.cpu1.commit.op_class_0::IprAccess 194682 3.26% 100.00% # Class of committed instruction 1271system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1272system.cpu1.commit.op_class_0::total 5965556 # Class of committed instruction 1273system.cpu1.commit.bw_lim_events 206720 # number cycles where commit BW limit reached 1274system.cpu1.rob.rob_reads 16752551 # The number of ROB reads 1275system.cpu1.rob.rob_writes 15324043 # The number of ROB writes 1276system.cpu1.timesIdled 69166 # Number of times that the entire CPU went into an idle state and unscheduled itself 1277system.cpu1.idleCycles 496122 # Total number of cycles that the CPU has spent unscheduled due to idling 1278system.cpu1.quiesceCycles 3807004634 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1279system.cpu1.committedInsts 5730020 # Number of Instructions Simulated 1280system.cpu1.committedOps 5730020 # Number of Ops (including micro ops) Simulated 1281system.cpu1.cpi 1.797471 # CPI: Cycles Per Instruction 1282system.cpu1.cpi_total 1.797471 # CPI: Total CPI of All Threads 1283system.cpu1.ipc 0.556337 # IPC: Instructions Per Cycle 1284system.cpu1.ipc_total 0.556337 # IPC: Total IPC of All Threads 1285system.cpu1.int_regfile_reads 8470716 # number of integer regfile reads 1286system.cpu1.int_regfile_writes 4619691 # number of integer regfile writes 1287system.cpu1.fp_regfile_reads 26922 # number of floating regfile reads 1288system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes 1289system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads 1290system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes
	1291system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1263system.cpu1.dcache.tags.replacements 64410 # number of replacements 1264system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use 1265system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. 1266system.cpu1.dcache.tags.sampled_refs 64922 # Sample count of references to valid blocks. 1267system.cpu1.dcache.tags.avg_refs 27.646006 # Average number of references to valid blocks. 1268system.cpu1.dcache.tags.warmup_cycle 1880101020500 # Cycle when the warmup percentage was hit. 1269system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.614906 # Average occupied blocks per requestor 1270system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905498 # Average percentage of cache occupancy 1271system.cpu1.dcache.tags.occ_percent::total 0.905498 # Average percentage of cache occupancy 1272system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1273system.cpu1.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id 1274system.cpu1.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 1275system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 1276system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1277system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses 1278system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses	1292system.cpu1.dcache.tags.replacements 64410 # number of replacements 1293system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use 1294system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. 1295system.cpu1.dcache.tags.sampled_refs 64922 # Sample count of references to valid blocks. 1296system.cpu1.dcache.tags.avg_refs 27.646006 # Average number of references to valid blocks. 1297system.cpu1.dcache.tags.warmup_cycle 1880101020500 # Cycle when the warmup percentage was hit. 1298system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.614906 # Average occupied blocks per requestor 1299system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905498 # Average percentage of cache occupancy 1300system.cpu1.dcache.tags.occ_percent::total 0.905498 # Average percentage of cache occupancy 1301system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1302system.cpu1.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id 1303system.cpu1.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 1304system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 1305system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1306system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses 1307system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses
	1308system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1279system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits 1280system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits 1281system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits 1282system.cpu1.dcache.WriteReq_hits::total 570377 # number of WriteReq hits 1283system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16198 # number of LoadLockedReq hits 1284system.cpu1.dcache.LoadLockedReq_hits::total 16198 # number of LoadLockedReq hits 1285system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15147 # number of StoreCondReq hits 1286system.cpu1.dcache.StoreCondReq_hits::total 15147 # number of StoreCondReq hits 1287system.cpu1.dcache.demand_hits::cpu1.data 1759259 # number of demand (read+write) hits 1288system.cpu1.dcache.demand_hits::total 1759259 # number of demand (read+write) hits 1289system.cpu1.dcache.overall_hits::cpu1.data 1759259 # number of overall hits 1290system.cpu1.dcache.overall_hits::total 1759259 # number of overall hits 1291system.cpu1.dcache.ReadReq_misses::cpu1.data 111545 # number of ReadReq misses 1292system.cpu1.dcache.ReadReq_misses::total 111545 # number of ReadReq misses 1293system.cpu1.dcache.WriteReq_misses::cpu1.data 161954 # number of WriteReq misses 1294system.cpu1.dcache.WriteReq_misses::total 161954 # number of WriteReq misses 1295system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1739 # number of LoadLockedReq misses 1296system.cpu1.dcache.LoadLockedReq_misses::total 1739 # number of LoadLockedReq misses 1297system.cpu1.dcache.StoreCondReq_misses::cpu1.data 840 # number of StoreCondReq misses 1298system.cpu1.dcache.StoreCondReq_misses::total 840 # number of StoreCondReq misses 1299system.cpu1.dcache.demand_misses::cpu1.data 273499 # number of demand (read+write) misses 1300system.cpu1.dcache.demand_misses::total 273499 # number of demand (read+write) misses 1301system.cpu1.dcache.overall_misses::cpu1.data 273499 # number of overall misses 1302system.cpu1.dcache.overall_misses::total 273499 # number of overall misses 1303system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1447207500 # number of ReadReq miss cycles 1304system.cpu1.dcache.ReadReq_miss_latency::total 1447207500 # number of ReadReq miss cycles 1305system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7450335261 # number of WriteReq miss cycles 1306system.cpu1.dcache.WriteReq_miss_latency::total 7450335261 # number of WriteReq miss cycles 1307system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 18882500 # number of LoadLockedReq miss cycles 1308system.cpu1.dcache.LoadLockedReq_miss_latency::total 18882500 # number of LoadLockedReq miss cycles 1309system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6469000 # number of StoreCondReq miss cycles 1310system.cpu1.dcache.StoreCondReq_miss_latency::total 6469000 # number of StoreCondReq miss cycles 1311system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles 1312system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles 1313system.cpu1.dcache.demand_miss_latency::cpu1.data 8897542761 # number of demand (read+write) miss cycles 1314system.cpu1.dcache.demand_miss_latency::total 8897542761 # number of demand (read+write) miss cycles 1315system.cpu1.dcache.overall_miss_latency::cpu1.data 8897542761 # number of overall miss cycles 1316system.cpu1.dcache.overall_miss_latency::total 8897542761 # number of overall miss cycles 1317system.cpu1.dcache.ReadReq_accesses::cpu1.data 1300427 # number of ReadReq accesses(hits+misses) 1318system.cpu1.dcache.ReadReq_accesses::total 1300427 # number of ReadReq accesses(hits+misses) 1319system.cpu1.dcache.WriteReq_accesses::cpu1.data 732331 # number of WriteReq accesses(hits+misses) 1320system.cpu1.dcache.WriteReq_accesses::total 732331 # number of WriteReq accesses(hits+misses) 1321system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 17937 # number of LoadLockedReq accesses(hits+misses) 1322system.cpu1.dcache.LoadLockedReq_accesses::total 17937 # number of LoadLockedReq accesses(hits+misses) 1323system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15987 # number of StoreCondReq accesses(hits+misses) 1324system.cpu1.dcache.StoreCondReq_accesses::total 15987 # number of StoreCondReq accesses(hits+misses) 1325system.cpu1.dcache.demand_accesses::cpu1.data 2032758 # number of demand (read+write) accesses 1326system.cpu1.dcache.demand_accesses::total 2032758 # number of demand (read+write) accesses 1327system.cpu1.dcache.overall_accesses::cpu1.data 2032758 # number of overall (read+write) accesses 1328system.cpu1.dcache.overall_accesses::total 2032758 # number of overall (read+write) accesses 1329system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.085776 # miss rate for ReadReq accesses 1330system.cpu1.dcache.ReadReq_miss_rate::total 0.085776 # miss rate for ReadReq accesses 1331system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221149 # miss rate for WriteReq accesses 1332system.cpu1.dcache.WriteReq_miss_rate::total 0.221149 # miss rate for WriteReq accesses 1333system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.096950 # miss rate for LoadLockedReq accesses 1334system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.096950 # miss rate for LoadLockedReq accesses 1335system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.052543 # miss rate for StoreCondReq accesses 1336system.cpu1.dcache.StoreCondReq_miss_rate::total 0.052543 # miss rate for StoreCondReq accesses 1337system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134546 # miss rate for demand accesses 1338system.cpu1.dcache.demand_miss_rate::total 0.134546 # miss rate for demand accesses 1339system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134546 # miss rate for overall accesses 1340system.cpu1.dcache.overall_miss_rate::total 0.134546 # miss rate for overall accesses 1341system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12974.203236 # average ReadReq miss latency 1342system.cpu1.dcache.ReadReq_avg_miss_latency::total 12974.203236 # average ReadReq miss latency 1343system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46002.786353 # average WriteReq miss latency 1344system.cpu1.dcache.WriteReq_avg_miss_latency::total 46002.786353 # average WriteReq miss latency 1345system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10858.251869 # average LoadLockedReq miss latency 1346system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10858.251869 # average LoadLockedReq miss latency 1347system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7701.190476 # average StoreCondReq miss latency 1348system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7701.190476 # average StoreCondReq miss latency 1349system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1350system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1351system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency 1352system.cpu1.dcache.demand_avg_miss_latency::total 32532.267983 # average overall miss latency 1353system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency 1354system.cpu1.dcache.overall_avg_miss_latency::total 32532.267983 # average overall miss latency 1355system.cpu1.dcache.blocked_cycles::no_mshrs 463151 # number of cycles access was blocked 1356system.cpu1.dcache.blocked_cycles::no_targets 490 # number of cycles access was blocked 1357system.cpu1.dcache.blocked::no_mshrs 15628 # number of cycles access was blocked 1358system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked 1359system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.635974 # average number of cycles each access was blocked 1360system.cpu1.dcache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked 1361system.cpu1.dcache.writebacks::writebacks 38002 # number of writebacks 1362system.cpu1.dcache.writebacks::total 38002 # number of writebacks 1363system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 65961 # number of ReadReq MSHR hits 1364system.cpu1.dcache.ReadReq_mshr_hits::total 65961 # number of ReadReq MSHR hits 1365system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137427 # number of WriteReq MSHR hits 1366system.cpu1.dcache.WriteReq_mshr_hits::total 137427 # number of WriteReq MSHR hits 1367system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 372 # number of LoadLockedReq MSHR hits 1368system.cpu1.dcache.LoadLockedReq_mshr_hits::total 372 # number of LoadLockedReq MSHR hits 1369system.cpu1.dcache.demand_mshr_hits::cpu1.data 203388 # number of demand (read+write) MSHR hits 1370system.cpu1.dcache.demand_mshr_hits::total 203388 # number of demand (read+write) MSHR hits 1371system.cpu1.dcache.overall_mshr_hits::cpu1.data 203388 # number of overall MSHR hits 1372system.cpu1.dcache.overall_mshr_hits::total 203388 # number of overall MSHR hits 1373system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 45584 # number of ReadReq MSHR misses 1374system.cpu1.dcache.ReadReq_mshr_misses::total 45584 # number of ReadReq MSHR misses 1375system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24527 # number of WriteReq MSHR misses 1376system.cpu1.dcache.WriteReq_mshr_misses::total 24527 # number of WriteReq MSHR misses 1377system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1367 # number of LoadLockedReq MSHR misses 1378system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1367 # number of LoadLockedReq MSHR misses 1379system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 840 # number of StoreCondReq MSHR misses 1380system.cpu1.dcache.StoreCondReq_mshr_misses::total 840 # number of StoreCondReq MSHR misses 1381system.cpu1.dcache.demand_mshr_misses::cpu1.data 70111 # number of demand (read+write) MSHR misses 1382system.cpu1.dcache.demand_mshr_misses::total 70111 # number of demand (read+write) MSHR misses 1383system.cpu1.dcache.overall_mshr_misses::cpu1.data 70111 # number of overall MSHR misses 1384system.cpu1.dcache.overall_mshr_misses::total 70111 # number of overall MSHR misses 1385system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable 1386system.cpu1.dcache.ReadReq_mshr_uncacheable::total 146 # number of ReadReq MSHR uncacheable 1387system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable 1388system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2584 # number of WriteReq MSHR uncacheable 1389system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses 1390system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2730 # number of overall MSHR uncacheable misses 1391system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 575200000 # number of ReadReq MSHR miss cycles 1392system.cpu1.dcache.ReadReq_mshr_miss_latency::total 575200000 # number of ReadReq MSHR miss cycles 1393system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1170679567 # number of WriteReq MSHR miss cycles 1394system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1170679567 # number of WriteReq MSHR miss cycles 1395system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13141000 # number of LoadLockedReq MSHR miss cycles 1396system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13141000 # number of LoadLockedReq MSHR miss cycles 1397system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5630000 # number of StoreCondReq MSHR miss cycles 1398system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5630000 # number of StoreCondReq MSHR miss cycles 1399system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles 1400system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles 1401system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1745879567 # number of demand (read+write) MSHR miss cycles 1402system.cpu1.dcache.demand_mshr_miss_latency::total 1745879567 # number of demand (read+write) MSHR miss cycles 1403system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1745879567 # number of overall MSHR miss cycles 1404system.cpu1.dcache.overall_mshr_miss_latency::total 1745879567 # number of overall MSHR miss cycles 1405system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29635500 # number of ReadReq MSHR uncacheable cycles 1406system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29635500 # number of ReadReq MSHR uncacheable cycles 1407system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 29635500 # number of overall MSHR uncacheable cycles 1408system.cpu1.dcache.overall_mshr_uncacheable_latency::total 29635500 # number of overall MSHR uncacheable cycles 1409system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035053 # mshr miss rate for ReadReq accesses 1410system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035053 # mshr miss rate for ReadReq accesses 1411system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033492 # mshr miss rate for WriteReq accesses 1412system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033492 # mshr miss rate for WriteReq accesses 1413system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076211 # mshr miss rate for LoadLockedReq accesses 1414system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076211 # mshr miss rate for LoadLockedReq accesses 1415system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.052543 # mshr miss rate for StoreCondReq accesses 1416system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.052543 # mshr miss rate for StoreCondReq accesses 1417system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for demand accesses 1418system.cpu1.dcache.demand_mshr_miss_rate::total 0.034491 # mshr miss rate for demand accesses 1419system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for overall accesses 1420system.cpu1.dcache.overall_mshr_miss_rate::total 0.034491 # mshr miss rate for overall accesses 1421system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.462618 # average ReadReq mshr miss latency 1422system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12618.462618 # average ReadReq mshr miss latency 1423system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47730.238798 # average WriteReq mshr miss latency 1424system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47730.238798 # average WriteReq mshr miss latency 1425system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9613.021214 # average LoadLockedReq mshr miss latency 1426system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9613.021214 # average LoadLockedReq mshr miss latency 1427system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6702.380952 # average StoreCondReq mshr miss latency 1428system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6702.380952 # average StoreCondReq mshr miss latency 1429system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1430system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1431system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency 1432system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency 1433system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency 1434system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency 1435system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 # average ReadReq mshr uncacheable latency 1436system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency 1437system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency 1438system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency	1309system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits 1310system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits 1311system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits 1312system.cpu1.dcache.WriteReq_hits::total 570377 # number of WriteReq hits 1313system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 16198 # number of LoadLockedReq hits 1314system.cpu1.dcache.LoadLockedReq_hits::total 16198 # number of LoadLockedReq hits 1315system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15147 # number of StoreCondReq hits 1316system.cpu1.dcache.StoreCondReq_hits::total 15147 # number of StoreCondReq hits 1317system.cpu1.dcache.demand_hits::cpu1.data 1759259 # number of demand (read+write) hits 1318system.cpu1.dcache.demand_hits::total 1759259 # number of demand (read+write) hits 1319system.cpu1.dcache.overall_hits::cpu1.data 1759259 # number of overall hits 1320system.cpu1.dcache.overall_hits::total 1759259 # number of overall hits 1321system.cpu1.dcache.ReadReq_misses::cpu1.data 111545 # number of ReadReq misses 1322system.cpu1.dcache.ReadReq_misses::total 111545 # number of ReadReq misses 1323system.cpu1.dcache.WriteReq_misses::cpu1.data 161954 # number of WriteReq misses 1324system.cpu1.dcache.WriteReq_misses::total 161954 # number of WriteReq misses 1325system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1739 # number of LoadLockedReq misses 1326system.cpu1.dcache.LoadLockedReq_misses::total 1739 # number of LoadLockedReq misses 1327system.cpu1.dcache.StoreCondReq_misses::cpu1.data 840 # number of StoreCondReq misses 1328system.cpu1.dcache.StoreCondReq_misses::total 840 # number of StoreCondReq misses 1329system.cpu1.dcache.demand_misses::cpu1.data 273499 # number of demand (read+write) misses 1330system.cpu1.dcache.demand_misses::total 273499 # number of demand (read+write) misses 1331system.cpu1.dcache.overall_misses::cpu1.data 273499 # number of overall misses 1332system.cpu1.dcache.overall_misses::total 273499 # number of overall misses 1333system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1447207500 # number of ReadReq miss cycles 1334system.cpu1.dcache.ReadReq_miss_latency::total 1447207500 # number of ReadReq miss cycles 1335system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7450335261 # number of WriteReq miss cycles 1336system.cpu1.dcache.WriteReq_miss_latency::total 7450335261 # number of WriteReq miss cycles 1337system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 18882500 # number of LoadLockedReq miss cycles 1338system.cpu1.dcache.LoadLockedReq_miss_latency::total 18882500 # number of LoadLockedReq miss cycles 1339system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6469000 # number of StoreCondReq miss cycles 1340system.cpu1.dcache.StoreCondReq_miss_latency::total 6469000 # number of StoreCondReq miss cycles 1341system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles 1342system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles 1343system.cpu1.dcache.demand_miss_latency::cpu1.data 8897542761 # number of demand (read+write) miss cycles 1344system.cpu1.dcache.demand_miss_latency::total 8897542761 # number of demand (read+write) miss cycles 1345system.cpu1.dcache.overall_miss_latency::cpu1.data 8897542761 # number of overall miss cycles 1346system.cpu1.dcache.overall_miss_latency::total 8897542761 # number of overall miss cycles 1347system.cpu1.dcache.ReadReq_accesses::cpu1.data 1300427 # number of ReadReq accesses(hits+misses) 1348system.cpu1.dcache.ReadReq_accesses::total 1300427 # number of ReadReq accesses(hits+misses) 1349system.cpu1.dcache.WriteReq_accesses::cpu1.data 732331 # number of WriteReq accesses(hits+misses) 1350system.cpu1.dcache.WriteReq_accesses::total 732331 # number of WriteReq accesses(hits+misses) 1351system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 17937 # number of LoadLockedReq accesses(hits+misses) 1352system.cpu1.dcache.LoadLockedReq_accesses::total 17937 # number of LoadLockedReq accesses(hits+misses) 1353system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 15987 # number of StoreCondReq accesses(hits+misses) 1354system.cpu1.dcache.StoreCondReq_accesses::total 15987 # number of StoreCondReq accesses(hits+misses) 1355system.cpu1.dcache.demand_accesses::cpu1.data 2032758 # number of demand (read+write) accesses 1356system.cpu1.dcache.demand_accesses::total 2032758 # number of demand (read+write) accesses 1357system.cpu1.dcache.overall_accesses::cpu1.data 2032758 # number of overall (read+write) accesses 1358system.cpu1.dcache.overall_accesses::total 2032758 # number of overall (read+write) accesses 1359system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.085776 # miss rate for ReadReq accesses 1360system.cpu1.dcache.ReadReq_miss_rate::total 0.085776 # miss rate for ReadReq accesses 1361system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221149 # miss rate for WriteReq accesses 1362system.cpu1.dcache.WriteReq_miss_rate::total 0.221149 # miss rate for WriteReq accesses 1363system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.096950 # miss rate for LoadLockedReq accesses 1364system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.096950 # miss rate for LoadLockedReq accesses 1365system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.052543 # miss rate for StoreCondReq accesses 1366system.cpu1.dcache.StoreCondReq_miss_rate::total 0.052543 # miss rate for StoreCondReq accesses 1367system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134546 # miss rate for demand accesses 1368system.cpu1.dcache.demand_miss_rate::total 0.134546 # miss rate for demand accesses 1369system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134546 # miss rate for overall accesses 1370system.cpu1.dcache.overall_miss_rate::total 0.134546 # miss rate for overall accesses 1371system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12974.203236 # average ReadReq miss latency 1372system.cpu1.dcache.ReadReq_avg_miss_latency::total 12974.203236 # average ReadReq miss latency 1373system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46002.786353 # average WriteReq miss latency 1374system.cpu1.dcache.WriteReq_avg_miss_latency::total 46002.786353 # average WriteReq miss latency 1375system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10858.251869 # average LoadLockedReq miss latency 1376system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10858.251869 # average LoadLockedReq miss latency 1377system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7701.190476 # average StoreCondReq miss latency 1378system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7701.190476 # average StoreCondReq miss latency 1379system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1380system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1381system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency 1382system.cpu1.dcache.demand_avg_miss_latency::total 32532.267983 # average overall miss latency 1383system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32532.267983 # average overall miss latency 1384system.cpu1.dcache.overall_avg_miss_latency::total 32532.267983 # average overall miss latency 1385system.cpu1.dcache.blocked_cycles::no_mshrs 463151 # number of cycles access was blocked 1386system.cpu1.dcache.blocked_cycles::no_targets 490 # number of cycles access was blocked 1387system.cpu1.dcache.blocked::no_mshrs 15628 # number of cycles access was blocked 1388system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked 1389system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.635974 # average number of cycles each access was blocked 1390system.cpu1.dcache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked 1391system.cpu1.dcache.writebacks::writebacks 38002 # number of writebacks 1392system.cpu1.dcache.writebacks::total 38002 # number of writebacks 1393system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 65961 # number of ReadReq MSHR hits 1394system.cpu1.dcache.ReadReq_mshr_hits::total 65961 # number of ReadReq MSHR hits 1395system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137427 # number of WriteReq MSHR hits 1396system.cpu1.dcache.WriteReq_mshr_hits::total 137427 # number of WriteReq MSHR hits 1397system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 372 # number of LoadLockedReq MSHR hits 1398system.cpu1.dcache.LoadLockedReq_mshr_hits::total 372 # number of LoadLockedReq MSHR hits 1399system.cpu1.dcache.demand_mshr_hits::cpu1.data 203388 # number of demand (read+write) MSHR hits 1400system.cpu1.dcache.demand_mshr_hits::total 203388 # number of demand (read+write) MSHR hits 1401system.cpu1.dcache.overall_mshr_hits::cpu1.data 203388 # number of overall MSHR hits 1402system.cpu1.dcache.overall_mshr_hits::total 203388 # number of overall MSHR hits 1403system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 45584 # number of ReadReq MSHR misses 1404system.cpu1.dcache.ReadReq_mshr_misses::total 45584 # number of ReadReq MSHR misses 1405system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24527 # number of WriteReq MSHR misses 1406system.cpu1.dcache.WriteReq_mshr_misses::total 24527 # number of WriteReq MSHR misses 1407system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1367 # number of LoadLockedReq MSHR misses 1408system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1367 # number of LoadLockedReq MSHR misses 1409system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 840 # number of StoreCondReq MSHR misses 1410system.cpu1.dcache.StoreCondReq_mshr_misses::total 840 # number of StoreCondReq MSHR misses 1411system.cpu1.dcache.demand_mshr_misses::cpu1.data 70111 # number of demand (read+write) MSHR misses 1412system.cpu1.dcache.demand_mshr_misses::total 70111 # number of demand (read+write) MSHR misses 1413system.cpu1.dcache.overall_mshr_misses::cpu1.data 70111 # number of overall MSHR misses 1414system.cpu1.dcache.overall_mshr_misses::total 70111 # number of overall MSHR misses 1415system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable 1416system.cpu1.dcache.ReadReq_mshr_uncacheable::total 146 # number of ReadReq MSHR uncacheable 1417system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable 1418system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2584 # number of WriteReq MSHR uncacheable 1419system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses 1420system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2730 # number of overall MSHR uncacheable misses 1421system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 575200000 # number of ReadReq MSHR miss cycles 1422system.cpu1.dcache.ReadReq_mshr_miss_latency::total 575200000 # number of ReadReq MSHR miss cycles 1423system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1170679567 # number of WriteReq MSHR miss cycles 1424system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1170679567 # number of WriteReq MSHR miss cycles 1425system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13141000 # number of LoadLockedReq MSHR miss cycles 1426system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13141000 # number of LoadLockedReq MSHR miss cycles 1427system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5630000 # number of StoreCondReq MSHR miss cycles 1428system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5630000 # number of StoreCondReq MSHR miss cycles 1429system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles 1430system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles 1431system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1745879567 # number of demand (read+write) MSHR miss cycles 1432system.cpu1.dcache.demand_mshr_miss_latency::total 1745879567 # number of demand (read+write) MSHR miss cycles 1433system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1745879567 # number of overall MSHR miss cycles 1434system.cpu1.dcache.overall_mshr_miss_latency::total 1745879567 # number of overall MSHR miss cycles 1435system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29635500 # number of ReadReq MSHR uncacheable cycles 1436system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29635500 # number of ReadReq MSHR uncacheable cycles 1437system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 29635500 # number of overall MSHR uncacheable cycles 1438system.cpu1.dcache.overall_mshr_uncacheable_latency::total 29635500 # number of overall MSHR uncacheable cycles 1439system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035053 # mshr miss rate for ReadReq accesses 1440system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035053 # mshr miss rate for ReadReq accesses 1441system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033492 # mshr miss rate for WriteReq accesses 1442system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033492 # mshr miss rate for WriteReq accesses 1443system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076211 # mshr miss rate for LoadLockedReq accesses 1444system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076211 # mshr miss rate for LoadLockedReq accesses 1445system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.052543 # mshr miss rate for StoreCondReq accesses 1446system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.052543 # mshr miss rate for StoreCondReq accesses 1447system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for demand accesses 1448system.cpu1.dcache.demand_mshr_miss_rate::total 0.034491 # mshr miss rate for demand accesses 1449system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034491 # mshr miss rate for overall accesses 1450system.cpu1.dcache.overall_mshr_miss_rate::total 0.034491 # mshr miss rate for overall accesses 1451system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.462618 # average ReadReq mshr miss latency 1452system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12618.462618 # average ReadReq mshr miss latency 1453system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47730.238798 # average WriteReq mshr miss latency 1454system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47730.238798 # average WriteReq mshr miss latency 1455system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9613.021214 # average LoadLockedReq mshr miss latency 1456system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9613.021214 # average LoadLockedReq mshr miss latency 1457system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6702.380952 # average StoreCondReq mshr miss latency 1458system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6702.380952 # average StoreCondReq mshr miss latency 1459system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1460system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1461system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency 1462system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency 1463system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.649770 # average overall mshr miss latency 1464system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24901.649770 # average overall mshr miss latency 1465system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 # average ReadReq mshr uncacheable latency 1466system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency 1467system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency 1468system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency
	1469system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1439system.cpu1.icache.tags.replacements 125381 # number of replacements 1440system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use 1441system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. 1442system.cpu1.icache.tags.sampled_refs 125892 # Sample count of references to valid blocks. 1443system.cpu1.icache.tags.avg_refs 8.394100 # Average number of references to valid blocks. 1444system.cpu1.icache.tags.warmup_cycle 1880706304500 # Cycle when the warmup percentage was hit. 1445system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.454678 # Average occupied blocks per requestor 1446system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911044 # Average percentage of cache occupancy 1447system.cpu1.icache.tags.occ_percent::total 0.911044 # Average percentage of cache occupancy 1448system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1449system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1450system.cpu1.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 1451system.cpu1.icache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id 1452system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1453system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1454system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses 1455system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses	1470system.cpu1.icache.tags.replacements 125381 # number of replacements 1471system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use 1472system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. 1473system.cpu1.icache.tags.sampled_refs 125892 # Sample count of references to valid blocks. 1474system.cpu1.icache.tags.avg_refs 8.394100 # Average number of references to valid blocks. 1475system.cpu1.icache.tags.warmup_cycle 1880706304500 # Cycle when the warmup percentage was hit. 1476system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.454678 # Average occupied blocks per requestor 1477system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911044 # Average percentage of cache occupancy 1478system.cpu1.icache.tags.occ_percent::total 0.911044 # Average percentage of cache occupancy 1479system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1480system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1481system.cpu1.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 1482system.cpu1.icache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id 1483system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1484system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1485system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses 1486system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses
	1487system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1456system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits 1457system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits 1458system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits 1459system.cpu1.icache.demand_hits::total 1056751 # number of demand (read+write) hits 1460system.cpu1.icache.overall_hits::cpu1.inst 1056751 # number of overall hits 1461system.cpu1.icache.overall_hits::total 1056751 # number of overall hits 1462system.cpu1.icache.ReadReq_misses::cpu1.inst 132616 # number of ReadReq misses 1463system.cpu1.icache.ReadReq_misses::total 132616 # number of ReadReq misses 1464system.cpu1.icache.demand_misses::cpu1.inst 132616 # number of demand (read+write) misses 1465system.cpu1.icache.demand_misses::total 132616 # number of demand (read+write) misses 1466system.cpu1.icache.overall_misses::cpu1.inst 132616 # number of overall misses 1467system.cpu1.icache.overall_misses::total 132616 # number of overall misses 1468system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1887030000 # number of ReadReq miss cycles 1469system.cpu1.icache.ReadReq_miss_latency::total 1887030000 # number of ReadReq miss cycles 1470system.cpu1.icache.demand_miss_latency::cpu1.inst 1887030000 # number of demand (read+write) miss cycles 1471system.cpu1.icache.demand_miss_latency::total 1887030000 # number of demand (read+write) miss cycles 1472system.cpu1.icache.overall_miss_latency::cpu1.inst 1887030000 # number of overall miss cycles 1473system.cpu1.icache.overall_miss_latency::total 1887030000 # number of overall miss cycles 1474system.cpu1.icache.ReadReq_accesses::cpu1.inst 1189367 # number of ReadReq accesses(hits+misses) 1475system.cpu1.icache.ReadReq_accesses::total 1189367 # number of ReadReq accesses(hits+misses) 1476system.cpu1.icache.demand_accesses::cpu1.inst 1189367 # number of demand (read+write) accesses 1477system.cpu1.icache.demand_accesses::total 1189367 # number of demand (read+write) accesses 1478system.cpu1.icache.overall_accesses::cpu1.inst 1189367 # number of overall (read+write) accesses 1479system.cpu1.icache.overall_accesses::total 1189367 # number of overall (read+write) accesses 1480system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111501 # miss rate for ReadReq accesses 1481system.cpu1.icache.ReadReq_miss_rate::total 0.111501 # miss rate for ReadReq accesses 1482system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111501 # miss rate for demand accesses 1483system.cpu1.icache.demand_miss_rate::total 0.111501 # miss rate for demand accesses 1484system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111501 # miss rate for overall accesses 1485system.cpu1.icache.overall_miss_rate::total 0.111501 # miss rate for overall accesses 1486system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14229.278518 # average ReadReq miss latency 1487system.cpu1.icache.ReadReq_avg_miss_latency::total 14229.278518 # average ReadReq miss latency 1488system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency 1489system.cpu1.icache.demand_avg_miss_latency::total 14229.278518 # average overall miss latency 1490system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency 1491system.cpu1.icache.overall_avg_miss_latency::total 14229.278518 # average overall miss latency 1492system.cpu1.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked 1493system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1494system.cpu1.icache.blocked::no_mshrs 31 # number of cycles access was blocked 1495system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1496system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.193548 # average number of cycles each access was blocked 1497system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1498system.cpu1.icache.writebacks::writebacks 125381 # number of writebacks 1499system.cpu1.icache.writebacks::total 125381 # number of writebacks 1500system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6669 # number of ReadReq MSHR hits 1501system.cpu1.icache.ReadReq_mshr_hits::total 6669 # number of ReadReq MSHR hits 1502system.cpu1.icache.demand_mshr_hits::cpu1.inst 6669 # number of demand (read+write) MSHR hits 1503system.cpu1.icache.demand_mshr_hits::total 6669 # number of demand (read+write) MSHR hits 1504system.cpu1.icache.overall_mshr_hits::cpu1.inst 6669 # number of overall MSHR hits 1505system.cpu1.icache.overall_mshr_hits::total 6669 # number of overall MSHR hits 1506system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125947 # number of ReadReq MSHR misses 1507system.cpu1.icache.ReadReq_mshr_misses::total 125947 # number of ReadReq MSHR misses 1508system.cpu1.icache.demand_mshr_misses::cpu1.inst 125947 # number of demand (read+write) MSHR misses 1509system.cpu1.icache.demand_mshr_misses::total 125947 # number of demand (read+write) MSHR misses 1510system.cpu1.icache.overall_mshr_misses::cpu1.inst 125947 # number of overall MSHR misses 1511system.cpu1.icache.overall_mshr_misses::total 125947 # number of overall MSHR misses 1512system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1682313500 # number of ReadReq MSHR miss cycles 1513system.cpu1.icache.ReadReq_mshr_miss_latency::total 1682313500 # number of ReadReq MSHR miss cycles 1514system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1682313500 # number of demand (read+write) MSHR miss cycles 1515system.cpu1.icache.demand_mshr_miss_latency::total 1682313500 # number of demand (read+write) MSHR miss cycles 1516system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1682313500 # number of overall MSHR miss cycles 1517system.cpu1.icache.overall_mshr_miss_latency::total 1682313500 # number of overall MSHR miss cycles 1518system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for ReadReq accesses 1519system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105894 # mshr miss rate for ReadReq accesses 1520system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for demand accesses 1521system.cpu1.icache.demand_mshr_miss_rate::total 0.105894 # mshr miss rate for demand accesses 1522system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for overall accesses 1523system.cpu1.icache.overall_mshr_miss_rate::total 0.105894 # mshr miss rate for overall accesses 1524system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average ReadReq mshr miss latency 1525system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.312997 # average ReadReq mshr miss latency 1526system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency 1527system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency 1528system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency 1529system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency 1530system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1531system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1532system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1533system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1534system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1535system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1536system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1537system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1538system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1539system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1540system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1541system.disk2.dma_write_txs 1 # Number of DMA write transactions.	1488system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits 1489system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits 1490system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits 1491system.cpu1.icache.demand_hits::total 1056751 # number of demand (read+write) hits 1492system.cpu1.icache.overall_hits::cpu1.inst 1056751 # number of overall hits 1493system.cpu1.icache.overall_hits::total 1056751 # number of overall hits 1494system.cpu1.icache.ReadReq_misses::cpu1.inst 132616 # number of ReadReq misses 1495system.cpu1.icache.ReadReq_misses::total 132616 # number of ReadReq misses 1496system.cpu1.icache.demand_misses::cpu1.inst 132616 # number of demand (read+write) misses 1497system.cpu1.icache.demand_misses::total 132616 # number of demand (read+write) misses 1498system.cpu1.icache.overall_misses::cpu1.inst 132616 # number of overall misses 1499system.cpu1.icache.overall_misses::total 132616 # number of overall misses 1500system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1887030000 # number of ReadReq miss cycles 1501system.cpu1.icache.ReadReq_miss_latency::total 1887030000 # number of ReadReq miss cycles 1502system.cpu1.icache.demand_miss_latency::cpu1.inst 1887030000 # number of demand (read+write) miss cycles 1503system.cpu1.icache.demand_miss_latency::total 1887030000 # number of demand (read+write) miss cycles 1504system.cpu1.icache.overall_miss_latency::cpu1.inst 1887030000 # number of overall miss cycles 1505system.cpu1.icache.overall_miss_latency::total 1887030000 # number of overall miss cycles 1506system.cpu1.icache.ReadReq_accesses::cpu1.inst 1189367 # number of ReadReq accesses(hits+misses) 1507system.cpu1.icache.ReadReq_accesses::total 1189367 # number of ReadReq accesses(hits+misses) 1508system.cpu1.icache.demand_accesses::cpu1.inst 1189367 # number of demand (read+write) accesses 1509system.cpu1.icache.demand_accesses::total 1189367 # number of demand (read+write) accesses 1510system.cpu1.icache.overall_accesses::cpu1.inst 1189367 # number of overall (read+write) accesses 1511system.cpu1.icache.overall_accesses::total 1189367 # number of overall (read+write) accesses 1512system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111501 # miss rate for ReadReq accesses 1513system.cpu1.icache.ReadReq_miss_rate::total 0.111501 # miss rate for ReadReq accesses 1514system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111501 # miss rate for demand accesses 1515system.cpu1.icache.demand_miss_rate::total 0.111501 # miss rate for demand accesses 1516system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111501 # miss rate for overall accesses 1517system.cpu1.icache.overall_miss_rate::total 0.111501 # miss rate for overall accesses 1518system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14229.278518 # average ReadReq miss latency 1519system.cpu1.icache.ReadReq_avg_miss_latency::total 14229.278518 # average ReadReq miss latency 1520system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency 1521system.cpu1.icache.demand_avg_miss_latency::total 14229.278518 # average overall miss latency 1522system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14229.278518 # average overall miss latency 1523system.cpu1.icache.overall_avg_miss_latency::total 14229.278518 # average overall miss latency 1524system.cpu1.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked 1525system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1526system.cpu1.icache.blocked::no_mshrs 31 # number of cycles access was blocked 1527system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1528system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.193548 # average number of cycles each access was blocked 1529system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1530system.cpu1.icache.writebacks::writebacks 125381 # number of writebacks 1531system.cpu1.icache.writebacks::total 125381 # number of writebacks 1532system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6669 # number of ReadReq MSHR hits 1533system.cpu1.icache.ReadReq_mshr_hits::total 6669 # number of ReadReq MSHR hits 1534system.cpu1.icache.demand_mshr_hits::cpu1.inst 6669 # number of demand (read+write) MSHR hits 1535system.cpu1.icache.demand_mshr_hits::total 6669 # number of demand (read+write) MSHR hits 1536system.cpu1.icache.overall_mshr_hits::cpu1.inst 6669 # number of overall MSHR hits 1537system.cpu1.icache.overall_mshr_hits::total 6669 # number of overall MSHR hits 1538system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125947 # number of ReadReq MSHR misses 1539system.cpu1.icache.ReadReq_mshr_misses::total 125947 # number of ReadReq MSHR misses 1540system.cpu1.icache.demand_mshr_misses::cpu1.inst 125947 # number of demand (read+write) MSHR misses 1541system.cpu1.icache.demand_mshr_misses::total 125947 # number of demand (read+write) MSHR misses 1542system.cpu1.icache.overall_mshr_misses::cpu1.inst 125947 # number of overall MSHR misses 1543system.cpu1.icache.overall_mshr_misses::total 125947 # number of overall MSHR misses 1544system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1682313500 # number of ReadReq MSHR miss cycles 1545system.cpu1.icache.ReadReq_mshr_miss_latency::total 1682313500 # number of ReadReq MSHR miss cycles 1546system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1682313500 # number of demand (read+write) MSHR miss cycles 1547system.cpu1.icache.demand_mshr_miss_latency::total 1682313500 # number of demand (read+write) MSHR miss cycles 1548system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1682313500 # number of overall MSHR miss cycles 1549system.cpu1.icache.overall_mshr_miss_latency::total 1682313500 # number of overall MSHR miss cycles 1550system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for ReadReq accesses 1551system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.105894 # mshr miss rate for ReadReq accesses 1552system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for demand accesses 1553system.cpu1.icache.demand_mshr_miss_rate::total 0.105894 # mshr miss rate for demand accesses 1554system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105894 # mshr miss rate for overall accesses 1555system.cpu1.icache.overall_mshr_miss_rate::total 0.105894 # mshr miss rate for overall accesses 1556system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average ReadReq mshr miss latency 1557system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.312997 # average ReadReq mshr miss latency 1558system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency 1559system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency 1560system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.312997 # average overall mshr miss latency 1561system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.312997 # average overall mshr miss latency 1562system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1563system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1564system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1565system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1566system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1567system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1568system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1569system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1570system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1571system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1572system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1573system.disk2.dma_write_txs 1 # Number of DMA write transactions.
	1574system.iobus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1542system.iobus.trans_dist::ReadReq 7381 # Transaction distribution 1543system.iobus.trans_dist::ReadResp 7381 # Transaction distribution 1544system.iobus.trans_dist::WriteReq 53943 # Transaction distribution 1545system.iobus.trans_dist::WriteResp 53943 # Transaction distribution 1546system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10586 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1551system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1552system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1553system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) 1554system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1555system.iobus.pkt_count_system.bridge.master::total 39180 # Packet count per connected master and slave (bytes) 1556system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83468 # Packet count per connected master and slave (bytes) 1557system.iobus.pkt_count_system.tsunami.ide.dma::total 83468 # Packet count per connected master and slave (bytes) 1558system.iobus.pkt_count::total 122648 # Packet count per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42344 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1562system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1563system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::total 68539 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661680 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.tsunami.ide.dma::total 2661680 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.pkt_size::total 2730219 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.reqLayer0.occupancy 10864500 # Layer occupancy (ticks) 1573system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1574system.iobus.reqLayer1.occupancy 814501 # Layer occupancy (ticks) 1575system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1576system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1577system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1578system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1579system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1580system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 1581system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1582system.iobus.reqLayer23.occupancy 14057500 # Layer occupancy (ticks) 1583system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1584system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1585system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1586system.iobus.reqLayer25.occupancy 6034500 # Layer occupancy (ticks) 1587system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1588system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) 1589system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1590system.iobus.reqLayer27.occupancy 216209541 # Layer occupancy (ticks) 1591system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1592system.iobus.respLayer0.occupancy 26789000 # Layer occupancy (ticks) 1593system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1594system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) 1595system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)	1575system.iobus.trans_dist::ReadReq 7381 # Transaction distribution 1576system.iobus.trans_dist::ReadResp 7381 # Transaction distribution 1577system.iobus.trans_dist::WriteReq 53943 # Transaction distribution 1578system.iobus.trans_dist::WriteResp 53943 # Transaction distribution 1579system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10586 # Packet count per connected master and slave (bytes) 1580system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) 1581system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1582system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1583system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1584system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1585system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1586system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) 1587system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1588system.iobus.pkt_count_system.bridge.master::total 39180 # Packet count per connected master and slave (bytes) 1589system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83468 # Packet count per connected master and slave (bytes) 1590system.iobus.pkt_count_system.tsunami.ide.dma::total 83468 # Packet count per connected master and slave (bytes) 1591system.iobus.pkt_count::total 122648 # Packet count per connected master and slave (bytes) 1592system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42344 # Cumulative packet size per connected master and slave (bytes) 1593system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) 1594system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1595system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1596system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1597system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1598system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1599system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) 1600system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1601system.iobus.pkt_size_system.bridge.master::total 68539 # Cumulative packet size per connected master and slave (bytes) 1602system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661680 # Cumulative packet size per connected master and slave (bytes) 1603system.iobus.pkt_size_system.tsunami.ide.dma::total 2661680 # Cumulative packet size per connected master and slave (bytes) 1604system.iobus.pkt_size::total 2730219 # Cumulative packet size per connected master and slave (bytes) 1605system.iobus.reqLayer0.occupancy 10864500 # Layer occupancy (ticks) 1606system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1607system.iobus.reqLayer1.occupancy 814501 # Layer occupancy (ticks) 1608system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1609system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) 1610system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1611system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1612system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1613system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) 1614system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1615system.iobus.reqLayer23.occupancy 14057500 # Layer occupancy (ticks) 1616system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1617system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1618system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1619system.iobus.reqLayer25.occupancy 6034500 # Layer occupancy (ticks) 1620system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1621system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) 1622system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1623system.iobus.reqLayer27.occupancy 216209541 # Layer occupancy (ticks) 1624system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1625system.iobus.respLayer0.occupancy 26789000 # Layer occupancy (ticks) 1626system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1627system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) 1628system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
	1629system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1596system.iocache.tags.replacements 41702 # number of replacements 1597system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use 1598system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1599system.iocache.tags.sampled_refs 41718 # Sample count of references to valid blocks. 1600system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1601system.iocache.tags.warmup_cycle 1712300449000 # Cycle when the warmup percentage was hit. 1602system.iocache.tags.occ_blocks::tsunami.ide 0.516326 # Average occupied blocks per requestor 1603system.iocache.tags.occ_percent::tsunami.ide 0.032270 # Average percentage of cache occupancy 1604system.iocache.tags.occ_percent::total 0.032270 # Average percentage of cache occupancy 1605system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1606system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1607system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1608system.iocache.tags.tag_accesses 375606 # Number of tag accesses 1609system.iocache.tags.data_accesses 375606 # Number of data accesses	1630system.iocache.tags.replacements 41702 # number of replacements 1631system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use 1632system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1633system.iocache.tags.sampled_refs 41718 # Sample count of references to valid blocks. 1634system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1635system.iocache.tags.warmup_cycle 1712300449000 # Cycle when the warmup percentage was hit. 1636system.iocache.tags.occ_blocks::tsunami.ide 0.516326 # Average occupied blocks per requestor 1637system.iocache.tags.occ_percent::tsunami.ide 0.032270 # Average percentage of cache occupancy 1638system.iocache.tags.occ_percent::total 0.032270 # Average percentage of cache occupancy 1639system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1640system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1641system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1642system.iocache.tags.tag_accesses 375606 # Number of tag accesses 1643system.iocache.tags.data_accesses 375606 # Number of data accesses
	1644system.iocache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1610system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses 1611system.iocache.ReadReq_misses::total 182 # number of ReadReq misses 1612system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1613system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1614system.iocache.demand_misses::tsunami.ide 41734 # number of demand (read+write) misses 1615system.iocache.demand_misses::total 41734 # number of demand (read+write) misses 1616system.iocache.overall_misses::tsunami.ide 41734 # number of overall misses 1617system.iocache.overall_misses::total 41734 # number of overall misses 1618system.iocache.ReadReq_miss_latency::tsunami.ide 22913883 # number of ReadReq miss cycles 1619system.iocache.ReadReq_miss_latency::total 22913883 # number of ReadReq miss cycles 1620system.iocache.WriteLineReq_miss_latency::tsunami.ide 4860118658 # number of WriteLineReq miss cycles 1621system.iocache.WriteLineReq_miss_latency::total 4860118658 # number of WriteLineReq miss cycles 1622system.iocache.demand_miss_latency::tsunami.ide 4883032541 # number of demand (read+write) miss cycles 1623system.iocache.demand_miss_latency::total 4883032541 # number of demand (read+write) miss cycles 1624system.iocache.overall_miss_latency::tsunami.ide 4883032541 # number of overall miss cycles 1625system.iocache.overall_miss_latency::total 4883032541 # number of overall miss cycles 1626system.iocache.ReadReq_accesses::tsunami.ide 182 # number of ReadReq accesses(hits+misses) 1627system.iocache.ReadReq_accesses::total 182 # number of ReadReq accesses(hits+misses) 1628system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1629system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1630system.iocache.demand_accesses::tsunami.ide 41734 # number of demand (read+write) accesses 1631system.iocache.demand_accesses::total 41734 # number of demand (read+write) accesses 1632system.iocache.overall_accesses::tsunami.ide 41734 # number of overall (read+write) accesses 1633system.iocache.overall_accesses::total 41734 # number of overall (read+write) accesses 1634system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1635system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1636system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1637system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1638system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1639system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1640system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1641system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1642system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125900.456044 # average ReadReq miss latency 1643system.iocache.ReadReq_avg_miss_latency::total 125900.456044 # average ReadReq miss latency 1644system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116964.734742 # average WriteLineReq miss latency 1645system.iocache.WriteLineReq_avg_miss_latency::total 116964.734742 # average WriteLineReq miss latency 1646system.iocache.demand_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency 1647system.iocache.demand_avg_miss_latency::total 117003.703000 # average overall miss latency 1648system.iocache.overall_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency 1649system.iocache.overall_avg_miss_latency::total 117003.703000 # average overall miss latency 1650system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked 1651system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1652system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1653system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1654system.iocache.avg_blocked_cycles::no_mshrs 37 # average number of cycles each access was blocked 1655system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1656system.iocache.writebacks::writebacks 41520 # number of writebacks 1657system.iocache.writebacks::total 41520 # number of writebacks 1658system.iocache.ReadReq_mshr_misses::tsunami.ide 182 # number of ReadReq MSHR misses 1659system.iocache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses 1660system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1661system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1662system.iocache.demand_mshr_misses::tsunami.ide 41734 # number of demand (read+write) MSHR misses 1663system.iocache.demand_mshr_misses::total 41734 # number of demand (read+write) MSHR misses 1664system.iocache.overall_mshr_misses::tsunami.ide 41734 # number of overall MSHR misses 1665system.iocache.overall_mshr_misses::total 41734 # number of overall MSHR misses 1666system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13813883 # number of ReadReq MSHR miss cycles 1667system.iocache.ReadReq_mshr_miss_latency::total 13813883 # number of ReadReq MSHR miss cycles 1668system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2780093407 # number of WriteLineReq MSHR miss cycles 1669system.iocache.WriteLineReq_mshr_miss_latency::total 2780093407 # number of WriteLineReq MSHR miss cycles 1670system.iocache.demand_mshr_miss_latency::tsunami.ide 2793907290 # number of demand (read+write) MSHR miss cycles 1671system.iocache.demand_mshr_miss_latency::total 2793907290 # number of demand (read+write) MSHR miss cycles 1672system.iocache.overall_mshr_miss_latency::tsunami.ide 2793907290 # number of overall MSHR miss cycles 1673system.iocache.overall_mshr_miss_latency::total 2793907290 # number of overall MSHR miss cycles 1674system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1675system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1676system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1677system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1678system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1679system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1680system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1681system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1682system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75900.456044 # average ReadReq mshr miss latency 1683system.iocache.ReadReq_avg_mshr_miss_latency::total 75900.456044 # average ReadReq mshr miss latency 1684system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66906.368093 # average WriteLineReq mshr miss latency 1685system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66906.368093 # average WriteLineReq mshr miss latency 1686system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency 1687system.iocache.demand_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency 1688system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency 1689system.iocache.overall_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency	1645system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses 1646system.iocache.ReadReq_misses::total 182 # number of ReadReq misses 1647system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1648system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1649system.iocache.demand_misses::tsunami.ide 41734 # number of demand (read+write) misses 1650system.iocache.demand_misses::total 41734 # number of demand (read+write) misses 1651system.iocache.overall_misses::tsunami.ide 41734 # number of overall misses 1652system.iocache.overall_misses::total 41734 # number of overall misses 1653system.iocache.ReadReq_miss_latency::tsunami.ide 22913883 # number of ReadReq miss cycles 1654system.iocache.ReadReq_miss_latency::total 22913883 # number of ReadReq miss cycles 1655system.iocache.WriteLineReq_miss_latency::tsunami.ide 4860118658 # number of WriteLineReq miss cycles 1656system.iocache.WriteLineReq_miss_latency::total 4860118658 # number of WriteLineReq miss cycles 1657system.iocache.demand_miss_latency::tsunami.ide 4883032541 # number of demand (read+write) miss cycles 1658system.iocache.demand_miss_latency::total 4883032541 # number of demand (read+write) miss cycles 1659system.iocache.overall_miss_latency::tsunami.ide 4883032541 # number of overall miss cycles 1660system.iocache.overall_miss_latency::total 4883032541 # number of overall miss cycles 1661system.iocache.ReadReq_accesses::tsunami.ide 182 # number of ReadReq accesses(hits+misses) 1662system.iocache.ReadReq_accesses::total 182 # number of ReadReq accesses(hits+misses) 1663system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1664system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1665system.iocache.demand_accesses::tsunami.ide 41734 # number of demand (read+write) accesses 1666system.iocache.demand_accesses::total 41734 # number of demand (read+write) accesses 1667system.iocache.overall_accesses::tsunami.ide 41734 # number of overall (read+write) accesses 1668system.iocache.overall_accesses::total 41734 # number of overall (read+write) accesses 1669system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1670system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1671system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1672system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1673system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1674system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1675system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1676system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1677system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125900.456044 # average ReadReq miss latency 1678system.iocache.ReadReq_avg_miss_latency::total 125900.456044 # average ReadReq miss latency 1679system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116964.734742 # average WriteLineReq miss latency 1680system.iocache.WriteLineReq_avg_miss_latency::total 116964.734742 # average WriteLineReq miss latency 1681system.iocache.demand_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency 1682system.iocache.demand_avg_miss_latency::total 117003.703000 # average overall miss latency 1683system.iocache.overall_avg_miss_latency::tsunami.ide 117003.703000 # average overall miss latency 1684system.iocache.overall_avg_miss_latency::total 117003.703000 # average overall miss latency 1685system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked 1686system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1687system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1688system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1689system.iocache.avg_blocked_cycles::no_mshrs 37 # average number of cycles each access was blocked 1690system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1691system.iocache.writebacks::writebacks 41520 # number of writebacks 1692system.iocache.writebacks::total 41520 # number of writebacks 1693system.iocache.ReadReq_mshr_misses::tsunami.ide 182 # number of ReadReq MSHR misses 1694system.iocache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses 1695system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1696system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1697system.iocache.demand_mshr_misses::tsunami.ide 41734 # number of demand (read+write) MSHR misses 1698system.iocache.demand_mshr_misses::total 41734 # number of demand (read+write) MSHR misses 1699system.iocache.overall_mshr_misses::tsunami.ide 41734 # number of overall MSHR misses 1700system.iocache.overall_mshr_misses::total 41734 # number of overall MSHR misses 1701system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13813883 # number of ReadReq MSHR miss cycles 1702system.iocache.ReadReq_mshr_miss_latency::total 13813883 # number of ReadReq MSHR miss cycles 1703system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2780093407 # number of WriteLineReq MSHR miss cycles 1704system.iocache.WriteLineReq_mshr_miss_latency::total 2780093407 # number of WriteLineReq MSHR miss cycles 1705system.iocache.demand_mshr_miss_latency::tsunami.ide 2793907290 # number of demand (read+write) MSHR miss cycles 1706system.iocache.demand_mshr_miss_latency::total 2793907290 # number of demand (read+write) MSHR miss cycles 1707system.iocache.overall_mshr_miss_latency::tsunami.ide 2793907290 # number of overall MSHR miss cycles 1708system.iocache.overall_mshr_miss_latency::total 2793907290 # number of overall MSHR miss cycles 1709system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1710system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1711system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1712system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1713system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1714system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1715system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1716system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1717system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75900.456044 # average ReadReq mshr miss latency 1718system.iocache.ReadReq_avg_mshr_miss_latency::total 75900.456044 # average ReadReq mshr miss latency 1719system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66906.368093 # average WriteLineReq mshr miss latency 1720system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66906.368093 # average WriteLineReq mshr miss latency 1721system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency 1722system.iocache.demand_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency 1723system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency 1724system.iocache.overall_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency
	1725system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1690system.l2c.tags.replacements 344399 # number of replacements 1691system.l2c.tags.tagsinuse 65257.528904 # Cycle average of tags in use 1692system.l2c.tags.total_refs 4049043 # Total number of references to valid blocks. 1693system.l2c.tags.sampled_refs 409397 # Sample count of references to valid blocks. 1694system.l2c.tags.avg_refs 9.890261 # Average number of references to valid blocks. 1695system.l2c.tags.warmup_cycle 7589084000 # Cycle when the warmup percentage was hit. 1696system.l2c.tags.occ_blocks::writebacks 53234.554738 # Average occupied blocks per requestor 1697system.l2c.tags.occ_blocks::cpu0.inst 5306.808814 # Average occupied blocks per requestor 1698system.l2c.tags.occ_blocks::cpu0.data 6471.614757 # Average occupied blocks per requestor 1699system.l2c.tags.occ_blocks::cpu1.inst 207.979433 # Average occupied blocks per requestor 1700system.l2c.tags.occ_blocks::cpu1.data 36.571163 # Average occupied blocks per requestor 1701system.l2c.tags.occ_percent::writebacks 0.812295 # Average percentage of cache occupancy 1702system.l2c.tags.occ_percent::cpu0.inst 0.080975 # Average percentage of cache occupancy 1703system.l2c.tags.occ_percent::cpu0.data 0.098749 # Average percentage of cache occupancy 1704system.l2c.tags.occ_percent::cpu1.inst 0.003174 # Average percentage of cache occupancy 1705system.l2c.tags.occ_percent::cpu1.data 0.000558 # Average percentage of cache occupancy 1706system.l2c.tags.occ_percent::total 0.995751 # Average percentage of cache occupancy 1707system.l2c.tags.occ_task_id_blocks::1024 64998 # Occupied blocks per task id 1708system.l2c.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 1709system.l2c.tags.age_task_id_blocks_1024::1 3509 # Occupied blocks per task id 1710system.l2c.tags.age_task_id_blocks_1024::2 3235 # Occupied blocks per task id 1711system.l2c.tags.age_task_id_blocks_1024::3 6125 # Occupied blocks per task id 1712system.l2c.tags.age_task_id_blocks_1024::4 51897 # Occupied blocks per task id 1713system.l2c.tags.occ_task_id_percent::1024 0.991791 # Percentage of cache occupancy per task id 1714system.l2c.tags.tag_accesses 38854214 # Number of tag accesses 1715system.l2c.tags.data_accesses 38854214 # Number of data accesses	1726system.l2c.tags.replacements 344399 # number of replacements 1727system.l2c.tags.tagsinuse 65257.528904 # Cycle average of tags in use 1728system.l2c.tags.total_refs 4049043 # Total number of references to valid blocks. 1729system.l2c.tags.sampled_refs 409397 # Sample count of references to valid blocks. 1730system.l2c.tags.avg_refs 9.890261 # Average number of references to valid blocks. 1731system.l2c.tags.warmup_cycle 7589084000 # Cycle when the warmup percentage was hit. 1732system.l2c.tags.occ_blocks::writebacks 53234.554738 # Average occupied blocks per requestor 1733system.l2c.tags.occ_blocks::cpu0.inst 5306.808814 # Average occupied blocks per requestor 1734system.l2c.tags.occ_blocks::cpu0.data 6471.614757 # Average occupied blocks per requestor 1735system.l2c.tags.occ_blocks::cpu1.inst 207.979433 # Average occupied blocks per requestor 1736system.l2c.tags.occ_blocks::cpu1.data 36.571163 # Average occupied blocks per requestor 1737system.l2c.tags.occ_percent::writebacks 0.812295 # Average percentage of cache occupancy 1738system.l2c.tags.occ_percent::cpu0.inst 0.080975 # Average percentage of cache occupancy 1739system.l2c.tags.occ_percent::cpu0.data 0.098749 # Average percentage of cache occupancy 1740system.l2c.tags.occ_percent::cpu1.inst 0.003174 # Average percentage of cache occupancy 1741system.l2c.tags.occ_percent::cpu1.data 0.000558 # Average percentage of cache occupancy 1742system.l2c.tags.occ_percent::total 0.995751 # Average percentage of cache occupancy 1743system.l2c.tags.occ_task_id_blocks::1024 64998 # Occupied blocks per task id 1744system.l2c.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 1745system.l2c.tags.age_task_id_blocks_1024::1 3509 # Occupied blocks per task id 1746system.l2c.tags.age_task_id_blocks_1024::2 3235 # Occupied blocks per task id 1747system.l2c.tags.age_task_id_blocks_1024::3 6125 # Occupied blocks per task id 1748system.l2c.tags.age_task_id_blocks_1024::4 51897 # Occupied blocks per task id 1749system.l2c.tags.occ_task_id_percent::1024 0.991791 # Percentage of cache occupancy per task id 1750system.l2c.tags.tag_accesses 38854214 # Number of tag accesses 1751system.l2c.tags.data_accesses 38854214 # Number of data accesses
	1752system.l2c.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
1716system.l2c.WritebackDirty_hits::writebacks 830750 # number of WritebackDirty hits 1717system.l2c.WritebackDirty_hits::total 830750 # number of WritebackDirty hits 1718system.l2c.WritebackClean_hits::writebacks 873391 # number of WritebackClean hits 1719system.l2c.WritebackClean_hits::total 873391 # number of WritebackClean hits 1720system.l2c.UpgradeReq_hits::cpu0.data 189 # number of UpgradeReq hits 1721system.l2c.UpgradeReq_hits::cpu1.data 76 # number of UpgradeReq hits 1722system.l2c.UpgradeReq_hits::total 265 # number of UpgradeReq hits 1723system.l2c.SCUpgradeReq_hits::cpu0.data 96 # number of SCUpgradeReq hits 1724system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1725system.l2c.SCUpgradeReq_hits::total 120 # number of SCUpgradeReq hits 1726system.l2c.ReadExReq_hits::cpu0.data 167999 # number of ReadExReq hits 1727system.l2c.ReadExReq_hits::cpu1.data 13850 # number of ReadExReq hits 1728system.l2c.ReadExReq_hits::total 181849 # number of ReadExReq hits 1729system.l2c.ReadCleanReq_hits::cpu0.inst 1008159 # number of ReadCleanReq hits 1730system.l2c.ReadCleanReq_hits::cpu1.inst 124281 # number of ReadCleanReq hits 1731system.l2c.ReadCleanReq_hits::total 1132440 # number of ReadCleanReq hits 1732system.l2c.ReadSharedReq_hits::cpu0.data 779840 # number of ReadSharedReq hits 1733system.l2c.ReadSharedReq_hits::cpu1.data 40945 # number of ReadSharedReq hits 1734system.l2c.ReadSharedReq_hits::total 820785 # number of ReadSharedReq hits 1735system.l2c.demand_hits::cpu0.inst 1008159 # number of demand (read+write) hits 1736system.l2c.demand_hits::cpu0.data 947839 # number of demand (read+write) hits 1737system.l2c.demand_hits::cpu1.inst 124281 # number of demand (read+write) hits 1738system.l2c.demand_hits::cpu1.data 54795 # number of demand (read+write) hits 1739system.l2c.demand_hits::total 2135074 # number of demand (read+write) hits 1740system.l2c.overall_hits::cpu0.inst 1008159 # number of overall hits 1741system.l2c.overall_hits::cpu0.data 947839 # number of overall hits 1742system.l2c.overall_hits::cpu1.inst 124281 # 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number of overall misses 1769system.l2c.overall_misses::total 410025 # number of overall misses 1770system.l2c.UpgradeReq_miss_latency::cpu0.data 1409000 # number of UpgradeReq miss cycles 1771system.l2c.UpgradeReq_miss_latency::cpu1.data 1507500 # number of UpgradeReq miss cycles 1772system.l2c.UpgradeReq_miss_latency::total 2916500 # number of UpgradeReq miss cycles 1773system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533500 # number of SCUpgradeReq miss cycles 1774system.l2c.SCUpgradeReq_miss_latency::cpu1.data 89500 # number of SCUpgradeReq miss cycles 1775system.l2c.SCUpgradeReq_miss_latency::total 623000 # number of SCUpgradeReq miss cycles 1776system.l2c.ReadExReq_miss_latency::cpu0.data 9988107000 # number of ReadExReq miss cycles 1777system.l2c.ReadExReq_miss_latency::cpu1.data 962206500 # number of ReadExReq miss cycles 1778system.l2c.ReadExReq_miss_latency::total 10950313500 # number of ReadExReq miss cycles 1779system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1153739000 # number of ReadCleanReq miss cycles 1780system.l2c.ReadCleanReq_miss_latency::cpu1.inst 140335000 # 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number of overall miss cycles 1792system.l2c.overall_miss_latency::cpu1.inst 140335000 # number of overall miss cycles 1793system.l2c.overall_miss_latency::cpu1.data 1032031000 # number of overall miss cycles 1794system.l2c.overall_miss_latency::total 32524998000 # number of overall miss cycles 1795system.l2c.WritebackDirty_accesses::writebacks 830750 # number of WritebackDirty accesses(hits+misses) 1796system.l2c.WritebackDirty_accesses::total 830750 # number of WritebackDirty accesses(hits+misses) 1797system.l2c.WritebackClean_accesses::writebacks 873391 # number of WritebackClean accesses(hits+misses) 1798system.l2c.WritebackClean_accesses::total 873391 # number of WritebackClean accesses(hits+misses) 1799system.l2c.UpgradeReq_accesses::cpu0.data 2678 # number of UpgradeReq accesses(hits+misses) 1800system.l2c.UpgradeReq_accesses::cpu1.data 681 # number of UpgradeReq accesses(hits+misses) 1801system.l2c.UpgradeReq_accesses::total 3359 # number of UpgradeReq accesses(hits+misses) 1802system.l2c.SCUpgradeReq_accesses::cpu0.data 166 # number of SCUpgradeReq accesses(hits+misses) 1803system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) 1804system.l2c.SCUpgradeReq_accesses::total 291 # number of SCUpgradeReq accesses(hits+misses) 1805system.l2c.ReadExReq_accesses::cpu0.data 279854 # number of ReadExReq accesses(hits+misses) 1806system.l2c.ReadExReq_accesses::cpu1.data 22282 # number of ReadExReq accesses(hits+misses) 1807system.l2c.ReadExReq_accesses::total 302136 # number of ReadExReq accesses(hits+misses) 1808system.l2c.ReadCleanReq_accesses::cpu0.inst 1021805 # number of ReadCleanReq accesses(hits+misses) 1809system.l2c.ReadCleanReq_accesses::cpu1.inst 125911 # number of ReadCleanReq accesses(hits+misses) 1810system.l2c.ReadCleanReq_accesses::total 1147716 # number of ReadCleanReq accesses(hits+misses) 1811system.l2c.ReadSharedReq_accesses::cpu0.data 1053532 # number of ReadSharedReq accesses(hits+misses) 1812system.l2c.ReadSharedReq_accesses::cpu1.data 41715 # number of ReadSharedReq accesses(hits+misses) 1813system.l2c.ReadSharedReq_accesses::total 1095247 # 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miss rate for UpgradeReq accesses 1825system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888399 # miss rate for UpgradeReq accesses 1826system.l2c.UpgradeReq_miss_rate::total 0.921107 # miss rate for UpgradeReq accesses 1827system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.421687 # miss rate for SCUpgradeReq accesses 1828system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.808000 # miss rate for SCUpgradeReq accesses 1829system.l2c.SCUpgradeReq_miss_rate::total 0.587629 # miss rate for SCUpgradeReq accesses 1830system.l2c.ReadExReq_miss_rate::cpu0.data 0.399691 # miss rate for ReadExReq accesses 1831system.l2c.ReadExReq_miss_rate::cpu1.data 0.378422 # miss rate for ReadExReq accesses 1832system.l2c.ReadExReq_miss_rate::total 0.398122 # miss rate for ReadExReq accesses 1833system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.013355 # miss rate for ReadCleanReq accesses 1834system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.012946 # miss rate for ReadCleanReq accesses 1835system.l2c.ReadCleanReq_miss_rate::total 0.013310 # miss rate for ReadCleanReq accesses 1836system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.259785 # miss rate for ReadSharedReq accesses 1837system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.018459 # miss rate for ReadSharedReq accesses 1838system.l2c.ReadSharedReq_miss_rate::total 0.250594 # miss rate for ReadSharedReq accesses 1839system.l2c.demand_miss_rate::cpu0.inst 0.013355 # miss rate for demand accesses 1840system.l2c.demand_miss_rate::cpu0.data 0.289149 # miss rate for demand accesses 1841system.l2c.demand_miss_rate::cpu1.inst 0.012946 # miss rate for demand accesses 1842system.l2c.demand_miss_rate::cpu1.data 0.143788 # miss rate for demand accesses 1843system.l2c.demand_miss_rate::total 0.161104 # miss rate for demand accesses 1844system.l2c.overall_miss_rate::cpu0.inst 0.013355 # miss rate for overall accesses 1845system.l2c.overall_miss_rate::cpu0.data 0.289149 # miss rate for overall accesses 1846system.l2c.overall_miss_rate::cpu1.inst 0.012946 # miss rate for overall accesses 1847system.l2c.overall_miss_rate::cpu1.data 0.143788 # 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average ReadCleanReq miss latency 1859system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86095.092025 # average ReadCleanReq miss latency 1860system.l2c.ReadCleanReq_avg_miss_latency::total 84712.882954 # average ReadCleanReq miss latency 1861system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73845.000950 # average ReadSharedReq miss latency 1862system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90681.168831 # average ReadSharedReq miss latency 1863system.l2c.ReadSharedReq_avg_miss_latency::total 73892.234626 # average ReadSharedReq miss latency 1864system.l2c.demand_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency 1865system.l2c.demand_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency 1866system.l2c.demand_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency 1867system.l2c.demand_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency 1868system.l2c.demand_avg_miss_latency::total 79324.426559 # average overall miss latency 1869system.l2c.overall_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency 1870system.l2c.overall_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency 1871system.l2c.overall_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency 1872system.l2c.overall_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency 1873system.l2c.overall_avg_miss_latency::total 79324.426559 # average overall miss latency 1874system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1875system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1876system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1877system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1878system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1879system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1880system.l2c.writebacks::writebacks 81135 # number of writebacks 1881system.l2c.writebacks::total 81135 # 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number of UpgradeReq MSHR misses 1895system.l2c.UpgradeReq_mshr_misses::total 3094 # number of UpgradeReq MSHR misses 1896system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 70 # number of SCUpgradeReq MSHR misses 1897system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 101 # number of SCUpgradeReq MSHR misses 1898system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses 1899system.l2c.ReadExReq_mshr_misses::cpu0.data 111855 # number of ReadExReq MSHR misses 1900system.l2c.ReadExReq_mshr_misses::cpu1.data 8432 # number of ReadExReq MSHR misses 1901system.l2c.ReadExReq_mshr_misses::total 120287 # number of ReadExReq MSHR misses 1902system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13645 # number of ReadCleanReq MSHR misses 1903system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1613 # number of ReadCleanReq MSHR misses 1904system.l2c.ReadCleanReq_mshr_misses::total 15258 # number of ReadCleanReq MSHR misses 1905system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273692 # number of ReadSharedReq MSHR misses 1906system.l2c.ReadSharedReq_mshr_misses::cpu1.data 770 # number of ReadSharedReq MSHR misses 1907system.l2c.ReadSharedReq_mshr_misses::total 274462 # number of ReadSharedReq MSHR misses 1908system.l2c.demand_mshr_misses::cpu0.inst 13645 # number of demand (read+write) MSHR misses 1909system.l2c.demand_mshr_misses::cpu0.data 385547 # number of demand (read+write) MSHR misses 1910system.l2c.demand_mshr_misses::cpu1.inst 1613 # number of demand (read+write) MSHR misses 1911system.l2c.demand_mshr_misses::cpu1.data 9202 # number of demand (read+write) MSHR misses 1912system.l2c.demand_mshr_misses::total 410007 # number of demand (read+write) MSHR misses 1913system.l2c.overall_mshr_misses::cpu0.inst 13645 # number of overall MSHR misses 1914system.l2c.overall_mshr_misses::cpu0.data 385547 # number of overall MSHR misses 1915system.l2c.overall_mshr_misses::cpu1.inst 1613 # number of overall MSHR misses 1916system.l2c.overall_mshr_misses::cpu1.data 9202 # number of overall MSHR misses 1917system.l2c.overall_mshr_misses::total 410007 # number of overall MSHR misses 1918system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable 1919system.l2c.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable 1920system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable 1921system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable 1922system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable 1923system.l2c.WriteReq_mshr_uncacheable::total 12391 # number of WriteReq MSHR uncacheable 1924system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses 1925system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses 1926system.l2c.overall_mshr_uncacheable_misses::total 19590 # number of overall MSHR uncacheable misses 1927system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49921000 # number of UpgradeReq MSHR miss cycles 1928system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12220000 # number of UpgradeReq MSHR miss cycles 1929system.l2c.UpgradeReq_mshr_miss_latency::total 62141000 # number of UpgradeReq MSHR miss cycles 1930system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1392500 # number of SCUpgradeReq MSHR miss cycles 1931system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1996500 # number of SCUpgradeReq MSHR miss cycles 1932system.l2c.SCUpgradeReq_mshr_miss_latency::total 3389000 # number of SCUpgradeReq MSHR miss cycles 1933system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8869557000 # number of ReadExReq MSHR miss cycles 1934system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 877886500 # number of ReadExReq MSHR miss cycles 1935system.l2c.ReadExReq_mshr_miss_latency::total 9747443500 # number of ReadExReq MSHR miss cycles 1936system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1017206501 # number of ReadCleanReq MSHR miss cycles 1937system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 122964001 # number of ReadCleanReq MSHR miss cycles 1938system.l2c.ReadCleanReq_mshr_miss_latency::total 1140170502 # number of ReadCleanReq MSHR miss cycles 1939system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17480141501 # number of ReadSharedReq MSHR miss cycles 1940system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 62124500 # number of ReadSharedReq MSHR miss cycles 1941system.l2c.ReadSharedReq_mshr_miss_latency::total 17542266001 # number of ReadSharedReq MSHR miss cycles 1942system.l2c.demand_mshr_miss_latency::cpu0.inst 1017206501 # number of demand (read+write) MSHR miss cycles 1943system.l2c.demand_mshr_miss_latency::cpu0.data 26349698501 # number of demand (read+write) MSHR miss cycles 1944system.l2c.demand_mshr_miss_latency::cpu1.inst 122964001 # number of demand (read+write) MSHR miss cycles 1945system.l2c.demand_mshr_miss_latency::cpu1.data 940011000 # number of demand (read+write) MSHR miss cycles 1946system.l2c.demand_mshr_miss_latency::total 28429880003 # number of demand (read+write) MSHR miss cycles 1947system.l2c.overall_mshr_miss_latency::cpu0.inst 1017206501 # number of overall MSHR miss cycles 1948system.l2c.overall_mshr_miss_latency::cpu0.data 26349698501 # number of overall MSHR miss cycles 1949system.l2c.overall_mshr_miss_latency::cpu1.inst 122964001 # number of overall MSHR miss cycles 1950system.l2c.overall_mshr_miss_latency::cpu1.data 940011000 # number of overall MSHR miss cycles 1951system.l2c.overall_mshr_miss_latency::total 28429880003 # number of overall MSHR miss cycles 1952system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1482000500 # number of ReadReq MSHR uncacheable cycles 1953system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27810500 # number of ReadReq MSHR uncacheable cycles 1954system.l2c.ReadReq_mshr_uncacheable_latency::total 1509811000 # number of ReadReq MSHR uncacheable cycles 1955system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1482000500 # number of overall MSHR uncacheable cycles 1956system.l2c.overall_mshr_uncacheable_latency::cpu1.data 27810500 # number of overall MSHR uncacheable cycles 1957system.l2c.overall_mshr_uncacheable_latency::total 1509811000 # number of overall MSHR uncacheable cycles 1958system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1959system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1960system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.929425 # mshr miss rate for UpgradeReq accesses 1961system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888399 # mshr miss rate for UpgradeReq accesses 1962system.l2c.UpgradeReq_mshr_miss_rate::total 0.921107 # mshr miss rate for UpgradeReq accesses 1963system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.421687 # mshr miss rate for SCUpgradeReq accesses 1964system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808000 # mshr miss rate for SCUpgradeReq accesses 1965system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587629 # mshr miss rate for SCUpgradeReq accesses 1966system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.399691 # mshr miss rate for ReadExReq accesses 1967system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.378422 # mshr miss rate for ReadExReq accesses 1968system.l2c.ReadExReq_mshr_miss_rate::total 0.398122 # mshr miss rate for ReadExReq accesses 1969system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for ReadCleanReq accesses 1970system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for ReadCleanReq accesses 1971system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013294 # mshr miss rate for ReadCleanReq accesses 1972system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.259785 # mshr miss rate for ReadSharedReq accesses 1973system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.018459 # mshr miss rate for ReadSharedReq accesses 1974system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250594 # mshr miss rate for ReadSharedReq accesses 1975system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for demand accesses 1976system.l2c.demand_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for demand accesses 1977system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for demand accesses 1978system.l2c.demand_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for demand accesses 1979system.l2c.demand_mshr_miss_rate::total 0.161097 # mshr miss rate for demand accesses 1980system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for overall accesses 1981system.l2c.overall_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for overall accesses 1982system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for overall accesses 1983system.l2c.overall_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for overall accesses 1984system.l2c.overall_mshr_miss_rate::total 0.161097 # mshr miss rate for overall accesses 1985system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20056.649257 # average UpgradeReq mshr miss latency 1986system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20198.347107 # average UpgradeReq mshr miss latency 1987system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20084.356820 # average UpgradeReq mshr miss latency 1988system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19892.857143 # average SCUpgradeReq mshr miss latency 1989system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19767.326733 # average SCUpgradeReq mshr miss latency 1990system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19818.713450 # average SCUpgradeReq mshr miss latency 1991system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79295.132091 # average ReadExReq mshr miss latency 1992system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104113.674099 # average ReadExReq mshr miss latency 1993system.l2c.ReadExReq_avg_mshr_miss_latency::total 81034.887394 # average ReadExReq mshr miss latency 1994system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average ReadCleanReq mshr miss latency 1995system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average ReadCleanReq mshr miss latency 1996system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74726.078254 # average ReadCleanReq mshr miss latency 1997system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63867.930013 # average ReadSharedReq mshr miss latency 1998system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80681.168831 # average ReadSharedReq mshr miss latency 1999system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63915.099362 # average ReadSharedReq mshr miss latency 2000system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency 2001system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency 2002system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency 2003system.l2c.demand_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency 2004system.l2c.demand_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency 2005system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency 2006system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency 2007system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency 2008system.l2c.overall_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency 2009system.l2c.overall_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency 2010system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210123.422657 # average ReadReq mshr uncacheable latency 2011system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190482.876712 # average ReadReq mshr uncacheable latency 2012system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209725.100708 # average ReadReq mshr uncacheable latency 2013system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87900.385528 # average overall mshr uncacheable latency 2014system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10186.996337 # average overall mshr uncacheable latency 2015system.l2c.overall_avg_mshr_uncacheable_latency::total 77070.495151 # average overall mshr uncacheable latency 2016system.membus.snoop_filter.tot_requests 843888 # Total number of requests made to the snoop filter. 2017system.membus.snoop_filter.hit_single_requests 393117 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2018system.membus.snoop_filter.hit_multi_requests 439 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2019system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2020system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2021system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	1753system.l2c.WritebackDirty_hits::writebacks 830750 # number of WritebackDirty hits 1754system.l2c.WritebackDirty_hits::total 830750 # number of WritebackDirty hits 1755system.l2c.WritebackClean_hits::writebacks 873391 # number of WritebackClean hits 1756system.l2c.WritebackClean_hits::total 873391 # number of WritebackClean hits 1757system.l2c.UpgradeReq_hits::cpu0.data 189 # number of UpgradeReq hits 1758system.l2c.UpgradeReq_hits::cpu1.data 76 # number of UpgradeReq hits 1759system.l2c.UpgradeReq_hits::total 265 # number of UpgradeReq hits 1760system.l2c.SCUpgradeReq_hits::cpu0.data 96 # number of SCUpgradeReq hits 1761system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1762system.l2c.SCUpgradeReq_hits::total 120 # number of SCUpgradeReq hits 1763system.l2c.ReadExReq_hits::cpu0.data 167999 # number of ReadExReq hits 1764system.l2c.ReadExReq_hits::cpu1.data 13850 # number of ReadExReq hits 1765system.l2c.ReadExReq_hits::total 181849 # number of ReadExReq hits 1766system.l2c.ReadCleanReq_hits::cpu0.inst 1008159 # number of ReadCleanReq hits 1767system.l2c.ReadCleanReq_hits::cpu1.inst 124281 # number of ReadCleanReq hits 1768system.l2c.ReadCleanReq_hits::total 1132440 # number of ReadCleanReq hits 1769system.l2c.ReadSharedReq_hits::cpu0.data 779840 # number of ReadSharedReq hits 1770system.l2c.ReadSharedReq_hits::cpu1.data 40945 # number of ReadSharedReq hits 1771system.l2c.ReadSharedReq_hits::total 820785 # number of ReadSharedReq hits 1772system.l2c.demand_hits::cpu0.inst 1008159 # number of demand (read+write) hits 1773system.l2c.demand_hits::cpu0.data 947839 # number of demand (read+write) hits 1774system.l2c.demand_hits::cpu1.inst 124281 # number of demand (read+write) hits 1775system.l2c.demand_hits::cpu1.data 54795 # number of demand (read+write) hits 1776system.l2c.demand_hits::total 2135074 # number of demand (read+write) hits 1777system.l2c.overall_hits::cpu0.inst 1008159 # number of overall hits 1778system.l2c.overall_hits::cpu0.data 947839 # number of overall hits 1779system.l2c.overall_hits::cpu1.inst 124281 # number of overall hits 1780system.l2c.overall_hits::cpu1.data 54795 # number of overall hits 1781system.l2c.overall_hits::total 2135074 # number of overall hits 1782system.l2c.UpgradeReq_misses::cpu0.data 2489 # number of UpgradeReq misses 1783system.l2c.UpgradeReq_misses::cpu1.data 605 # number of UpgradeReq misses 1784system.l2c.UpgradeReq_misses::total 3094 # number of UpgradeReq misses 1785system.l2c.SCUpgradeReq_misses::cpu0.data 70 # number of SCUpgradeReq misses 1786system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses 1787system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses 1788system.l2c.ReadExReq_misses::cpu0.data 111855 # number of ReadExReq misses 1789system.l2c.ReadExReq_misses::cpu1.data 8432 # number of ReadExReq misses 1790system.l2c.ReadExReq_misses::total 120287 # number of ReadExReq misses 1791system.l2c.ReadCleanReq_misses::cpu0.inst 13646 # number of ReadCleanReq misses 1792system.l2c.ReadCleanReq_misses::cpu1.inst 1630 # number of ReadCleanReq misses 1793system.l2c.ReadCleanReq_misses::total 15276 # number of ReadCleanReq misses 1794system.l2c.ReadSharedReq_misses::cpu0.data 273692 # number of ReadSharedReq misses 1795system.l2c.ReadSharedReq_misses::cpu1.data 770 # number of ReadSharedReq misses 1796system.l2c.ReadSharedReq_misses::total 274462 # number of ReadSharedReq misses 1797system.l2c.demand_misses::cpu0.inst 13646 # number of demand (read+write) misses 1798system.l2c.demand_misses::cpu0.data 385547 # number of demand (read+write) misses 1799system.l2c.demand_misses::cpu1.inst 1630 # number of demand (read+write) misses 1800system.l2c.demand_misses::cpu1.data 9202 # number of demand (read+write) misses 1801system.l2c.demand_misses::total 410025 # number of demand (read+write) misses 1802system.l2c.overall_misses::cpu0.inst 13646 # number of overall misses 1803system.l2c.overall_misses::cpu0.data 385547 # number of overall misses 1804system.l2c.overall_misses::cpu1.inst 1630 # number of overall misses 1805system.l2c.overall_misses::cpu1.data 9202 # number of overall misses 1806system.l2c.overall_misses::total 410025 # number of overall misses 1807system.l2c.UpgradeReq_miss_latency::cpu0.data 1409000 # number of UpgradeReq miss cycles 1808system.l2c.UpgradeReq_miss_latency::cpu1.data 1507500 # number of UpgradeReq miss cycles 1809system.l2c.UpgradeReq_miss_latency::total 2916500 # number of UpgradeReq miss cycles 1810system.l2c.SCUpgradeReq_miss_latency::cpu0.data 533500 # number of SCUpgradeReq miss cycles 1811system.l2c.SCUpgradeReq_miss_latency::cpu1.data 89500 # number of SCUpgradeReq miss cycles 1812system.l2c.SCUpgradeReq_miss_latency::total 623000 # number of SCUpgradeReq miss cycles 1813system.l2c.ReadExReq_miss_latency::cpu0.data 9988107000 # number of ReadExReq miss cycles 1814system.l2c.ReadExReq_miss_latency::cpu1.data 962206500 # number of ReadExReq miss cycles 1815system.l2c.ReadExReq_miss_latency::total 10950313500 # number of ReadExReq miss cycles 1816system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1153739000 # number of ReadCleanReq miss cycles 1817system.l2c.ReadCleanReq_miss_latency::cpu1.inst 140335000 # number of ReadCleanReq miss cycles 1818system.l2c.ReadCleanReq_miss_latency::total 1294074000 # number of ReadCleanReq miss cycles 1819system.l2c.ReadSharedReq_miss_latency::cpu0.data 20210786000 # number of ReadSharedReq miss cycles 1820system.l2c.ReadSharedReq_miss_latency::cpu1.data 69824500 # number of ReadSharedReq miss cycles 1821system.l2c.ReadSharedReq_miss_latency::total 20280610500 # number of ReadSharedReq miss cycles 1822system.l2c.demand_miss_latency::cpu0.inst 1153739000 # number of demand (read+write) miss cycles 1823system.l2c.demand_miss_latency::cpu0.data 30198893000 # number of demand (read+write) miss cycles 1824system.l2c.demand_miss_latency::cpu1.inst 140335000 # number of demand (read+write) miss cycles 1825system.l2c.demand_miss_latency::cpu1.data 1032031000 # number of demand (read+write) miss cycles 1826system.l2c.demand_miss_latency::total 32524998000 # number of demand (read+write) miss cycles 1827system.l2c.overall_miss_latency::cpu0.inst 1153739000 # number of overall miss cycles 1828system.l2c.overall_miss_latency::cpu0.data 30198893000 # number of overall miss cycles 1829system.l2c.overall_miss_latency::cpu1.inst 140335000 # number of overall miss cycles 1830system.l2c.overall_miss_latency::cpu1.data 1032031000 # number of overall miss cycles 1831system.l2c.overall_miss_latency::total 32524998000 # number of overall miss cycles 1832system.l2c.WritebackDirty_accesses::writebacks 830750 # number of WritebackDirty accesses(hits+misses) 1833system.l2c.WritebackDirty_accesses::total 830750 # number of WritebackDirty accesses(hits+misses) 1834system.l2c.WritebackClean_accesses::writebacks 873391 # number of WritebackClean accesses(hits+misses) 1835system.l2c.WritebackClean_accesses::total 873391 # number of WritebackClean accesses(hits+misses) 1836system.l2c.UpgradeReq_accesses::cpu0.data 2678 # number of UpgradeReq accesses(hits+misses) 1837system.l2c.UpgradeReq_accesses::cpu1.data 681 # number of UpgradeReq accesses(hits+misses) 1838system.l2c.UpgradeReq_accesses::total 3359 # number of UpgradeReq accesses(hits+misses) 1839system.l2c.SCUpgradeReq_accesses::cpu0.data 166 # number of SCUpgradeReq accesses(hits+misses) 1840system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) 1841system.l2c.SCUpgradeReq_accesses::total 291 # number of SCUpgradeReq accesses(hits+misses) 1842system.l2c.ReadExReq_accesses::cpu0.data 279854 # number of ReadExReq accesses(hits+misses) 1843system.l2c.ReadExReq_accesses::cpu1.data 22282 # number of ReadExReq accesses(hits+misses) 1844system.l2c.ReadExReq_accesses::total 302136 # number of ReadExReq accesses(hits+misses) 1845system.l2c.ReadCleanReq_accesses::cpu0.inst 1021805 # number of ReadCleanReq accesses(hits+misses) 1846system.l2c.ReadCleanReq_accesses::cpu1.inst 125911 # number of ReadCleanReq accesses(hits+misses) 1847system.l2c.ReadCleanReq_accesses::total 1147716 # number of ReadCleanReq accesses(hits+misses) 1848system.l2c.ReadSharedReq_accesses::cpu0.data 1053532 # number of ReadSharedReq accesses(hits+misses) 1849system.l2c.ReadSharedReq_accesses::cpu1.data 41715 # number of ReadSharedReq accesses(hits+misses) 1850system.l2c.ReadSharedReq_accesses::total 1095247 # number of ReadSharedReq accesses(hits+misses) 1851system.l2c.demand_accesses::cpu0.inst 1021805 # number of demand (read+write) accesses 1852system.l2c.demand_accesses::cpu0.data 1333386 # number of demand (read+write) accesses 1853system.l2c.demand_accesses::cpu1.inst 125911 # number of demand (read+write) accesses 1854system.l2c.demand_accesses::cpu1.data 63997 # number of demand (read+write) accesses 1855system.l2c.demand_accesses::total 2545099 # number of demand (read+write) accesses 1856system.l2c.overall_accesses::cpu0.inst 1021805 # number of overall (read+write) accesses 1857system.l2c.overall_accesses::cpu0.data 1333386 # number of overall (read+write) accesses 1858system.l2c.overall_accesses::cpu1.inst 125911 # number of overall (read+write) accesses 1859system.l2c.overall_accesses::cpu1.data 63997 # number of overall (read+write) accesses 1860system.l2c.overall_accesses::total 2545099 # number of overall (read+write) accesses 1861system.l2c.UpgradeReq_miss_rate::cpu0.data 0.929425 # miss rate for UpgradeReq accesses 1862system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888399 # miss rate for UpgradeReq accesses 1863system.l2c.UpgradeReq_miss_rate::total 0.921107 # miss rate for UpgradeReq accesses 1864system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.421687 # miss rate for SCUpgradeReq accesses 1865system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.808000 # miss rate for SCUpgradeReq accesses 1866system.l2c.SCUpgradeReq_miss_rate::total 0.587629 # miss rate for SCUpgradeReq accesses 1867system.l2c.ReadExReq_miss_rate::cpu0.data 0.399691 # miss rate for ReadExReq accesses 1868system.l2c.ReadExReq_miss_rate::cpu1.data 0.378422 # miss rate for ReadExReq accesses 1869system.l2c.ReadExReq_miss_rate::total 0.398122 # miss rate for ReadExReq accesses 1870system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.013355 # miss rate for ReadCleanReq accesses 1871system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.012946 # miss rate for ReadCleanReq accesses 1872system.l2c.ReadCleanReq_miss_rate::total 0.013310 # miss rate for ReadCleanReq accesses 1873system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.259785 # miss rate for ReadSharedReq accesses 1874system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.018459 # miss rate for ReadSharedReq accesses 1875system.l2c.ReadSharedReq_miss_rate::total 0.250594 # miss rate for ReadSharedReq accesses 1876system.l2c.demand_miss_rate::cpu0.inst 0.013355 # miss rate for demand accesses 1877system.l2c.demand_miss_rate::cpu0.data 0.289149 # miss rate for demand accesses 1878system.l2c.demand_miss_rate::cpu1.inst 0.012946 # miss rate for demand accesses 1879system.l2c.demand_miss_rate::cpu1.data 0.143788 # miss rate for demand accesses 1880system.l2c.demand_miss_rate::total 0.161104 # miss rate for demand accesses 1881system.l2c.overall_miss_rate::cpu0.inst 0.013355 # miss rate for overall accesses 1882system.l2c.overall_miss_rate::cpu0.data 0.289149 # miss rate for overall accesses 1883system.l2c.overall_miss_rate::cpu1.inst 0.012946 # miss rate for overall accesses 1884system.l2c.overall_miss_rate::cpu1.data 0.143788 # miss rate for overall accesses 1885system.l2c.overall_miss_rate::total 0.161104 # miss rate for overall accesses 1886system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 566.090800 # average UpgradeReq miss latency 1887system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2491.735537 # average UpgradeReq miss latency 1888system.l2c.UpgradeReq_avg_miss_latency::total 942.630899 # average UpgradeReq miss latency 1889system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7621.428571 # average SCUpgradeReq miss latency 1890system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.138614 # average SCUpgradeReq miss latency 1891system.l2c.SCUpgradeReq_avg_miss_latency::total 3643.274854 # average SCUpgradeReq miss latency 1892system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89295.132091 # average ReadExReq miss latency 1893system.l2c.ReadExReq_avg_miss_latency::cpu1.data 114113.674099 # average ReadExReq miss latency 1894system.l2c.ReadExReq_avg_miss_latency::total 91034.887394 # average ReadExReq miss latency 1895system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84547.779569 # average ReadCleanReq miss latency 1896system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86095.092025 # average ReadCleanReq miss latency 1897system.l2c.ReadCleanReq_avg_miss_latency::total 84712.882954 # average ReadCleanReq miss latency 1898system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73845.000950 # average ReadSharedReq miss latency 1899system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90681.168831 # average ReadSharedReq miss latency 1900system.l2c.ReadSharedReq_avg_miss_latency::total 73892.234626 # average ReadSharedReq miss latency 1901system.l2c.demand_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency 1902system.l2c.demand_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency 1903system.l2c.demand_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency 1904system.l2c.demand_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency 1905system.l2c.demand_avg_miss_latency::total 79324.426559 # average overall miss latency 1906system.l2c.overall_avg_miss_latency::cpu0.inst 84547.779569 # average overall miss latency 1907system.l2c.overall_avg_miss_latency::cpu0.data 78327.397179 # average overall miss latency 1908system.l2c.overall_avg_miss_latency::cpu1.inst 86095.092025 # average overall miss latency 1909system.l2c.overall_avg_miss_latency::cpu1.data 112152.901543 # average overall miss latency 1910system.l2c.overall_avg_miss_latency::total 79324.426559 # average overall miss latency 1911system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1912system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1913system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1914system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1915system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1916system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1917system.l2c.writebacks::writebacks 81135 # number of writebacks 1918system.l2c.writebacks::total 81135 # number of writebacks 1919system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 1920system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits 1921system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits 1922system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 1923system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits 1924system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 1925system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 1926system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits 1927system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 1928system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1929system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1930system.l2c.UpgradeReq_mshr_misses::cpu0.data 2489 # number of UpgradeReq MSHR misses 1931system.l2c.UpgradeReq_mshr_misses::cpu1.data 605 # number of UpgradeReq MSHR misses 1932system.l2c.UpgradeReq_mshr_misses::total 3094 # number of UpgradeReq MSHR misses 1933system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 70 # number of SCUpgradeReq MSHR misses 1934system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 101 # number of SCUpgradeReq MSHR misses 1935system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses 1936system.l2c.ReadExReq_mshr_misses::cpu0.data 111855 # number of ReadExReq MSHR misses 1937system.l2c.ReadExReq_mshr_misses::cpu1.data 8432 # number of ReadExReq MSHR misses 1938system.l2c.ReadExReq_mshr_misses::total 120287 # number of ReadExReq MSHR misses 1939system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13645 # number of ReadCleanReq MSHR misses 1940system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1613 # number of ReadCleanReq MSHR misses 1941system.l2c.ReadCleanReq_mshr_misses::total 15258 # number of ReadCleanReq MSHR misses 1942system.l2c.ReadSharedReq_mshr_misses::cpu0.data 273692 # number of ReadSharedReq MSHR misses 1943system.l2c.ReadSharedReq_mshr_misses::cpu1.data 770 # number of ReadSharedReq MSHR misses 1944system.l2c.ReadSharedReq_mshr_misses::total 274462 # number of ReadSharedReq MSHR misses 1945system.l2c.demand_mshr_misses::cpu0.inst 13645 # number of demand (read+write) MSHR misses 1946system.l2c.demand_mshr_misses::cpu0.data 385547 # number of demand (read+write) MSHR misses 1947system.l2c.demand_mshr_misses::cpu1.inst 1613 # number of demand (read+write) MSHR misses 1948system.l2c.demand_mshr_misses::cpu1.data 9202 # number of demand (read+write) MSHR misses 1949system.l2c.demand_mshr_misses::total 410007 # number of demand (read+write) MSHR misses 1950system.l2c.overall_mshr_misses::cpu0.inst 13645 # number of overall MSHR misses 1951system.l2c.overall_mshr_misses::cpu0.data 385547 # number of overall MSHR misses 1952system.l2c.overall_mshr_misses::cpu1.inst 1613 # number of overall MSHR misses 1953system.l2c.overall_mshr_misses::cpu1.data 9202 # number of overall MSHR misses 1954system.l2c.overall_mshr_misses::total 410007 # number of overall MSHR misses 1955system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7053 # number of ReadReq MSHR uncacheable 1956system.l2c.ReadReq_mshr_uncacheable::cpu1.data 146 # number of ReadReq MSHR uncacheable 1957system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable 1958system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9807 # number of WriteReq MSHR uncacheable 1959system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2584 # number of WriteReq MSHR uncacheable 1960system.l2c.WriteReq_mshr_uncacheable::total 12391 # number of WriteReq MSHR uncacheable 1961system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16860 # number of overall MSHR uncacheable misses 1962system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2730 # number of overall MSHR uncacheable misses 1963system.l2c.overall_mshr_uncacheable_misses::total 19590 # number of overall MSHR uncacheable misses 1964system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49921000 # number of UpgradeReq MSHR miss cycles 1965system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12220000 # number of UpgradeReq MSHR miss cycles 1966system.l2c.UpgradeReq_mshr_miss_latency::total 62141000 # number of UpgradeReq MSHR miss cycles 1967system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1392500 # number of SCUpgradeReq MSHR miss cycles 1968system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1996500 # number of SCUpgradeReq MSHR miss cycles 1969system.l2c.SCUpgradeReq_mshr_miss_latency::total 3389000 # number of SCUpgradeReq MSHR miss cycles 1970system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8869557000 # number of ReadExReq MSHR miss cycles 1971system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 877886500 # number of ReadExReq MSHR miss cycles 1972system.l2c.ReadExReq_mshr_miss_latency::total 9747443500 # number of ReadExReq MSHR miss cycles 1973system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1017206501 # number of ReadCleanReq MSHR miss cycles 1974system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 122964001 # number of ReadCleanReq MSHR miss cycles 1975system.l2c.ReadCleanReq_mshr_miss_latency::total 1140170502 # number of ReadCleanReq MSHR miss cycles 1976system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17480141501 # number of ReadSharedReq MSHR miss cycles 1977system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 62124500 # number of ReadSharedReq MSHR miss cycles 1978system.l2c.ReadSharedReq_mshr_miss_latency::total 17542266001 # number of ReadSharedReq MSHR miss cycles 1979system.l2c.demand_mshr_miss_latency::cpu0.inst 1017206501 # number of demand (read+write) MSHR miss cycles 1980system.l2c.demand_mshr_miss_latency::cpu0.data 26349698501 # number of demand (read+write) MSHR miss cycles 1981system.l2c.demand_mshr_miss_latency::cpu1.inst 122964001 # number of demand (read+write) MSHR miss cycles 1982system.l2c.demand_mshr_miss_latency::cpu1.data 940011000 # number of demand (read+write) MSHR miss cycles 1983system.l2c.demand_mshr_miss_latency::total 28429880003 # number of demand (read+write) MSHR miss cycles 1984system.l2c.overall_mshr_miss_latency::cpu0.inst 1017206501 # number of overall MSHR miss cycles 1985system.l2c.overall_mshr_miss_latency::cpu0.data 26349698501 # number of overall MSHR miss cycles 1986system.l2c.overall_mshr_miss_latency::cpu1.inst 122964001 # number of overall MSHR miss cycles 1987system.l2c.overall_mshr_miss_latency::cpu1.data 940011000 # number of overall MSHR miss cycles 1988system.l2c.overall_mshr_miss_latency::total 28429880003 # number of overall MSHR miss cycles 1989system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1482000500 # number of ReadReq MSHR uncacheable cycles 1990system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27810500 # number of ReadReq MSHR uncacheable cycles 1991system.l2c.ReadReq_mshr_uncacheable_latency::total 1509811000 # number of ReadReq MSHR uncacheable cycles 1992system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1482000500 # number of overall MSHR uncacheable cycles 1993system.l2c.overall_mshr_uncacheable_latency::cpu1.data 27810500 # number of overall MSHR uncacheable cycles 1994system.l2c.overall_mshr_uncacheable_latency::total 1509811000 # number of overall MSHR uncacheable cycles 1995system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1996system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1997system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.929425 # mshr miss rate for UpgradeReq accesses 1998system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888399 # mshr miss rate for UpgradeReq accesses 1999system.l2c.UpgradeReq_mshr_miss_rate::total 0.921107 # mshr miss rate for UpgradeReq accesses 2000system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.421687 # mshr miss rate for SCUpgradeReq accesses 2001system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808000 # mshr miss rate for SCUpgradeReq accesses 2002system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587629 # mshr miss rate for SCUpgradeReq accesses 2003system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.399691 # mshr miss rate for ReadExReq accesses 2004system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.378422 # mshr miss rate for ReadExReq accesses 2005system.l2c.ReadExReq_mshr_miss_rate::total 0.398122 # mshr miss rate for ReadExReq accesses 2006system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for ReadCleanReq accesses 2007system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for ReadCleanReq accesses 2008system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013294 # mshr miss rate for ReadCleanReq accesses 2009system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.259785 # mshr miss rate for ReadSharedReq accesses 2010system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.018459 # mshr miss rate for ReadSharedReq accesses 2011system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250594 # mshr miss rate for ReadSharedReq accesses 2012system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for demand accesses 2013system.l2c.demand_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for demand accesses 2014system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for demand accesses 2015system.l2c.demand_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for demand accesses 2016system.l2c.demand_mshr_miss_rate::total 0.161097 # mshr miss rate for demand accesses 2017system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013354 # mshr miss rate for overall accesses 2018system.l2c.overall_mshr_miss_rate::cpu0.data 0.289149 # mshr miss rate for overall accesses 2019system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012811 # mshr miss rate for overall accesses 2020system.l2c.overall_mshr_miss_rate::cpu1.data 0.143788 # mshr miss rate for overall accesses 2021system.l2c.overall_mshr_miss_rate::total 0.161097 # mshr miss rate for overall accesses 2022system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20056.649257 # average UpgradeReq mshr miss latency 2023system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20198.347107 # average UpgradeReq mshr miss latency 2024system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20084.356820 # average UpgradeReq mshr miss latency 2025system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19892.857143 # average SCUpgradeReq mshr miss latency 2026system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19767.326733 # average SCUpgradeReq mshr miss latency 2027system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19818.713450 # average SCUpgradeReq mshr miss latency 2028system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79295.132091 # average ReadExReq mshr miss latency 2029system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104113.674099 # average ReadExReq mshr miss latency 2030system.l2c.ReadExReq_avg_mshr_miss_latency::total 81034.887394 # average ReadExReq mshr miss latency 2031system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average ReadCleanReq mshr miss latency 2032system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average ReadCleanReq mshr miss latency 2033system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74726.078254 # average ReadCleanReq mshr miss latency 2034system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63867.930013 # average ReadSharedReq mshr miss latency 2035system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80681.168831 # average ReadSharedReq mshr miss latency 2036system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63915.099362 # average ReadSharedReq mshr miss latency 2037system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency 2038system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency 2039system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency 2040system.l2c.demand_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency 2041system.l2c.demand_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency 2042system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74547.929718 # average overall mshr miss latency 2043system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68343.674055 # average overall mshr miss latency 2044system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76233.106634 # average overall mshr miss latency 2045system.l2c.overall_avg_mshr_miss_latency::cpu1.data 102152.901543 # average overall mshr miss latency 2046system.l2c.overall_avg_mshr_miss_latency::total 69339.986886 # average overall mshr miss latency 2047system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210123.422657 # average ReadReq mshr uncacheable latency 2048system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190482.876712 # average ReadReq mshr uncacheable latency 2049system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209725.100708 # average ReadReq mshr uncacheable latency 2050system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87900.385528 # average overall mshr uncacheable latency 2051system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10186.996337 # average overall mshr uncacheable latency 2052system.l2c.overall_avg_mshr_uncacheable_latency::total 77070.495151 # average overall mshr uncacheable latency 2053system.membus.snoop_filter.tot_requests 843888 # Total number of requests made to the snoop filter. 2054system.membus.snoop_filter.hit_single_requests 393117 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2055system.membus.snoop_filter.hit_multi_requests 439 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2056system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2057system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2058system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	2059system.membus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
2022system.membus.trans_dist::ReadReq 7199 # Transaction distribution 2023system.membus.trans_dist::ReadResp 297053 # Transaction distribution 2024system.membus.trans_dist::WriteReq 12391 # Transaction distribution 2025system.membus.trans_dist::WriteResp 12391 # Transaction distribution 2026system.membus.trans_dist::WritebackDirty 122655 # Transaction distribution 2027system.membus.trans_dist::CleanEvict 262560 # Transaction distribution 2028system.membus.trans_dist::UpgradeReq 5361 # Transaction distribution 2029system.membus.trans_dist::SCUpgradeReq 1592 # Transaction distribution 2030system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 2031system.membus.trans_dist::ReadExReq 120253 # Transaction distribution 2032system.membus.trans_dist::ReadExResp 120107 # Transaction distribution 2033system.membus.trans_dist::ReadSharedReq 289902 # Transaction distribution 2034system.membus.trans_dist::BadAddressError 48 # Transaction distribution 2035system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 2036system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39180 # Packet count per connected master and slave (bytes) 2037system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1169885 # Packet count per connected master and slave (bytes) 2038system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 96 # Packet count per connected master and slave (bytes) 2039system.membus.pkt_count_system.l2c.mem_side::total 1209161 # Packet count per connected master and slave (bytes) 2040system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83451 # Packet count per connected master and slave (bytes) 2041system.membus.pkt_count_system.iocache.mem_side::total 83451 # Packet count per connected master and slave (bytes) 2042system.membus.pkt_count::total 1292612 # Packet count per connected master and slave (bytes) 2043system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68539 # Cumulative packet size per connected master and slave (bytes) 2044system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31400256 # Cumulative packet size per connected master and slave (bytes) 2045system.membus.pkt_size_system.l2c.mem_side::total 31468795 # Cumulative packet size per connected master and slave (bytes) 2046system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 2047system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 2048system.membus.pkt_size::total 34127035 # Cumulative packet size per connected master and slave (bytes) 2049system.membus.snoops 4109 # Total snoops (count) 2050system.membus.snoop_fanout::samples 478250 # Request fanout histogram 2051system.membus.snoop_fanout::mean 0.001409 # Request fanout histogram 2052system.membus.snoop_fanout::stdev 0.037514 # Request fanout histogram 2053system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2054system.membus.snoop_fanout::0 477576 99.86% 99.86% # Request fanout histogram 2055system.membus.snoop_fanout::1 674 0.14% 100.00% # Request fanout histogram 2056system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2057system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2058system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2059system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2060system.membus.snoop_fanout::total 478250 # Request fanout histogram 2061system.membus.reqLayer0.occupancy 34894499 # Layer occupancy (ticks) 2062system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2063system.membus.reqLayer1.occupancy 1351079796 # Layer occupancy (ticks) 2064system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 2065system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) 2066system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2067system.membus.respLayer1.occupancy 2171993250 # Layer occupancy (ticks) 2068system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 2069system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) 2070system.membus.respLayer2.utilization 0.0 # Layer utilization (%)	2060system.membus.trans_dist::ReadReq 7199 # Transaction distribution 2061system.membus.trans_dist::ReadResp 297053 # Transaction distribution 2062system.membus.trans_dist::WriteReq 12391 # Transaction distribution 2063system.membus.trans_dist::WriteResp 12391 # Transaction distribution 2064system.membus.trans_dist::WritebackDirty 122655 # Transaction distribution 2065system.membus.trans_dist::CleanEvict 262560 # Transaction distribution 2066system.membus.trans_dist::UpgradeReq 5361 # Transaction distribution 2067system.membus.trans_dist::SCUpgradeReq 1592 # Transaction distribution 2068system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 2069system.membus.trans_dist::ReadExReq 120253 # Transaction distribution 2070system.membus.trans_dist::ReadExResp 120107 # Transaction distribution 2071system.membus.trans_dist::ReadSharedReq 289902 # Transaction distribution 2072system.membus.trans_dist::BadAddressError 48 # Transaction distribution 2073system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 2074system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39180 # Packet count per connected master and slave (bytes) 2075system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1169885 # Packet count per connected master and slave (bytes) 2076system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 96 # Packet count per connected master and slave (bytes) 2077system.membus.pkt_count_system.l2c.mem_side::total 1209161 # Packet count per connected master and slave (bytes) 2078system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83451 # Packet count per connected master and slave (bytes) 2079system.membus.pkt_count_system.iocache.mem_side::total 83451 # Packet count per connected master and slave (bytes) 2080system.membus.pkt_count::total 1292612 # Packet count per connected master and slave (bytes) 2081system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68539 # Cumulative packet size per connected master and slave (bytes) 2082system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31400256 # Cumulative packet size per connected master and slave (bytes) 2083system.membus.pkt_size_system.l2c.mem_side::total 31468795 # Cumulative packet size per connected master and slave (bytes) 2084system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 2085system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 2086system.membus.pkt_size::total 34127035 # Cumulative packet size per connected master and slave (bytes) 2087system.membus.snoops 4109 # Total snoops (count) 2088system.membus.snoop_fanout::samples 478250 # Request fanout histogram 2089system.membus.snoop_fanout::mean 0.001409 # Request fanout histogram 2090system.membus.snoop_fanout::stdev 0.037514 # Request fanout histogram 2091system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2092system.membus.snoop_fanout::0 477576 99.86% 99.86% # Request fanout histogram 2093system.membus.snoop_fanout::1 674 0.14% 100.00% # Request fanout histogram 2094system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2095system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2096system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2097system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2098system.membus.snoop_fanout::total 478250 # Request fanout histogram 2099system.membus.reqLayer0.occupancy 34894499 # Layer occupancy (ticks) 2100system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2101system.membus.reqLayer1.occupancy 1351079796 # Layer occupancy (ticks) 2102system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 2103system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) 2104system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2105system.membus.respLayer1.occupancy 2171993250 # Layer occupancy (ticks) 2106system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 2107system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) 2108system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
	2109system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
2071system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. 2072system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2073system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2074system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. 2075system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2076system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	2110system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. 2111system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2112system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2113system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. 2114system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2115system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	2116system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
2077system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 2078system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution 2079system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution 2080system.toL2Bus.trans_dist::WriteResp 12391 # Transaction distribution 2081system.toL2Bus.trans_dist::WritebackDirty 911885 # Transaction distribution 2082system.toL2Bus.trans_dist::WritebackClean 1146691 # Transaction distribution 2083system.toL2Bus.trans_dist::CleanEvict 834780 # Transaction distribution 2084system.toL2Bus.trans_dist::UpgradeReq 5446 # Transaction distribution 2085system.toL2Bus.trans_dist::SCUpgradeReq 1712 # Transaction distribution 2086system.toL2Bus.trans_dist::UpgradeResp 7158 # Transaction distribution 2087system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2088system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 2089system.toL2Bus.trans_dist::ReadExReq 303166 # Transaction distribution 2090system.toL2Bus.trans_dist::ReadExResp 303166 # Transaction distribution 2091system.toL2Bus.trans_dist::ReadCleanReq 1147985 # Transaction distribution 2092system.toL2Bus.trans_dist::ReadSharedReq 1108204 # Transaction distribution 2093system.toL2Bus.trans_dist::BadAddressError 48 # Transaction distribution 2094system.toL2Bus.trans_dist::InvalidateReq 217 # Transaction distribution 2095system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3065153 # Packet count per connected master and slave (bytes) 2096system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4053991 # Packet count per connected master and slave (bytes) 2097system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 377239 # Packet count per connected master and slave (bytes) 2098system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 207014 # Packet count per connected master and slave (bytes) 2099system.toL2Bus.pkt_count::total 7703397 # Packet count per connected master and slave (bytes) 2100system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 130759360 # Cumulative packet size per connected master and slave (bytes) 2101system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 136128589 # Cumulative packet size per connected master and slave (bytes) 2102system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16082688 # Cumulative packet size per connected master and slave (bytes) 2103system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6548014 # Cumulative packet size per connected master and slave (bytes) 2104system.toL2Bus.pkt_size::total 289518651 # Cumulative packet size per connected master and slave (bytes) 2105system.toL2Bus.snoops 362547 # Total snoops (count) 2106system.toL2Bus.snoop_fanout::samples 2930720 # Request fanout histogram 2107system.toL2Bus.snoop_fanout::mean 0.118515 # Request fanout histogram 2108system.toL2Bus.snoop_fanout::stdev 0.323634 # Request fanout histogram 2109system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2110system.toL2Bus.snoop_fanout::0 2583760 88.16% 88.16% # Request fanout histogram 2111system.toL2Bus.snoop_fanout::1 346605 11.83% 99.99% # Request fanout histogram 2112system.toL2Bus.snoop_fanout::2 335 0.01% 100.00% # Request fanout histogram 2113system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram 2114system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2115system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2116system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2117system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2118system.toL2Bus.snoop_fanout::total 2930720 # Request fanout histogram 2119system.toL2Bus.reqLayer0.occupancy 4551122919 # Layer occupancy (ticks) 2120system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 2121system.toL2Bus.snoopLayer0.occupancy 306385 # Layer occupancy (ticks) 2122system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2123system.toL2Bus.respLayer0.occupancy 1534824957 # Layer occupancy (ticks) 2124system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2125system.toL2Bus.respLayer1.occupancy 2028150819 # Layer occupancy (ticks) 2126system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2127system.toL2Bus.respLayer2.occupancy 190444943 # Layer occupancy (ticks) 2128system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2129system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) 2130system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)	2117system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 2118system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution 2119system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution 2120system.toL2Bus.trans_dist::WriteResp 12391 # Transaction distribution 2121system.toL2Bus.trans_dist::WritebackDirty 911885 # Transaction distribution 2122system.toL2Bus.trans_dist::WritebackClean 1146691 # Transaction distribution 2123system.toL2Bus.trans_dist::CleanEvict 834780 # Transaction distribution 2124system.toL2Bus.trans_dist::UpgradeReq 5446 # Transaction distribution 2125system.toL2Bus.trans_dist::SCUpgradeReq 1712 # Transaction distribution 2126system.toL2Bus.trans_dist::UpgradeResp 7158 # Transaction distribution 2127system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2128system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 2129system.toL2Bus.trans_dist::ReadExReq 303166 # Transaction distribution 2130system.toL2Bus.trans_dist::ReadExResp 303166 # Transaction distribution 2131system.toL2Bus.trans_dist::ReadCleanReq 1147985 # Transaction distribution 2132system.toL2Bus.trans_dist::ReadSharedReq 1108204 # Transaction distribution 2133system.toL2Bus.trans_dist::BadAddressError 48 # Transaction distribution 2134system.toL2Bus.trans_dist::InvalidateReq 217 # Transaction distribution 2135system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3065153 # Packet count per connected master and slave (bytes) 2136system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4053991 # Packet count per connected master and slave (bytes) 2137system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 377239 # Packet count per connected master and slave (bytes) 2138system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 207014 # Packet count per connected master and slave (bytes) 2139system.toL2Bus.pkt_count::total 7703397 # Packet count per connected master and slave (bytes) 2140system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 130759360 # Cumulative packet size per connected master and slave (bytes) 2141system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 136128589 # Cumulative packet size per connected master and slave (bytes) 2142system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16082688 # Cumulative packet size per connected master and slave (bytes) 2143system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6548014 # Cumulative packet size per connected master and slave (bytes) 2144system.toL2Bus.pkt_size::total 289518651 # Cumulative packet size per connected master and slave (bytes) 2145system.toL2Bus.snoops 362547 # Total snoops (count) 2146system.toL2Bus.snoop_fanout::samples 2930720 # Request fanout histogram 2147system.toL2Bus.snoop_fanout::mean 0.118515 # Request fanout histogram 2148system.toL2Bus.snoop_fanout::stdev 0.323634 # Request fanout histogram 2149system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2150system.toL2Bus.snoop_fanout::0 2583760 88.16% 88.16% # Request fanout histogram 2151system.toL2Bus.snoop_fanout::1 346605 11.83% 99.99% # Request fanout histogram 2152system.toL2Bus.snoop_fanout::2 335 0.01% 100.00% # Request fanout histogram 2153system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram 2154system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 2155system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2156system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2157system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 2158system.toL2Bus.snoop_fanout::total 2930720 # Request fanout histogram 2159system.toL2Bus.reqLayer0.occupancy 4551122919 # Layer occupancy (ticks) 2160system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 2161system.toL2Bus.snoopLayer0.occupancy 306385 # Layer occupancy (ticks) 2162system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2163system.toL2Bus.respLayer0.occupancy 1534824957 # Layer occupancy (ticks) 2164system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2165system.toL2Bus.respLayer1.occupancy 2028150819 # Layer occupancy (ticks) 2166system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 2167system.toL2Bus.respLayer2.occupancy 190444943 # Layer occupancy (ticks) 2168system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2169system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) 2170system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
	2171system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2172system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2173system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2174system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
2131system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2132system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2133system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2134system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2135system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2136system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2137system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2138system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2139system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2140system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2141system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2142system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2143system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2144system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2145system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2146system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2147system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2148system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2149system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2150system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2151system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2152system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2153system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2154system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2155system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2156system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2157system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2158system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2159system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2160system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2161system.tsunami.ethernet.droppedPackets 0 # number of packets dropped	2175system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2176system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2177system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2178system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2179system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2180system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2181system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2182system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2183system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2184system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2185system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2186system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2187system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2188system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2189system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2190system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2191system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2192system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2193system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2194system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2195system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2196system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2197system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2198system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2199system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2200system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2201system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2202system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2203system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2204system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2205system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
	2206system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2207system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2208system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2209system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2210system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2211system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2212system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2213system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2214system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2215system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2216system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2217system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2218system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2219system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2220system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2221system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2222system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2223system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2224system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2225system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2226system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2227system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states 2228system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states
2162system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2163system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed 2164system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed 2165system.cpu0.kern.ipl_count::0 71138 40.62% 40.62% # number of times we switched to this ipl 2166system.cpu0.kern.ipl_count::21 133 0.08% 40.69% # number of times we switched to this ipl 2167system.cpu0.kern.ipl_count::22 1928 1.10% 41.79% # number of times we switched to this ipl 2168system.cpu0.kern.ipl_count::30 20 0.01% 41.80% # number of times we switched to this ipl 2169system.cpu0.kern.ipl_count::31 101928 58.20% 100.00% # number of times we switched to this ipl 2170system.cpu0.kern.ipl_count::total 175147 # number of times we switched to this ipl 2171system.cpu0.kern.ipl_good::0 69801 49.27% 49.27% # number of times we switched to this ipl from a different ipl 2172system.cpu0.kern.ipl_good::21 133 0.09% 49.37% # number of times we switched to this ipl from a different ipl 2173system.cpu0.kern.ipl_good::22 1928 1.36% 50.73% # number of times we switched to this ipl from a different ipl 2174system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl 2175system.cpu0.kern.ipl_good::31 69782 49.26% 100.00% # number of times we switched to this ipl from a different ipl 2176system.cpu0.kern.ipl_good::total 141664 # number of times we switched to this ipl from a different ipl 2177system.cpu0.kern.ipl_ticks::0 1864307233500 97.69% 97.69% # number of cycles we spent at this ipl 2178system.cpu0.kern.ipl_ticks::21 66845500 0.00% 97.70% # number of cycles we spent at this ipl 2179system.cpu0.kern.ipl_ticks::22 580922500 0.03% 97.73% # number of cycles we spent at this ipl 2180system.cpu0.kern.ipl_ticks::30 11315500 0.00% 97.73% # number of cycles we spent at this ipl 2181system.cpu0.kern.ipl_ticks::31 43373119000 2.27% 100.00% # number of cycles we spent at this ipl 2182system.cpu0.kern.ipl_ticks::total 1908339436000 # number of cycles we spent at this ipl 2183system.cpu0.kern.ipl_used::0 0.981206 # fraction of swpipl calls that actually changed the ipl 2184system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2185system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2186system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2187system.cpu0.kern.ipl_used::31 0.684621 # fraction of swpipl calls that actually changed the ipl 2188system.cpu0.kern.ipl_used::total 0.808829 # fraction of swpipl calls that actually changed the ipl 2189system.cpu0.kern.syscall::2 8 3.70% 3.70% # number of syscalls executed 2190system.cpu0.kern.syscall::3 18 8.33% 12.04% # number of syscalls executed 2191system.cpu0.kern.syscall::4 4 1.85% 13.89% # number of syscalls executed 2192system.cpu0.kern.syscall::6 32 14.81% 28.70% # number of syscalls executed 2193system.cpu0.kern.syscall::12 1 0.46% 29.17% # number of syscalls executed 2194system.cpu0.kern.syscall::17 8 3.70% 32.87% # number of syscalls executed 2195system.cpu0.kern.syscall::19 10 4.63% 37.50% # number of syscalls executed 2196system.cpu0.kern.syscall::20 6 2.78% 40.28% # number of syscalls executed 2197system.cpu0.kern.syscall::23 1 0.46% 40.74% # number of syscalls executed 2198system.cpu0.kern.syscall::24 3 1.39% 42.13% # number of syscalls executed 2199system.cpu0.kern.syscall::33 6 2.78% 44.91% # number of syscalls executed 2200system.cpu0.kern.syscall::41 2 0.93% 45.83% # number of syscalls executed 2201system.cpu0.kern.syscall::45 33 15.28% 61.11% # number of syscalls executed 2202system.cpu0.kern.syscall::47 3 1.39% 62.50% # number of syscalls executed 2203system.cpu0.kern.syscall::48 10 4.63% 67.13% # number of syscalls executed 2204system.cpu0.kern.syscall::54 10 4.63% 71.76% # number of syscalls executed 2205system.cpu0.kern.syscall::58 1 0.46% 72.22% # number of syscalls executed 2206system.cpu0.kern.syscall::59 6 2.78% 75.00% # number of syscalls executed 2207system.cpu0.kern.syscall::71 23 10.65% 85.65% # number of syscalls executed 2208system.cpu0.kern.syscall::73 3 1.39% 87.04% # number of syscalls executed 2209system.cpu0.kern.syscall::74 6 2.78% 89.81% # number of syscalls executed 2210system.cpu0.kern.syscall::87 1 0.46% 90.28% # number of syscalls executed 2211system.cpu0.kern.syscall::90 3 1.39% 91.67% # number of syscalls executed 2212system.cpu0.kern.syscall::92 9 4.17% 95.83% # number of syscalls executed 2213system.cpu0.kern.syscall::97 2 0.93% 96.76% # number of syscalls executed 2214system.cpu0.kern.syscall::98 2 0.93% 97.69% # number of syscalls executed 2215system.cpu0.kern.syscall::132 1 0.46% 98.15% # number of syscalls executed 2216system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed 2217system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed 2218system.cpu0.kern.syscall::total 216 # number of syscalls executed 2219system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2220system.cpu0.kern.callpal::wripir 116 0.06% 0.06% # number of callpals executed 2221system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 2222system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 2223system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 2224system.cpu0.kern.callpal::swpctx 3824 2.08% 2.14% # number of callpals executed 2225system.cpu0.kern.callpal::tbi 51 0.03% 2.17% # number of callpals executed 2226system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed 2227system.cpu0.kern.callpal::swpipl 168401 91.54% 93.72% # number of callpals executed 2228system.cpu0.kern.callpal::rdps 6369 3.46% 97.18% # number of callpals executed 2229system.cpu0.kern.callpal::wrkgp 1 0.00% 97.18% # number of callpals executed 2230system.cpu0.kern.callpal::wrusp 2 0.00% 97.18% # number of callpals executed 2231system.cpu0.kern.callpal::rdusp 9 0.00% 97.19% # number of callpals executed 2232system.cpu0.kern.callpal::whami 2 0.00% 97.19% # number of callpals executed 2233system.cpu0.kern.callpal::rti 4665 2.54% 99.72% # number of callpals executed 2234system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed 2235system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 2236system.cpu0.kern.callpal::total 183960 # number of callpals executed 2237system.cpu0.kern.mode_switch::kernel 7174 # number of protection mode switches 2238system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches 2239system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2240system.cpu0.kern.mode_good::kernel 1257 2241system.cpu0.kern.mode_good::user 1257 2242system.cpu0.kern.mode_good::idle 0 2243system.cpu0.kern.mode_switch_good::kernel 0.175216 # fraction of useful protection mode switches 2244system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2245system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2246system.cpu0.kern.mode_switch_good::total 0.298185 # fraction of useful protection mode switches 2247system.cpu0.kern.mode_ticks::kernel 1906404052500 99.90% 99.90% # number of ticks spent at the given mode 2248system.cpu0.kern.mode_ticks::user 1926707500 0.10% 100.00% # number of ticks spent at the given mode 2249system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2250system.cpu0.kern.swap_context 3825 # number of times the context was actually changed 2251system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2252system.cpu1.kern.inst.quiesce 2309 # number of quiesce instructions executed 2253system.cpu1.kern.inst.hwrei 39314 # number of hwrei instructions executed 2254system.cpu1.kern.ipl_count::0 10555 33.51% 33.51% # number of times we switched to this ipl 2255system.cpu1.kern.ipl_count::22 1926 6.11% 39.62% # number of times we switched to this ipl 2256system.cpu1.kern.ipl_count::30 116 0.37% 39.99% # number of times we switched to this ipl 2257system.cpu1.kern.ipl_count::31 18905 60.01% 100.00% # number of times we switched to this ipl 2258system.cpu1.kern.ipl_count::total 31502 # number of times we switched to this ipl 2259system.cpu1.kern.ipl_good::0 10515 45.81% 45.81% # number of times we switched to this ipl from a different ipl 2260system.cpu1.kern.ipl_good::22 1926 8.39% 54.19% # number of times we switched to this ipl from a different ipl 2261system.cpu1.kern.ipl_good::30 116 0.51% 54.70% # number of times we switched to this ipl from a different ipl 2262system.cpu1.kern.ipl_good::31 10399 45.30% 100.00% # number of times we switched to this ipl from a different ipl 2263system.cpu1.kern.ipl_good::total 22956 # number of times we switched to this ipl from a different ipl 2264system.cpu1.kern.ipl_ticks::0 1877342030500 98.36% 98.36% # number of cycles we spent at this ipl 2265system.cpu1.kern.ipl_ticks::22 564972500 0.03% 98.39% # number of cycles we spent at this ipl 2266system.cpu1.kern.ipl_ticks::30 56160500 0.00% 98.39% # number of cycles we spent at this ipl 2267system.cpu1.kern.ipl_ticks::31 30688096500 1.61% 100.00% # number of cycles we spent at this ipl 2268system.cpu1.kern.ipl_ticks::total 1908651260000 # number of cycles we spent at this ipl 2269system.cpu1.kern.ipl_used::0 0.996210 # fraction of swpipl calls that actually changed the ipl 2270system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2271system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2272system.cpu1.kern.ipl_used::31 0.550066 # fraction of swpipl calls that actually changed the ipl 2273system.cpu1.kern.ipl_used::total 0.728716 # fraction of swpipl calls that actually changed the ipl 2274system.cpu1.kern.syscall::3 12 10.91% 10.91% # number of syscalls executed 2275system.cpu1.kern.syscall::6 10 9.09% 20.00% # number of syscalls executed 2276system.cpu1.kern.syscall::15 1 0.91% 20.91% # number of syscalls executed 2277system.cpu1.kern.syscall::17 7 6.36% 27.27% # number of syscalls executed 2278system.cpu1.kern.syscall::23 3 2.73% 30.00% # number of syscalls executed 2279system.cpu1.kern.syscall::24 3 2.73% 32.73% # number of syscalls executed 2280system.cpu1.kern.syscall::33 5 4.55% 37.27% # number of syscalls executed 2281system.cpu1.kern.syscall::45 21 19.09% 56.36% # number of syscalls executed 2282system.cpu1.kern.syscall::47 3 2.73% 59.09% # number of syscalls executed 2283system.cpu1.kern.syscall::59 1 0.91% 60.00% # number of syscalls executed 2284system.cpu1.kern.syscall::71 31 28.18% 88.18% # number of syscalls executed 2285system.cpu1.kern.syscall::74 10 9.09% 97.27% # number of syscalls executed 2286system.cpu1.kern.syscall::132 3 2.73% 100.00% # number of syscalls executed 2287system.cpu1.kern.syscall::total 110 # number of syscalls executed 2288system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2289system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed 2290system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2291system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2292system.cpu1.kern.callpal::swpctx 440 1.35% 1.42% # number of callpals executed 2293system.cpu1.kern.callpal::tbi 3 0.01% 1.43% # number of callpals executed 2294system.cpu1.kern.callpal::wrent 7 0.02% 1.45% # number of callpals executed 2295system.cpu1.kern.callpal::swpipl 26890 82.68% 84.13% # number of callpals executed 2296system.cpu1.kern.callpal::rdps 2393 7.36% 91.49% # number of callpals executed 2297system.cpu1.kern.callpal::wrkgp 1 0.00% 91.50% # number of callpals executed 2298system.cpu1.kern.callpal::wrusp 5 0.02% 91.51% # number of callpals executed 2299system.cpu1.kern.callpal::whami 3 0.01% 91.52% # number of callpals executed 2300system.cpu1.kern.callpal::rti 2569 7.90% 99.42% # number of callpals executed 2301system.cpu1.kern.callpal::callsys 144 0.44% 99.86% # number of callpals executed 2302system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed 2303system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2304system.cpu1.kern.callpal::total 32523 # number of callpals executed 2305system.cpu1.kern.mode_switch::kernel 900 # number of protection mode switches 2306system.cpu1.kern.mode_switch::user 488 # number of protection mode switches 2307system.cpu1.kern.mode_switch::idle 2082 # number of protection mode switches 2308system.cpu1.kern.mode_good::kernel 529 2309system.cpu1.kern.mode_good::user 488 2310system.cpu1.kern.mode_good::idle 41 2311system.cpu1.kern.mode_switch_good::kernel 0.587778 # fraction of useful protection mode switches 2312system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2313system.cpu1.kern.mode_switch_good::idle 0.019693 # fraction of useful protection mode switches 2314system.cpu1.kern.mode_switch_good::total 0.304899 # fraction of useful protection mode switches 2315system.cpu1.kern.mode_ticks::kernel 2122812500 0.11% 0.11% # number of ticks spent at the given mode 2316system.cpu1.kern.mode_ticks::user 785064000 0.04% 0.15% # number of ticks spent at the given mode 2317system.cpu1.kern.mode_ticks::idle 1905743375500 99.85% 100.00% # number of ticks spent at the given mode 2318system.cpu1.kern.swap_context 441 # number of times the context was actually changed 2319 2320---------- End Simulation Statistics ----------	2229system.cpu0.kern.inst.arm 0 # number of arm instructions executed 2230system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed 2231system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed 2232system.cpu0.kern.ipl_count::0 71138 40.62% 40.62% # number of times we switched to this ipl 2233system.cpu0.kern.ipl_count::21 133 0.08% 40.69% # number of times we switched to this ipl 2234system.cpu0.kern.ipl_count::22 1928 1.10% 41.79% # number of times we switched to this ipl 2235system.cpu0.kern.ipl_count::30 20 0.01% 41.80% # number of times we switched to this ipl 2236system.cpu0.kern.ipl_count::31 101928 58.20% 100.00% # number of times we switched to this ipl 2237system.cpu0.kern.ipl_count::total 175147 # number of times we switched to this ipl 2238system.cpu0.kern.ipl_good::0 69801 49.27% 49.27% # number of times we switched to this ipl from a different ipl 2239system.cpu0.kern.ipl_good::21 133 0.09% 49.37% # number of times we switched to this ipl from a different ipl 2240system.cpu0.kern.ipl_good::22 1928 1.36% 50.73% # number of times we switched to this ipl from a different ipl 2241system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl 2242system.cpu0.kern.ipl_good::31 69782 49.26% 100.00% # number of times we switched to this ipl from a different ipl 2243system.cpu0.kern.ipl_good::total 141664 # number of times we switched to this ipl from a different ipl 2244system.cpu0.kern.ipl_ticks::0 1864307233500 97.69% 97.69% # number of cycles we spent at this ipl 2245system.cpu0.kern.ipl_ticks::21 66845500 0.00% 97.70% # number of cycles we spent at this ipl 2246system.cpu0.kern.ipl_ticks::22 580922500 0.03% 97.73% # number of cycles we spent at this ipl 2247system.cpu0.kern.ipl_ticks::30 11315500 0.00% 97.73% # number of cycles we spent at this ipl 2248system.cpu0.kern.ipl_ticks::31 43373119000 2.27% 100.00% # number of cycles we spent at this ipl 2249system.cpu0.kern.ipl_ticks::total 1908339436000 # number of cycles we spent at this ipl 2250system.cpu0.kern.ipl_used::0 0.981206 # fraction of swpipl calls that actually changed the ipl 2251system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2252system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2253system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2254system.cpu0.kern.ipl_used::31 0.684621 # fraction of swpipl calls that actually changed the ipl 2255system.cpu0.kern.ipl_used::total 0.808829 # fraction of swpipl calls that actually changed the ipl 2256system.cpu0.kern.syscall::2 8 3.70% 3.70% # number of syscalls executed 2257system.cpu0.kern.syscall::3 18 8.33% 12.04% # number of syscalls executed 2258system.cpu0.kern.syscall::4 4 1.85% 13.89% # number of syscalls executed 2259system.cpu0.kern.syscall::6 32 14.81% 28.70% # number of syscalls executed 2260system.cpu0.kern.syscall::12 1 0.46% 29.17% # number of syscalls executed 2261system.cpu0.kern.syscall::17 8 3.70% 32.87% # number of syscalls executed 2262system.cpu0.kern.syscall::19 10 4.63% 37.50% # number of syscalls executed 2263system.cpu0.kern.syscall::20 6 2.78% 40.28% # number of syscalls executed 2264system.cpu0.kern.syscall::23 1 0.46% 40.74% # number of syscalls executed 2265system.cpu0.kern.syscall::24 3 1.39% 42.13% # number of syscalls executed 2266system.cpu0.kern.syscall::33 6 2.78% 44.91% # number of syscalls executed 2267system.cpu0.kern.syscall::41 2 0.93% 45.83% # number of syscalls executed 2268system.cpu0.kern.syscall::45 33 15.28% 61.11% # number of syscalls executed 2269system.cpu0.kern.syscall::47 3 1.39% 62.50% # number of syscalls executed 2270system.cpu0.kern.syscall::48 10 4.63% 67.13% # number of syscalls executed 2271system.cpu0.kern.syscall::54 10 4.63% 71.76% # number of syscalls executed 2272system.cpu0.kern.syscall::58 1 0.46% 72.22% # number of syscalls executed 2273system.cpu0.kern.syscall::59 6 2.78% 75.00% # number of syscalls executed 2274system.cpu0.kern.syscall::71 23 10.65% 85.65% # number of syscalls executed 2275system.cpu0.kern.syscall::73 3 1.39% 87.04% # number of syscalls executed 2276system.cpu0.kern.syscall::74 6 2.78% 89.81% # number of syscalls executed 2277system.cpu0.kern.syscall::87 1 0.46% 90.28% # number of syscalls executed 2278system.cpu0.kern.syscall::90 3 1.39% 91.67% # number of syscalls executed 2279system.cpu0.kern.syscall::92 9 4.17% 95.83% # number of syscalls executed 2280system.cpu0.kern.syscall::97 2 0.93% 96.76% # number of syscalls executed 2281system.cpu0.kern.syscall::98 2 0.93% 97.69% # number of syscalls executed 2282system.cpu0.kern.syscall::132 1 0.46% 98.15% # number of syscalls executed 2283system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed 2284system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed 2285system.cpu0.kern.syscall::total 216 # number of syscalls executed 2286system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2287system.cpu0.kern.callpal::wripir 116 0.06% 0.06% # number of callpals executed 2288system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed 2289system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed 2290system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed 2291system.cpu0.kern.callpal::swpctx 3824 2.08% 2.14% # number of callpals executed 2292system.cpu0.kern.callpal::tbi 51 0.03% 2.17% # number of callpals executed 2293system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed 2294system.cpu0.kern.callpal::swpipl 168401 91.54% 93.72% # number of callpals executed 2295system.cpu0.kern.callpal::rdps 6369 3.46% 97.18% # number of callpals executed 2296system.cpu0.kern.callpal::wrkgp 1 0.00% 97.18% # number of callpals executed 2297system.cpu0.kern.callpal::wrusp 2 0.00% 97.18% # number of callpals executed 2298system.cpu0.kern.callpal::rdusp 9 0.00% 97.19% # number of callpals executed 2299system.cpu0.kern.callpal::whami 2 0.00% 97.19% # number of callpals executed 2300system.cpu0.kern.callpal::rti 4665 2.54% 99.72% # number of callpals executed 2301system.cpu0.kern.callpal::callsys 373 0.20% 99.93% # number of callpals executed 2302system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 2303system.cpu0.kern.callpal::total 183960 # number of callpals executed 2304system.cpu0.kern.mode_switch::kernel 7174 # number of protection mode switches 2305system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches 2306system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 2307system.cpu0.kern.mode_good::kernel 1257 2308system.cpu0.kern.mode_good::user 1257 2309system.cpu0.kern.mode_good::idle 0 2310system.cpu0.kern.mode_switch_good::kernel 0.175216 # fraction of useful protection mode switches 2311system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2312system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 2313system.cpu0.kern.mode_switch_good::total 0.298185 # fraction of useful protection mode switches 2314system.cpu0.kern.mode_ticks::kernel 1906404052500 99.90% 99.90% # number of ticks spent at the given mode 2315system.cpu0.kern.mode_ticks::user 1926707500 0.10% 100.00% # number of ticks spent at the given mode 2316system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 2317system.cpu0.kern.swap_context 3825 # number of times the context was actually changed 2318system.cpu1.kern.inst.arm 0 # number of arm instructions executed 2319system.cpu1.kern.inst.quiesce 2309 # number of quiesce instructions executed 2320system.cpu1.kern.inst.hwrei 39314 # number of hwrei instructions executed 2321system.cpu1.kern.ipl_count::0 10555 33.51% 33.51% # number of times we switched to this ipl 2322system.cpu1.kern.ipl_count::22 1926 6.11% 39.62% # number of times we switched to this ipl 2323system.cpu1.kern.ipl_count::30 116 0.37% 39.99% # number of times we switched to this ipl 2324system.cpu1.kern.ipl_count::31 18905 60.01% 100.00% # number of times we switched to this ipl 2325system.cpu1.kern.ipl_count::total 31502 # number of times we switched to this ipl 2326system.cpu1.kern.ipl_good::0 10515 45.81% 45.81% # number of times we switched to this ipl from a different ipl 2327system.cpu1.kern.ipl_good::22 1926 8.39% 54.19% # number of times we switched to this ipl from a different ipl 2328system.cpu1.kern.ipl_good::30 116 0.51% 54.70% # number of times we switched to this ipl from a different ipl 2329system.cpu1.kern.ipl_good::31 10399 45.30% 100.00% # number of times we switched to this ipl from a different ipl 2330system.cpu1.kern.ipl_good::total 22956 # number of times we switched to this ipl from a different ipl 2331system.cpu1.kern.ipl_ticks::0 1877342030500 98.36% 98.36% # number of cycles we spent at this ipl 2332system.cpu1.kern.ipl_ticks::22 564972500 0.03% 98.39% # number of cycles we spent at this ipl 2333system.cpu1.kern.ipl_ticks::30 56160500 0.00% 98.39% # number of cycles we spent at this ipl 2334system.cpu1.kern.ipl_ticks::31 30688096500 1.61% 100.00% # number of cycles we spent at this ipl 2335system.cpu1.kern.ipl_ticks::total 1908651260000 # number of cycles we spent at this ipl 2336system.cpu1.kern.ipl_used::0 0.996210 # fraction of swpipl calls that actually changed the ipl 2337system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 2338system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 2339system.cpu1.kern.ipl_used::31 0.550066 # fraction of swpipl calls that actually changed the ipl 2340system.cpu1.kern.ipl_used::total 0.728716 # fraction of swpipl calls that actually changed the ipl 2341system.cpu1.kern.syscall::3 12 10.91% 10.91% # number of syscalls executed 2342system.cpu1.kern.syscall::6 10 9.09% 20.00% # number of syscalls executed 2343system.cpu1.kern.syscall::15 1 0.91% 20.91% # number of syscalls executed 2344system.cpu1.kern.syscall::17 7 6.36% 27.27% # number of syscalls executed 2345system.cpu1.kern.syscall::23 3 2.73% 30.00% # number of syscalls executed 2346system.cpu1.kern.syscall::24 3 2.73% 32.73% # number of syscalls executed 2347system.cpu1.kern.syscall::33 5 4.55% 37.27% # number of syscalls executed 2348system.cpu1.kern.syscall::45 21 19.09% 56.36% # number of syscalls executed 2349system.cpu1.kern.syscall::47 3 2.73% 59.09% # number of syscalls executed 2350system.cpu1.kern.syscall::59 1 0.91% 60.00% # number of syscalls executed 2351system.cpu1.kern.syscall::71 31 28.18% 88.18% # number of syscalls executed 2352system.cpu1.kern.syscall::74 10 9.09% 97.27% # number of syscalls executed 2353system.cpu1.kern.syscall::132 3 2.73% 100.00% # number of syscalls executed 2354system.cpu1.kern.syscall::total 110 # number of syscalls executed 2355system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2356system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed 2357system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 2358system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 2359system.cpu1.kern.callpal::swpctx 440 1.35% 1.42% # number of callpals executed 2360system.cpu1.kern.callpal::tbi 3 0.01% 1.43% # number of callpals executed 2361system.cpu1.kern.callpal::wrent 7 0.02% 1.45% # number of callpals executed 2362system.cpu1.kern.callpal::swpipl 26890 82.68% 84.13% # number of callpals executed 2363system.cpu1.kern.callpal::rdps 2393 7.36% 91.49% # number of callpals executed 2364system.cpu1.kern.callpal::wrkgp 1 0.00% 91.50% # number of callpals executed 2365system.cpu1.kern.callpal::wrusp 5 0.02% 91.51% # number of callpals executed 2366system.cpu1.kern.callpal::whami 3 0.01% 91.52% # number of callpals executed 2367system.cpu1.kern.callpal::rti 2569 7.90% 99.42% # number of callpals executed 2368system.cpu1.kern.callpal::callsys 144 0.44% 99.86% # number of callpals executed 2369system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed 2370system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 2371system.cpu1.kern.callpal::total 32523 # number of callpals executed 2372system.cpu1.kern.mode_switch::kernel 900 # number of protection mode switches 2373system.cpu1.kern.mode_switch::user 488 # number of protection mode switches 2374system.cpu1.kern.mode_switch::idle 2082 # number of protection mode switches 2375system.cpu1.kern.mode_good::kernel 529 2376system.cpu1.kern.mode_good::user 488 2377system.cpu1.kern.mode_good::idle 41 2378system.cpu1.kern.mode_switch_good::kernel 0.587778 # fraction of useful protection mode switches 2379system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2380system.cpu1.kern.mode_switch_good::idle 0.019693 # fraction of useful protection mode switches 2381system.cpu1.kern.mode_switch_good::total 0.304899 # fraction of useful protection mode switches 2382system.cpu1.kern.mode_ticks::kernel 2122812500 0.11% 0.11% # number of ticks spent at the given mode 2383system.cpu1.kern.mode_ticks::user 785064000 0.04% 0.15% # number of ticks spent at the given mode 2384system.cpu1.kern.mode_ticks::idle 1905743375500 99.85% 100.00% # number of ticks spent at the given mode 2385system.cpu1.kern.swap_context 441 # number of times the context was actually changed 2386 2387---------- End Simulation Statistics ----------