Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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stats.txt (11441:0edcf757b6a2)	stats.txt (11456:c0fb4435b80f)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.929078 # Number of seconds simulated 4sim_ticks 1929077876500 # Number of ticks simulated 5final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.929078 # Number of seconds simulated 4sim_ticks 1929077876500 # Number of ticks simulated 5final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 158135 # Simulator instruction rate (inst/s) 8host_op_rate 158134 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5371969736 # Simulator tick rate (ticks/s)	7host_inst_rate 169237 # Simulator instruction rate (inst/s) 8host_op_rate 169237 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5749129790 # Simulator tick rate (ticks/s)
10host_mem_usage 339544 # Number of bytes of host memory used	10host_mem_usage 339544 # Number of bytes of host memory used
11host_seconds 359.10 # Real time elapsed on the host	11host_seconds 335.54 # Real time elapsed on the host
12sim_insts 56786201 # Number of instructions simulated 13sim_ops 56786201 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 410442 # Number of read requests accepted 54system.physmem.writeReqs 122992 # Number of write requests accepted 55system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 26358 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25853 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25982 # Per bank write bursts 68system.physmem.perBankRdBursts::3 25455 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25391 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25779 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25718 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25362 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25502 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25880 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25847 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25125 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25573 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25368 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25415 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25720 # Per bank write bursts 81system.physmem.perBankWrBursts::0 8608 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7821 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8027 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7496 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7316 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7320 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7241 # Per bank write bursts 88system.physmem.perBankWrBursts::7 6937 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7156 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7588 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7741 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7304 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7945 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8097 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8174 # Per bank write bursts 96system.physmem.perBankWrBursts::15 8189 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 99system.physmem.totGap 1929076824500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 410442 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 122992 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads 265system.physmem.totQLat 4416821750 # Total ticks spent queuing 266system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.14 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing 281system.physmem.readRowHits 369361 # Number of row buffer hits during reads 282system.physmem.writeRowHits 98593 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes 285system.physmem.avgGap 3616336.46 # Average gap between requests 286system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) 294system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) 295system.physmem_0.averagePower 670.576874 # Core power per rank (mW) 296system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states 297system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states 298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states 300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) 302system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) 303system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) 304system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) 305system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) 306system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) 307system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) 309system.physmem_1.averagePower 670.573972 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states 311system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.cpu0.branchPred.lookups 17100345 # Number of BP lookups 316system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted 317system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect 318system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups 319system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits 320system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 321system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage 322system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. 323system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. 324system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. 325system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. 326system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. 327system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. 328system.cpu_clk_domain.clock 500 # Clock period in ticks 329system.cpu0.dtb.fetch_hits 0 # ITB hits 330system.cpu0.dtb.fetch_misses 0 # ITB misses 331system.cpu0.dtb.fetch_acv 0 # ITB acv 332system.cpu0.dtb.fetch_accesses 0 # ITB accesses 333system.cpu0.dtb.read_hits 9634816 # DTB read hits 334system.cpu0.dtb.read_misses 36704 # DTB read misses 335system.cpu0.dtb.read_acv 586 # DTB read access violations 336system.cpu0.dtb.read_accesses 618265 # DTB read accesses 337system.cpu0.dtb.write_hits 5807101 # DTB write hits 338system.cpu0.dtb.write_misses 8981 # DTB write misses 339system.cpu0.dtb.write_acv 421 # DTB write access violations 340system.cpu0.dtb.write_accesses 195454 # DTB write accesses 341system.cpu0.dtb.data_hits 15441917 # DTB hits 342system.cpu0.dtb.data_misses 45685 # DTB misses 343system.cpu0.dtb.data_acv 1007 # DTB access violations 344system.cpu0.dtb.data_accesses 813719 # DTB accesses 345system.cpu0.itb.fetch_hits 1375653 # ITB hits 346system.cpu0.itb.fetch_misses 7396 # ITB misses 347system.cpu0.itb.fetch_acv 601 # ITB acv 348system.cpu0.itb.fetch_accesses 1383049 # ITB accesses 349system.cpu0.itb.read_hits 0 # DTB read hits 350system.cpu0.itb.read_misses 0 # DTB read misses 351system.cpu0.itb.read_acv 0 # DTB read access violations 352system.cpu0.itb.read_accesses 0 # DTB read accesses 353system.cpu0.itb.write_hits 0 # DTB write hits 354system.cpu0.itb.write_misses 0 # DTB write misses 355system.cpu0.itb.write_acv 0 # DTB write access violations 356system.cpu0.itb.write_accesses 0 # DTB write accesses 357system.cpu0.itb.data_hits 0 # DTB hits 358system.cpu0.itb.data_misses 0 # DTB misses 359system.cpu0.itb.data_acv 0 # DTB access violations 360system.cpu0.itb.data_accesses 0 # DTB accesses 361system.cpu0.numCycles 146500468 # number of cpu cycles simulated 362system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 364system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss 365system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed 366system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered 367system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken 368system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked 369system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing 370system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb 371system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 372system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps 373system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions 374system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR 375system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched 376system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed 377system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) 378system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) 379system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) 380system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 381system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) 382system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) 383system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) 384system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) 385system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) 386system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) 387system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) 388system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) 389system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) 390system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 391system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 392system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 393system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) 394system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle 395system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle 396system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle 397system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked 398system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running 399system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking 400system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing 401system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch 402system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction 403system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode 404system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode 405system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing 406system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle 407system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking 408system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst 409system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running 410system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking 411system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename 412system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full 413system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full 414system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full 415system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full 416system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed 417system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made 418system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups 419system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups 420system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed 421system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing 422system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed 423system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed 424system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer 425system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. 426system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. 427system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. 428system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. 429system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) 430system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ 431system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued 432system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued 433system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph 435system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed 436system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle 437system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle 438system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle 439system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 440system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle 441system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle 442system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle 443system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle 444system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle 445system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle 446system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle 447system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle 448system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle 449system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 451system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 452system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle 453system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 454system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available 455system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available 456system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available 457system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available 458system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available 459system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available 460system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available 461system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available 462system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available 463system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available 464system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available 465system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available 466system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available 467system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available 468system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available 469system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available 470system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available 471system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available 472system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available 473system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available 474system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available 475system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available 476system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available 477system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available 478system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available 479system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available 480system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available 481system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available 482system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available 483system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available 484system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available 485system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 487system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued 488system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued 489system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued 490system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued 491system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued 492system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued 493system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued 494system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued 495system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued 496system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued 497system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued 498system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued 499system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued 500system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued 501system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued 502system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued 503system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued 504system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued 505system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued 506system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued 507system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued 508system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued 509system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued 510system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued 511system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued 512system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued 513system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued 514system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued 515system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued 516system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued 517system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued 518system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued 519system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued 520system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 521system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued 522system.cpu0.iq.rate 0.365631 # Inst issue rate 523system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested 524system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) 525system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads 526system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes 527system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses 528system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads 529system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes 530system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses 531system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses 532system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses 533system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores 534system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 535system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed 536system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed 537system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations 538system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed 539system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 540system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 541system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled 542system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked 543system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 544system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing 545system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking 546system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking 547system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ 548system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch 549system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions 550system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions 551system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions 552system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall 553system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall 554system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations 555system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly 556system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly 557system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute 558system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions 559system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed 560system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute 561system.cpu0.iew.exec_swp 0 # number of swp insts executed 562system.cpu0.iew.exec_nop 3577054 # number of nop insts executed 563system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed 564system.cpu0.iew.exec_branches 8401878 # Number of branches executed 565system.cpu0.iew.exec_stores 5833203 # Number of stores executed 566system.cpu0.iew.exec_rate 0.360886 # Inst execution rate 567system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit 568system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back 569system.cpu0.iew.wb_producers 26703720 # num instructions producing a value 570system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value 571system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle 572system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back 573system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit 574system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards 575system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted 576system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle 577system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle 578system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle 579system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 580system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle 581system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle 582system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle 583system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle 584system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle 585system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle 586system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle 587system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle 588system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle 589system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 590system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 591system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 592system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle 593system.cpu0.commit.committedInsts 50389922 # Number of instructions committed 594system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed 595system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 596system.cpu0.commit.refs 13516410 # Number of memory references committed 597system.cpu0.commit.loads 8024417 # Number of loads committed 598system.cpu0.commit.membars 195679 # Number of memory barriers committed 599system.cpu0.commit.branches 7630866 # Number of branches committed 600system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. 601system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. 602system.cpu0.commit.function_calls 644656 # Number of function calls committed. 603system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction 604system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction 605system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction 606system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction 607system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction 608system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction 609system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction 610system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction 611system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction 612system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction 613system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction 614system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction 615system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction 616system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction 617system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction 618system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction 619system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction 620system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction 621system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction 622system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction 623system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction 624system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction 625system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction 626system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction 627system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction 628system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction 629system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction 630system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction 631system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction 632system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction 633system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction 634system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction 635system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction 636system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 637system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction 638system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached 639system.cpu0.rob.rob_reads 197034230 # The number of ROB reads 640system.cpu0.rob.rob_writes 122856265 # The number of ROB writes 641system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself 642system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling 643system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 644system.cpu0.committedInsts 47480420 # Number of Instructions Simulated 645system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated 646system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction 647system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads 648system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle 649system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads 650system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads 651system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes 652system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads 653system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes 654system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads 655system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes 656system.cpu0.dcache.tags.replacements 1263704 # number of replacements 657system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use 658system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. 659system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. 660system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. 661system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 662system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor 663system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy 664system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id 666system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id 668system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id 669system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses 670system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses 671system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits 672system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits 673system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits 674system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits 675system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits 676system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits 677system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits 678system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits 679system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits 680system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits 681system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits 682system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits 683system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses 684system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses 685system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses 686system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses 687system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses 688system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses 689system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses 690system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses 691system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses 692system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses 693system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses 694system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses 695system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles 696system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles 697system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles 698system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles 699system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles 700system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles 701system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles 702system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles 703system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles 704system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles 705system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles 706system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles 707system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) 708system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) 709system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) 710system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) 711system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) 712system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) 713system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) 714system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) 715system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses 716system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses 717system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses 718system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses 719system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses 720system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses 721system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses 722system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses 723system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses 724system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses 725system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses 726system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses 727system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses 728system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses 729system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses 730system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses 731system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency 732system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency 733system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency 734system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency 735system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency 736system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency 737system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency 738system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency 739system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency 740system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency 741system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency 742system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency 743system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked 744system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked 745system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked 746system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked 747system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked 748system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked	12sim_insts 56786201 # Number of instructions simulated 13sim_ops 56786201 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 856320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24603328 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 123072 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 684608 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26268288 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 856320 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 123072 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 979392 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7871488 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7871488 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13380 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 384427 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 1923 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 10697 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 410442 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 122992 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 122992 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 443901 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12753932 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 63798 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 354889 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13617018 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 443901 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 63798 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 507700 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 4080441 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 4080441 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 4080441 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 443901 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12753932 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 63798 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 354889 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17697459 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 410442 # Number of read requests accepted 54system.physmem.writeReqs 122992 # Number of write requests accepted 55system.physmem.readBursts 410442 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 122992 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7869440 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26268288 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7871488 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 26358 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25853 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25982 # Per bank write bursts 68system.physmem.perBankRdBursts::3 25455 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25391 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25779 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25718 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25362 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25502 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25880 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25847 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25125 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25573 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25368 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25415 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25720 # Per bank write bursts 81system.physmem.perBankWrBursts::0 8608 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7821 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8027 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7496 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7316 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7320 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7241 # Per bank write bursts 88system.physmem.perBankWrBursts::7 6937 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7156 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7588 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7741 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7304 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7945 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8097 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8174 # Per bank write bursts 96system.physmem.perBankWrBursts::15 8189 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 99system.physmem.totGap 1929076824500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 410442 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 122992 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 318267 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 37921 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 29360 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 24678 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 83 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1676 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 5222 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4727 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6475 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6373 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 6303 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6763 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7317 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 6854 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8917 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 9221 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7788 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 8406 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 8757 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7842 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6881 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 287 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 217 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 149 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 127 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 166 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 149 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 65334 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 522.399241 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 318.882184 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 410.899985 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 14976 22.92% 22.92% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11360 17.39% 40.31% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5432 8.31% 48.62% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2850 4.36% 52.99% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2530 3.87% 56.86% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1671 2.56% 59.42% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 3857 5.90% 65.32% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1188 1.82% 67.14% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 21470 32.86% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 65334 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5522 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 74.304962 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2840.771031 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5519 99.95% 99.95% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5522 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5522 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.267294 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.111227 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 20.252131 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4917 89.04% 89.04% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 44 0.80% 89.84% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 22 0.40% 90.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 38 0.69% 90.93% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 207 3.75% 94.68% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 6 0.11% 94.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 12 0.22% 95.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 27 0.49% 95.49% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 186 3.37% 98.86% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 6 0.11% 98.97% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 8 0.14% 99.11% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 4 0.07% 99.19% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 2 0.04% 99.22% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::128-135 8 0.14% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::136-143 6 0.11% 99.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::152-159 2 0.04% 99.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::160-167 4 0.07% 99.60% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-175 5 0.09% 99.69% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::184-191 3 0.05% 99.76% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 3 0.05% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 3 0.05% 99.89% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-231 1 0.02% 99.91% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::240-247 1 0.02% 99.93% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::256-263 3 0.05% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5522 # Writes before turning the bus around for reads 265system.physmem.totQLat 4416821750 # Total ticks spent queuing 266system.physmem.totMemAccLat 12110471750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10764.12 # Average queueing delay per DRAM burst 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 270system.physmem.avgMemAccLat 29514.12 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.61 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 4.08 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.62 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 4.08 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.14 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing 280system.physmem.avgWrQLen 26.77 # Average write queue length when enqueuing 281system.physmem.readRowHits 369361 # Number of row buffer hits during reads 282system.physmem.writeRowHits 98593 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 80.16 # Row buffer hit rate for writes 285system.physmem.avgGap 3616336.46 # Average gap between requests 286system.physmem.pageHitRate 87.74 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 246047760 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 134252250 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 1606004400 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 393763680 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 63271865610 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 1101943260750 # Energy for precharge background per rank (pJ) 294system.physmem_0.totalEnergy 1293592968690 # Total energy per rank (pJ) 295system.physmem_0.averagePower 670.576874 # Core power per rank (mW) 296system.physmem_0.memoryStateTime::IDLE 1832974418500 # Time in different power states 297system.physmem_0.memoryStateTime::REF 64416040000 # Time in different power states 298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_0.memoryStateTime::ACT 31684384000 # Time in different power states 300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.physmem_1.actEnergy 247877280 # Energy for activate commands per rank (pJ) 302system.physmem_1.preEnergy 135250500 # Energy for precharge commands per rank (pJ) 303system.physmem_1.readEnergy 1594554000 # Energy for read commands per rank (pJ) 304system.physmem_1.writeEnergy 403017120 # Energy for write commands per rank (pJ) 305system.physmem_1.refreshEnergy 125997774240 # Energy for refresh commands per rank (pJ) 306system.physmem_1.actBackEnergy 63221156415 # Energy for active background per rank (pJ) 307system.physmem_1.preBackEnergy 1101987750750 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1293587380305 # Total energy per rank (pJ) 309system.physmem_1.averagePower 670.573972 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 1833051648500 # Time in different power states 311system.physmem_1.memoryStateTime::REF 64416040000 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 31607167750 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.cpu0.branchPred.lookups 17100345 # Number of BP lookups 316system.cpu0.branchPred.condPredicted 14625316 # Number of conditional branches predicted 317system.cpu0.branchPred.condIncorrect 474432 # Number of conditional branches incorrect 318system.cpu0.branchPred.BTBLookups 10759421 # Number of BTB lookups 319system.cpu0.branchPred.BTBHits 4832502 # Number of BTB hits 320system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 321system.cpu0.branchPred.BTBHitPct 44.914145 # BTB Hit Percentage 322system.cpu0.branchPred.usedRAS 945329 # Number of times the RAS was used to get a target. 323system.cpu0.branchPred.RASInCorrect 34555 # Number of incorrect RAS predictions. 324system.cpu0.branchPred.indirectLookups 5020643 # Number of indirect predictor lookups. 325system.cpu0.branchPred.indirectHits 507910 # Number of indirect target hits. 326system.cpu0.branchPred.indirectMisses 4512733 # Number of indirect misses. 327system.cpu0.branchPredindirectMispredicted 209375 # Number of mispredicted indirect branches. 328system.cpu_clk_domain.clock 500 # Clock period in ticks 329system.cpu0.dtb.fetch_hits 0 # ITB hits 330system.cpu0.dtb.fetch_misses 0 # ITB misses 331system.cpu0.dtb.fetch_acv 0 # ITB acv 332system.cpu0.dtb.fetch_accesses 0 # ITB accesses 333system.cpu0.dtb.read_hits 9634816 # DTB read hits 334system.cpu0.dtb.read_misses 36704 # DTB read misses 335system.cpu0.dtb.read_acv 586 # DTB read access violations 336system.cpu0.dtb.read_accesses 618265 # DTB read accesses 337system.cpu0.dtb.write_hits 5807101 # DTB write hits 338system.cpu0.dtb.write_misses 8981 # DTB write misses 339system.cpu0.dtb.write_acv 421 # DTB write access violations 340system.cpu0.dtb.write_accesses 195454 # DTB write accesses 341system.cpu0.dtb.data_hits 15441917 # DTB hits 342system.cpu0.dtb.data_misses 45685 # DTB misses 343system.cpu0.dtb.data_acv 1007 # DTB access violations 344system.cpu0.dtb.data_accesses 813719 # DTB accesses 345system.cpu0.itb.fetch_hits 1375653 # ITB hits 346system.cpu0.itb.fetch_misses 7396 # ITB misses 347system.cpu0.itb.fetch_acv 601 # ITB acv 348system.cpu0.itb.fetch_accesses 1383049 # ITB accesses 349system.cpu0.itb.read_hits 0 # DTB read hits 350system.cpu0.itb.read_misses 0 # DTB read misses 351system.cpu0.itb.read_acv 0 # DTB read access violations 352system.cpu0.itb.read_accesses 0 # DTB read accesses 353system.cpu0.itb.write_hits 0 # DTB write hits 354system.cpu0.itb.write_misses 0 # DTB write misses 355system.cpu0.itb.write_acv 0 # DTB write access violations 356system.cpu0.itb.write_accesses 0 # DTB write accesses 357system.cpu0.itb.data_hits 0 # DTB hits 358system.cpu0.itb.data_misses 0 # DTB misses 359system.cpu0.itb.data_acv 0 # DTB access violations 360system.cpu0.itb.data_accesses 0 # DTB accesses 361system.cpu0.numCycles 146500468 # number of cpu cycles simulated 362system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 364system.cpu0.fetch.icacheStallCycles 26225748 # Number of cycles fetch is stalled on an Icache miss 365system.cpu0.fetch.Insts 74880065 # Number of instructions fetch has processed 366system.cpu0.fetch.Branches 17100345 # Number of branches that fetch encountered 367system.cpu0.fetch.predictedBranches 6285741 # Number of branches that fetch has predicted taken 368system.cpu0.fetch.Cycles 112740313 # Number of cycles fetch has run and was not squashing or blocked 369system.cpu0.fetch.SquashCycles 1369370 # Number of cycles fetch has spent squashing 370system.cpu0.fetch.TlbCycles 398 # Number of cycles fetch has spent waiting for tlb 371system.cpu0.fetch.MiscStallCycles 30412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 372system.cpu0.fetch.PendingTrapStallCycles 147220 # Number of stall cycles due to pending traps 373system.cpu0.fetch.PendingQuiesceStallCycles 425638 # Number of stall cycles due to pending quiesce instructions 374system.cpu0.fetch.IcacheWaitRetryStallCycles 504 # Number of stall cycles due to full MSHR 375system.cpu0.fetch.CacheLines 8642043 # Number of cache lines fetched 376system.cpu0.fetch.IcacheSquashes 322305 # Number of outstanding Icache misses that were squashed 377system.cpu0.fetch.rateDist::samples 140254918 # Number of instructions fetched each cycle (Total) 378system.cpu0.fetch.rateDist::mean 0.533885 # Number of instructions fetched each cycle (Total) 379system.cpu0.fetch.rateDist::stdev 1.795707 # Number of instructions fetched each cycle (Total) 380system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 381system.cpu0.fetch.rateDist::0 126345960 90.08% 90.08% # Number of instructions fetched each cycle (Total) 382system.cpu0.fetch.rateDist::1 903115 0.64% 90.73% # Number of instructions fetched each cycle (Total) 383system.cpu0.fetch.rateDist::2 1906918 1.36% 92.09% # Number of instructions fetched each cycle (Total) 384system.cpu0.fetch.rateDist::3 803345 0.57% 92.66% # Number of instructions fetched each cycle (Total) 385system.cpu0.fetch.rateDist::4 2649453 1.89% 94.55% # Number of instructions fetched each cycle (Total) 386system.cpu0.fetch.rateDist::5 589849 0.42% 94.97% # Number of instructions fetched each cycle (Total) 387system.cpu0.fetch.rateDist::6 700559 0.50% 95.47% # Number of instructions fetched each cycle (Total) 388system.cpu0.fetch.rateDist::7 843084 0.60% 96.07% # Number of instructions fetched each cycle (Total) 389system.cpu0.fetch.rateDist::8 5512635 3.93% 100.00% # Number of instructions fetched each cycle (Total) 390system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 391system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 392system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 393system.cpu0.fetch.rateDist::total 140254918 # Number of instructions fetched each cycle (Total) 394system.cpu0.fetch.branchRate 0.116726 # Number of branch fetches per cycle 395system.cpu0.fetch.rate 0.511125 # Number of inst fetches per cycle 396system.cpu0.decode.IdleCycles 20974212 # Number of cycles decode is idle 397system.cpu0.decode.BlockedCycles 107876486 # Number of cycles decode is blocked 398system.cpu0.decode.RunCycles 8907132 # Number of cycles decode is running 399system.cpu0.decode.UnblockCycles 1841497 # Number of cycles decode is unblocking 400system.cpu0.decode.SquashCycles 655590 # Number of cycles decode is squashing 401system.cpu0.decode.BranchResolved 626155 # Number of times decode resolved a branch 402system.cpu0.decode.BranchMispred 29675 # Number of times decode detected a branch misprediction 403system.cpu0.decode.DecodedInsts 64967024 # Number of instructions handled by decode 404system.cpu0.decode.SquashedInsts 87739 # Number of squashed instructions handled by decode 405system.cpu0.rename.SquashCycles 655590 # Number of cycles rename is squashing 406system.cpu0.rename.IdleCycles 21855511 # Number of cycles rename is idle 407system.cpu0.rename.BlockCycles 78567360 # Number of cycles rename is blocking 408system.cpu0.rename.serializeStallCycles 18275925 # count of cycles rename stalled for serializing inst 409system.cpu0.rename.RunCycles 9798485 # Number of cycles rename is running 410system.cpu0.rename.UnblockCycles 11102045 # Number of cycles rename is unblocking 411system.cpu0.rename.RenamedInsts 62456562 # Number of instructions processed by rename 412system.cpu0.rename.ROBFullEvents 201631 # Number of times rename has blocked due to ROB full 413system.cpu0.rename.IQFullEvents 2042440 # Number of times rename has blocked due to IQ full 414system.cpu0.rename.LQFullEvents 306402 # Number of times rename has blocked due to LQ full 415system.cpu0.rename.SQFullEvents 7083961 # Number of times rename has blocked due to SQ full 416system.cpu0.rename.RenamedOperands 42144620 # Number of destination operands rename has renamed 417system.cpu0.rename.RenameLookups 75447660 # Number of register rename lookups that rename has made 418system.cpu0.rename.int_rename_lookups 75312247 # Number of integer rename lookups 419system.cpu0.rename.fp_rename_lookups 126226 # Number of floating rename lookups 420system.cpu0.rename.CommittedMaps 34366321 # Number of HB maps that are committed 421system.cpu0.rename.UndoneMaps 7778299 # Number of HB maps that are undone due to squashing 422system.cpu0.rename.serializingInsts 1457881 # count of serializing insts renamed 423system.cpu0.rename.tempSerializingInsts 236313 # count of temporary serializing insts renamed 424system.cpu0.rename.skidInsts 12541674 # count of insts added to the skid buffer 425system.cpu0.memDep0.insertedLoads 10026235 # Number of loads inserted to the mem dependence unit. 426system.cpu0.memDep0.insertedStores 6171298 # Number of stores inserted to the mem dependence unit. 427system.cpu0.memDep0.conflictingLoads 1512964 # Number of conflicting loads. 428system.cpu0.memDep0.conflictingStores 977849 # Number of conflicting stores. 429system.cpu0.iq.iqInstsAdded 55240015 # Number of instructions added to the IQ (excludes non-spec) 430system.cpu0.iq.iqNonSpecInstsAdded 1897630 # Number of non-speculative instructions added to the IQ 431system.cpu0.iq.iqInstsIssued 53565100 # Number of instructions issued 432system.cpu0.iq.iqSquashedInstsIssued 74212 # Number of squashed instructions issued 433system.cpu0.iq.iqSquashedInstsExamined 9657224 # Number of squashed instructions iterated over during squash; mainly for profiling 434system.cpu0.iq.iqSquashedOperandsExamined 4199823 # Number of squashed operands that are examined and possibly removed from graph 435system.cpu0.iq.iqSquashedNonSpecRemoved 1322202 # Number of squashed non-spec instructions that were removed 436system.cpu0.iq.issued_per_cycle::samples 140254918 # Number of insts issued each cycle 437system.cpu0.iq.issued_per_cycle::mean 0.381912 # Number of insts issued each cycle 438system.cpu0.iq.issued_per_cycle::stdev 1.107336 # Number of insts issued each cycle 439system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 440system.cpu0.iq.issued_per_cycle::0 118450817 84.45% 84.45% # Number of insts issued each cycle 441system.cpu0.iq.issued_per_cycle::1 9324559 6.65% 91.10% # Number of insts issued each cycle 442system.cpu0.iq.issued_per_cycle::2 3896910 2.78% 93.88% # Number of insts issued each cycle 443system.cpu0.iq.issued_per_cycle::3 2805800 2.00% 95.88% # Number of insts issued each cycle 444system.cpu0.iq.issued_per_cycle::4 2901850 2.07% 97.95% # Number of insts issued each cycle 445system.cpu0.iq.issued_per_cycle::5 1433856 1.02% 98.97% # Number of insts issued each cycle 446system.cpu0.iq.issued_per_cycle::6 954902 0.68% 99.65% # Number of insts issued each cycle 447system.cpu0.iq.issued_per_cycle::7 366563 0.26% 99.91% # Number of insts issued each cycle 448system.cpu0.iq.issued_per_cycle::8 119661 0.09% 100.00% # Number of insts issued each cycle 449system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 451system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 452system.cpu0.iq.issued_per_cycle::total 140254918 # Number of insts issued each cycle 453system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 454system.cpu0.iq.fu_full::IntAlu 172960 16.73% 16.73% # attempts to use FU when none available 455system.cpu0.iq.fu_full::IntMult 0 0.00% 16.73% # attempts to use FU when none available 456system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.73% # attempts to use FU when none available 457system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.73% # attempts to use FU when none available 458system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.73% # attempts to use FU when none available 459system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.73% # attempts to use FU when none available 460system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.73% # attempts to use FU when none available 461system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.73% # attempts to use FU when none available 462system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.73% # attempts to use FU when none available 463system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.73% # attempts to use FU when none available 464system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.73% # attempts to use FU when none available 465system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.73% # attempts to use FU when none available 466system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.73% # attempts to use FU when none available 467system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.73% # attempts to use FU when none available 468system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.73% # attempts to use FU when none available 469system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.73% # attempts to use FU when none available 470system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.73% # attempts to use FU when none available 471system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.73% # attempts to use FU when none available 472system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.73% # attempts to use FU when none available 473system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.73% # attempts to use FU when none available 474system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.73% # attempts to use FU when none available 475system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.73% # attempts to use FU when none available 476system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.73% # attempts to use FU when none available 477system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.73% # attempts to use FU when none available 478system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.73% # attempts to use FU when none available 479system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.73% # attempts to use FU when none available 480system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.73% # attempts to use FU when none available 481system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.73% # attempts to use FU when none available 482system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.73% # attempts to use FU when none available 483system.cpu0.iq.fu_full::MemRead 530801 51.33% 68.06% # attempts to use FU when none available 484system.cpu0.iq.fu_full::MemWrite 330287 31.94% 100.00% # attempts to use FU when none available 485system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 486system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 487system.cpu0.iq.FU_type_0::No_OpClass 3306 0.01% 0.01% # Type of FU issued 488system.cpu0.iq.FU_type_0::IntAlu 36704403 68.52% 68.53% # Type of FU issued 489system.cpu0.iq.FU_type_0::IntMult 56318 0.11% 68.63% # Type of FU issued 490system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.63% # Type of FU issued 491system.cpu0.iq.FU_type_0::FloatAdd 27375 0.05% 68.69% # Type of FU issued 492system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued 493system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued 494system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued 495system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 68.69% # Type of FU issued 496system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued 497system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued 498system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued 499system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued 500system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued 501system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued 502system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued 503system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued 504system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued 505system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued 506system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued 507system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued 508system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued 509system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued 510system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued 511system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued 512system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued 513system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued 514system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued 515system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued 516system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued 517system.cpu0.iq.FU_type_0::MemRead 10076531 18.81% 87.50% # Type of FU issued 518system.cpu0.iq.FU_type_0::MemWrite 5896825 11.01% 98.51% # Type of FU issued 519system.cpu0.iq.FU_type_0::IprAccess 798690 1.49% 100.00% # Type of FU issued 520system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 521system.cpu0.iq.FU_type_0::total 53565100 # Type of FU issued 522system.cpu0.iq.rate 0.365631 # Inst issue rate 523system.cpu0.iq.fu_busy_cnt 1034048 # FU busy when requested 524system.cpu0.iq.fu_busy_rate 0.019305 # FU busy rate (busy events/executed inst) 525system.cpu0.iq.int_inst_queue_reads 247915569 # Number of integer instruction queue reads 526system.cpu0.iq.int_inst_queue_writes 66533789 # Number of integer instruction queue writes 527system.cpu0.iq.int_inst_queue_wakeup_accesses 51792941 # Number of integer instruction queue wakeup accesses 528system.cpu0.iq.fp_inst_queue_reads 577809 # Number of floating instruction queue reads 529system.cpu0.iq.fp_inst_queue_writes 279350 # Number of floating instruction queue writes 530system.cpu0.iq.fp_inst_queue_wakeup_accesses 262536 # Number of floating instruction queue wakeup accesses 531system.cpu0.iq.int_alu_accesses 54284218 # Number of integer alu accesses 532system.cpu0.iq.fp_alu_accesses 311624 # Number of floating point alu accesses 533system.cpu0.iew.lsq.thread0.forwLoads 608466 # Number of loads that had data forwarded from stores 534system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 535system.cpu0.iew.lsq.thread0.squashedLoads 2001818 # Number of loads squashed 536system.cpu0.iew.lsq.thread0.ignoredResponses 4069 # Number of memory responses ignored because the instruction is squashed 537system.cpu0.iew.lsq.thread0.memOrderViolation 18629 # Number of memory ordering violations 538system.cpu0.iew.lsq.thread0.squashedStores 679305 # Number of stores squashed 539system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 540system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 541system.cpu0.iew.lsq.thread0.rescheduledLoads 18387 # Number of loads that were rescheduled 542system.cpu0.iew.lsq.thread0.cacheBlocked 376944 # Number of times an access to memory failed due to the cache being blocked 543system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 544system.cpu0.iew.iewSquashCycles 655590 # Number of cycles IEW is squashing 545system.cpu0.iew.iewBlockCycles 75078561 # Number of cycles IEW is blocking 546system.cpu0.iew.iewUnblockCycles 955285 # Number of cycles IEW is unblocking 547system.cpu0.iew.iewDispatchedInsts 60714699 # Number of instructions dispatched to IQ 548system.cpu0.iew.iewDispSquashedInsts 160012 # Number of squashed instructions skipped by dispatch 549system.cpu0.iew.iewDispLoadInsts 10026235 # Number of dispatched load instructions 550system.cpu0.iew.iewDispStoreInsts 6171298 # Number of dispatched store instructions 551system.cpu0.iew.iewDispNonSpecInsts 1682472 # Number of dispatched non-speculative instructions 552system.cpu0.iew.iewIQFullEvents 42874 # Number of times the IQ has become full, causing a stall 553system.cpu0.iew.iewLSQFullEvents 711273 # Number of times the LSQ has become full, causing a stall 554system.cpu0.iew.memOrderViolationEvents 18629 # Number of memory order violations 555system.cpu0.iew.predictedTakenIncorrect 185912 # Number of branches that were predicted taken incorrectly 556system.cpu0.iew.predictedNotTakenIncorrect 515422 # Number of branches that were predicted not taken incorrectly 557system.cpu0.iew.branchMispredicts 701334 # Number of branch mispredicts detected at execute 558system.cpu0.iew.iewExecutedInsts 52870028 # Number of executed instructions 559system.cpu0.iew.iewExecLoadInsts 9698038 # Number of load instructions executed 560system.cpu0.iew.iewExecSquashedInsts 695072 # Number of squashed instructions skipped in execute 561system.cpu0.iew.exec_swp 0 # number of swp insts executed 562system.cpu0.iew.exec_nop 3577054 # number of nop insts executed 563system.cpu0.iew.exec_refs 15531241 # number of memory reference insts executed 564system.cpu0.iew.exec_branches 8401878 # Number of branches executed 565system.cpu0.iew.exec_stores 5833203 # Number of stores executed 566system.cpu0.iew.exec_rate 0.360886 # Inst execution rate 567system.cpu0.iew.wb_sent 52244753 # cumulative count of insts sent to commit 568system.cpu0.iew.wb_count 52055477 # cumulative count of insts written-back 569system.cpu0.iew.wb_producers 26703720 # num instructions producing a value 570system.cpu0.iew.wb_consumers 36905470 # num instructions consuming a value 571system.cpu0.iew.wb_rate 0.355326 # insts written-back per cycle 572system.cpu0.iew.wb_fanout 0.723571 # average fanout of values written-back 573system.cpu0.commit.commitSquashedInsts 10154720 # The number of squashed insts skipped by commit 574system.cpu0.commit.commitNonSpecStalls 575428 # The number of times commit has been forced to stall to communicate backwards 575system.cpu0.commit.branchMispredicts 626255 # The number of times a branch was mispredicted 576system.cpu0.commit.committed_per_cycle::samples 138489248 # Number of insts commited each cycle 577system.cpu0.commit.committed_per_cycle::mean 0.363854 # Number of insts commited each cycle 578system.cpu0.commit.committed_per_cycle::stdev 1.249176 # Number of insts commited each cycle 579system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 580system.cpu0.commit.committed_per_cycle::0 120648787 87.12% 87.12% # Number of insts commited each cycle 581system.cpu0.commit.committed_per_cycle::1 7115506 5.14% 92.26% # Number of insts commited each cycle 582system.cpu0.commit.committed_per_cycle::2 3823437 2.76% 95.02% # Number of insts commited each cycle 583system.cpu0.commit.committed_per_cycle::3 2034446 1.47% 96.49% # Number of insts commited each cycle 584system.cpu0.commit.committed_per_cycle::4 1589267 1.15% 97.63% # Number of insts commited each cycle 585system.cpu0.commit.committed_per_cycle::5 580000 0.42% 98.05% # Number of insts commited each cycle 586system.cpu0.commit.committed_per_cycle::6 430694 0.31% 98.36% # Number of insts commited each cycle 587system.cpu0.commit.committed_per_cycle::7 453916 0.33% 98.69% # Number of insts commited each cycle 588system.cpu0.commit.committed_per_cycle::8 1813195 1.31% 100.00% # Number of insts commited each cycle 589system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 590system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 591system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 592system.cpu0.commit.committed_per_cycle::total 138489248 # Number of insts commited each cycle 593system.cpu0.commit.committedInsts 50389922 # Number of instructions committed 594system.cpu0.commit.committedOps 50389922 # Number of ops (including micro ops) committed 595system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 596system.cpu0.commit.refs 13516410 # Number of memory references committed 597system.cpu0.commit.loads 8024417 # Number of loads committed 598system.cpu0.commit.membars 195679 # Number of memory barriers committed 599system.cpu0.commit.branches 7630866 # Number of branches committed 600system.cpu0.commit.fp_insts 253714 # Number of committed floating point instructions. 601system.cpu0.commit.int_insts 46654336 # Number of committed integer instructions. 602system.cpu0.commit.function_calls 644656 # Number of function calls committed. 603system.cpu0.commit.op_class_0::No_OpClass 2912807 5.78% 5.78% # Class of committed instruction 604system.cpu0.commit.op_class_0::IntAlu 32876835 65.24% 71.03% # Class of committed instruction 605system.cpu0.commit.op_class_0::IntMult 54961 0.11% 71.13% # Class of committed instruction 606system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.13% # Class of committed instruction 607system.cpu0.commit.op_class_0::FloatAdd 26901 0.05% 71.19% # Class of committed instruction 608system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.19% # Class of committed instruction 609system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.19% # Class of committed instruction 610system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.19% # Class of committed instruction 611system.cpu0.commit.op_class_0::FloatDiv 1652 0.00% 71.19% # Class of committed instruction 612system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.19% # Class of committed instruction 613system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.19% # Class of committed instruction 614system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.19% # Class of committed instruction 615system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.19% # Class of committed instruction 616system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.19% # Class of committed instruction 617system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.19% # Class of committed instruction 618system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.19% # Class of committed instruction 619system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.19% # Class of committed instruction 620system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.19% # Class of committed instruction 621system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.19% # Class of committed instruction 622system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.19% # Class of committed instruction 623system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.19% # Class of committed instruction 624system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.19% # Class of committed instruction 625system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.19% # Class of committed instruction 626system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.19% # Class of committed instruction 627system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.19% # Class of committed instruction 628system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.19% # Class of committed instruction 629system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.19% # Class of committed instruction 630system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.19% # Class of committed instruction 631system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.19% # Class of committed instruction 632system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.19% # Class of committed instruction 633system.cpu0.commit.op_class_0::MemRead 8220096 16.31% 87.50% # Class of committed instruction 634system.cpu0.commit.op_class_0::MemWrite 5497981 10.91% 98.41% # Class of committed instruction 635system.cpu0.commit.op_class_0::IprAccess 798689 1.59% 100.00% # Class of committed instruction 636system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 637system.cpu0.commit.op_class_0::total 50389922 # Class of committed instruction 638system.cpu0.commit.bw_lim_events 1813195 # number cycles where commit BW limit reached 639system.cpu0.rob.rob_reads 197034230 # The number of ROB reads 640system.cpu0.rob.rob_writes 122856265 # The number of ROB writes 641system.cpu0.timesIdled 490676 # Number of times that the entire CPU went into an idle state and unscheduled itself 642system.cpu0.idleCycles 6245550 # Total number of cycles that the CPU has spent unscheduled due to idling 643system.cpu0.quiesceCycles 3710936476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 644system.cpu0.committedInsts 47480420 # Number of Instructions Simulated 645system.cpu0.committedOps 47480420 # Number of Ops (including micro ops) Simulated 646system.cpu0.cpi 3.085492 # CPI: Cycles Per Instruction 647system.cpu0.cpi_total 3.085492 # CPI: Total CPI of All Threads 648system.cpu0.ipc 0.324097 # IPC: Instructions Per Cycle 649system.cpu0.ipc_total 0.324097 # IPC: Total IPC of All Threads 650system.cpu0.int_regfile_reads 69229174 # number of integer regfile reads 651system.cpu0.int_regfile_writes 37925510 # number of integer regfile writes 652system.cpu0.fp_regfile_reads 125098 # number of floating regfile reads 653system.cpu0.fp_regfile_writes 133204 # number of floating regfile writes 654system.cpu0.misc_regfile_reads 1692059 # number of misc regfile reads 655system.cpu0.misc_regfile_writes 801866 # number of misc regfile writes 656system.cpu0.dcache.tags.replacements 1263704 # number of replacements 657system.cpu0.dcache.tags.tagsinuse 506.064166 # Cycle average of tags in use 658system.cpu0.dcache.tags.total_refs 10905904 # Total number of references to valid blocks. 659system.cpu0.dcache.tags.sampled_refs 1264137 # Sample count of references to valid blocks. 660system.cpu0.dcache.tags.avg_refs 8.627154 # Average number of references to valid blocks. 661system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. 662system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.064166 # Average occupied blocks per requestor 663system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988407 # Average percentage of cache occupancy 664system.cpu0.dcache.tags.occ_percent::total 0.988407 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_task_id_blocks::1024 433 # Occupied blocks per task id 666system.cpu0.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id 668system.cpu0.dcache.tags.occ_task_id_percent::1024 0.845703 # Percentage of cache occupancy per task id 669system.cpu0.dcache.tags.tag_accesses 58069444 # Number of tag accesses 670system.cpu0.dcache.tags.data_accesses 58069444 # Number of data accesses 671system.cpu0.dcache.ReadReq_hits::cpu0.data 6953524 # number of ReadReq hits 672system.cpu0.dcache.ReadReq_hits::total 6953524 # number of ReadReq hits 673system.cpu0.dcache.WriteReq_hits::cpu0.data 3586613 # number of WriteReq hits 674system.cpu0.dcache.WriteReq_hits::total 3586613 # number of WriteReq hits 675system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 178977 # number of LoadLockedReq hits 676system.cpu0.dcache.LoadLockedReq_hits::total 178977 # number of LoadLockedReq hits 677system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184325 # number of StoreCondReq hits 678system.cpu0.dcache.StoreCondReq_hits::total 184325 # number of StoreCondReq hits 679system.cpu0.dcache.demand_hits::cpu0.data 10540137 # number of demand (read+write) hits 680system.cpu0.dcache.demand_hits::total 10540137 # number of demand (read+write) hits 681system.cpu0.dcache.overall_hits::cpu0.data 10540137 # number of overall hits 682system.cpu0.dcache.overall_hits::total 10540137 # number of overall hits 683system.cpu0.dcache.ReadReq_misses::cpu0.data 1569058 # number of ReadReq misses 684system.cpu0.dcache.ReadReq_misses::total 1569058 # number of ReadReq misses 685system.cpu0.dcache.WriteReq_misses::cpu0.data 1703592 # number of WriteReq misses 686system.cpu0.dcache.WriteReq_misses::total 1703592 # number of WriteReq misses 687system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20226 # number of LoadLockedReq misses 688system.cpu0.dcache.LoadLockedReq_misses::total 20226 # number of LoadLockedReq misses 689system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2959 # number of StoreCondReq misses 690system.cpu0.dcache.StoreCondReq_misses::total 2959 # number of StoreCondReq misses 691system.cpu0.dcache.demand_misses::cpu0.data 3272650 # number of demand (read+write) misses 692system.cpu0.dcache.demand_misses::total 3272650 # number of demand (read+write) misses 693system.cpu0.dcache.overall_misses::cpu0.data 3272650 # number of overall misses 694system.cpu0.dcache.overall_misses::total 3272650 # number of overall misses 695system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54620758000 # number of ReadReq miss cycles 696system.cpu0.dcache.ReadReq_miss_latency::total 54620758000 # number of ReadReq miss cycles 697system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 110116261626 # number of WriteReq miss cycles 698system.cpu0.dcache.WriteReq_miss_latency::total 110116261626 # number of WriteReq miss cycles 699system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 348212000 # number of LoadLockedReq miss cycles 700system.cpu0.dcache.LoadLockedReq_miss_latency::total 348212000 # number of LoadLockedReq miss cycles 701system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46063500 # number of StoreCondReq miss cycles 702system.cpu0.dcache.StoreCondReq_miss_latency::total 46063500 # number of StoreCondReq miss cycles 703system.cpu0.dcache.demand_miss_latency::cpu0.data 164737019626 # number of demand (read+write) miss cycles 704system.cpu0.dcache.demand_miss_latency::total 164737019626 # number of demand (read+write) miss cycles 705system.cpu0.dcache.overall_miss_latency::cpu0.data 164737019626 # number of overall miss cycles 706system.cpu0.dcache.overall_miss_latency::total 164737019626 # number of overall miss cycles 707system.cpu0.dcache.ReadReq_accesses::cpu0.data 8522582 # number of ReadReq accesses(hits+misses) 708system.cpu0.dcache.ReadReq_accesses::total 8522582 # number of ReadReq accesses(hits+misses) 709system.cpu0.dcache.WriteReq_accesses::cpu0.data 5290205 # number of WriteReq accesses(hits+misses) 710system.cpu0.dcache.WriteReq_accesses::total 5290205 # number of WriteReq accesses(hits+misses) 711system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 199203 # number of LoadLockedReq accesses(hits+misses) 712system.cpu0.dcache.LoadLockedReq_accesses::total 199203 # number of LoadLockedReq accesses(hits+misses) 713system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187284 # number of StoreCondReq accesses(hits+misses) 714system.cpu0.dcache.StoreCondReq_accesses::total 187284 # number of StoreCondReq accesses(hits+misses) 715system.cpu0.dcache.demand_accesses::cpu0.data 13812787 # number of demand (read+write) accesses 716system.cpu0.dcache.demand_accesses::total 13812787 # number of demand (read+write) accesses 717system.cpu0.dcache.overall_accesses::cpu0.data 13812787 # number of overall (read+write) accesses 718system.cpu0.dcache.overall_accesses::total 13812787 # number of overall (read+write) accesses 719system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184106 # miss rate for ReadReq accesses 720system.cpu0.dcache.ReadReq_miss_rate::total 0.184106 # miss rate for ReadReq accesses 721system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322028 # miss rate for WriteReq accesses 722system.cpu0.dcache.WriteReq_miss_rate::total 0.322028 # miss rate for WriteReq accesses 723system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101535 # miss rate for LoadLockedReq accesses 724system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101535 # miss rate for LoadLockedReq accesses 725system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015800 # miss rate for StoreCondReq accesses 726system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015800 # miss rate for StoreCondReq accesses 727system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236929 # miss rate for demand accesses 728system.cpu0.dcache.demand_miss_rate::total 0.236929 # miss rate for demand accesses 729system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236929 # miss rate for overall accesses 730system.cpu0.dcache.overall_miss_rate::total 0.236929 # miss rate for overall accesses 731system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34811.178427 # average ReadReq miss latency 732system.cpu0.dcache.ReadReq_avg_miss_latency::total 34811.178427 # average ReadReq miss latency 733system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64637.695895 # average WriteReq miss latency 734system.cpu0.dcache.WriteReq_avg_miss_latency::total 64637.695895 # average WriteReq miss latency 735system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17216.058539 # average LoadLockedReq miss latency 736system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17216.058539 # average LoadLockedReq miss latency 737system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15567.252450 # average StoreCondReq miss latency 738system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15567.252450 # average StoreCondReq miss latency 739system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency 740system.cpu0.dcache.demand_avg_miss_latency::total 50337.500077 # average overall miss latency 741system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50337.500077 # average overall miss latency 742system.cpu0.dcache.overall_avg_miss_latency::total 50337.500077 # average overall miss latency 743system.cpu0.dcache.blocked_cycles::no_mshrs 6721817 # number of cycles access was blocked 744system.cpu0.dcache.blocked_cycles::no_targets 17671 # number of cycles access was blocked 745system.cpu0.dcache.blocked::no_mshrs 111036 # number of cycles access was blocked 746system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked 747system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked 748system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked
749system.cpu0.dcache.fast_writes 0 # number of fast writes performed 750system.cpu0.dcache.cache_copies 0 # number of cache copies performed
751system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks 752system.cpu0.dcache.writebacks::total 741086 # number of writebacks 753system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits 754system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits 755system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits 756system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits 757system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits 758system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits 759system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits 760system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits 761system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits 762system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits 763system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses 764system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses 765system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses 766system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses 767system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses 768system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses 769system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses 770system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses 771system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses 772system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses 773system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses 774system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses 775system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable 776system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable 777system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable 778system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable 779system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses 780system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses 781system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles 782system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles 783system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles 784system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles 785system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles 786system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles 787system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles 788system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles 789system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles 790system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles 791system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles 792system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles 793system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles 794system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles	749system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks 750system.cpu0.dcache.writebacks::total 741086 # number of writebacks 751system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits 752system.cpu0.dcache.ReadReq_mshr_hits::total 559859 # number of ReadReq MSHR hits 753system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449235 # number of WriteReq MSHR hits 754system.cpu0.dcache.WriteReq_mshr_hits::total 1449235 # number of WriteReq MSHR hits 755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5567 # number of LoadLockedReq MSHR hits 756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5567 # number of LoadLockedReq MSHR hits 757system.cpu0.dcache.demand_mshr_hits::cpu0.data 2009094 # number of demand (read+write) MSHR hits 758system.cpu0.dcache.demand_mshr_hits::total 2009094 # number of demand (read+write) MSHR hits 759system.cpu0.dcache.overall_mshr_hits::cpu0.data 2009094 # number of overall MSHR hits 760system.cpu0.dcache.overall_mshr_hits::total 2009094 # number of overall MSHR hits 761system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1009199 # number of ReadReq MSHR misses 762system.cpu0.dcache.ReadReq_mshr_misses::total 1009199 # number of ReadReq MSHR misses 763system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 254357 # number of WriteReq MSHR misses 764system.cpu0.dcache.WriteReq_mshr_misses::total 254357 # number of WriteReq MSHR misses 765system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14659 # number of LoadLockedReq MSHR misses 766system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14659 # number of LoadLockedReq MSHR misses 767system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2959 # number of StoreCondReq MSHR misses 768system.cpu0.dcache.StoreCondReq_mshr_misses::total 2959 # number of StoreCondReq MSHR misses 769system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263556 # number of demand (read+write) MSHR misses 770system.cpu0.dcache.demand_mshr_misses::total 1263556 # number of demand (read+write) MSHR misses 771system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263556 # number of overall MSHR misses 772system.cpu0.dcache.overall_mshr_misses::total 1263556 # number of overall MSHR misses 773system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable 774system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable 775system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10105 # number of WriteReq MSHR uncacheable 776system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10105 # number of WriteReq MSHR uncacheable 777system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17136 # number of overall MSHR uncacheable misses 778system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17136 # number of overall MSHR uncacheable misses 779system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43480023500 # number of ReadReq MSHR miss cycles 780system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43480023500 # number of ReadReq MSHR miss cycles 781system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17474692057 # number of WriteReq MSHR miss cycles 782system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17474692057 # number of WriteReq MSHR miss cycles 783system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 173733500 # number of LoadLockedReq MSHR miss cycles 784system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 173733500 # number of LoadLockedReq MSHR miss cycles 785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 43104500 # number of StoreCondReq MSHR miss cycles 786system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 43104500 # number of StoreCondReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60954715557 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 60954715557 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles
795system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles 796system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles 797system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles 798system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles	793system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles
799system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses 800system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses 804system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses 805system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses 806system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses 807system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses 808system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses 809system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses 810system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses 811system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency 812system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency 813system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency 814system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency 815system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency 816system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency 817system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency 818system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency 819system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 820system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 821system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 822system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 823system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency 824system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency	795system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses 796system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048081 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.073588 # mshr miss rate for LoadLockedReq accesses 800system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.073588 # mshr miss rate for LoadLockedReq accesses 801system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015800 # mshr miss rate for StoreCondReq accesses 802system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015800 # mshr miss rate for StoreCondReq accesses 803system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for demand accesses 804system.cpu0.dcache.demand_mshr_miss_rate::total 0.091477 # mshr miss rate for demand accesses 805system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091477 # mshr miss rate for overall accesses 806system.cpu0.dcache.overall_mshr_miss_rate::total 0.091477 # mshr miss rate for overall accesses 807system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43083.696575 # average ReadReq mshr miss latency 808system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43083.696575 # average ReadReq mshr miss latency 809system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68701.439540 # average WriteReq mshr miss latency 810system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68701.439540 # average WriteReq mshr miss latency 811system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11851.661096 # average LoadLockedReq mshr miss latency 812system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11851.661096 # average LoadLockedReq mshr miss latency 813system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14567.252450 # average StoreCondReq mshr miss latency 814system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14567.252450 # average StoreCondReq mshr miss latency 815system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 816system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 817system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 # average overall mshr miss latency 818system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency 819system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency 820system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency
825system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency 826system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency 827system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency 828system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency 829system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	821system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency 822system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency
830system.cpu0.icache.tags.replacements 911237 # number of replacements 831system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use 832system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. 833system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. 834system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. 835system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. 836system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor 837system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy 838system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy 839system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 840system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id 841system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id 842system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 843system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses 844system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses 845system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits 846system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits 847system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits 848system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits 849system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits 850system.cpu0.icache.overall_hits::total 7675800 # number of overall hits 851system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses 852system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses 853system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses 854system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses 855system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses 856system.cpu0.icache.overall_misses::total 966240 # number of overall misses 857system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles 858system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles 859system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles 860system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles 861system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles 862system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles 863system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) 864system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) 865system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses 866system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses 867system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses 868system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses 869system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses 870system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses 871system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses 872system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses 873system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses 874system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses 875system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency 876system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency 877system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency 878system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency 879system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency 880system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency 881system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked 882system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 883system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked 884system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 885system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked 886system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	823system.cpu0.icache.tags.replacements 911237 # number of replacements 824system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use 825system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. 826system.cpu0.icache.tags.sampled_refs 911749 # Sample count of references to valid blocks. 827system.cpu0.icache.tags.avg_refs 8.418764 # Average number of references to valid blocks. 828system.cpu0.icache.tags.warmup_cycle 42368821500 # Cycle when the warmup percentage was hit. 829system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.249711 # Average occupied blocks per requestor 830system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992675 # Average percentage of cache occupancy 831system.cpu0.icache.tags.occ_percent::total 0.992675 # Average percentage of cache occupancy 832system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 833system.cpu0.icache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id 834system.cpu0.icache.tags.age_task_id_blocks_1024::3 196 # Occupied blocks per task id 835system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 836system.cpu0.icache.tags.tag_accesses 9554008 # Number of tag accesses 837system.cpu0.icache.tags.data_accesses 9554008 # Number of data accesses 838system.cpu0.icache.ReadReq_hits::cpu0.inst 7675800 # number of ReadReq hits 839system.cpu0.icache.ReadReq_hits::total 7675800 # number of ReadReq hits 840system.cpu0.icache.demand_hits::cpu0.inst 7675800 # number of demand (read+write) hits 841system.cpu0.icache.demand_hits::total 7675800 # number of demand (read+write) hits 842system.cpu0.icache.overall_hits::cpu0.inst 7675800 # number of overall hits 843system.cpu0.icache.overall_hits::total 7675800 # number of overall hits 844system.cpu0.icache.ReadReq_misses::cpu0.inst 966240 # number of ReadReq misses 845system.cpu0.icache.ReadReq_misses::total 966240 # number of ReadReq misses 846system.cpu0.icache.demand_misses::cpu0.inst 966240 # number of demand (read+write) misses 847system.cpu0.icache.demand_misses::total 966240 # number of demand (read+write) misses 848system.cpu0.icache.overall_misses::cpu0.inst 966240 # number of overall misses 849system.cpu0.icache.overall_misses::total 966240 # number of overall misses 850system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14731064486 # number of ReadReq miss cycles 851system.cpu0.icache.ReadReq_miss_latency::total 14731064486 # number of ReadReq miss cycles 852system.cpu0.icache.demand_miss_latency::cpu0.inst 14731064486 # number of demand (read+write) miss cycles 853system.cpu0.icache.demand_miss_latency::total 14731064486 # number of demand (read+write) miss cycles 854system.cpu0.icache.overall_miss_latency::cpu0.inst 14731064486 # number of overall miss cycles 855system.cpu0.icache.overall_miss_latency::total 14731064486 # number of overall miss cycles 856system.cpu0.icache.ReadReq_accesses::cpu0.inst 8642040 # number of ReadReq accesses(hits+misses) 857system.cpu0.icache.ReadReq_accesses::total 8642040 # number of ReadReq accesses(hits+misses) 858system.cpu0.icache.demand_accesses::cpu0.inst 8642040 # number of demand (read+write) accesses 859system.cpu0.icache.demand_accesses::total 8642040 # number of demand (read+write) accesses 860system.cpu0.icache.overall_accesses::cpu0.inst 8642040 # number of overall (read+write) accesses 861system.cpu0.icache.overall_accesses::total 8642040 # number of overall (read+write) accesses 862system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111807 # miss rate for ReadReq accesses 863system.cpu0.icache.ReadReq_miss_rate::total 0.111807 # miss rate for ReadReq accesses 864system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111807 # miss rate for demand accesses 865system.cpu0.icache.demand_miss_rate::total 0.111807 # miss rate for demand accesses 866system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111807 # miss rate for overall accesses 867system.cpu0.icache.overall_miss_rate::total 0.111807 # miss rate for overall accesses 868system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15245.761391 # average ReadReq miss latency 869system.cpu0.icache.ReadReq_avg_miss_latency::total 15245.761391 # average ReadReq miss latency 870system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency 871system.cpu0.icache.demand_avg_miss_latency::total 15245.761391 # average overall miss latency 872system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15245.761391 # average overall miss latency 873system.cpu0.icache.overall_avg_miss_latency::total 15245.761391 # average overall miss latency 874system.cpu0.icache.blocked_cycles::no_mshrs 11439 # number of cycles access was blocked 875system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 876system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked 877system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 878system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked 879system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
887system.cpu0.icache.fast_writes 0 # number of fast writes performed 888system.cpu0.icache.cache_copies 0 # number of cache copies performed
889system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks 890system.cpu0.icache.writebacks::total 911237 # number of writebacks 891system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits 892system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits 893system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits 894system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits 895system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits 896system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits 897system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses 898system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses 899system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses 900system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses 901system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses 902system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses 903system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles 904system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles 905system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles 906system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles 907system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles 908system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles 909system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses 910system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses 911system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses 912system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses 913system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses 914system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses 915system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency 916system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency 917system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 918system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency 919system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 920system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency	880system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks 881system.cpu0.icache.writebacks::total 911237 # number of writebacks 882system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits 883system.cpu0.icache.ReadReq_mshr_hits::total 54272 # number of ReadReq MSHR hits 884system.cpu0.icache.demand_mshr_hits::cpu0.inst 54272 # number of demand (read+write) MSHR hits 885system.cpu0.icache.demand_mshr_hits::total 54272 # number of demand (read+write) MSHR hits 886system.cpu0.icache.overall_mshr_hits::cpu0.inst 54272 # number of overall MSHR hits 887system.cpu0.icache.overall_mshr_hits::total 54272 # number of overall MSHR hits 888system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 911968 # number of ReadReq MSHR misses 889system.cpu0.icache.ReadReq_mshr_misses::total 911968 # number of ReadReq MSHR misses 890system.cpu0.icache.demand_mshr_misses::cpu0.inst 911968 # number of demand (read+write) MSHR misses 891system.cpu0.icache.demand_mshr_misses::total 911968 # number of demand (read+write) MSHR misses 892system.cpu0.icache.overall_mshr_misses::cpu0.inst 911968 # number of overall MSHR misses 893system.cpu0.icache.overall_mshr_misses::total 911968 # number of overall MSHR misses 894system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12931897989 # number of ReadReq MSHR miss cycles 895system.cpu0.icache.ReadReq_mshr_miss_latency::total 12931897989 # number of ReadReq MSHR miss cycles 896system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12931897989 # number of demand (read+write) MSHR miss cycles 897system.cpu0.icache.demand_mshr_miss_latency::total 12931897989 # number of demand (read+write) MSHR miss cycles 898system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12931897989 # number of overall MSHR miss cycles 899system.cpu0.icache.overall_mshr_miss_latency::total 12931897989 # number of overall MSHR miss cycles 900system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for ReadReq accesses 901system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105527 # mshr miss rate for ReadReq accesses 902system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for demand accesses 903system.cpu0.icache.demand_mshr_miss_rate::total 0.105527 # mshr miss rate for demand accesses 904system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105527 # mshr miss rate for overall accesses 905system.cpu0.icache.overall_mshr_miss_rate::total 0.105527 # mshr miss rate for overall accesses 906system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average ReadReq mshr miss latency 907system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14180.210258 # average ReadReq mshr miss latency 908system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 909system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency 910system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency 911system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency
921system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
922system.cpu1.branchPred.lookups 4129053 # Number of BP lookups 923system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted 924system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect 925system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups 926system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits 927system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 928system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage 929system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. 930system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. 931system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. 932system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. 933system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. 934system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. 935system.cpu1.dtb.fetch_hits 0 # ITB hits 936system.cpu1.dtb.fetch_misses 0 # ITB misses 937system.cpu1.dtb.fetch_acv 0 # ITB acv 938system.cpu1.dtb.fetch_accesses 0 # ITB accesses 939system.cpu1.dtb.read_hits 2247369 # DTB read hits 940system.cpu1.dtb.read_misses 13283 # DTB read misses 941system.cpu1.dtb.read_acv 72 # DTB read access violations 942system.cpu1.dtb.read_accesses 382556 # DTB read accesses 943system.cpu1.dtb.write_hits 1356336 # DTB write hits 944system.cpu1.dtb.write_misses 3091 # DTB write misses 945system.cpu1.dtb.write_acv 71 # DTB write access violations 946system.cpu1.dtb.write_accesses 152961 # DTB write accesses 947system.cpu1.dtb.data_hits 3603705 # DTB hits 948system.cpu1.dtb.data_misses 16374 # DTB misses 949system.cpu1.dtb.data_acv 143 # DTB access violations 950system.cpu1.dtb.data_accesses 535517 # DTB accesses 951system.cpu1.itb.fetch_hits 615373 # ITB hits 952system.cpu1.itb.fetch_misses 3011 # ITB misses 953system.cpu1.itb.fetch_acv 117 # ITB acv 954system.cpu1.itb.fetch_accesses 618384 # ITB accesses 955system.cpu1.itb.read_hits 0 # DTB read hits 956system.cpu1.itb.read_misses 0 # DTB read misses 957system.cpu1.itb.read_acv 0 # DTB read access violations 958system.cpu1.itb.read_accesses 0 # DTB read accesses 959system.cpu1.itb.write_hits 0 # DTB write hits 960system.cpu1.itb.write_misses 0 # DTB write misses 961system.cpu1.itb.write_acv 0 # DTB write access violations 962system.cpu1.itb.write_accesses 0 # DTB write accesses 963system.cpu1.itb.data_hits 0 # DTB hits 964system.cpu1.itb.data_misses 0 # DTB misses 965system.cpu1.itb.data_acv 0 # DTB access violations 966system.cpu1.itb.data_accesses 0 # DTB accesses 967system.cpu1.numCycles 16726806 # number of cpu cycles simulated 968system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 969system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 970system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss 971system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed 972system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered 973system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken 974system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked 975system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing 976system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 977system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps 978system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions 979system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR 980system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched 981system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed 982system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) 983system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) 984system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) 985system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 986system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) 987system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) 988system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) 989system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) 990system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) 991system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) 992system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) 993system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) 994system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) 995system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 996system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 997system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 998system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) 999system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle 1000system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle 1001system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle 1002system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked 1003system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running 1004system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking 1005system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing 1006system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch 1007system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction 1008system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode 1009system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode 1010system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing 1011system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle 1012system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking 1013system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst 1014system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running 1015system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking 1016system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename 1017system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full 1018system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full 1019system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full 1020system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full 1021system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed 1022system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made 1023system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups 1024system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups 1025system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed 1026system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing 1027system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed 1028system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed 1029system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer 1030system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. 1031system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. 1032system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. 1033system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. 1034system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) 1035system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ 1036system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued 1037system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued 1038system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling 1039system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph 1040system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed 1041system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle 1042system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle 1043system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle 1044system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1045system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle 1046system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle 1047system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle 1048system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle 1049system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle 1050system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle 1051system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle 1052system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle 1053system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle 1054system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1055system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1056system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1057system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle 1058system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1059system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available 1060system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available 1061system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available 1062system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available 1063system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available 1064system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available 1065system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available 1066system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available 1067system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available 1068system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available 1069system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available 1070system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available 1071system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available 1072system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available 1073system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available 1074system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available 1075system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available 1076system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available 1077system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available 1078system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available 1079system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available 1080system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available 1081system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available 1082system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available 1083system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available 1084system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available 1085system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available 1086system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available 1087system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available 1088system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available 1089system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available 1090system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1091system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1092system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued 1093system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued 1094system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued 1095system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 1096system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued 1097system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued 1098system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued 1099system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued 1100system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued 1101system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued 1102system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued 1103system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued 1104system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued 1105system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued 1106system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued 1107system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued 1108system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued 1109system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued 1110system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued 1111system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued 1112system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued 1113system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued 1114system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued 1115system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued 1116system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued 1117system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued 1118system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued 1119system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued 1120system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued 1121system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued 1122system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued 1123system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued 1124system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued 1125system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1126system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued 1127system.cpu1.iq.rate 0.637969 # Inst issue rate 1128system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested 1129system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) 1130system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads 1131system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes 1132system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses 1133system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads 1134system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes 1135system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses 1136system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses 1137system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses 1138system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores 1139system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1140system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed 1141system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed 1142system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations 1143system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed 1144system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1145system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1146system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled 1147system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked 1148system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1149system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing 1150system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking 1151system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking 1152system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ 1153system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch 1154system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions 1155system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions 1156system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions 1157system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall 1158system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall 1159system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations 1160system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly 1161system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly 1162system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute 1163system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions 1164system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed 1165system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute 1166system.cpu1.iew.exec_swp 0 # number of swp insts executed 1167system.cpu1.iew.exec_nop 619841 # number of nop insts executed 1168system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed 1169system.cpu1.iew.exec_branches 1567515 # Number of branches executed 1170system.cpu1.iew.exec_stores 1365805 # Number of stores executed 1171system.cpu1.iew.exec_rate 0.627451 # Inst execution rate 1172system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit 1173system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back 1174system.cpu1.iew.wb_producers 4904906 # num instructions producing a value 1175system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value 1176system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle 1177system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back 1178system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit 1179system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards 1180system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted 1181system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle 1182system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle 1183system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle 1184system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1185system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle 1186system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle 1187system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle 1188system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle 1189system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle 1190system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle 1191system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle 1192system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle 1193system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle 1194system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1195system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1196system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1197system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle 1198system.cpu1.commit.committedInsts 9770342 # Number of instructions committed 1199system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed 1200system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1201system.cpu1.commit.refs 3138451 # Number of memory references committed 1202system.cpu1.commit.loads 1852265 # Number of loads committed 1203system.cpu1.commit.membars 45725 # Number of memory barriers committed 1204system.cpu1.commit.branches 1397481 # Number of branches committed 1205system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. 1206system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. 1207system.cpu1.commit.function_calls 152839 # Number of function calls committed. 1208system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction 1209system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction 1210system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction 1211system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction 1212system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction 1213system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction 1214system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction 1215system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction 1216system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction 1217system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction 1218system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction 1219system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction 1220system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction 1221system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction 1222system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction 1223system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction 1224system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction 1225system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction 1226system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction 1227system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction 1228system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction 1229system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction 1230system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction 1231system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction 1232system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction 1233system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction 1234system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction 1235system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction 1236system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction 1237system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction 1238system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction 1239system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction 1240system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction 1241system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1242system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction 1243system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached 1244system.cpu1.rob.rob_reads 26989101 # The number of ROB reads 1245system.cpu1.rob.rob_writes 24630830 # The number of ROB writes 1246system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself 1247system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling 1248system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1249system.cpu1.committedInsts 9305781 # Number of Instructions Simulated 1250system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated 1251system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction 1252system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads 1253system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle 1254system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads 1255system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads 1256system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes 1257system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads 1258system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes 1259system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads 1260system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes 1261system.cpu1.dcache.tags.replacements 120114 # number of replacements 1262system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use 1263system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. 1264system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. 1265system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. 1266system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. 1267system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor 1268system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy 1269system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy 1270system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1271system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id 1272system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 1273system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 1274system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1275system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses 1276system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses 1277system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits 1278system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits 1279system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits 1280system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits 1281system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits 1282system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits 1283system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits 1284system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits 1285system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits 1286system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits 1287system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits 1288system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits 1289system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses 1290system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses 1291system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses 1292system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses 1293system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses 1294system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses 1295system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses 1296system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses 1297system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses 1298system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses 1299system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses 1300system.cpu1.dcache.overall_misses::total 493010 # number of overall misses 1301system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles 1302system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles 1303system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles 1304system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles 1305system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles 1306system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles 1307system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles 1308system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles 1309system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles 1310system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles 1311system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles 1312system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles 1313system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) 1314system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) 1315system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) 1316system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) 1317system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) 1318system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) 1319system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) 1320system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) 1321system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses 1322system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses 1323system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses 1324system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses 1325system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses 1326system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses 1327system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses 1328system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses 1329system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses 1330system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses 1331system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses 1332system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses 1333system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses 1334system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses 1335system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses 1336system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses 1337system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency 1338system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency 1339system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency 1340system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency 1341system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency 1342system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency 1343system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency 1344system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency 1345system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency 1346system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency 1347system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency 1348system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency 1349system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked 1350system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked 1351system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked 1352system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked 1353system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked 1354system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked	912system.cpu1.branchPred.lookups 4129053 # Number of BP lookups 913system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted 914system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect 915system.cpu1.branchPred.BTBLookups 2303722 # Number of BTB lookups 916system.cpu1.branchPred.BTBHits 822541 # Number of BTB hits 917system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 918system.cpu1.branchPred.BTBHitPct 35.704872 # BTB Hit Percentage 919system.cpu1.branchPred.usedRAS 211273 # Number of times the RAS was used to get a target. 920system.cpu1.branchPred.RASInCorrect 8217 # Number of incorrect RAS predictions. 921system.cpu1.branchPred.indirectLookups 1287279 # Number of indirect predictor lookups. 922system.cpu1.branchPred.indirectHits 153619 # Number of indirect target hits. 923system.cpu1.branchPred.indirectMisses 1133660 # Number of indirect misses. 924system.cpu1.branchPredindirectMispredicted 37557 # Number of mispredicted indirect branches. 925system.cpu1.dtb.fetch_hits 0 # ITB hits 926system.cpu1.dtb.fetch_misses 0 # ITB misses 927system.cpu1.dtb.fetch_acv 0 # ITB acv 928system.cpu1.dtb.fetch_accesses 0 # ITB accesses 929system.cpu1.dtb.read_hits 2247369 # DTB read hits 930system.cpu1.dtb.read_misses 13283 # DTB read misses 931system.cpu1.dtb.read_acv 72 # DTB read access violations 932system.cpu1.dtb.read_accesses 382556 # DTB read accesses 933system.cpu1.dtb.write_hits 1356336 # DTB write hits 934system.cpu1.dtb.write_misses 3091 # DTB write misses 935system.cpu1.dtb.write_acv 71 # DTB write access violations 936system.cpu1.dtb.write_accesses 152961 # DTB write accesses 937system.cpu1.dtb.data_hits 3603705 # DTB hits 938system.cpu1.dtb.data_misses 16374 # DTB misses 939system.cpu1.dtb.data_acv 143 # DTB access violations 940system.cpu1.dtb.data_accesses 535517 # DTB accesses 941system.cpu1.itb.fetch_hits 615373 # ITB hits 942system.cpu1.itb.fetch_misses 3011 # ITB misses 943system.cpu1.itb.fetch_acv 117 # ITB acv 944system.cpu1.itb.fetch_accesses 618384 # ITB accesses 945system.cpu1.itb.read_hits 0 # DTB read hits 946system.cpu1.itb.read_misses 0 # DTB read misses 947system.cpu1.itb.read_acv 0 # DTB read access violations 948system.cpu1.itb.read_accesses 0 # DTB read accesses 949system.cpu1.itb.write_hits 0 # DTB write hits 950system.cpu1.itb.write_misses 0 # DTB write misses 951system.cpu1.itb.write_acv 0 # DTB write access violations 952system.cpu1.itb.write_accesses 0 # DTB write accesses 953system.cpu1.itb.data_hits 0 # DTB hits 954system.cpu1.itb.data_misses 0 # DTB misses 955system.cpu1.itb.data_acv 0 # DTB access violations 956system.cpu1.itb.data_accesses 0 # DTB accesses 957system.cpu1.numCycles 16726806 # number of cpu cycles simulated 958system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 959system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 960system.cpu1.fetch.icacheStallCycles 6696452 # Number of cycles fetch is stalled on an Icache miss 961system.cpu1.fetch.Insts 16370488 # Number of instructions fetch has processed 962system.cpu1.fetch.Branches 4129053 # Number of branches that fetch encountered 963system.cpu1.fetch.predictedBranches 1187433 # Number of branches that fetch has predicted taken 964system.cpu1.fetch.Cycles 8741861 # Number of cycles fetch has run and was not squashing or blocked 965system.cpu1.fetch.SquashCycles 347188 # Number of cycles fetch has spent squashing 966system.cpu1.fetch.MiscStallCycles 25893 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 967system.cpu1.fetch.PendingTrapStallCycles 58137 # Number of stall cycles due to pending traps 968system.cpu1.fetch.PendingQuiesceStallCycles 49356 # Number of stall cycles due to pending quiesce instructions 969system.cpu1.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR 970system.cpu1.fetch.CacheLines 1820963 # Number of cache lines fetched 971system.cpu1.fetch.IcacheSquashes 76422 # Number of outstanding Icache misses that were squashed 972system.cpu1.fetch.rateDist::samples 15745356 # Number of instructions fetched each cycle (Total) 973system.cpu1.fetch.rateDist::mean 1.039703 # Number of instructions fetched each cycle (Total) 974system.cpu1.fetch.rateDist::stdev 2.449166 # Number of instructions fetched each cycle (Total) 975system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 976system.cpu1.fetch.rateDist::0 12876670 81.78% 81.78% # Number of instructions fetched each cycle (Total) 977system.cpu1.fetch.rateDist::1 185062 1.18% 82.96% # Number of instructions fetched each cycle (Total) 978system.cpu1.fetch.rateDist::2 297924 1.89% 84.85% # Number of instructions fetched each cycle (Total) 979system.cpu1.fetch.rateDist::3 209767 1.33% 86.18% # Number of instructions fetched each cycle (Total) 980system.cpu1.fetch.rateDist::4 372753 2.37% 88.55% # Number of instructions fetched each cycle (Total) 981system.cpu1.fetch.rateDist::5 143050 0.91% 89.46% # Number of instructions fetched each cycle (Total) 982system.cpu1.fetch.rateDist::6 159866 1.02% 90.47% # Number of instructions fetched each cycle (Total) 983system.cpu1.fetch.rateDist::7 207293 1.32% 91.79% # Number of instructions fetched each cycle (Total) 984system.cpu1.fetch.rateDist::8 1292971 8.21% 100.00% # Number of instructions fetched each cycle (Total) 985system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 986system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 987system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 988system.cpu1.fetch.rateDist::total 15745356 # Number of instructions fetched each cycle (Total) 989system.cpu1.fetch.branchRate 0.246852 # Number of branch fetches per cycle 990system.cpu1.fetch.rate 0.978698 # Number of inst fetches per cycle 991system.cpu1.decode.IdleCycles 5498623 # Number of cycles decode is idle 992system.cpu1.decode.BlockedCycles 7777976 # Number of cycles decode is blocked 993system.cpu1.decode.RunCycles 2045729 # Number of cycles decode is running 994system.cpu1.decode.UnblockCycles 256320 # Number of cycles decode is unblocking 995system.cpu1.decode.SquashCycles 166707 # Number of cycles decode is squashing 996system.cpu1.decode.BranchResolved 143442 # Number of times decode resolved a branch 997system.cpu1.decode.BranchMispred 7016 # Number of times decode detected a branch misprediction 998system.cpu1.decode.DecodedInsts 13354105 # Number of instructions handled by decode 999system.cpu1.decode.SquashedInsts 22028 # Number of squashed instructions handled by decode 1000system.cpu1.rename.SquashCycles 166707 # Number of cycles rename is squashing 1001system.cpu1.rename.IdleCycles 5670233 # Number of cycles rename is idle 1002system.cpu1.rename.BlockCycles 826473 # Number of cycles rename is blocking 1003system.cpu1.rename.serializeStallCycles 5769862 # count of cycles rename stalled for serializing inst 1004system.cpu1.rename.RunCycles 2131801 # Number of cycles rename is running 1005system.cpu1.rename.UnblockCycles 1180278 # Number of cycles rename is unblocking 1006system.cpu1.rename.RenamedInsts 12651091 # Number of instructions processed by rename 1007system.cpu1.rename.ROBFullEvents 3750 # Number of times rename has blocked due to ROB full 1008system.cpu1.rename.IQFullEvents 88341 # Number of times rename has blocked due to IQ full 1009system.cpu1.rename.LQFullEvents 32960 # Number of times rename has blocked due to LQ full 1010system.cpu1.rename.SQFullEvents 615086 # Number of times rename has blocked due to SQ full 1011system.cpu1.rename.RenamedOperands 8374295 # Number of destination operands rename has renamed 1012system.cpu1.rename.RenameLookups 15046844 # Number of register rename lookups that rename has made 1013system.cpu1.rename.int_rename_lookups 14984377 # Number of integer rename lookups 1014system.cpu1.rename.fp_rename_lookups 56291 # Number of floating rename lookups 1015system.cpu1.rename.CommittedMaps 6609856 # Number of HB maps that are committed 1016system.cpu1.rename.UndoneMaps 1764431 # Number of HB maps that are undone due to squashing 1017system.cpu1.rename.serializingInsts 476570 # count of serializing insts renamed 1018system.cpu1.rename.tempSerializingInsts 48769 # count of temporary serializing insts renamed 1019system.cpu1.rename.skidInsts 2080322 # count of insts added to the skid buffer 1020system.cpu1.memDep0.insertedLoads 2346654 # Number of loads inserted to the mem dependence unit. 1021system.cpu1.memDep0.insertedStores 1454994 # Number of stores inserted to the mem dependence unit. 1022system.cpu1.memDep0.conflictingLoads 292964 # Number of conflicting loads. 1023system.cpu1.memDep0.conflictingStores 152733 # Number of conflicting stores. 1024system.cpu1.iq.iqInstsAdded 11085695 # Number of instructions added to the IQ (excludes non-spec) 1025system.cpu1.iq.iqNonSpecInstsAdded 541496 # Number of non-speculative instructions added to the IQ 1026system.cpu1.iq.iqInstsIssued 10671183 # Number of instructions issued 1027system.cpu1.iq.iqSquashedInstsIssued 25309 # Number of squashed instructions issued 1028system.cpu1.iq.iqSquashedInstsExamined 2321405 # Number of squashed instructions iterated over during squash; mainly for profiling 1029system.cpu1.iq.iqSquashedOperandsExamined 1075261 # Number of squashed operands that are examined and possibly removed from graph 1030system.cpu1.iq.iqSquashedNonSpecRemoved 398456 # Number of squashed non-spec instructions that were removed 1031system.cpu1.iq.issued_per_cycle::samples 15745356 # Number of insts issued each cycle 1032system.cpu1.iq.issued_per_cycle::mean 0.677735 # Number of insts issued each cycle 1033system.cpu1.iq.issued_per_cycle::stdev 1.406788 # Number of insts issued each cycle 1034system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1035system.cpu1.iq.issued_per_cycle::0 11382155 72.29% 72.29% # Number of insts issued each cycle 1036system.cpu1.iq.issued_per_cycle::1 1870956 11.88% 84.17% # Number of insts issued each cycle 1037system.cpu1.iq.issued_per_cycle::2 802175 5.09% 89.27% # Number of insts issued each cycle 1038system.cpu1.iq.issued_per_cycle::3 575742 3.66% 92.92% # Number of insts issued each cycle 1039system.cpu1.iq.issued_per_cycle::4 534921 3.40% 96.32% # Number of insts issued each cycle 1040system.cpu1.iq.issued_per_cycle::5 285738 1.81% 98.13% # Number of insts issued each cycle 1041system.cpu1.iq.issued_per_cycle::6 185455 1.18% 99.31% # Number of insts issued each cycle 1042system.cpu1.iq.issued_per_cycle::7 78165 0.50% 99.81% # Number of insts issued each cycle 1043system.cpu1.iq.issued_per_cycle::8 30049 0.19% 100.00% # Number of insts issued each cycle 1044system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1045system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1046system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1047system.cpu1.iq.issued_per_cycle::total 15745356 # Number of insts issued each cycle 1048system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1049system.cpu1.iq.fu_full::IntAlu 27488 9.05% 9.05% # attempts to use FU when none available 1050system.cpu1.iq.fu_full::IntMult 0 0.00% 9.05% # attempts to use FU when none available 1051system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available 1052system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available 1053system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available 1054system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available 1055system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available 1056system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available 1057system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available 1058system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available 1059system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available 1060system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available 1061system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available 1062system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available 1063system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available 1064system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available 1065system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available 1066system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available 1067system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available 1068system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available 1069system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available 1070system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available 1071system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available 1072system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available 1073system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available 1074system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available 1075system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available 1076system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available 1077system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available 1078system.cpu1.iq.fu_full::MemRead 170713 56.19% 65.24% # attempts to use FU when none available 1079system.cpu1.iq.fu_full::MemWrite 105586 34.76% 100.00% # attempts to use FU when none available 1080system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1081system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1082system.cpu1.iq.FU_type_0::No_OpClass 3991 0.04% 0.04% # Type of FU issued 1083system.cpu1.iq.FU_type_0::IntAlu 6611083 61.95% 61.99% # Type of FU issued 1084system.cpu1.iq.FU_type_0::IntMult 16524 0.15% 62.14% # Type of FU issued 1085system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued 1086system.cpu1.iq.FU_type_0::FloatAdd 12068 0.11% 62.26% # Type of FU issued 1087system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued 1088system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued 1089system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued 1090system.cpu1.iq.FU_type_0::FloatDiv 1990 0.02% 62.28% # Type of FU issued 1091system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued 1092system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued 1093system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued 1094system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued 1095system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued 1096system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued 1097system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued 1098system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued 1099system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued 1100system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued 1101system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued 1102system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued 1103system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued 1104system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued 1105system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued 1106system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued 1107system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued 1108system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued 1109system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued 1110system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued 1111system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued 1112system.cpu1.iq.FU_type_0::MemRead 2360403 22.12% 84.40% # Type of FU issued 1113system.cpu1.iq.FU_type_0::MemWrite 1384355 12.97% 97.37% # Type of FU issued 1114system.cpu1.iq.FU_type_0::IprAccess 280769 2.63% 100.00% # Type of FU issued 1115system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 1116system.cpu1.iq.FU_type_0::total 10671183 # Type of FU issued 1117system.cpu1.iq.rate 0.637969 # Inst issue rate 1118system.cpu1.iq.fu_busy_cnt 303787 # FU busy when requested 1119system.cpu1.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) 1120system.cpu1.iq.int_inst_queue_reads 37199457 # Number of integer instruction queue reads 1121system.cpu1.iq.int_inst_queue_writes 13849868 # Number of integer instruction queue writes 1122system.cpu1.iq.int_inst_queue_wakeup_accesses 10195275 # Number of integer instruction queue wakeup accesses 1123system.cpu1.iq.fp_inst_queue_reads 217360 # Number of floating instruction queue reads 1124system.cpu1.iq.fp_inst_queue_writes 103372 # Number of floating instruction queue writes 1125system.cpu1.iq.fp_inst_queue_wakeup_accesses 100900 # Number of floating instruction queue wakeup accesses 1126system.cpu1.iq.int_alu_accesses 10854739 # Number of integer alu accesses 1127system.cpu1.iq.fp_alu_accesses 116240 # Number of floating point alu accesses 1128system.cpu1.iew.lsq.thread0.forwLoads 112250 # Number of loads that had data forwarded from stores 1129system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 1130system.cpu1.iew.lsq.thread0.squashedLoads 494389 # Number of loads squashed 1131system.cpu1.iew.lsq.thread0.ignoredResponses 1075 # Number of memory responses ignored because the instruction is squashed 1132system.cpu1.iew.lsq.thread0.memOrderViolation 4794 # Number of memory ordering violations 1133system.cpu1.iew.lsq.thread0.squashedStores 168808 # Number of stores squashed 1134system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1135system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 1136system.cpu1.iew.lsq.thread0.rescheduledLoads 442 # Number of loads that were rescheduled 1137system.cpu1.iew.lsq.thread0.cacheBlocked 89761 # Number of times an access to memory failed due to the cache being blocked 1138system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 1139system.cpu1.iew.iewSquashCycles 166707 # Number of cycles IEW is squashing 1140system.cpu1.iew.iewBlockCycles 440216 # Number of cycles IEW is blocking 1141system.cpu1.iew.iewUnblockCycles 341566 # Number of cycles IEW is unblocking 1142system.cpu1.iew.iewDispatchedInsts 12247032 # Number of instructions dispatched to IQ 1143system.cpu1.iew.iewDispSquashedInsts 53191 # Number of squashed instructions skipped by dispatch 1144system.cpu1.iew.iewDispLoadInsts 2346654 # Number of dispatched load instructions 1145system.cpu1.iew.iewDispStoreInsts 1454994 # Number of dispatched store instructions 1146system.cpu1.iew.iewDispNonSpecInsts 491166 # Number of dispatched non-speculative instructions 1147system.cpu1.iew.iewIQFullEvents 5461 # Number of times the IQ has become full, causing a stall 1148system.cpu1.iew.iewLSQFullEvents 335179 # Number of times the LSQ has become full, causing a stall 1149system.cpu1.iew.memOrderViolationEvents 4794 # Number of memory order violations 1150system.cpu1.iew.predictedTakenIncorrect 42007 # Number of branches that were predicted taken incorrectly 1151system.cpu1.iew.predictedNotTakenIncorrect 137108 # Number of branches that were predicted not taken incorrectly 1152system.cpu1.iew.branchMispredicts 179115 # Number of branch mispredicts detected at execute 1153system.cpu1.iew.iewExecutedInsts 10495256 # Number of executed instructions 1154system.cpu1.iew.iewExecLoadInsts 2269179 # Number of load instructions executed 1155system.cpu1.iew.iewExecSquashedInsts 175926 # Number of squashed instructions skipped in execute 1156system.cpu1.iew.exec_swp 0 # number of swp insts executed 1157system.cpu1.iew.exec_nop 619841 # number of nop insts executed 1158system.cpu1.iew.exec_refs 3634984 # number of memory reference insts executed 1159system.cpu1.iew.exec_branches 1567515 # Number of branches executed 1160system.cpu1.iew.exec_stores 1365805 # Number of stores executed 1161system.cpu1.iew.exec_rate 0.627451 # Inst execution rate 1162system.cpu1.iew.wb_sent 10344393 # cumulative count of insts sent to commit 1163system.cpu1.iew.wb_count 10296175 # cumulative count of insts written-back 1164system.cpu1.iew.wb_producers 4904906 # num instructions producing a value 1165system.cpu1.iew.wb_consumers 6922372 # num instructions consuming a value 1166system.cpu1.iew.wb_rate 0.615549 # insts written-back per cycle 1167system.cpu1.iew.wb_fanout 0.708559 # average fanout of values written-back 1168system.cpu1.commit.commitSquashedInsts 2337439 # The number of squashed insts skipped by commit 1169system.cpu1.commit.commitNonSpecStalls 143040 # The number of times commit has been forced to stall to communicate backwards 1170system.cpu1.commit.branchMispredicts 155210 # The number of times a branch was mispredicted 1171system.cpu1.commit.committed_per_cycle::samples 15327667 # Number of insts commited each cycle 1172system.cpu1.commit.committed_per_cycle::mean 0.637432 # Number of insts commited each cycle 1173system.cpu1.commit.committed_per_cycle::stdev 1.616488 # Number of insts commited each cycle 1174system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 1175system.cpu1.commit.committed_per_cycle::0 11807980 77.04% 77.04% # Number of insts commited each cycle 1176system.cpu1.commit.committed_per_cycle::1 1622081 10.58% 87.62% # Number of insts commited each cycle 1177system.cpu1.commit.committed_per_cycle::2 578152 3.77% 91.39% # Number of insts commited each cycle 1178system.cpu1.commit.committed_per_cycle::3 357481 2.33% 93.72% # Number of insts commited each cycle 1179system.cpu1.commit.committed_per_cycle::4 274261 1.79% 95.51% # Number of insts commited each cycle 1180system.cpu1.commit.committed_per_cycle::5 117588 0.77% 96.28% # Number of insts commited each cycle 1181system.cpu1.commit.committed_per_cycle::6 104376 0.68% 96.96% # Number of insts commited each cycle 1182system.cpu1.commit.committed_per_cycle::7 117710 0.77% 97.73% # Number of insts commited each cycle 1183system.cpu1.commit.committed_per_cycle::8 348038 2.27% 100.00% # Number of insts commited each cycle 1184system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1185system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1186system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 1187system.cpu1.commit.committed_per_cycle::total 15327667 # Number of insts commited each cycle 1188system.cpu1.commit.committedInsts 9770342 # Number of instructions committed 1189system.cpu1.commit.committedOps 9770342 # Number of ops (including micro ops) committed 1190system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 1191system.cpu1.commit.refs 3138451 # Number of memory references committed 1192system.cpu1.commit.loads 1852265 # Number of loads committed 1193system.cpu1.commit.membars 45725 # Number of memory barriers committed 1194system.cpu1.commit.branches 1397481 # Number of branches committed 1195system.cpu1.commit.fp_insts 99132 # Number of committed floating point instructions. 1196system.cpu1.commit.int_insts 9064844 # Number of committed integer instructions. 1197system.cpu1.commit.function_calls 152839 # Number of function calls committed. 1198system.cpu1.commit.op_class_0::No_OpClass 468541 4.80% 4.80% # Class of committed instruction 1199system.cpu1.commit.op_class_0::IntAlu 5805964 59.42% 64.22% # Class of committed instruction 1200system.cpu1.commit.op_class_0::IntMult 16275 0.17% 64.39% # Class of committed instruction 1201system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.39% # Class of committed instruction 1202system.cpu1.commit.op_class_0::FloatAdd 12061 0.12% 64.51% # Class of committed instruction 1203system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction 1204system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction 1205system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction 1206system.cpu1.commit.op_class_0::FloatDiv 1990 0.02% 64.53% # Class of committed instruction 1207system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction 1208system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction 1209system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction 1210system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction 1211system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction 1212system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction 1213system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction 1214system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction 1215system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction 1216system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction 1217system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction 1218system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction 1219system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction 1220system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction 1221system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction 1222system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction 1223system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction 1224system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction 1225system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction 1226system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction 1227system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction 1228system.cpu1.commit.op_class_0::MemRead 1897990 19.43% 83.96% # Class of committed instruction 1229system.cpu1.commit.op_class_0::MemWrite 1286752 13.17% 97.13% # Class of committed instruction 1230system.cpu1.commit.op_class_0::IprAccess 280769 2.87% 100.00% # Class of committed instruction 1231system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1232system.cpu1.commit.op_class_0::total 9770342 # Class of committed instruction 1233system.cpu1.commit.bw_lim_events 348038 # number cycles where commit BW limit reached 1234system.cpu1.rob.rob_reads 26989101 # The number of ROB reads 1235system.cpu1.rob.rob_writes 24630830 # The number of ROB writes 1236system.cpu1.timesIdled 131471 # Number of times that the entire CPU went into an idle state and unscheduled itself 1237system.cpu1.idleCycles 981450 # Total number of cycles that the CPU has spent unscheduled due to idling 1238system.cpu1.quiesceCycles 3841428948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1239system.cpu1.committedInsts 9305781 # Number of Instructions Simulated 1240system.cpu1.committedOps 9305781 # Number of Ops (including micro ops) Simulated 1241system.cpu1.cpi 1.797464 # CPI: Cycles Per Instruction 1242system.cpu1.cpi_total 1.797464 # CPI: Total CPI of All Threads 1243system.cpu1.ipc 0.556339 # IPC: Instructions Per Cycle 1244system.cpu1.ipc_total 0.556339 # IPC: Total IPC of All Threads 1245system.cpu1.int_regfile_reads 13488576 # number of integer regfile reads 1246system.cpu1.int_regfile_writes 7349661 # number of integer regfile writes 1247system.cpu1.fp_regfile_reads 55714 # number of floating regfile reads 1248system.cpu1.fp_regfile_writes 55051 # number of floating regfile writes 1249system.cpu1.misc_regfile_reads 538402 # number of misc regfile reads 1250system.cpu1.misc_regfile_writes 228232 # number of misc regfile writes 1251system.cpu1.dcache.tags.replacements 120114 # number of replacements 1252system.cpu1.dcache.tags.tagsinuse 486.559727 # Cycle average of tags in use 1253system.cpu1.dcache.tags.total_refs 2854712 # Total number of references to valid blocks. 1254system.cpu1.dcache.tags.sampled_refs 120626 # Sample count of references to valid blocks. 1255system.cpu1.dcache.tags.avg_refs 23.665810 # Average number of references to valid blocks. 1256system.cpu1.dcache.tags.warmup_cycle 62007957000 # Cycle when the warmup percentage was hit. 1257system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.559727 # Average occupied blocks per requestor 1258system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950312 # Average percentage of cache occupancy 1259system.cpu1.dcache.tags.occ_percent::total 0.950312 # Average percentage of cache occupancy 1260system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1261system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id 1262system.cpu1.dcache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 1263system.cpu1.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id 1264system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1265system.cpu1.dcache.tags.tag_accesses 13510694 # Number of tag accesses 1266system.cpu1.dcache.tags.data_accesses 13510694 # Number of data accesses 1267system.cpu1.dcache.ReadReq_hits::cpu1.data 1801260 # number of ReadReq hits 1268system.cpu1.dcache.ReadReq_hits::total 1801260 # number of ReadReq hits 1269system.cpu1.dcache.WriteReq_hits::cpu1.data 972413 # number of WriteReq hits 1270system.cpu1.dcache.WriteReq_hits::total 972413 # number of WriteReq hits 1271system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 37246 # number of LoadLockedReq hits 1272system.cpu1.dcache.LoadLockedReq_hits::total 37246 # number of LoadLockedReq hits 1273system.cpu1.dcache.StoreCondReq_hits::cpu1.data 33039 # number of StoreCondReq hits 1274system.cpu1.dcache.StoreCondReq_hits::total 33039 # number of StoreCondReq hits 1275system.cpu1.dcache.demand_hits::cpu1.data 2773673 # number of demand (read+write) hits 1276system.cpu1.dcache.demand_hits::total 2773673 # number of demand (read+write) hits 1277system.cpu1.dcache.overall_hits::cpu1.data 2773673 # number of overall hits 1278system.cpu1.dcache.overall_hits::total 2773673 # number of overall hits 1279system.cpu1.dcache.ReadReq_misses::cpu1.data 221542 # number of ReadReq misses 1280system.cpu1.dcache.ReadReq_misses::total 221542 # number of ReadReq misses 1281system.cpu1.dcache.WriteReq_misses::cpu1.data 271468 # number of WriteReq misses 1282system.cpu1.dcache.WriteReq_misses::total 271468 # number of WriteReq misses 1283system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5109 # number of LoadLockedReq misses 1284system.cpu1.dcache.LoadLockedReq_misses::total 5109 # number of LoadLockedReq misses 1285system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3089 # number of StoreCondReq misses 1286system.cpu1.dcache.StoreCondReq_misses::total 3089 # number of StoreCondReq misses 1287system.cpu1.dcache.demand_misses::cpu1.data 493010 # number of demand (read+write) misses 1288system.cpu1.dcache.demand_misses::total 493010 # number of demand (read+write) misses 1289system.cpu1.dcache.overall_misses::cpu1.data 493010 # number of overall misses 1290system.cpu1.dcache.overall_misses::total 493010 # number of overall misses 1291system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2936746000 # number of ReadReq miss cycles 1292system.cpu1.dcache.ReadReq_miss_latency::total 2936746000 # number of ReadReq miss cycles 1293system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12570320655 # number of WriteReq miss cycles 1294system.cpu1.dcache.WriteReq_miss_latency::total 12570320655 # number of WriteReq miss cycles 1295system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51167000 # number of LoadLockedReq miss cycles 1296system.cpu1.dcache.LoadLockedReq_miss_latency::total 51167000 # number of LoadLockedReq miss cycles 1297system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47352500 # number of StoreCondReq miss cycles 1298system.cpu1.dcache.StoreCondReq_miss_latency::total 47352500 # number of StoreCondReq miss cycles 1299system.cpu1.dcache.demand_miss_latency::cpu1.data 15507066655 # number of demand (read+write) miss cycles 1300system.cpu1.dcache.demand_miss_latency::total 15507066655 # number of demand (read+write) miss cycles 1301system.cpu1.dcache.overall_miss_latency::cpu1.data 15507066655 # number of overall miss cycles 1302system.cpu1.dcache.overall_miss_latency::total 15507066655 # number of overall miss cycles 1303system.cpu1.dcache.ReadReq_accesses::cpu1.data 2022802 # number of ReadReq accesses(hits+misses) 1304system.cpu1.dcache.ReadReq_accesses::total 2022802 # number of ReadReq accesses(hits+misses) 1305system.cpu1.dcache.WriteReq_accesses::cpu1.data 1243881 # number of WriteReq accesses(hits+misses) 1306system.cpu1.dcache.WriteReq_accesses::total 1243881 # number of WriteReq accesses(hits+misses) 1307system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 42355 # number of LoadLockedReq accesses(hits+misses) 1308system.cpu1.dcache.LoadLockedReq_accesses::total 42355 # number of LoadLockedReq accesses(hits+misses) 1309system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 36128 # number of StoreCondReq accesses(hits+misses) 1310system.cpu1.dcache.StoreCondReq_accesses::total 36128 # number of StoreCondReq accesses(hits+misses) 1311system.cpu1.dcache.demand_accesses::cpu1.data 3266683 # number of demand (read+write) accesses 1312system.cpu1.dcache.demand_accesses::total 3266683 # number of demand (read+write) accesses 1313system.cpu1.dcache.overall_accesses::cpu1.data 3266683 # number of overall (read+write) accesses 1314system.cpu1.dcache.overall_accesses::total 3266683 # number of overall (read+write) accesses 1315system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109522 # miss rate for ReadReq accesses 1316system.cpu1.dcache.ReadReq_miss_rate::total 0.109522 # miss rate for ReadReq accesses 1317system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218243 # miss rate for WriteReq accesses 1318system.cpu1.dcache.WriteReq_miss_rate::total 0.218243 # miss rate for WriteReq accesses 1319system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120623 # miss rate for LoadLockedReq accesses 1320system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120623 # miss rate for LoadLockedReq accesses 1321system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085502 # miss rate for StoreCondReq accesses 1322system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085502 # miss rate for StoreCondReq accesses 1323system.cpu1.dcache.demand_miss_rate::cpu1.data 0.150921 # miss rate for demand accesses 1324system.cpu1.dcache.demand_miss_rate::total 0.150921 # miss rate for demand accesses 1325system.cpu1.dcache.overall_miss_rate::cpu1.data 0.150921 # miss rate for overall accesses 1326system.cpu1.dcache.overall_miss_rate::total 0.150921 # miss rate for overall accesses 1327system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13255.933412 # average ReadReq miss latency 1328system.cpu1.dcache.ReadReq_avg_miss_latency::total 13255.933412 # average ReadReq miss latency 1329system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46304.981269 # average WriteReq miss latency 1330system.cpu1.dcache.WriteReq_avg_miss_latency::total 46304.981269 # average WriteReq miss latency 1331system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10015.071443 # average LoadLockedReq miss latency 1332system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10015.071443 # average LoadLockedReq miss latency 1333system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15329.394626 # average StoreCondReq miss latency 1334system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15329.394626 # average StoreCondReq miss latency 1335system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency 1336system.cpu1.dcache.demand_avg_miss_latency::total 31453.858248 # average overall miss latency 1337system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31453.858248 # average overall miss latency 1338system.cpu1.dcache.overall_avg_miss_latency::total 31453.858248 # average overall miss latency 1339system.cpu1.dcache.blocked_cycles::no_mshrs 759613 # number of cycles access was blocked 1340system.cpu1.dcache.blocked_cycles::no_targets 1583 # number of cycles access was blocked 1341system.cpu1.dcache.blocked::no_mshrs 22564 # number of cycles access was blocked 1342system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked 1343system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked 1344system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked
1355system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1356system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1357system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks 1358system.cpu1.dcache.writebacks::total 79554 # number of writebacks 1359system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits 1360system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits 1361system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits 1362system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits 1363system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits 1364system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits 1365system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits 1366system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits 1367system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits 1368system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits 1369system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses 1370system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses 1371system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses 1372system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses 1373system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses 1374system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses 1375system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses 1376system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses 1377system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses 1378system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses 1379system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses 1380system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses 1381system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable 1382system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable 1383system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable 1384system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable 1385system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses 1386system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses 1387system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles 1388system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles 1389system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles 1390system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles 1391system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles 1392system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles 1393system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles 1394system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles 1395system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles 1396system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles 1397system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles 1398system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles 1399system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles 1400system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles	1345system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks 1346system.cpu1.dcache.writebacks::total 79554 # number of writebacks 1347system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits 1348system.cpu1.dcache.ReadReq_mshr_hits::total 136401 # number of ReadReq MSHR hits 1349system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 226329 # number of WriteReq MSHR hits 1350system.cpu1.dcache.WriteReq_mshr_hits::total 226329 # number of WriteReq MSHR hits 1351system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 689 # number of LoadLockedReq MSHR hits 1352system.cpu1.dcache.LoadLockedReq_mshr_hits::total 689 # number of LoadLockedReq MSHR hits 1353system.cpu1.dcache.demand_mshr_hits::cpu1.data 362730 # number of demand (read+write) MSHR hits 1354system.cpu1.dcache.demand_mshr_hits::total 362730 # number of demand (read+write) MSHR hits 1355system.cpu1.dcache.overall_mshr_hits::cpu1.data 362730 # number of overall MSHR hits 1356system.cpu1.dcache.overall_mshr_hits::total 362730 # number of overall MSHR hits 1357system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 85141 # number of ReadReq MSHR misses 1358system.cpu1.dcache.ReadReq_mshr_misses::total 85141 # number of ReadReq MSHR misses 1359system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45139 # number of WriteReq MSHR misses 1360system.cpu1.dcache.WriteReq_mshr_misses::total 45139 # number of WriteReq MSHR misses 1361system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4420 # number of LoadLockedReq MSHR misses 1362system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4420 # number of LoadLockedReq MSHR misses 1363system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3085 # number of StoreCondReq MSHR misses 1364system.cpu1.dcache.StoreCondReq_mshr_misses::total 3085 # number of StoreCondReq MSHR misses 1365system.cpu1.dcache.demand_mshr_misses::cpu1.data 130280 # number of demand (read+write) MSHR misses 1366system.cpu1.dcache.demand_mshr_misses::total 130280 # number of demand (read+write) MSHR misses 1367system.cpu1.dcache.overall_mshr_misses::cpu1.data 130280 # number of overall MSHR misses 1368system.cpu1.dcache.overall_mshr_misses::total 130280 # number of overall MSHR misses 1369system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable 1370system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable 1371system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2990 # number of WriteReq MSHR uncacheable 1372system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2990 # number of WriteReq MSHR uncacheable 1373system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3152 # number of overall MSHR uncacheable misses 1374system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3152 # number of overall MSHR uncacheable misses 1375system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1075350000 # number of ReadReq MSHR miss cycles 1376system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1075350000 # number of ReadReq MSHR miss cycles 1377system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2078906462 # number of WriteReq MSHR miss cycles 1378system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2078906462 # number of WriteReq MSHR miss cycles 1379system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39137500 # number of LoadLockedReq MSHR miss cycles 1380system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39137500 # number of LoadLockedReq MSHR miss cycles 1381system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44267500 # number of StoreCondReq MSHR miss cycles 1382system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44267500 # number of StoreCondReq MSHR miss cycles 1383system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3154256462 # number of demand (read+write) MSHR miss cycles 1384system.cpu1.dcache.demand_mshr_miss_latency::total 3154256462 # number of demand (read+write) MSHR miss cycles 1385system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 # number of overall MSHR miss cycles 1386system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles 1387system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles 1388system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles
1401system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles 1402system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles 1403system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles 1404system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles	1389system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles 1390system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles
1405system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses 1406system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses 1407system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses 1408system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses 1409system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses 1410system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses 1411system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses 1412system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses 1413system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses 1414system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses 1415system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses 1416system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses 1417system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency 1418system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency 1419system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency 1420system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency 1421system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency 1422system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency 1423system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency 1424system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency 1425system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1426system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1427system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1428system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1429system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency 1430system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency	1391system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses 1392system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses 1393system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses 1394system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036289 # mshr miss rate for WriteReq accesses 1395system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104356 # mshr miss rate for LoadLockedReq accesses 1396system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104356 # mshr miss rate for LoadLockedReq accesses 1397system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085391 # mshr miss rate for StoreCondReq accesses 1398system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085391 # mshr miss rate for StoreCondReq accesses 1399system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for demand accesses 1400system.cpu1.dcache.demand_mshr_miss_rate::total 0.039881 # mshr miss rate for demand accesses 1401system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039881 # mshr miss rate for overall accesses 1402system.cpu1.dcache.overall_mshr_miss_rate::total 0.039881 # mshr miss rate for overall accesses 1403system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12630.225156 # average ReadReq mshr miss latency 1404system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12630.225156 # average ReadReq mshr miss latency 1405system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46055.660560 # average WriteReq mshr miss latency 1406system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46055.660560 # average WriteReq mshr miss latency 1407system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8854.638009 # average LoadLockedReq mshr miss latency 1408system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8854.638009 # average LoadLockedReq mshr miss latency 1409system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14349.270665 # average StoreCondReq mshr miss latency 1410system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14349.270665 # average StoreCondReq mshr miss latency 1411system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1412system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1413system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 # average overall mshr miss latency 1414system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency 1415system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency 1416system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency
1431system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency 1432system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency 1433system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency 1434system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency 1435system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	1417system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency 1418system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency
1436system.cpu1.icache.tags.replacements 244089 # number of replacements 1437system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use 1438system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. 1439system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. 1440system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. 1441system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. 1442system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor 1443system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy 1444system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy 1445system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1446system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1447system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 1448system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id 1449system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1450system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses 1451system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses 1452system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits 1453system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits 1454system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits 1455system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits 1456system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits 1457system.cpu1.icache.overall_hits::total 1565201 # number of overall hits 1458system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses 1459system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses 1460system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses 1461system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses 1462system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses 1463system.cpu1.icache.overall_misses::total 255762 # number of overall misses 1464system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles 1465system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles 1466system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles 1467system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles 1468system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles 1469system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles 1470system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) 1471system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) 1472system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses 1473system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses 1474system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses 1475system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses 1476system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses 1477system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses 1478system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses 1479system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses 1480system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses 1481system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses 1482system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency 1483system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency 1484system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency 1485system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency 1486system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency 1487system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency 1488system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked 1489system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1490system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked 1491system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1492system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked 1493system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	1419system.cpu1.icache.tags.replacements 244089 # number of replacements 1420system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use 1421system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. 1422system.cpu1.icache.tags.sampled_refs 244601 # Sample count of references to valid blocks. 1423system.cpu1.icache.tags.avg_refs 6.398997 # Average number of references to valid blocks. 1424system.cpu1.icache.tags.warmup_cycle 1896682174500 # Cycle when the warmup percentage was hit. 1425system.cpu1.icache.tags.occ_blocks::cpu1.inst 469.435893 # Average occupied blocks per requestor 1426system.cpu1.icache.tags.occ_percent::cpu1.inst 0.916867 # Average percentage of cache occupancy 1427system.cpu1.icache.tags.occ_percent::total 0.916867 # Average percentage of cache occupancy 1428system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1429system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1430system.cpu1.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 1431system.cpu1.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id 1432system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1433system.cpu1.icache.tags.tag_accesses 2065632 # Number of tag accesses 1434system.cpu1.icache.tags.data_accesses 2065632 # Number of data accesses 1435system.cpu1.icache.ReadReq_hits::cpu1.inst 1565201 # number of ReadReq hits 1436system.cpu1.icache.ReadReq_hits::total 1565201 # number of ReadReq hits 1437system.cpu1.icache.demand_hits::cpu1.inst 1565201 # number of demand (read+write) hits 1438system.cpu1.icache.demand_hits::total 1565201 # number of demand (read+write) hits 1439system.cpu1.icache.overall_hits::cpu1.inst 1565201 # number of overall hits 1440system.cpu1.icache.overall_hits::total 1565201 # number of overall hits 1441system.cpu1.icache.ReadReq_misses::cpu1.inst 255762 # number of ReadReq misses 1442system.cpu1.icache.ReadReq_misses::total 255762 # number of ReadReq misses 1443system.cpu1.icache.demand_misses::cpu1.inst 255762 # number of demand (read+write) misses 1444system.cpu1.icache.demand_misses::total 255762 # number of demand (read+write) misses 1445system.cpu1.icache.overall_misses::cpu1.inst 255762 # number of overall misses 1446system.cpu1.icache.overall_misses::total 255762 # number of overall misses 1447system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3690348499 # number of ReadReq miss cycles 1448system.cpu1.icache.ReadReq_miss_latency::total 3690348499 # number of ReadReq miss cycles 1449system.cpu1.icache.demand_miss_latency::cpu1.inst 3690348499 # number of demand (read+write) miss cycles 1450system.cpu1.icache.demand_miss_latency::total 3690348499 # number of demand (read+write) miss cycles 1451system.cpu1.icache.overall_miss_latency::cpu1.inst 3690348499 # number of overall miss cycles 1452system.cpu1.icache.overall_miss_latency::total 3690348499 # number of overall miss cycles 1453system.cpu1.icache.ReadReq_accesses::cpu1.inst 1820963 # number of ReadReq accesses(hits+misses) 1454system.cpu1.icache.ReadReq_accesses::total 1820963 # number of ReadReq accesses(hits+misses) 1455system.cpu1.icache.demand_accesses::cpu1.inst 1820963 # number of demand (read+write) accesses 1456system.cpu1.icache.demand_accesses::total 1820963 # number of demand (read+write) accesses 1457system.cpu1.icache.overall_accesses::cpu1.inst 1820963 # number of overall (read+write) accesses 1458system.cpu1.icache.overall_accesses::total 1820963 # number of overall (read+write) accesses 1459system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.140454 # miss rate for ReadReq accesses 1460system.cpu1.icache.ReadReq_miss_rate::total 0.140454 # miss rate for ReadReq accesses 1461system.cpu1.icache.demand_miss_rate::cpu1.inst 0.140454 # miss rate for demand accesses 1462system.cpu1.icache.demand_miss_rate::total 0.140454 # miss rate for demand accesses 1463system.cpu1.icache.overall_miss_rate::cpu1.inst 0.140454 # miss rate for overall accesses 1464system.cpu1.icache.overall_miss_rate::total 0.140454 # miss rate for overall accesses 1465system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14428.838135 # average ReadReq miss latency 1466system.cpu1.icache.ReadReq_avg_miss_latency::total 14428.838135 # average ReadReq miss latency 1467system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency 1468system.cpu1.icache.demand_avg_miss_latency::total 14428.838135 # average overall miss latency 1469system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14428.838135 # average overall miss latency 1470system.cpu1.icache.overall_avg_miss_latency::total 14428.838135 # average overall miss latency 1471system.cpu1.icache.blocked_cycles::no_mshrs 721 # number of cycles access was blocked 1472system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1473system.cpu1.icache.blocked::no_mshrs 56 # number of cycles access was blocked 1474system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1475system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked 1476system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1494system.cpu1.icache.fast_writes 0 # number of fast writes performed 1495system.cpu1.icache.cache_copies 0 # number of cache copies performed
1496system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks 1497system.cpu1.icache.writebacks::total 244089 # number of writebacks 1498system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits 1499system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits 1500system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits 1501system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits 1502system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits 1503system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits 1504system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses 1505system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses 1506system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses 1507system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses 1508system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses 1509system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses 1510system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles 1511system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles 1512system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles 1513system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles 1514system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles 1515system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles 1516system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses 1517system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses 1518system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses 1519system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses 1520system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses 1521system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses 1522system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency 1523system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency 1524system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1525system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency 1526system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1527system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency	1477system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks 1478system.cpu1.icache.writebacks::total 244089 # number of writebacks 1479system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits 1480system.cpu1.icache.ReadReq_mshr_hits::total 11093 # number of ReadReq MSHR hits 1481system.cpu1.icache.demand_mshr_hits::cpu1.inst 11093 # number of demand (read+write) MSHR hits 1482system.cpu1.icache.demand_mshr_hits::total 11093 # number of demand (read+write) MSHR hits 1483system.cpu1.icache.overall_mshr_hits::cpu1.inst 11093 # number of overall MSHR hits 1484system.cpu1.icache.overall_mshr_hits::total 11093 # number of overall MSHR hits 1485system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244669 # number of ReadReq MSHR misses 1486system.cpu1.icache.ReadReq_mshr_misses::total 244669 # number of ReadReq MSHR misses 1487system.cpu1.icache.demand_mshr_misses::cpu1.inst 244669 # number of demand (read+write) MSHR misses 1488system.cpu1.icache.demand_mshr_misses::total 244669 # number of demand (read+write) MSHR misses 1489system.cpu1.icache.overall_mshr_misses::cpu1.inst 244669 # number of overall MSHR misses 1490system.cpu1.icache.overall_mshr_misses::total 244669 # number of overall MSHR misses 1491system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3289647499 # number of ReadReq MSHR miss cycles 1492system.cpu1.icache.ReadReq_mshr_miss_latency::total 3289647499 # number of ReadReq MSHR miss cycles 1493system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3289647499 # number of demand (read+write) MSHR miss cycles 1494system.cpu1.icache.demand_mshr_miss_latency::total 3289647499 # number of demand (read+write) MSHR miss cycles 1495system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3289647499 # number of overall MSHR miss cycles 1496system.cpu1.icache.overall_mshr_miss_latency::total 3289647499 # number of overall MSHR miss cycles 1497system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for ReadReq accesses 1498system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.134362 # mshr miss rate for ReadReq accesses 1499system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for demand accesses 1500system.cpu1.icache.demand_mshr_miss_rate::total 0.134362 # mshr miss rate for demand accesses 1501system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.134362 # mshr miss rate for overall accesses 1502system.cpu1.icache.overall_mshr_miss_rate::total 0.134362 # mshr miss rate for overall accesses 1503system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average ReadReq mshr miss latency 1504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13445.297520 # average ReadReq mshr miss latency 1505system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1506system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency 1507system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency 1508system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency
1528system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1529system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1530system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1531system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1532system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1533system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1534system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1535system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1536system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1537system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1538system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1539system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1540system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1541system.iobus.trans_dist::ReadReq 7368 # Transaction distribution 1542system.iobus.trans_dist::ReadResp 7368 # Transaction distribution 1543system.iobus.trans_dist::WriteReq 54647 # Transaction distribution 1544system.iobus.trans_dist::WriteResp 54647 # Transaction distribution 1545system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1551system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1552system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1553system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1554system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) 1555system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1556system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1557system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1562system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1563system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) 1572system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1573system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) 1574system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1575system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1576system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1577system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1578system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1579system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) 1580system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1581system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) 1582system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1583system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1584system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) 1586system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1587system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1588system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1589system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) 1590system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1591system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) 1592system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1593system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) 1594system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1595system.iocache.tags.replacements 41695 # number of replacements 1596system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use 1597system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1598system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1599system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1600system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. 1601system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor 1602system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy 1603system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy 1604system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1605system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1606system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1607system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1608system.iocache.tags.data_accesses 375543 # Number of data accesses 1609system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1610system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1611system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1612system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses	1509system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1510system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1511system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1512system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1513system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1514system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1515system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1516system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1517system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1518system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1519system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1520system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1521system.iobus.trans_dist::ReadReq 7368 # Transaction distribution 1522system.iobus.trans_dist::ReadResp 7368 # Transaction distribution 1523system.iobus.trans_dist::WriteReq 54647 # Transaction distribution 1524system.iobus.trans_dist::WriteResp 54647 # Transaction distribution 1525system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11984 # Packet count per connected master and slave (bytes) 1526system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) 1527system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count_system.bridge.master::total 40576 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1536system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1537system.iobus.pkt_count::total 124030 # Packet count per connected master and slave (bytes) 1538system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47936 # Cumulative packet size per connected master and slave (bytes) 1539system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) 1540system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1541system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1542system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1543system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1544system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) 1545system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1546system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1547system.iobus.pkt_size_system.bridge.master::total 74130 # Cumulative packet size per connected master and slave (bytes) 1548system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1549system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1550system.iobus.pkt_size::total 2735754 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.reqLayer0.occupancy 12444500 # Layer occupancy (ticks) 1552system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1553system.iobus.reqLayer1.occupancy 814000 # Layer occupancy (ticks) 1554system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1555system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1556system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1557system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1558system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1559system.iobus.reqLayer22.occupancy 176000 # Layer occupancy (ticks) 1560system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1561system.iobus.reqLayer23.occupancy 14015000 # Layer occupancy (ticks) 1562system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1563system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) 1564system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1565system.iobus.reqLayer25.occupancy 6047501 # Layer occupancy (ticks) 1566system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1567system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) 1568system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1569system.iobus.reqLayer27.occupancy 215709165 # Layer occupancy (ticks) 1570system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1571system.iobus.respLayer0.occupancy 27481000 # Layer occupancy (ticks) 1572system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1573system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) 1574system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1575system.iocache.tags.replacements 41695 # number of replacements 1576system.iocache.tags.tagsinuse 0.551900 # Cycle average of tags in use 1577system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1578system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1579system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1580system.iocache.tags.warmup_cycle 1726981964000 # Cycle when the warmup percentage was hit. 1581system.iocache.tags.occ_blocks::tsunami.ide 0.551900 # Average occupied blocks per requestor 1582system.iocache.tags.occ_percent::tsunami.ide 0.034494 # Average percentage of cache occupancy 1583system.iocache.tags.occ_percent::total 0.034494 # Average percentage of cache occupancy 1584system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1585system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1586system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1587system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1588system.iocache.tags.data_accesses 375543 # Number of data accesses 1589system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1590system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1591system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1592system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1613system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 1614system.iocache.demand_misses::total 175 # number of demand (read+write) misses 1615system.iocache.overall_misses::tsunami.ide 175 # number of overall misses 1616system.iocache.overall_misses::total 175 # number of overall misses	1593system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 1594system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 1595system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 1596system.iocache.overall_misses::total 41727 # number of overall misses
1617system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles 1618system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles 1619system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles 1620system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles	1597system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles 1598system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles 1599system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles 1600system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles
1621system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles 1622system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles 1623system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles 1624system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles	1601system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles 1602system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles 1603system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles 1604system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles
1625system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1626system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1627system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1628system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)	1605system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1606system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1607system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1608system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1629system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 1630system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 1631system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 1632system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses	1609system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 1610system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 1611system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 1612system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1633system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1634system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1635system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1636system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1637system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1638system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1639system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1640system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1641system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency 1642system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency 1643system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency 1644system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency	1613system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1614system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1615system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1616system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1617system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1618system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1619system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1620system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1621system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 # average ReadReq miss latency 1622system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency 1623system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency 1624system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency
1645system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency 1646system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency 1647system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency 1648system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency	1625system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency 1626system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency 1627system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency 1628system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency
1649system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1650system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1651system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1652system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1653system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1654system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	1629system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1630system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1631system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1632system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1633system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1634system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1655system.iocache.fast_writes 0 # number of fast writes performed 1656system.iocache.cache_copies 0 # number of cache copies performed
1657system.iocache.writebacks::writebacks 41520 # number of writebacks 1658system.iocache.writebacks::total 41520 # number of writebacks 1659system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1660system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1661system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1662system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses	1635system.iocache.writebacks::writebacks 41520 # number of writebacks 1636system.iocache.writebacks::total 41520 # number of writebacks 1637system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1638system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1639system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1640system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1663system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses 1664system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 1665system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses 1666system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses	1641system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses 1642system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses 1643system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses 1644system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1667system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles 1668system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles 1669system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles 1670system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles	1645system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles 1646system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles 1647system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles 1648system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles
1671system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles 1672system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles 1673system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles 1674system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles	1649system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles 1650system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles 1651system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles 1652system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles
1675system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1676system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1677system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1678system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1679system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1680system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1681system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1682system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1683system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency 1684system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency 1685system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency 1686system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency	1653system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1654system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1655system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1656system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1657system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1658system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1659system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1660system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1661system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average ReadReq mshr miss latency 1662system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency 1663system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency 1664system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency
1687system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency 1688system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency 1689system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency 1690system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency 1691system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate	1665system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency 1666system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency 1667system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency 1668system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency