1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.907980 # Number of seconds simulated
4sim_ticks 1907980084000 # Number of ticks simulated
5final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 144634 # Simulator instruction rate (inst/s)
8host_op_rate 144633 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4918211693 # Simulator tick rate (ticks/s)
10host_mem_usage 381420 # Number of bytes of host memory used
11host_seconds 387.94 # Real time elapsed on the host
12sim_insts 56109384 # Number of instructions simulated
13sim_ops 56109384 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 411682 # Number of read requests accepted
54system.physmem.writeReqs 124264 # Number of write requests accepted
55system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
59system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25908 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25789 # Per bank write bursts
67system.physmem.perBankRdBursts::2 26010 # Per bank write bursts
68system.physmem.perBankRdBursts::3 25614 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25643 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25797 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25922 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25550 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25897 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25701 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25484 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25508 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25696 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25817 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25547 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25690 # Per bank write bursts
81system.physmem.perBankWrBursts::0 7970 # Per bank write bursts
82system.physmem.perBankWrBursts::1 7556 # Per bank write bursts
83system.physmem.perBankWrBursts::2 7711 # Per bank write bursts
84system.physmem.perBankWrBursts::3 7606 # Per bank write bursts
85system.physmem.perBankWrBursts::4 7633 # Per bank write bursts
86system.physmem.perBankWrBursts::5 7951 # Per bank write bursts
87system.physmem.perBankWrBursts::6 7934 # Per bank write bursts
88system.physmem.perBankWrBursts::7 7815 # Per bank write bursts
89system.physmem.perBankWrBursts::8 8060 # Per bank write bursts
90system.physmem.perBankWrBursts::9 8044 # Per bank write bursts
91system.physmem.perBankWrBursts::10 7565 # Per bank write bursts
92system.physmem.perBankWrBursts::11 7446 # Per bank write bursts
93system.physmem.perBankWrBursts::12 7634 # Per bank write bursts
94system.physmem.perBankWrBursts::13 8000 # Per bank write bursts
95system.physmem.perBankWrBursts::14 7754 # Per bank write bursts
96system.physmem.perBankWrBursts::15 7564 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 18 # Number of times write queue was full causing retry
99system.physmem.totGap 1907975777500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 411682 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 124264 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see

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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads
279system.physmem.totQLat 4128600500 # Total ticks spent queuing
280system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM
281system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers
282system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst
283system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
284system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst
285system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s
286system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s
287system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s
288system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s
289system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
290system.physmem.busUtil 0.14 # Data bus utilization in percentage
291system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
292system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
293system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing
294system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing
295system.physmem.readRowHits 370844 # Number of row buffer hits during reads
296system.physmem.writeRowHits 99842 # Number of row buffer hits during writes
297system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads
298system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes
299system.physmem.avgGap 3560014.96 # Average gap between requests
300system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
301system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ)
302system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ)
303system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ)
304system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ)
305system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ)
306system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ)
307system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ)
308system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ)
309system.physmem_0.averagePower 670.267627 # Core power per rank (mW)
310system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states
311system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states
312system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
313system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states
314system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
315system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ)
316system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ)
317system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ)
318system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ)
319system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ)
320system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ)
321system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ)
322system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ)
323system.physmem_1.averagePower 670.276229 # Core power per rank (mW)
324system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states
325system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states
326system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
327system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states
328system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
329system.cpu0.branchPred.lookups 11788808 # Number of BP lookups
330system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted
331system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect
332system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups
333system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits
334system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
335system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage
336system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target.
337system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions.
338system.cpu_clk_domain.clock 500 # Clock period in ticks
339system.cpu0.dtb.fetch_hits 0 # ITB hits
340system.cpu0.dtb.fetch_misses 0 # ITB misses
341system.cpu0.dtb.fetch_acv 0 # ITB acv
342system.cpu0.dtb.fetch_accesses 0 # ITB accesses
343system.cpu0.dtb.read_hits 7021210 # DTB read hits
344system.cpu0.dtb.read_misses 28922 # DTB read misses
345system.cpu0.dtb.read_acv 549 # DTB read access violations
346system.cpu0.dtb.read_accesses 680178 # DTB read accesses
347system.cpu0.dtb.write_hits 4516223 # DTB write hits
348system.cpu0.dtb.write_misses 6969 # DTB write misses
349system.cpu0.dtb.write_acv 383 # DTB write access violations
350system.cpu0.dtb.write_accesses 234540 # DTB write accesses
351system.cpu0.dtb.data_hits 11537433 # DTB hits
352system.cpu0.dtb.data_misses 35891 # DTB misses
353system.cpu0.dtb.data_acv 932 # DTB access violations
354system.cpu0.dtb.data_accesses 914718 # DTB accesses
355system.cpu0.itb.fetch_hits 1192769 # ITB hits
356system.cpu0.itb.fetch_misses 29243 # ITB misses
357system.cpu0.itb.fetch_acv 632 # ITB acv
358system.cpu0.itb.fetch_accesses 1222012 # ITB accesses
359system.cpu0.itb.read_hits 0 # DTB read hits
360system.cpu0.itb.read_misses 0 # DTB read misses
361system.cpu0.itb.read_acv 0 # DTB read access violations
362system.cpu0.itb.read_accesses 0 # DTB read accesses
363system.cpu0.itb.write_hits 0 # DTB write hits
364system.cpu0.itb.write_misses 0 # DTB write misses
365system.cpu0.itb.write_acv 0 # DTB write access violations
366system.cpu0.itb.write_accesses 0 # DTB write accesses
367system.cpu0.itb.data_hits 0 # DTB hits
368system.cpu0.itb.data_misses 0 # DTB misses
369system.cpu0.itb.data_acv 0 # DTB access violations
370system.cpu0.itb.data_accesses 0 # DTB accesses
371system.cpu0.numCycles 94258709 # number of cpu cycles simulated
372system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
373system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
374system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss
375system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed
376system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered
377system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken
378system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked
379system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing
380system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb
381system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
382system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps
383system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions
384system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR
385system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched
386system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed
387system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total)
388system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total)
389system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total)
390system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
391system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total)
392system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total)
393system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total)
394system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total)
395system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total)
396system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total)
397system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total)
398system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total)
399system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total)
400system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
401system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
402system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
403system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total)
404system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle
405system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle
406system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle
407system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked
408system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running
409system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking
410system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing
411system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch
412system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction
413system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode
414system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode
415system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing
416system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle
417system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking
418system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst
419system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running
420system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking
421system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename
422system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full
423system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full
424system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full
425system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full
426system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed
427system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made
428system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups
429system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups
430system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed
431system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing
432system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed
433system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed
434system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer
435system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit.
436system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit.
437system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads.
438system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores.
439system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec)
440system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ
441system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued
442system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued
443system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling
444system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph
445system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed
446system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle
447system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle
448system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle
449system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
450system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle
451system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle
452system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle
453system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle
454system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle
455system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle
456system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle
457system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle
458system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle
459system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
460system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
461system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
462system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle
463system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
464system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available
465system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available
466system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available
467system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available
468system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available
469system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available
470system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available
471system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available
472system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available
473system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available
474system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available
475system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available
476system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available
477system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available
478system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available
479system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available
480system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available
481system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available
482system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available
483system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available
484system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available
485system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available
486system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available
487system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available
488system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available
489system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available
490system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available
491system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available
492system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available
493system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available
494system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available
495system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
496system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
497system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued
498system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued
499system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued
500system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued
501system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued
502system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued
503system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued
504system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued
505system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued
506system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued
507system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued
508system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued
509system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued
510system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued
511system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued
512system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued
513system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued
514system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued
515system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued
516system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued
517system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued
518system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued
519system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued
520system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued
521system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued
522system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued
523system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued
524system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued
525system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued
526system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued
527system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued
528system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued
529system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued
530system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
531system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued
532system.cpu0.iq.rate 0.421350 # Inst issue rate
533system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested
534system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst)
535system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads
536system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes
537system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses
538system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads
539system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes
540system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses
541system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses
542system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses
543system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores
544system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
545system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed
546system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed
547system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations
548system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed
549system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
550system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
551system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled
552system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked
553system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
554system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing
555system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking
556system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking
557system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ
558system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch
559system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions
560system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions
561system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions
562system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall
563system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall
564system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations
565system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly
566system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly
567system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute
568system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions
569system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed
570system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute
571system.cpu0.iew.exec_swp 0 # number of swp insts executed
572system.cpu0.iew.exec_nop 2437996 # number of nop insts executed
573system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed
574system.cpu0.iew.exec_branches 6171265 # Number of branches executed
575system.cpu0.iew.exec_stores 4532745 # Number of stores executed
576system.cpu0.iew.exec_rate 0.417390 # Inst execution rate
577system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit
578system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back
579system.cpu0.iew.wb_producers 20149850 # num instructions producing a value
580system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value
581system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
582system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle
583system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back
584system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
585system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit
586system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards
587system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted
588system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle
589system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle
590system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle
591system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
592system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle
593system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle
594system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle
595system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle
596system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle
597system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle
598system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle
599system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle
600system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle
601system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
602system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
603system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
604system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle
605system.cpu0.commit.committedInsts 38919724 # Number of instructions committed
606system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed
607system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
608system.cpu0.commit.refs 10540382 # Number of memory references committed
609system.cpu0.commit.loads 6202306 # Number of loads committed
610system.cpu0.commit.membars 144405 # Number of memory barriers committed
611system.cpu0.commit.branches 5839773 # Number of branches committed
612system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions.
613system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions.
614system.cpu0.commit.function_calls 471449 # Number of function calls committed.
615system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction
616system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction
617system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction
618system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction
619system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction
620system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction
621system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction
622system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction
623system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction
624system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction
625system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction
626system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction
627system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction
628system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction
629system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction
630system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction
631system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction
632system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction
633system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction
634system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction
635system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction
636system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction
637system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction
638system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction
639system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction
640system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction
641system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction
642system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction
643system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction
644system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction
645system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction
646system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction
647system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction
648system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
649system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction
650system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached
651system.cpu0.rob.rob_reads 132264444 # The number of ROB reads
652system.cpu0.rob.rob_writes 89122078 # The number of ROB writes
653system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself
654system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling
655system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
656system.cpu0.committedInsts 36785489 # Number of Instructions Simulated
657system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated
658system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction
659system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads
660system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle
661system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads
662system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads
663system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes
664system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads
665system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes
666system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads
667system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes
668system.cpu0.dcache.tags.replacements 898491 # number of replacements
669system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use
670system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks.
671system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks.
672system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks.
673system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit.
674system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor
675system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy
676system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy
677system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
678system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id
679system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
680system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
681system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
682system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses
683system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses
684system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits
685system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits
686system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits
687system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits
688system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits
689system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits
690system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits
691system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits
692system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits
693system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits
694system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits
695system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits
696system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses
697system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses
698system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses
699system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses
700system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses
701system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses
702system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses
703system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses
704system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses
705system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses
706system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses
707system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses
708system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles
709system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles
710system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles
711system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles
712system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles
713system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles
714system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles
715system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles
716system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles
717system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles
718system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles
719system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles
720system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses)
721system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses)
722system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses)
723system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses)
724system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses)
725system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses)
726system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses)
727system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses)
728system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses
729system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses
730system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses
731system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses
732system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses
733system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses
734system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses
735system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses
736system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses
737system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses
738system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses
739system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses
740system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses
741system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses
742system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses
743system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses
744system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency
745system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency
746system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency
747system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency
748system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency
749system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency
750system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency
751system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency
752system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency
753system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency
754system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency
755system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency
756system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked
757system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked
758system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked
759system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked
760system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked
761system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked
762system.cpu0.dcache.fast_writes 0 # number of fast writes performed
763system.cpu0.dcache.cache_copies 0 # number of cache copies performed
764system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks
765system.cpu0.dcache.writebacks::total 426068 # number of writebacks
766system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits
767system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits
768system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits
769system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits
770system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits
771system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits
772system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits
773system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits
774system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits
775system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits
776system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses
777system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses
778system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses
779system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses
780system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses
781system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses
782system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses
783system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses
784system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses
785system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses
786system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses
787system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses
788system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable
789system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable
790system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable
791system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable
792system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses
793system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses
794system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles
795system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles
796system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles
797system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles
798system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles
799system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles
800system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles
801system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles
802system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles
803system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles
804system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles
805system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles
806system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles
807system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles
808system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles
809system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles
810system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles
811system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles
812system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses
813system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses
814system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses
815system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses
816system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses
817system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses
818system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses
819system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses
820system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses
821system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses
822system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses
823system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses
824system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency
825system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency
826system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency
827system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency
828system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency
829system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency
830system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency
831system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency
832system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency
833system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency
834system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency
835system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency
836system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency
837system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency
838system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency
839system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency
840system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency
841system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency
842system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
843system.cpu0.icache.tags.replacements 615978 # number of replacements
844system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use
845system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks.
846system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks.
847system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks.
848system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit.
849system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor
850system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy
851system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy
852system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
853system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
854system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
855system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id
856system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
857system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses
858system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses
859system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits
860system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits
861system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits
862system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits
863system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits
864system.cpu0.icache.overall_hits::total 5692804 # number of overall hits
865system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses
866system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses
867system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses
868system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses
869system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses
870system.cpu0.icache.overall_misses::total 650065 # number of overall misses
871system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles
872system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles
873system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles
874system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles
875system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles
876system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles
877system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses)
878system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses)
879system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses
880system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses
881system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses
882system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses
883system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses
884system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses
885system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses
886system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses
887system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses
888system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses
889system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency
890system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency
891system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency
892system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency
893system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency
894system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency
895system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked
896system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
897system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked
898system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
899system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked
900system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
901system.cpu0.icache.fast_writes 0 # number of fast writes performed
902system.cpu0.icache.cache_copies 0 # number of cache copies performed
903system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits
904system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits
905system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits
906system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits
907system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits
908system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits
909system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses
910system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses
911system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses
912system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses
913system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses
914system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses
915system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles
916system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles
917system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles
918system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles
919system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles
920system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles
921system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses
922system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses
923system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses
924system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses
925system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses
926system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses
927system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency
928system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency
929system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency
930system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency
931system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency
932system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency
933system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
934system.cpu1.branchPred.lookups 7710185 # Number of BP lookups
935system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted
936system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect
937system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups
938system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits
939system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
940system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage
941system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target.
942system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions.
943system.cpu1.dtb.fetch_hits 0 # ITB hits
944system.cpu1.dtb.fetch_misses 0 # ITB misses
945system.cpu1.dtb.fetch_acv 0 # ITB acv
946system.cpu1.dtb.fetch_accesses 0 # ITB accesses
947system.cpu1.dtb.read_hits 4026297 # DTB read hits
948system.cpu1.dtb.read_misses 14233 # DTB read misses
949system.cpu1.dtb.read_acv 6 # DTB read access violations
950system.cpu1.dtb.read_accesses 293572 # DTB read accesses
951system.cpu1.dtb.write_hits 2497972 # DTB write hits
952system.cpu1.dtb.write_misses 2408 # DTB write misses
953system.cpu1.dtb.write_acv 37 # DTB write access violations
954system.cpu1.dtb.write_accesses 109195 # DTB write accesses
955system.cpu1.dtb.data_hits 6524269 # DTB hits
956system.cpu1.dtb.data_misses 16641 # DTB misses
957system.cpu1.dtb.data_acv 43 # DTB access violations
958system.cpu1.dtb.data_accesses 402767 # DTB accesses
959system.cpu1.itb.fetch_hits 750930 # ITB hits
960system.cpu1.itb.fetch_misses 5383 # ITB misses
961system.cpu1.itb.fetch_acv 53 # ITB acv
962system.cpu1.itb.fetch_accesses 756313 # ITB accesses
963system.cpu1.itb.read_hits 0 # DTB read hits
964system.cpu1.itb.read_misses 0 # DTB read misses
965system.cpu1.itb.read_acv 0 # DTB read access violations
966system.cpu1.itb.read_accesses 0 # DTB read accesses
967system.cpu1.itb.write_hits 0 # DTB write hits
968system.cpu1.itb.write_misses 0 # DTB write misses
969system.cpu1.itb.write_acv 0 # DTB write access violations
970system.cpu1.itb.write_accesses 0 # DTB write accesses
971system.cpu1.itb.data_hits 0 # DTB hits
972system.cpu1.itb.data_misses 0 # DTB misses
973system.cpu1.itb.data_acv 0 # DTB access violations
974system.cpu1.itb.data_accesses 0 # DTB accesses
975system.cpu1.numCycles 34369930 # number of cpu cycles simulated
976system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
977system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
978system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss
979system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed
980system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered
981system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken
982system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked
983system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing
984system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb
985system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
986system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps
987system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions
988system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR
989system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched
990system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed
991system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total)
992system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total)
993system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total)
994system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
995system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total)
996system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total)
997system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total)
998system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total)
999system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total)
1000system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total)
1001system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total)
1002system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total)
1003system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total)
1004system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1005system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1006system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1007system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total)
1008system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle
1009system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle
1010system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle
1011system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked
1012system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running
1013system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking
1014system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing
1015system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch
1016system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction
1017system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode
1018system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode
1019system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing
1020system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle
1021system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking
1022system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst
1023system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running
1024system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking
1025system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename
1026system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full
1027system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full
1028system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full
1029system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full
1030system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed
1031system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made
1032system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups
1033system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups
1034system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed
1035system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing
1036system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed
1037system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed
1038system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer
1039system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit.
1040system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit.
1041system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads.
1042system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores.
1043system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec)
1044system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ
1045system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued
1046system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued
1047system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling
1048system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph
1049system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed
1050system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle
1051system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle
1052system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle
1053system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1054system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle
1055system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle
1056system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle
1057system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle
1058system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle
1059system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle
1060system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle
1061system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle
1062system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle
1063system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1064system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1065system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1066system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle
1067system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1068system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available
1069system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available
1070system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available
1071system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available
1072system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available
1073system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available
1074system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available
1075system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available
1076system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available
1077system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available
1078system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available
1079system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available
1080system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available
1081system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available
1082system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available
1083system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available
1084system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available
1085system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available
1086system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available
1087system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available
1088system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available
1089system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available
1090system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available
1091system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available
1092system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available
1093system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available
1094system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available
1095system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available
1096system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available
1097system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available
1098system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available
1099system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1100system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1101system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
1102system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued
1103system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued
1104system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued
1105system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued
1106system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued
1107system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued
1108system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued
1109system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued
1110system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued
1111system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued
1112system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued
1113system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued
1114system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued
1115system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued
1116system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued
1117system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued
1118system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued
1119system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued
1120system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued
1121system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued
1122system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued
1123system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued
1124system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued
1125system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued
1126system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued
1127system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued
1128system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued
1129system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued
1130system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued
1131system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued
1132system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued
1133system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued
1134system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1135system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued
1136system.cpu1.iq.rate 0.619251 # Inst issue rate
1137system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested
1138system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst)
1139system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads
1140system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes
1141system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses
1142system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads
1143system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes
1144system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses
1145system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses
1146system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses
1147system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores
1148system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1149system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed
1150system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed
1151system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations
1152system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed
1153system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1154system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1155system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled
1156system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked
1157system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1158system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing
1159system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking
1160system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking
1161system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ
1162system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch
1163system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions
1164system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions
1165system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions
1166system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall
1167system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall
1168system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations
1169system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly
1170system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly
1171system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute
1172system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions
1173system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed
1174system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute
1175system.cpu1.iew.exec_swp 0 # number of swp insts executed
1176system.cpu1.iew.exec_nop 1431237 # number of nop insts executed
1177system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed
1178system.cpu1.iew.exec_branches 3322997 # Number of branches executed
1179system.cpu1.iew.exec_stores 2508398 # Number of stores executed
1180system.cpu1.iew.exec_rate 0.611625 # Inst execution rate
1181system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit
1182system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back
1183system.cpu1.iew.wb_producers 10210202 # num instructions producing a value
1184system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value
1185system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1186system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle
1187system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back
1188system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1189system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit
1190system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards
1191system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted
1192system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle
1193system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle
1194system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle
1195system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1196system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle
1197system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle
1198system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle
1199system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle
1200system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle
1201system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle
1202system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle
1203system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle
1204system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle
1205system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1206system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1207system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1208system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle
1209system.cpu1.commit.committedInsts 20524993 # Number of instructions committed
1210system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed
1211system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1212system.cpu1.commit.refs 5937635 # Number of memory references committed
1213system.cpu1.commit.loads 3555213 # Number of loads committed
1214system.cpu1.commit.membars 92415 # Number of memory barriers committed
1215system.cpu1.commit.branches 3082130 # Number of branches committed
1216system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions.
1217system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions.
1218system.cpu1.commit.function_calls 318960 # Number of function calls committed.
1219system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction
1220system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction
1221system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction
1222system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction
1223system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction
1224system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction
1225system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction
1226system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction
1227system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction
1228system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction
1229system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction
1230system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction
1231system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction
1232system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction
1233system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction
1234system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction
1235system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction
1236system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction
1237system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction
1238system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction
1239system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction
1240system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction
1241system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction
1242system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction
1243system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction
1244system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction
1245system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction
1246system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction
1247system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction
1248system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction
1249system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction
1250system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction
1251system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction
1252system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1253system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction
1254system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached
1255system.cpu1.rob.rob_reads 54833276 # The number of ROB reads
1256system.cpu1.rob.rob_writes 48835744 # The number of ROB writes
1257system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself
1258system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling
1259system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1260system.cpu1.committedInsts 19323895 # Number of Instructions Simulated
1261system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated
1262system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction
1263system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads
1264system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle
1265system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads
1266system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads
1267system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes
1268system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads
1269system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes
1270system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads
1271system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes
1272system.cpu1.dcache.tags.replacements 561653 # number of replacements
1273system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use
1274system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks.
1275system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks.
1276system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks.
1277system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit.
1278system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor
1279system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy
1280system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy
1281system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id
1282system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id
1283system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id
1284system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses
1285system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses
1286system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits
1287system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits
1288system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits
1289system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits
1290system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits
1291system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits
1292system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits
1293system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits
1294system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits
1295system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits
1296system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits
1297system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits
1298system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses
1299system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses
1300system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses
1301system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses
1302system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses
1303system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses
1304system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses
1305system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses
1306system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses
1307system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses
1308system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses
1309system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses
1310system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles
1311system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles
1312system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles
1313system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles
1314system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles
1315system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles
1316system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles
1317system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles
1318system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles
1319system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles
1320system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles
1321system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles
1322system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses)
1323system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses)
1324system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses)
1325system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses)
1326system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses)
1327system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses)
1328system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses)
1329system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses)
1330system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses
1331system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses
1332system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses
1333system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses
1334system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses
1335system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses
1336system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses
1337system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses
1338system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses
1339system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses
1340system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses
1341system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses
1342system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses
1343system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses
1344system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses
1345system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses
1346system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency
1347system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency
1348system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency
1349system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency
1350system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency
1351system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency
1352system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency
1353system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency
1354system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency
1355system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency
1356system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency
1357system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency
1358system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked
1359system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked
1360system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked
1361system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked
1362system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked
1363system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked
1364system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1365system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1366system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks
1367system.cpu1.dcache.writebacks::total 435263 # number of writebacks
1368system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits
1369system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits
1370system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits
1371system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits
1372system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits
1373system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits
1374system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits
1375system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits
1376system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits
1377system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits
1378system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses
1379system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses
1380system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses
1381system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses
1382system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses
1383system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses
1384system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses
1385system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses
1386system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses
1387system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses
1388system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses
1389system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses
1390system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable
1391system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable
1392system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable
1393system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable
1394system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses
1395system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses
1396system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles
1397system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles
1398system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles
1399system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles
1400system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles
1401system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles
1402system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles
1403system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles
1404system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles
1405system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles
1406system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles
1407system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles
1408system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles
1409system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles
1410system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles
1411system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles
1412system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles
1413system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles
1414system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses
1415system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses
1416system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses
1417system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses
1418system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses
1419system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses
1420system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses
1421system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses
1422system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses
1423system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses
1424system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses
1425system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses
1426system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency
1427system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency
1428system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency
1429system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency
1430system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency
1431system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency
1432system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency
1433system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency
1434system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency
1435system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency
1436system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency
1437system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency
1438system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency
1439system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency
1440system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency
1441system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency
1442system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency
1443system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency
1444system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1445system.cpu1.icache.tags.replacements 499853 # number of replacements
1446system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use
1447system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks.
1448system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks.
1449system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks.
1450system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit.
1451system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor
1452system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy
1453system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy
1454system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1455system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
1456system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1457system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses
1458system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses
1459system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits
1460system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits
1461system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits
1462system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits
1463system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits
1464system.cpu1.icache.overall_hits::total 2783351 # number of overall hits
1465system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses
1466system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses
1467system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses
1468system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses
1469system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses
1470system.cpu1.icache.overall_misses::total 520843 # number of overall misses
1471system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles
1472system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles
1473system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles
1474system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles
1475system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles
1476system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles
1477system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses)
1478system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses)
1479system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses
1480system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses
1481system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses
1482system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses
1483system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses
1484system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses
1485system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses
1486system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses
1487system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses
1488system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses
1489system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency
1490system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency
1491system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency
1492system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency
1493system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency
1494system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency
1495system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked
1496system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1497system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked
1498system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1499system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked
1500system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1501system.cpu1.icache.fast_writes 0 # number of fast writes performed
1502system.cpu1.icache.cache_copies 0 # number of cache copies performed
1503system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits
1504system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits
1505system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits
1506system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits
1507system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits
1508system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits
1509system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses
1510system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses
1511system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses
1512system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses
1513system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses
1514system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses
1515system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles
1516system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles
1517system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles
1518system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles
1519system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles
1520system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles
1521system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses
1522system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses
1523system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses
1524system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses
1525system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses
1526system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses
1527system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency
1528system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency
1529system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency
1530system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency
1531system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency
1532system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency
1533system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1534system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1535system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1536system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1537system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1538system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1539system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1540system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1541system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1542system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1543system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1544system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1545system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1546system.iobus.trans_dist::ReadReq 7377 # Transaction distribution
1547system.iobus.trans_dist::ReadResp 7377 # Transaction distribution
1548system.iobus.trans_dist::WriteReq 53912 # Transaction distribution
1549system.iobus.trans_dist::WriteResp 53912 # Transaction distribution
1550system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes)
1551system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1552system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1553system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1554system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1555system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1556system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
1557system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
1558system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1559system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1560system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1561system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1562system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes)
1563system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
1564system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
1565system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes)
1566system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes)
1567system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1568system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1569system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1570system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1571system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1572system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
1573system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
1574system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1575system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1576system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1577system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1578system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes)
1579system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
1580system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
1581system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes)
1582system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks)
1583system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1584system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1585system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1586system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1587system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1588system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1589system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1590system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1591system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1592system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1593system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1594system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
1595system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1596system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks)
1597system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1598system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1599system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1600system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1601system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1602system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1603system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1604system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks)
1605system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1606system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1607system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1608system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks)
1609system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1610system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks)
1611system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1612system.iocache.tags.replacements 41701 # number of replacements
1613system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use
1614system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1615system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks.
1616system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1617system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit.
1618system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor
1619system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy
1620system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy
1621system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1622system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1623system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1624system.iocache.tags.tag_accesses 375543 # Number of tag accesses
1625system.iocache.tags.data_accesses 375543 # Number of data accesses
1626system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
1627system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
1628system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1629system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1630system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
1631system.iocache.demand_misses::total 175 # number of demand (read+write) misses
1632system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
1633system.iocache.overall_misses::total 175 # number of overall misses
1634system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles
1635system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles
1636system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles
1637system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles
1638system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles
1639system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles
1640system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles
1641system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles
1642system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
1643system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
1644system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1645system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1646system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
1647system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
1648system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
1649system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
1650system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1651system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1652system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1653system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1654system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1655system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1656system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1657system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1658system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency
1659system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency
1660system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency
1661system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency
1662system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency
1663system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency
1664system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency
1665system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency
1666system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1667system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1668system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1669system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1670system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1671system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1672system.iocache.fast_writes 0 # number of fast writes performed
1673system.iocache.cache_copies 0 # number of cache copies performed
1674system.iocache.writebacks::writebacks 41526 # number of writebacks
1675system.iocache.writebacks::total 41526 # number of writebacks
1676system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
1677system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
1678system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1679system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1680system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
1681system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
1682system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
1683system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
1684system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles
1685system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles
1686system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles
1687system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles
1688system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles
1689system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles
1690system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles
1691system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles
1692system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1693system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1694system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1695system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1696system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1697system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1698system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1699system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1700system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency
1701system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency
1702system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency
1703system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # average WriteLineReq mshr miss latency
1704system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency
1705system.iocache.demand_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency
1706system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency
1707system.iocache.overall_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency
1708system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1709system.l2c.tags.replacements 346141 # number of replacements
1710system.l2c.tags.tagsinuse 65297.340756 # Cycle average of tags in use
1711system.l2c.tags.total_refs 4025883 # Total number of references to valid blocks.
1712system.l2c.tags.sampled_refs 411324 # Sample count of references to valid blocks.
1713system.l2c.tags.avg_refs 9.787620 # Average number of references to valid blocks.
1714system.l2c.tags.warmup_cycle 7535768000 # Cycle when the warmup percentage was hit.
1715system.l2c.tags.occ_blocks::writebacks 53443.709143 # Average occupied blocks per requestor
1716system.l2c.tags.occ_blocks::cpu0.inst 4213.616295 # Average occupied blocks per requestor
1717system.l2c.tags.occ_blocks::cpu0.data 5688.285915 # Average occupied blocks per requestor
1718system.l2c.tags.occ_blocks::cpu1.inst 1375.831057 # Average occupied blocks per requestor
1719system.l2c.tags.occ_blocks::cpu1.data 575.898345 # Average occupied blocks per requestor
1720system.l2c.tags.occ_percent::writebacks 0.815486 # Average percentage of cache occupancy
1721system.l2c.tags.occ_percent::cpu0.inst 0.064295 # Average percentage of cache occupancy
1722system.l2c.tags.occ_percent::cpu0.data 0.086796 # Average percentage of cache occupancy
1723system.l2c.tags.occ_percent::cpu1.inst 0.020994 # Average percentage of cache occupancy
1724system.l2c.tags.occ_percent::cpu1.data 0.008788 # Average percentage of cache occupancy
1725system.l2c.tags.occ_percent::total 0.996358 # Average percentage of cache occupancy
1726system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id
1727system.l2c.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
1728system.l2c.tags.age_task_id_blocks_1024::1 2225 # Occupied blocks per task id
1729system.l2c.tags.age_task_id_blocks_1024::2 5965 # Occupied blocks per task id
1730system.l2c.tags.age_task_id_blocks_1024::3 6968 # Occupied blocks per task id
1731system.l2c.tags.age_task_id_blocks_1024::4 49797 # Occupied blocks per task id
1732system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id
1733system.l2c.tags.tag_accesses 38794162 # Number of tag accesses
1734system.l2c.tags.data_accesses 38794162 # Number of data accesses
1735system.l2c.Writeback_hits::writebacks 861331 # number of Writeback hits
1736system.l2c.Writeback_hits::total 861331 # number of Writeback hits
1737system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
1738system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits
1739system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits
1740system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
1741system.l2c.SCUpgradeReq_hits::cpu1.data 36 # number of SCUpgradeReq hits
1742system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
1743system.l2c.ReadExReq_hits::cpu0.data 115055 # number of ReadExReq hits
1744system.l2c.ReadExReq_hits::cpu1.data 78240 # number of ReadExReq hits
1745system.l2c.ReadExReq_hits::total 193295 # number of ReadExReq hits
1746system.l2c.ReadCleanReq_hits::cpu0.inst 604919 # number of ReadCleanReq hits
1747system.l2c.ReadCleanReq_hits::cpu1.inst 496677 # number of ReadCleanReq hits
1748system.l2c.ReadCleanReq_hits::total 1101596 # number of ReadCleanReq hits
1749system.l2c.ReadSharedReq_hits::cpu0.data 403562 # number of ReadSharedReq hits
1750system.l2c.ReadSharedReq_hits::cpu1.data 443803 # number of ReadSharedReq hits
1751system.l2c.ReadSharedReq_hits::total 847365 # number of ReadSharedReq hits
1752system.l2c.demand_hits::cpu0.inst 604919 # number of demand (read+write) hits
1753system.l2c.demand_hits::cpu0.data 518617 # number of demand (read+write) hits
1754system.l2c.demand_hits::cpu1.inst 496677 # number of demand (read+write) hits
1755system.l2c.demand_hits::cpu1.data 522043 # number of demand (read+write) hits
1756system.l2c.demand_hits::total 2142256 # number of demand (read+write) hits
1757system.l2c.overall_hits::cpu0.inst 604919 # number of overall hits
1758system.l2c.overall_hits::cpu0.data 518617 # number of overall hits
1759system.l2c.overall_hits::cpu1.inst 496677 # number of overall hits
1760system.l2c.overall_hits::cpu1.data 522043 # number of overall hits
1761system.l2c.overall_hits::total 2142256 # number of overall hits
1762system.l2c.UpgradeReq_misses::cpu0.data 2583 # number of UpgradeReq misses
1763system.l2c.UpgradeReq_misses::cpu1.data 538 # number of UpgradeReq misses
1764system.l2c.UpgradeReq_misses::total 3121 # number of UpgradeReq misses
1765system.l2c.SCUpgradeReq_misses::cpu0.data 69 # number of SCUpgradeReq misses
1766system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
1767system.l2c.SCUpgradeReq_misses::total 169 # number of SCUpgradeReq misses
1768system.l2c.ReadExReq_misses::cpu0.data 105448 # number of ReadExReq misses
1769system.l2c.ReadExReq_misses::cpu1.data 17488 # number of ReadExReq misses
1770system.l2c.ReadExReq_misses::total 122936 # number of ReadExReq misses
1771system.l2c.ReadCleanReq_misses::cpu0.inst 11627 # number of ReadCleanReq misses
1772system.l2c.ReadCleanReq_misses::cpu1.inst 3714 # number of ReadCleanReq misses
1773system.l2c.ReadCleanReq_misses::total 15341 # number of ReadCleanReq misses
1774system.l2c.ReadSharedReq_misses::cpu0.data 272098 # number of ReadSharedReq misses
1775system.l2c.ReadSharedReq_misses::cpu1.data 2179 # number of ReadSharedReq misses
1776system.l2c.ReadSharedReq_misses::total 274277 # number of ReadSharedReq misses
1777system.l2c.demand_misses::cpu0.inst 11627 # number of demand (read+write) misses
1778system.l2c.demand_misses::cpu0.data 377546 # number of demand (read+write) misses
1779system.l2c.demand_misses::cpu1.inst 3714 # number of demand (read+write) misses
1780system.l2c.demand_misses::cpu1.data 19667 # number of demand (read+write) misses
1781system.l2c.demand_misses::total 412554 # number of demand (read+write) misses
1782system.l2c.overall_misses::cpu0.inst 11627 # number of overall misses
1783system.l2c.overall_misses::cpu0.data 377546 # number of overall misses
1784system.l2c.overall_misses::cpu1.inst 3714 # number of overall misses
1785system.l2c.overall_misses::cpu1.data 19667 # number of overall misses
1786system.l2c.overall_misses::total 412554 # number of overall misses
1787system.l2c.UpgradeReq_miss_latency::cpu0.data 1390000 # number of UpgradeReq miss cycles
1788system.l2c.UpgradeReq_miss_latency::cpu1.data 1722000 # number of UpgradeReq miss cycles
1789system.l2c.UpgradeReq_miss_latency::total 3112000 # number of UpgradeReq miss cycles
1790system.l2c.SCUpgradeReq_miss_latency::cpu0.data 341500 # number of SCUpgradeReq miss cycles
1791system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214500 # number of SCUpgradeReq miss cycles
1792system.l2c.SCUpgradeReq_miss_latency::total 556000 # number of SCUpgradeReq miss cycles
1793system.l2c.ReadExReq_miss_latency::cpu0.data 9317536000 # number of ReadExReq miss cycles
1794system.l2c.ReadExReq_miss_latency::cpu1.data 1807849000 # number of ReadExReq miss cycles
1795system.l2c.ReadExReq_miss_latency::total 11125385000 # number of ReadExReq miss cycles
1796system.l2c.ReadCleanReq_miss_latency::cpu0.inst 964295500 # number of ReadCleanReq miss cycles
1797system.l2c.ReadCleanReq_miss_latency::cpu1.inst 315495500 # number of ReadCleanReq miss cycles
1798system.l2c.ReadCleanReq_miss_latency::total 1279791000 # number of ReadCleanReq miss cycles
1799system.l2c.ReadSharedReq_miss_latency::cpu0.data 19840935500 # number of ReadSharedReq miss cycles
1800system.l2c.ReadSharedReq_miss_latency::cpu1.data 172644000 # number of ReadSharedReq miss cycles
1801system.l2c.ReadSharedReq_miss_latency::total 20013579500 # number of ReadSharedReq miss cycles
1802system.l2c.demand_miss_latency::cpu0.inst 964295500 # number of demand (read+write) miss cycles
1803system.l2c.demand_miss_latency::cpu0.data 29158471500 # number of demand (read+write) miss cycles
1804system.l2c.demand_miss_latency::cpu1.inst 315495500 # number of demand (read+write) miss cycles
1805system.l2c.demand_miss_latency::cpu1.data 1980493000 # number of demand (read+write) miss cycles
1806system.l2c.demand_miss_latency::total 32418755500 # number of demand (read+write) miss cycles
1807system.l2c.overall_miss_latency::cpu0.inst 964295500 # number of overall miss cycles
1808system.l2c.overall_miss_latency::cpu0.data 29158471500 # number of overall miss cycles
1809system.l2c.overall_miss_latency::cpu1.inst 315495500 # number of overall miss cycles
1810system.l2c.overall_miss_latency::cpu1.data 1980493000 # number of overall miss cycles
1811system.l2c.overall_miss_latency::total 32418755500 # number of overall miss cycles
1812system.l2c.Writeback_accesses::writebacks 861331 # number of Writeback accesses(hits+misses)
1813system.l2c.Writeback_accesses::total 861331 # number of Writeback accesses(hits+misses)
1814system.l2c.UpgradeReq_accesses::cpu0.data 2724 # number of UpgradeReq accesses(hits+misses)
1815system.l2c.UpgradeReq_accesses::cpu1.data 618 # number of UpgradeReq accesses(hits+misses)
1816system.l2c.UpgradeReq_accesses::total 3342 # number of UpgradeReq accesses(hits+misses)
1817system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses)
1818system.l2c.SCUpgradeReq_accesses::cpu1.data 136 # number of SCUpgradeReq accesses(hits+misses)
1819system.l2c.SCUpgradeReq_accesses::total 243 # number of SCUpgradeReq accesses(hits+misses)
1820system.l2c.ReadExReq_accesses::cpu0.data 220503 # number of ReadExReq accesses(hits+misses)
1821system.l2c.ReadExReq_accesses::cpu1.data 95728 # number of ReadExReq accesses(hits+misses)
1822system.l2c.ReadExReq_accesses::total 316231 # number of ReadExReq accesses(hits+misses)
1823system.l2c.ReadCleanReq_accesses::cpu0.inst 616546 # number of ReadCleanReq accesses(hits+misses)
1824system.l2c.ReadCleanReq_accesses::cpu1.inst 500391 # number of ReadCleanReq accesses(hits+misses)
1825system.l2c.ReadCleanReq_accesses::total 1116937 # number of ReadCleanReq accesses(hits+misses)
1826system.l2c.ReadSharedReq_accesses::cpu0.data 675660 # number of ReadSharedReq accesses(hits+misses)
1827system.l2c.ReadSharedReq_accesses::cpu1.data 445982 # number of ReadSharedReq accesses(hits+misses)
1828system.l2c.ReadSharedReq_accesses::total 1121642 # number of ReadSharedReq accesses(hits+misses)
1829system.l2c.demand_accesses::cpu0.inst 616546 # number of demand (read+write) accesses
1830system.l2c.demand_accesses::cpu0.data 896163 # number of demand (read+write) accesses
1831system.l2c.demand_accesses::cpu1.inst 500391 # number of demand (read+write) accesses
1832system.l2c.demand_accesses::cpu1.data 541710 # number of demand (read+write) accesses
1833system.l2c.demand_accesses::total 2554810 # number of demand (read+write) accesses
1834system.l2c.overall_accesses::cpu0.inst 616546 # number of overall (read+write) accesses
1835system.l2c.overall_accesses::cpu0.data 896163 # number of overall (read+write) accesses
1836system.l2c.overall_accesses::cpu1.inst 500391 # number of overall (read+write) accesses
1837system.l2c.overall_accesses::cpu1.data 541710 # number of overall (read+write) accesses
1838system.l2c.overall_accesses::total 2554810 # number of overall (read+write) accesses
1839system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948238 # miss rate for UpgradeReq accesses
1840system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870550 # miss rate for UpgradeReq accesses
1841system.l2c.UpgradeReq_miss_rate::total 0.933872 # miss rate for UpgradeReq accesses
1842system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.644860 # miss rate for SCUpgradeReq accesses
1843system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735294 # miss rate for SCUpgradeReq accesses
1844system.l2c.SCUpgradeReq_miss_rate::total 0.695473 # miss rate for SCUpgradeReq accesses
1845system.l2c.ReadExReq_miss_rate::cpu0.data 0.478216 # miss rate for ReadExReq accesses
1846system.l2c.ReadExReq_miss_rate::cpu1.data 0.182684 # miss rate for ReadExReq accesses
1847system.l2c.ReadExReq_miss_rate::total 0.388754 # miss rate for ReadExReq accesses
1848system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018858 # miss rate for ReadCleanReq accesses
1849system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007422 # miss rate for ReadCleanReq accesses
1850system.l2c.ReadCleanReq_miss_rate::total 0.013735 # miss rate for ReadCleanReq accesses
1851system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.402714 # miss rate for ReadSharedReq accesses
1852system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.004886 # miss rate for ReadSharedReq accesses
1853system.l2c.ReadSharedReq_miss_rate::total 0.244532 # miss rate for ReadSharedReq accesses
1854system.l2c.demand_miss_rate::cpu0.inst 0.018858 # miss rate for demand accesses
1855system.l2c.demand_miss_rate::cpu0.data 0.421292 # miss rate for demand accesses
1856system.l2c.demand_miss_rate::cpu1.inst 0.007422 # miss rate for demand accesses
1857system.l2c.demand_miss_rate::cpu1.data 0.036305 # miss rate for demand accesses
1858system.l2c.demand_miss_rate::total 0.161481 # miss rate for demand accesses
1859system.l2c.overall_miss_rate::cpu0.inst 0.018858 # miss rate for overall accesses
1860system.l2c.overall_miss_rate::cpu0.data 0.421292 # miss rate for overall accesses
1861system.l2c.overall_miss_rate::cpu1.inst 0.007422 # miss rate for overall accesses
1862system.l2c.overall_miss_rate::cpu1.data 0.036305 # miss rate for overall accesses
1863system.l2c.overall_miss_rate::total 0.161481 # miss rate for overall accesses
1864system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 538.133953 # average UpgradeReq miss latency
1865system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3200.743494 # average UpgradeReq miss latency
1866system.l2c.UpgradeReq_avg_miss_latency::total 997.116309 # average UpgradeReq miss latency
1867system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4949.275362 # average SCUpgradeReq miss latency
1868system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2145 # average SCUpgradeReq miss latency
1869system.l2c.SCUpgradeReq_avg_miss_latency::total 3289.940828 # average SCUpgradeReq miss latency
1870system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88361.429330 # average ReadExReq miss latency
1871system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103376.543916 # average ReadExReq miss latency
1872system.l2c.ReadExReq_avg_miss_latency::total 90497.372617 # average ReadExReq miss latency
1873system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82935.881999 # average ReadCleanReq miss latency
1874system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84947.630587 # average ReadCleanReq miss latency
1875system.l2c.ReadCleanReq_avg_miss_latency::total 83422.918975 # average ReadCleanReq miss latency
1876system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72918.343758 # average ReadSharedReq miss latency
1877system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 79230.839835 # average ReadSharedReq miss latency
1878system.l2c.ReadSharedReq_avg_miss_latency::total 72968.493530 # average ReadSharedReq miss latency
1879system.l2c.demand_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency
1880system.l2c.demand_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency
1881system.l2c.demand_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency
1882system.l2c.demand_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency
1883system.l2c.demand_avg_miss_latency::total 78580.635505 # average overall miss latency
1884system.l2c.overall_avg_miss_latency::cpu0.inst 82935.881999 # average overall miss latency
1885system.l2c.overall_avg_miss_latency::cpu0.data 77231.573106 # average overall miss latency
1886system.l2c.overall_avg_miss_latency::cpu1.inst 84947.630587 # average overall miss latency
1887system.l2c.overall_avg_miss_latency::cpu1.data 100701.327096 # average overall miss latency
1888system.l2c.overall_avg_miss_latency::total 78580.635505 # average overall miss latency
1889system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1890system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1891system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1892system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1893system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1894system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1895system.l2c.fast_writes 0 # number of fast writes performed
1896system.l2c.cache_copies 0 # number of cache copies performed
1897system.l2c.writebacks::writebacks 82738 # number of writebacks
1898system.l2c.writebacks::total 82738 # number of writebacks
1899system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
1900system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits
1901system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
1902system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
1903system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
1904system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
1905system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits
1906system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
1907system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
1908system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
1909system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits
1910system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
1911system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
1912system.l2c.CleanEvict_mshr_misses::writebacks 356 # number of CleanEvict MSHR misses
1913system.l2c.CleanEvict_mshr_misses::total 356 # number of CleanEvict MSHR misses
1914system.l2c.UpgradeReq_mshr_misses::cpu0.data 2583 # number of UpgradeReq MSHR misses
1915system.l2c.UpgradeReq_mshr_misses::cpu1.data 538 # number of UpgradeReq MSHR misses
1916system.l2c.UpgradeReq_mshr_misses::total 3121 # number of UpgradeReq MSHR misses
1917system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 69 # number of SCUpgradeReq MSHR misses
1918system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 100 # number of SCUpgradeReq MSHR misses
1919system.l2c.SCUpgradeReq_mshr_misses::total 169 # number of SCUpgradeReq MSHR misses
1920system.l2c.ReadExReq_mshr_misses::cpu0.data 105448 # number of ReadExReq MSHR misses
1921system.l2c.ReadExReq_mshr_misses::cpu1.data 17488 # number of ReadExReq MSHR misses
1922system.l2c.ReadExReq_mshr_misses::total 122936 # number of ReadExReq MSHR misses
1923system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 11626 # number of ReadCleanReq MSHR misses
1924system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 3697 # number of ReadCleanReq MSHR misses
1925system.l2c.ReadCleanReq_mshr_misses::total 15323 # number of ReadCleanReq MSHR misses
1926system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272098 # number of ReadSharedReq MSHR misses
1927system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2178 # number of ReadSharedReq MSHR misses
1928system.l2c.ReadSharedReq_mshr_misses::total 274276 # number of ReadSharedReq MSHR misses
1929system.l2c.demand_mshr_misses::cpu0.inst 11626 # number of demand (read+write) MSHR misses
1930system.l2c.demand_mshr_misses::cpu0.data 377546 # number of demand (read+write) MSHR misses
1931system.l2c.demand_mshr_misses::cpu1.inst 3697 # number of demand (read+write) MSHR misses
1932system.l2c.demand_mshr_misses::cpu1.data 19666 # number of demand (read+write) MSHR misses
1933system.l2c.demand_mshr_misses::total 412535 # number of demand (read+write) MSHR misses
1934system.l2c.overall_mshr_misses::cpu0.inst 11626 # number of overall MSHR misses
1935system.l2c.overall_mshr_misses::cpu0.data 377546 # number of overall MSHR misses
1936system.l2c.overall_mshr_misses::cpu1.inst 3697 # number of overall MSHR misses
1937system.l2c.overall_mshr_misses::cpu1.data 19666 # number of overall MSHR misses
1938system.l2c.overall_mshr_misses::total 412535 # number of overall MSHR misses
1939system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable
1940system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable
1941system.l2c.ReadReq_mshr_uncacheable::total 7202 # number of ReadReq MSHR uncacheable
1942system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable
1943system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable
1944system.l2c.WriteReq_mshr_uncacheable::total 12360 # number of WriteReq MSHR uncacheable
1945system.l2c.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses
1946system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses
1947system.l2c.overall_mshr_uncacheable_misses::total 19562 # number of overall MSHR uncacheable misses
1948system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 53861495 # number of UpgradeReq MSHR miss cycles
1949system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11082500 # number of UpgradeReq MSHR miss cycles
1950system.l2c.UpgradeReq_mshr_miss_latency::total 64943995 # number of UpgradeReq MSHR miss cycles
1951system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1433500 # number of SCUpgradeReq MSHR miss cycles
1952system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2068000 # number of SCUpgradeReq MSHR miss cycles
1953system.l2c.SCUpgradeReq_mshr_miss_latency::total 3501500 # number of SCUpgradeReq MSHR miss cycles
1954system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8263056000 # number of ReadExReq MSHR miss cycles
1955system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1632969000 # number of ReadExReq MSHR miss cycles
1956system.l2c.ReadExReq_mshr_miss_latency::total 9896025000 # number of ReadExReq MSHR miss cycles
1957system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 847954500 # number of ReadCleanReq MSHR miss cycles
1958system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 277279000 # number of ReadCleanReq MSHR miss cycles
1959system.l2c.ReadCleanReq_mshr_miss_latency::total 1125233500 # number of ReadCleanReq MSHR miss cycles
1960system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17126346500 # number of ReadSharedReq MSHR miss cycles
1961system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 197172000 # number of ReadSharedReq MSHR miss cycles
1962system.l2c.ReadSharedReq_mshr_miss_latency::total 17323518500 # number of ReadSharedReq MSHR miss cycles
1963system.l2c.demand_mshr_miss_latency::cpu0.inst 847954500 # number of demand (read+write) MSHR miss cycles
1964system.l2c.demand_mshr_miss_latency::cpu0.data 25389402500 # number of demand (read+write) MSHR miss cycles
1965system.l2c.demand_mshr_miss_latency::cpu1.inst 277279000 # number of demand (read+write) MSHR miss cycles
1966system.l2c.demand_mshr_miss_latency::cpu1.data 1830141000 # number of demand (read+write) MSHR miss cycles
1967system.l2c.demand_mshr_miss_latency::total 28344777000 # number of demand (read+write) MSHR miss cycles
1968system.l2c.overall_mshr_miss_latency::cpu0.inst 847954500 # number of overall MSHR miss cycles
1969system.l2c.overall_mshr_miss_latency::cpu0.data 25389402500 # number of overall MSHR miss cycles
1970system.l2c.overall_mshr_miss_latency::cpu1.inst 277279000 # number of overall MSHR miss cycles
1971system.l2c.overall_mshr_miss_latency::cpu1.data 1830141000 # number of overall MSHR miss cycles
1972system.l2c.overall_mshr_miss_latency::total 28344777000 # number of overall MSHR miss cycles
1973system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 953578000 # number of ReadReq MSHR uncacheable cycles
1974system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 469134500 # number of ReadReq MSHR uncacheable cycles
1975system.l2c.ReadReq_mshr_uncacheable_latency::total 1422712500 # number of ReadReq MSHR uncacheable cycles
1976system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1615175500 # number of WriteReq MSHR uncacheable cycles
1977system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 905955000 # number of WriteReq MSHR uncacheable cycles
1978system.l2c.WriteReq_mshr_uncacheable_latency::total 2521130500 # number of WriteReq MSHR uncacheable cycles
1979system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2568753500 # number of overall MSHR uncacheable cycles
1980system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1375089500 # number of overall MSHR uncacheable cycles
1981system.l2c.overall_mshr_uncacheable_latency::total 3943843000 # number of overall MSHR uncacheable cycles
1982system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1983system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1984system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948238 # mshr miss rate for UpgradeReq accesses
1985system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870550 # mshr miss rate for UpgradeReq accesses
1986system.l2c.UpgradeReq_mshr_miss_rate::total 0.933872 # mshr miss rate for UpgradeReq accesses
1987system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644860 # mshr miss rate for SCUpgradeReq accesses
1988system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735294 # mshr miss rate for SCUpgradeReq accesses
1989system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.695473 # mshr miss rate for SCUpgradeReq accesses
1990system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.478216 # mshr miss rate for ReadExReq accesses
1991system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.182684 # mshr miss rate for ReadExReq accesses
1992system.l2c.ReadExReq_mshr_miss_rate::total 0.388754 # mshr miss rate for ReadExReq accesses
1993system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for ReadCleanReq accesses
1994system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for ReadCleanReq accesses
1995system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013719 # mshr miss rate for ReadCleanReq accesses
1996system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.402714 # mshr miss rate for ReadSharedReq accesses
1997system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.004884 # mshr miss rate for ReadSharedReq accesses
1998system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244531 # mshr miss rate for ReadSharedReq accesses
1999system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for demand accesses
2000system.l2c.demand_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for demand accesses
2001system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for demand accesses
2002system.l2c.demand_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for demand accesses
2003system.l2c.demand_mshr_miss_rate::total 0.161474 # mshr miss rate for demand accesses
2004system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for overall accesses
2005system.l2c.overall_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for overall accesses
2006system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for overall accesses
2007system.l2c.overall_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for overall accesses
2008system.l2c.overall_mshr_miss_rate::total 0.161474 # mshr miss rate for overall accesses
2009system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587 # average UpgradeReq mshr miss latency
2010system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379 # average UpgradeReq mshr miss latency
2011system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553 # average UpgradeReq mshr miss latency
2012system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319 # average SCUpgradeReq mshr miss latency
2013system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20680 # average SCUpgradeReq mshr miss latency
2014system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911 # average SCUpgradeReq mshr miss latency
2015system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330 # average ReadExReq mshr miss latency
2016system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916 # average ReadExReq mshr miss latency
2017system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617 # average ReadExReq mshr miss latency
2018system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average ReadCleanReq mshr miss latency
2019system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average ReadCleanReq mshr miss latency
2020system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799 # average ReadCleanReq mshr miss latency
2021system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619 # average ReadSharedReq mshr miss latency
2022system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620 # average ReadSharedReq mshr miss latency
2023system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146 # average ReadSharedReq mshr miss latency
2024system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency
2025system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency
2026system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency
2027system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency
2028system.l2c.demand_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency
2029system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency
2030system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency
2031system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency
2032system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency
2033system.l2c.overall_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency
2034system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073 # average ReadReq mshr uncacheable latency
2035system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773 # average ReadReq mshr uncacheable latency
2036system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976 # average ReadReq mshr uncacheable latency
2037system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865 # average WriteReq mshr uncacheable latency
2038system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705 # average WriteReq mshr uncacheable latency
2039system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency
2040system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency
2041system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency
2042system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency
2043system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2044system.membus.trans_dist::ReadReq 7202 # Transaction distribution
2045system.membus.trans_dist::ReadResp 296546 # Transaction distribution
2046system.membus.trans_dist::WriteReq 12360 # Transaction distribution
2047system.membus.trans_dist::WriteResp 12360 # Transaction distribution
2048system.membus.trans_dist::Writeback 124264 # Transaction distribution
2049system.membus.trans_dist::CleanEvict 262871 # Transaction distribution
2050system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution
2051system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution
2052system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution
2053system.membus.trans_dist::ReadExReq 122900 # Transaction distribution
2054system.membus.trans_dist::ReadExResp 122774 # Transaction distribution
2055system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution
2056system.membus.trans_dist::BadAddressError 430 # Transaction distribution
2057system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
2058system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
2059system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes)
2060system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes)
2061system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes)
2062system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes)
2063system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes)
2064system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes)
2065system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes)
2066system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes)
2067system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes)
2068system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes)
2069system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes)
2070system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes)
2071system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes)
2072system.membus.snoops 3872 # Total snoops (count)
2073system.membus.snoop_fanout::samples 867863 # Request fanout histogram
2074system.membus.snoop_fanout::mean 1 # Request fanout histogram
2075system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2076system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2077system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2078system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram
2079system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2080system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2081system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2082system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2083system.membus.snoop_fanout::total 867863 # Request fanout histogram
2084system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks)
2085system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2086system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks)
2087system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2088system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks)
2089system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2090system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks)
2091system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2092system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks)
2093system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2094system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution
2095system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution
2096system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution
2097system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution
2098system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution
2099system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution
2100system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution
2101system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution
2102system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution
2103system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution
2104system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution
2105system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution
2106system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution
2107system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution
2108system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
2109system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes)
2110system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes)
2111system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes)
2112system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes)
2113system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes)
2114system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes)
2115system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes)
2116system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes)
2117system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes)
2118system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes)
2119system.toL2Bus.snoops 464381 # Total snoops (count)
2120system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram
2121system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram
2122system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram
2123system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2124system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2125system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2126system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2127system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram
2128system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram
2129system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2130system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2131system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2132system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram
2133system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks)
2134system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2135system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks)
2136system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2137system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks)
2138system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2139system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks)
2140system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2141system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks)
2142system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2143system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks)
2144system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2145system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2146system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2147system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2148system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2149system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2150system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2151system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 17 unchanged lines hidden (view full) ---

2169system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2170system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2171system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2172system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2173system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2174system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
2175system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2176system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2177system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed
2178system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed
2179system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl
2180system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl
2181system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl
2182system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl
2183system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl
2184system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl
2185system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl
2186system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl
2187system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl
2188system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl
2189system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl
2190system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl
2191system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl
2192system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl
2193system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl
2194system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl
2195system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl
2196system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl
2197system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl
2198system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
2199system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2200system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2201system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl
2202system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl
2203system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed
2204system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed
2205system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed
2206system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed
2207system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed
2208system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed
2209system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed
2210system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

2226system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed
2227system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed
2228system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed
2229system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed
2230system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed
2231system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
2232system.cpu0.kern.syscall::total 225 # number of syscalls executed
2233system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2234system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed
2235system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed
2236system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed
2237system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed
2238system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed
2239system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed
2240system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed
2241system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed
2242system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed
2243system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed
2244system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed
2245system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed
2246system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed
2247system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed
2248system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed
2249system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed
2250system.cpu0.kern.callpal::total 124254 # number of callpals executed
2251system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches
2252system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches
2253system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2254system.cpu0.kern.mode_good::kernel 1341
2255system.cpu0.kern.mode_good::user 1342
2256system.cpu0.kern.mode_good::idle 0
2257system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches
2258system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2259system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2260system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches
2261system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode
2262system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode
2263system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2264system.cpu0.kern.swap_context 2294 # number of times the context was actually changed
2265system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2266system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed
2267system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed
2268system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl
2269system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl
2270system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl
2271system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl
2272system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl
2273system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl
2274system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl
2275system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl
2276system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl
2277system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl
2278system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl
2279system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl
2280system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl
2281system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl
2282system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl
2283system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl
2284system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2285system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2286system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl
2287system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl
2288system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
2289system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
2290system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
2291system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed
2292system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed
2293system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed
2294system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed
2295system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed
2296system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed
2297system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed
2298system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed
2299system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed
2300system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
2301system.cpu1.kern.syscall::total 101 # number of syscalls executed
2302system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2303system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
2304system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
2305system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
2306system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed
2307system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed
2308system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed
2309system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed
2310system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed
2311system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed
2312system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed
2313system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed
2314system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed
2315system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed
2316system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed
2317system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2318system.cpu1.kern.callpal::total 92064 # number of callpals executed
2319system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches
2320system.cpu1.kern.mode_switch::user 395 # number of protection mode switches
2321system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
2322system.cpu1.kern.mode_good::kernel 461
2323system.cpu1.kern.mode_good::user 395
2324system.cpu1.kern.mode_good::idle 66
2325system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches
2326system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2327system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
2328system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches
2329system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode
2330system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode
2331system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode
2332system.cpu1.kern.swap_context 1950 # number of times the context was actually changed
2333
2334---------- End Simulation Statistics ----------