1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.901175 # Number of seconds simulated
4sim_ticks 1901175003500 # Number of ticks simulated
5final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 154934 # Simulator instruction rate (inst/s)
8host_op_rate 154934 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5197600055 # Simulator tick rate (ticks/s)
10host_mem_usage 378544 # Number of bytes of host memory used
11host_seconds 365.78 # Real time elapsed on the host
12sim_insts 56671579 # Number of instructions simulated
13sim_ops 56671579 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 410534 # Number of read requests accepted
54system.physmem.writeReqs 164756 # Number of write requests accepted
55system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue
59system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25742 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25822 # Per bank write bursts
67system.physmem.perBankRdBursts::2 25939 # Per bank write bursts
68system.physmem.perBankRdBursts::3 25643 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25873 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25657 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25709 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25201 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25222 # Per bank write bursts
74system.physmem.perBankRdBursts::9 26115 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25677 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25575 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25800 # Per bank write bursts
78system.physmem.perBankRdBursts::13 26085 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25301 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25075 # Per bank write bursts
81system.physmem.perBankWrBursts::0 10194 # Per bank write bursts
82system.physmem.perBankWrBursts::1 10103 # Per bank write bursts
83system.physmem.perBankWrBursts::2 10030 # Per bank write bursts
84system.physmem.perBankWrBursts::3 9736 # Per bank write bursts
85system.physmem.perBankWrBursts::4 9490 # Per bank write bursts
86system.physmem.perBankWrBursts::5 10167 # Per bank write bursts
87system.physmem.perBankWrBursts::6 10200 # Per bank write bursts
88system.physmem.perBankWrBursts::7 9338 # Per bank write bursts
89system.physmem.perBankWrBursts::8 9741 # Per bank write bursts
90system.physmem.perBankWrBursts::9 10459 # Per bank write bursts
91system.physmem.perBankWrBursts::10 10157 # Per bank write bursts
92system.physmem.perBankWrBursts::11 10688 # Per bank write bursts
93system.physmem.perBankWrBursts::12 11170 # Per bank write bursts
94system.physmem.perBankWrBursts::13 11200 # Per bank write bursts
95system.physmem.perBankWrBursts::14 10147 # Per bank write bursts
96system.physmem.perBankWrBursts::15 9577 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
99system.physmem.totGap 1901170614000 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 410534 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 164756 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see

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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads
268system.physmem.totQLat 3885054500 # Total ticks spent queuing
269system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM
270system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers
271system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst
272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
273system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst
274system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s
275system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s
276system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s
277system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s
278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
279system.physmem.busUtil 0.15 # Data bus utilization in percentage
280system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
281system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
282system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing
283system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing
284system.physmem.readRowHits 370181 # Number of row buffer hits during reads
285system.physmem.writeRowHits 135448 # Number of row buffer hits during writes
286system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads
287system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes
288system.physmem.avgGap 3304716.95 # Average gap between requests
289system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined
290system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ)
291system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ)
292system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ)
293system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ)
294system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ)
295system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ)
296system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ)
297system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ)
298system.physmem_0.averagePower 670.322456 # Core power per rank (mW)
299system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states
300system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states
301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
302system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states
303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
304system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ)
305system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ)
306system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ)
307system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ)
308system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ)
309system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ)
310system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ)
311system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ)
312system.physmem_1.averagePower 670.329412 # Core power per rank (mW)
313system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states
314system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states
315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
316system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states
317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
318system.cpu0.branchPred.lookups 16131633 # Number of BP lookups
319system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted
320system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect
321system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups
322system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits
323system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
324system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage
325system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target.
326system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions.
327system.cpu_clk_domain.clock 500 # Clock period in ticks
328system.cpu0.dtb.fetch_hits 0 # ITB hits
329system.cpu0.dtb.fetch_misses 0 # ITB misses
330system.cpu0.dtb.fetch_acv 0 # ITB acv
331system.cpu0.dtb.fetch_accesses 0 # ITB accesses
332system.cpu0.dtb.read_hits 9231009 # DTB read hits
333system.cpu0.dtb.read_misses 34580 # DTB read misses
334system.cpu0.dtb.read_acv 535 # DTB read access violations
335system.cpu0.dtb.read_accesses 687791 # DTB read accesses
336system.cpu0.dtb.write_hits 5940395 # DTB write hits
337system.cpu0.dtb.write_misses 7538 # DTB write misses
338system.cpu0.dtb.write_acv 382 # DTB write access violations
339system.cpu0.dtb.write_accesses 237219 # DTB write accesses
340system.cpu0.dtb.data_hits 15171404 # DTB hits
341system.cpu0.dtb.data_misses 42118 # DTB misses
342system.cpu0.dtb.data_acv 917 # DTB access violations
343system.cpu0.dtb.data_accesses 925010 # DTB accesses
344system.cpu0.itb.fetch_hits 1435355 # ITB hits
345system.cpu0.itb.fetch_misses 29386 # ITB misses
346system.cpu0.itb.fetch_acv 625 # ITB acv
347system.cpu0.itb.fetch_accesses 1464741 # ITB accesses
348system.cpu0.itb.read_hits 0 # DTB read hits
349system.cpu0.itb.read_misses 0 # DTB read misses
350system.cpu0.itb.read_acv 0 # DTB read access violations
351system.cpu0.itb.read_accesses 0 # DTB read accesses
352system.cpu0.itb.write_hits 0 # DTB write hits
353system.cpu0.itb.write_misses 0 # DTB write misses
354system.cpu0.itb.write_acv 0 # DTB write access violations
355system.cpu0.itb.write_accesses 0 # DTB write accesses
356system.cpu0.itb.data_hits 0 # DTB hits
357system.cpu0.itb.data_misses 0 # DTB misses
358system.cpu0.itb.data_acv 0 # DTB access violations
359system.cpu0.itb.data_accesses 0 # DTB accesses
360system.cpu0.numCycles 112944275 # number of cpu cycles simulated
361system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
362system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
363system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss
364system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed
365system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered
366system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken
367system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked
368system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing
369system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb
370system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
371system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps
372system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions
373system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR
374system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched
375system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed
376system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total)
377system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total)
378system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total)
379system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
380system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total)
381system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total)
382system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total)
383system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total)
384system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total)
385system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total)
386system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total)
387system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total)
388system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total)
389system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
390system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
391system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
392system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total)
393system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle
394system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle
395system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle
396system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked
397system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running
398system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking
399system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing
400system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch
401system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction
402system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode
403system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode
404system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing
405system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle
406system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking
407system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst
408system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running
409system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking
410system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename
411system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full
412system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full
413system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full
414system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full
415system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed
416system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made
417system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups
418system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups
419system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed
420system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing
421system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed
422system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed
423system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer
424system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit.
425system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit.
426system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads.
427system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores.
428system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec)
429system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ
430system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued
431system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued
432system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling
433system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph
434system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed
435system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle
436system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle
437system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle
438system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
439system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle
440system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle
441system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle
442system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle
443system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle
444system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle
445system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle
446system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle
447system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle
448system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
449system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
450system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
451system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle
452system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
453system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available
454system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available
455system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available
456system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available
457system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available
458system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available
459system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available
460system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available
461system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available
462system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available
463system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available
464system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available
465system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available
466system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available
467system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available
468system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available
469system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available
470system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available
471system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available
472system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available
473system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available
474system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available
475system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available
476system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available
477system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available
478system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available
479system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available
480system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available
481system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available
482system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available
483system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available
484system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
485system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
486system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued
487system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued
488system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued
489system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued
490system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued
491system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued
492system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued
493system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued
494system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued
495system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued
496system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued
497system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued
498system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued
499system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued
500system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued
501system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued
502system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued
503system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued
504system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued
505system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued
506system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued
507system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued
508system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued
509system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued
510system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued
511system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued
512system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued
513system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued
514system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued
515system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued
516system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued
517system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued
518system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued
519system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
520system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued
521system.cpu0.iq.rate 0.465714 # Inst issue rate
522system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested
523system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst)
524system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads
525system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes
526system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses
527system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads
528system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes
529system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses
530system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses
531system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses
532system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores
533system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
534system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed
535system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed
536system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations
537system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed
538system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
539system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
540system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled
541system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked
542system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
543system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing
544system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking
545system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking
546system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ
547system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch
548system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions
549system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions
550system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions
551system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall
552system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall
553system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations
554system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly
555system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly
556system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute
557system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions
558system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed
559system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute
560system.cpu0.iew.exec_swp 0 # number of swp insts executed
561system.cpu0.iew.exec_nop 3408998 # number of nop insts executed
562system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed
563system.cpu0.iew.exec_branches 8273174 # Number of branches executed
564system.cpu0.iew.exec_stores 5961648 # Number of stores executed
565system.cpu0.iew.exec_rate 0.461213 # Inst execution rate
566system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit
567system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back
568system.cpu0.iew.wb_producers 26436063 # num instructions producing a value
569system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value
570system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
571system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle
572system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back
573system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
574system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit
575system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards
576system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted
577system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle
578system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle
579system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle
580system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
581system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle
582system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle
583system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle
584system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle
585system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle
586system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle
587system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle
588system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle
589system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle
590system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
591system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
592system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
593system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle
594system.cpu0.commit.committedInsts 51697359 # Number of instructions committed
595system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed
596system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
597system.cpu0.commit.refs 13959169 # Number of memory references committed
598system.cpu0.commit.loads 8256071 # Number of loads committed
599system.cpu0.commit.membars 200989 # Number of memory barriers committed
600system.cpu0.commit.branches 7816314 # Number of branches committed
601system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions.
602system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions.
603system.cpu0.commit.function_calls 663768 # Number of function calls committed.
604system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction
605system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction
606system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction
607system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction
608system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction
609system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction
610system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction
611system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction
612system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction
613system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction
614system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction
615system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction
616system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction
617system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction
618system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction
619system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction
620system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction
621system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction
622system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction
623system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction
624system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction
625system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction
626system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction
627system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction
628system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction
629system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction
630system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction
631system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction
632system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction
633system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction
634system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction
635system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction
636system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction
637system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
638system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction
639system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached
640system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
641system.cpu0.rob.rob_reads 163161097 # The number of ROB reads
642system.cpu0.rob.rob_writes 118660594 # The number of ROB writes
643system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself
644system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling
645system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
646system.cpu0.committedInsts 48729536 # Number of Instructions Simulated
647system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated
648system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction
649system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads
650system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle
651system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads
652system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads
653system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes
654system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads
655system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes
656system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads
657system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes
658system.cpu0.dcache.tags.replacements 1291740 # number of replacements
659system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use
660system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks.
661system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks.
662system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks.
663system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit.
664system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor
665system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy
666system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy
667system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
668system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
669system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
670system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
671system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
672system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses
673system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses
674system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits
675system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits
676system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits
677system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits
678system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits
679system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits
680system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits
681system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits
682system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits
683system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits
684system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits
685system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits
686system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses
687system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses
688system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses
689system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses
690system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses
691system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses
692system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses
693system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses
694system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses
695system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses
696system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses
697system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses
698system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles
699system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles
700system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles
701system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles
702system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles
703system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles
704system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles
705system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles
706system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles
707system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles
708system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles
709system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles
710system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses)
711system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses)
712system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses)
713system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses)
714system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses)
715system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses)
716system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses)
717system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses)
718system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses
719system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses
720system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses
721system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses
722system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses
723system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses
724system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses
725system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses
726system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses
727system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses
728system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses
729system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses
730system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses
731system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses
732system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses
733system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses
734system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency
735system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency
736system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency
737system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency
738system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency
739system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency
740system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency
741system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency
742system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency
743system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency
744system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency
745system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency
746system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked
747system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked
748system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked
749system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked
750system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked
751system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked
752system.cpu0.dcache.fast_writes 0 # number of fast writes performed
753system.cpu0.dcache.cache_copies 0 # number of cache copies performed
754system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks
755system.cpu0.dcache.writebacks::total 762456 # number of writebacks
756system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits
757system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits
758system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits
759system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits
760system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits
761system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits
762system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits
763system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits
764system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits
765system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits
766system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses
767system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses
768system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses
769system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses
770system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses
771system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses
772system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses
773system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses
774system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses
775system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses
776system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses
777system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses
778system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles
779system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles
780system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles
781system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles
782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles
783system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles
784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles
785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles
786system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles
787system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles
788system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles
789system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles
790system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles
791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles
792system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles
793system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles
794system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles
795system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles
796system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses
797system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses
798system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses
799system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses
800system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses
801system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses
802system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses
803system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses
804system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses
805system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses
806system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses
807system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses
808system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency
809system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency
810system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency
811system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency
812system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency
813system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency
814system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency
815system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency
816system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency
817system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency
818system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency
819system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency
820system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
821system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
822system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
823system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
824system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
825system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
826system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
827system.cpu0.icache.tags.replacements 914535 # number of replacements
828system.cpu0.icache.tags.tagsinuse 509.589702 # Cycle average of tags in use
829system.cpu0.icache.tags.total_refs 7236389 # Total number of references to valid blocks.
830system.cpu0.icache.tags.sampled_refs 915045 # Sample count of references to valid blocks.
831system.cpu0.icache.tags.avg_refs 7.908233 # Average number of references to valid blocks.
832system.cpu0.icache.tags.warmup_cycle 26485919250 # Cycle when the warmup percentage was hit.
833system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.589702 # Average occupied blocks per requestor
834system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995292 # Average percentage of cache occupancy
835system.cpu0.icache.tags.occ_percent::total 0.995292 # Average percentage of cache occupancy
836system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
837system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
838system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
839system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id
840system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
841system.cpu0.icache.tags.tag_accesses 9110810 # Number of tag accesses
842system.cpu0.icache.tags.data_accesses 9110810 # Number of data accesses
843system.cpu0.icache.ReadReq_hits::cpu0.inst 7236389 # number of ReadReq hits
844system.cpu0.icache.ReadReq_hits::total 7236389 # number of ReadReq hits
845system.cpu0.icache.demand_hits::cpu0.inst 7236389 # number of demand (read+write) hits
846system.cpu0.icache.demand_hits::total 7236389 # number of demand (read+write) hits
847system.cpu0.icache.overall_hits::cpu0.inst 7236389 # number of overall hits
848system.cpu0.icache.overall_hits::total 7236389 # number of overall hits
849system.cpu0.icache.ReadReq_misses::cpu0.inst 959193 # number of ReadReq misses
850system.cpu0.icache.ReadReq_misses::total 959193 # number of ReadReq misses
851system.cpu0.icache.demand_misses::cpu0.inst 959193 # number of demand (read+write) misses
852system.cpu0.icache.demand_misses::total 959193 # number of demand (read+write) misses
853system.cpu0.icache.overall_misses::cpu0.inst 959193 # number of overall misses
854system.cpu0.icache.overall_misses::total 959193 # number of overall misses
855system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13598697683 # number of ReadReq miss cycles
856system.cpu0.icache.ReadReq_miss_latency::total 13598697683 # number of ReadReq miss cycles
857system.cpu0.icache.demand_miss_latency::cpu0.inst 13598697683 # number of demand (read+write) miss cycles
858system.cpu0.icache.demand_miss_latency::total 13598697683 # number of demand (read+write) miss cycles
859system.cpu0.icache.overall_miss_latency::cpu0.inst 13598697683 # number of overall miss cycles
860system.cpu0.icache.overall_miss_latency::total 13598697683 # number of overall miss cycles
861system.cpu0.icache.ReadReq_accesses::cpu0.inst 8195582 # number of ReadReq accesses(hits+misses)
862system.cpu0.icache.ReadReq_accesses::total 8195582 # number of ReadReq accesses(hits+misses)
863system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses
864system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses
865system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses
866system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses
867system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses
868system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses
869system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses
870system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses
871system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses
872system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses
873system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency
874system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency
875system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency
876system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency
877system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency
878system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency
879system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked
880system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
881system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked
882system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
883system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.177665 # average number of cycles each access was blocked
884system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
885system.cpu0.icache.fast_writes 0 # number of fast writes performed
886system.cpu0.icache.cache_copies 0 # number of cache copies performed
887system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits
888system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits
889system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits
890system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits
891system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits
892system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits
893system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses
894system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses
895system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses
896system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses
897system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses
898system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses
899system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles
900system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles
901system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles
902system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles
903system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles
904system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles
905system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses
906system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses
907system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses
908system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses
909system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses
910system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses
911system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency
912system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency
913system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency
914system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency
915system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency
916system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency
917system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
918system.cpu1.branchPred.lookups 3410499 # Number of BP lookups
919system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted
920system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect
921system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups
922system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits
923system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
924system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage
925system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target.
926system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions.
927system.cpu1.dtb.fetch_hits 0 # ITB hits
928system.cpu1.dtb.fetch_misses 0 # ITB misses
929system.cpu1.dtb.fetch_acv 0 # ITB acv
930system.cpu1.dtb.fetch_accesses 0 # ITB accesses
931system.cpu1.dtb.read_hits 1800297 # DTB read hits
932system.cpu1.dtb.read_misses 9623 # DTB read misses
933system.cpu1.dtb.read_acv 4 # DTB read access violations
934system.cpu1.dtb.read_accesses 290908 # DTB read accesses
935system.cpu1.dtb.write_hits 1120103 # DTB write hits
936system.cpu1.dtb.write_misses 2035 # DTB write misses
937system.cpu1.dtb.write_acv 37 # DTB write access violations
938system.cpu1.dtb.write_accesses 109629 # DTB write accesses
939system.cpu1.dtb.data_hits 2920400 # DTB hits
940system.cpu1.dtb.data_misses 11658 # DTB misses
941system.cpu1.dtb.data_acv 41 # DTB access violations
942system.cpu1.dtb.data_accesses 400537 # DTB accesses
943system.cpu1.itb.fetch_hits 513208 # ITB hits
944system.cpu1.itb.fetch_misses 5417 # ITB misses
945system.cpu1.itb.fetch_acv 59 # ITB acv
946system.cpu1.itb.fetch_accesses 518625 # ITB accesses
947system.cpu1.itb.read_hits 0 # DTB read hits
948system.cpu1.itb.read_misses 0 # DTB read misses
949system.cpu1.itb.read_acv 0 # DTB read access violations
950system.cpu1.itb.read_accesses 0 # DTB read accesses
951system.cpu1.itb.write_hits 0 # DTB write hits
952system.cpu1.itb.write_misses 0 # DTB write misses
953system.cpu1.itb.write_acv 0 # DTB write access violations
954system.cpu1.itb.write_accesses 0 # DTB write accesses
955system.cpu1.itb.data_hits 0 # DTB hits
956system.cpu1.itb.data_misses 0 # DTB misses
957system.cpu1.itb.data_acv 0 # DTB access violations
958system.cpu1.itb.data_accesses 0 # DTB accesses
959system.cpu1.numCycles 13834996 # number of cpu cycles simulated
960system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
961system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
962system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss
963system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed
964system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered
965system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken
966system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked
967system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing
968system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
969system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps
970system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions
971system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR
972system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched
973system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed
974system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total)
975system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total)
976system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total)
977system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
978system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total)
979system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total)
980system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total)
981system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total)
982system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total)
983system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total)
984system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total)
985system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total)
986system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total)
987system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
988system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
989system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
990system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total)
991system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle
992system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle
993system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle
994system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked
995system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running
996system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking
997system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing
998system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch
999system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction
1000system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode
1001system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode
1002system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing
1003system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle
1004system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking
1005system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst
1006system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running
1007system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking
1008system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename
1009system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full
1010system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full
1011system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full
1012system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full
1013system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed
1014system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made
1015system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups
1016system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups
1017system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed
1018system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing
1019system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed
1020system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed
1021system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer
1022system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit.
1023system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit.
1024system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads.
1025system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores.
1026system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec)
1027system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ
1028system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued
1029system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued
1030system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling
1031system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph
1032system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed
1033system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle
1034system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle
1035system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle
1036system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1037system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle
1038system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle
1039system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle
1040system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle
1041system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle
1042system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle
1043system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle
1044system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle
1045system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle
1046system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1047system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1048system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1049system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle
1050system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1051system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available
1052system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available
1053system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available
1054system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available
1055system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available
1056system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available
1057system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available
1058system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available
1059system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available
1060system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available
1061system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available
1062system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available
1063system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available
1064system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available
1065system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available
1066system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available
1067system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available
1068system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available
1069system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available
1070system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available
1071system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available
1072system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available
1073system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available
1074system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available
1075system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available
1076system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available
1077system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available
1078system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available
1079system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available
1080system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available
1081system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available
1082system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1083system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1084system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
1085system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued
1086system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued
1087system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued
1088system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued
1089system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued
1090system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued
1091system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued
1092system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued
1093system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
1094system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
1095system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
1096system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
1097system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
1098system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
1099system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
1100system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
1101system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
1102system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
1103system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
1104system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
1105system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
1106system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
1107system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
1108system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
1109system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
1110system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued
1111system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
1112system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
1113system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
1114system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued
1115system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued
1116system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued
1117system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1118system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued
1119system.cpu1.iq.rate 0.630763 # Inst issue rate
1120system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested
1121system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst)
1122system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads
1123system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes
1124system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses
1125system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads
1126system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes
1127system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses
1128system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses
1129system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses
1130system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores
1131system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1132system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed
1133system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed
1134system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations
1135system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed
1136system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1137system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1138system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled
1139system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked
1140system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1141system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing
1142system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking
1143system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking
1144system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ
1145system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch
1146system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions
1147system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions
1148system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions
1149system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall
1150system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall
1151system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations
1152system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly
1153system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly
1154system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute
1155system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions
1156system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed
1157system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute
1158system.cpu1.iew.exec_swp 0 # number of swp insts executed
1159system.cpu1.iew.exec_nop 494140 # number of nop insts executed
1160system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed
1161system.cpu1.iew.exec_branches 1279494 # Number of branches executed
1162system.cpu1.iew.exec_stores 1127581 # Number of stores executed
1163system.cpu1.iew.exec_rate 0.622051 # Inst execution rate
1164system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit
1165system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back
1166system.cpu1.iew.wb_producers 4051784 # num instructions producing a value
1167system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value
1168system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1169system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle
1170system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back
1171system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1172system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit
1173system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards
1174system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted
1175system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle
1176system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle
1177system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle
1178system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1179system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle
1180system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle
1181system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle
1182system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle
1183system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle
1184system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle
1185system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle
1186system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle
1187system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle
1188system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1189system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1190system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1191system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle
1192system.cpu1.commit.committedInsts 8342954 # Number of instructions committed
1193system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed
1194system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1195system.cpu1.commit.refs 2660112 # Number of memory references committed
1196system.cpu1.commit.loads 1593766 # Number of loads committed
1197system.cpu1.commit.membars 39768 # Number of memory barriers committed
1198system.cpu1.commit.branches 1189273 # Number of branches committed
1199system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions.
1200system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions.
1201system.cpu1.commit.function_calls 132492 # Number of function calls committed.
1202system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction
1203system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction
1204system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction
1205system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction
1206system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction
1207system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction
1208system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction
1209system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction
1210system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction
1211system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction
1212system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction
1213system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction
1214system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction
1215system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction
1216system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction
1217system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction
1218system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction
1219system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction
1220system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction
1221system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction
1222system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction
1223system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction
1224system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction
1225system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction
1226system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction
1227system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction
1228system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction
1229system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction
1230system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction
1231system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction
1232system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction
1233system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction
1234system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction
1235system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1236system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction
1237system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached
1238system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1239system.cpu1.rob.rob_reads 22401053 # The number of ROB reads
1240system.cpu1.rob.rob_writes 19972727 # The number of ROB writes
1241system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself
1242system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling
1243system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1244system.cpu1.committedInsts 7942043 # Number of Instructions Simulated
1245system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated
1246system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction
1247system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads
1248system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle
1249system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads
1250system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads
1251system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes
1252system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads
1253system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes
1254system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads
1255system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes
1256system.cpu1.dcache.tags.replacements 93396 # number of replacements
1257system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use
1258system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks.
1259system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks.
1260system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks.
1261system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit.
1262system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor
1263system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy
1264system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy
1265system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id
1266system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id
1267system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id
1268system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses
1269system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses
1270system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits
1271system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits
1272system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits
1273system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits
1274system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits
1275system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits
1276system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits
1277system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits
1278system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits
1279system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits
1280system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits
1281system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits
1282system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses
1283system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses
1284system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses
1285system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses
1286system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses
1287system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses
1288system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses
1289system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses
1290system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses
1291system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses
1292system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses
1293system.cpu1.dcache.overall_misses::total 362184 # number of overall misses
1294system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles
1295system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles
1296system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles
1297system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles
1298system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles
1299system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles
1300system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles
1301system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles
1302system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles
1303system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles
1304system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles
1305system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles
1306system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses)
1307system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses)
1308system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses)
1309system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses)
1310system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses)
1311system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses)
1312system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses)
1313system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses)
1314system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses
1315system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses
1316system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses
1317system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses
1318system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses
1319system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses
1320system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses
1321system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses
1322system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses
1323system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses
1324system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses
1325system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses
1326system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses
1327system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses
1328system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses
1329system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses
1330system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency
1331system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency
1332system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency
1333system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency
1334system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency
1335system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency
1336system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency
1337system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency
1338system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency
1339system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency
1340system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency
1341system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency
1342system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked
1343system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked
1344system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked
1345system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked
1346system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked
1347system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked
1348system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1349system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1350system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks
1351system.cpu1.dcache.writebacks::total 60059 # number of writebacks
1352system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits
1353system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits
1354system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits
1355system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits
1356system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits
1357system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits
1358system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits
1359system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits
1360system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits
1361system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits
1362system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses
1363system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses
1364system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses
1365system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses
1366system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses
1367system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses
1368system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses
1369system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses
1370system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses
1371system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses
1372system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses
1373system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses
1374system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles
1375system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles
1376system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles
1377system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles
1378system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles
1379system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles
1380system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles
1381system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles
1382system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles
1383system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles
1384system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles
1385system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles
1386system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles
1387system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles
1388system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles
1389system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles
1390system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles
1391system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles
1392system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses
1393system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses
1394system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses
1395system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses
1396system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses
1397system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses
1398system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses
1399system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses
1400system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses
1401system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses
1402system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses
1403system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses
1404system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency
1405system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency
1406system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency
1407system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency
1408system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency
1409system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency
1410system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency
1411system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency
1412system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency
1413system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency
1414system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency
1415system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency
1416system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1417system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1418system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1419system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1420system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1421system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1422system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1423system.cpu1.icache.tags.replacements 205003 # number of replacements
1424system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use
1425system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks.
1426system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks.
1427system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks.
1428system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit.
1429system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor
1430system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy
1431system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy
1432system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1433system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id
1434system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1435system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1436system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses
1437system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses
1438system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits
1439system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits
1440system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits
1441system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits
1442system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits
1443system.cpu1.icache.overall_hits::total 1269898 # number of overall hits
1444system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses
1445system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses
1446system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses
1447system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses
1448system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses
1449system.cpu1.icache.overall_misses::total 212310 # number of overall misses
1450system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles
1451system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles
1452system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles
1453system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles
1454system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles
1455system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles
1456system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses)
1457system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses)
1458system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses
1459system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses
1460system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses
1461system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses
1462system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses
1463system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses
1464system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses
1465system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses
1466system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses
1467system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses
1468system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency
1469system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency
1470system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency
1471system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency
1472system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency
1473system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency
1474system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked
1475system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1476system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked
1477system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1478system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked
1479system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1480system.cpu1.icache.fast_writes 0 # number of fast writes performed
1481system.cpu1.icache.cache_copies 0 # number of cache copies performed
1482system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits
1483system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits
1484system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits
1485system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits
1486system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits
1487system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits
1488system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses
1489system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses
1490system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses
1491system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses
1492system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses
1493system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses
1494system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles
1495system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles
1496system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles
1497system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles
1498system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles
1499system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles
1500system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses
1501system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses
1502system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses
1503system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses
1504system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses
1505system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses
1506system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency
1507system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency
1508system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency
1509system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency
1510system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency
1511system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency
1512system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1513system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1514system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1515system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1516system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1517system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1518system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1519system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1520system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1521system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1522system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1523system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1524system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1525system.iobus.trans_dist::ReadReq 7377 # Transaction distribution
1526system.iobus.trans_dist::ReadResp 7377 # Transaction distribution
1527system.iobus.trans_dist::WriteReq 54536 # Transaction distribution
1528system.iobus.trans_dist::WriteResp 12984 # Transaction distribution
1529system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1530system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes)
1531system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1532system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1533system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1534system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1535system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1536system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
1537system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1538system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1539system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1540system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1541system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1542system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes)
1543system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes)
1544system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes)
1545system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes)
1546system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes)
1547system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1548system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1549system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1550system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1551system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1552system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
1553system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1554system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1555system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1556system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1557system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1558system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes)
1559system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes)
1560system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes)
1561system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes)
1562system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks)
1563system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1564system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1565system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1566system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1567system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1568system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1569system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1570system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1571system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1572system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1573system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1574system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
1575system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1576system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1577system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1578system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1579system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1580system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1581system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1582system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1583system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1584system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks)
1585system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1586system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1587system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1588system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks)
1589system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1590system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks)
1591system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1592system.iocache.tags.replacements 41701 # number of replacements
1593system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use
1594system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1595system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks.
1596system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1597system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit.
1598system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor
1599system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy
1600system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy
1601system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1602system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1603system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1604system.iocache.tags.tag_accesses 375597 # Number of tag accesses
1605system.iocache.tags.data_accesses 375597 # Number of data accesses
1606system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses
1607system.iocache.ReadReq_misses::total 181 # number of ReadReq misses
1608system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1609system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1610system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses
1611system.iocache.demand_misses::total 181 # number of demand (read+write) misses
1612system.iocache.overall_misses::tsunami.ide 181 # number of overall misses
1613system.iocache.overall_misses::total 181 # number of overall misses
1614system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles
1615system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles
1616system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles
1617system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles
1618system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles
1619system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles
1620system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles
1621system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles
1622system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses)
1623system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses)
1624system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1625system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1626system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses
1627system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses
1628system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses
1629system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses
1630system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1631system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1632system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1633system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1634system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1635system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1636system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1637system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1638system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency
1639system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency
1640system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency
1641system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency
1642system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency
1643system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency
1644system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency
1645system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency
1646system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked
1647system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1648system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked
1649system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1650system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked
1651system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1652system.iocache.fast_writes 0 # number of fast writes performed
1653system.iocache.cache_copies 0 # number of cache copies performed
1654system.iocache.writebacks::writebacks 41520 # number of writebacks
1655system.iocache.writebacks::total 41520 # number of writebacks
1656system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses
1657system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
1658system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1659system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1660system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses
1661system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses
1662system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses
1663system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses
1664system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles
1665system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles
1666system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles
1667system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles
1668system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles
1669system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles
1670system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles
1671system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles
1672system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1673system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1674system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1675system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1676system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1677system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1678system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1679system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1680system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency
1681system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency
1682system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency
1683system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency
1684system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency
1685system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency
1686system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency
1687system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency
1688system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1689system.l2c.tags.replacements 345072 # number of replacements
1690system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use
1691system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks.
1692system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks.
1693system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks.
1694system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit.
1695system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor
1696system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor
1697system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor
1698system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor
1699system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor
1700system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy
1701system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy
1702system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy
1703system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy
1704system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy
1705system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy
1706system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id
1707system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id
1708system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id
1709system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id
1710system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id
1711system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id
1712system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id
1713system.l2c.tags.tag_accesses 27343076 # Number of tag accesses
1714system.l2c.tags.data_accesses 27343076 # Number of data accesses
1715system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits
1716system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits
1717system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits
1718system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits
1719system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits
1720system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits
1721system.l2c.Writeback_hits::total 822515 # number of Writeback hits
1722system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits
1723system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits
1724system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits
1725system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits
1726system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
1727system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits
1728system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits
1729system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits
1730system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits
1731system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits
1732system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits
1733system.l2c.demand_hits::cpu1.inst 204045 # number of demand (read+write) hits
1734system.l2c.demand_hits::cpu1.data 84090 # number of demand (read+write) hits
1735system.l2c.demand_hits::total 2090069 # number of demand (read+write) hits
1736system.l2c.overall_hits::cpu0.inst 901250 # number of overall hits
1737system.l2c.overall_hits::cpu0.data 900684 # number of overall hits
1738system.l2c.overall_hits::cpu1.inst 204045 # number of overall hits
1739system.l2c.overall_hits::cpu1.data 84090 # number of overall hits
1740system.l2c.overall_hits::total 2090069 # number of overall hits
1741system.l2c.ReadReq_misses::cpu0.inst 13855 # number of ReadReq misses
1742system.l2c.ReadReq_misses::cpu0.data 273150 # number of ReadReq misses
1743system.l2c.ReadReq_misses::cpu1.inst 1501 # number of ReadReq misses
1744system.l2c.ReadReq_misses::cpu1.data 784 # number of ReadReq misses
1745system.l2c.ReadReq_misses::total 289290 # number of ReadReq misses
1746system.l2c.UpgradeReq_misses::cpu0.data 2701 # number of UpgradeReq misses
1747system.l2c.UpgradeReq_misses::cpu1.data 1143 # number of UpgradeReq misses
1748system.l2c.UpgradeReq_misses::total 3844 # number of UpgradeReq misses
1749system.l2c.SCUpgradeReq_misses::cpu0.data 381 # number of SCUpgradeReq misses
1750system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses
1751system.l2c.SCUpgradeReq_misses::total 797 # number of SCUpgradeReq misses
1752system.l2c.ReadExReq_misses::cpu0.data 114840 # number of ReadExReq misses
1753system.l2c.ReadExReq_misses::cpu1.data 7053 # number of ReadExReq misses
1754system.l2c.ReadExReq_misses::total 121893 # number of ReadExReq misses
1755system.l2c.demand_misses::cpu0.inst 13855 # number of demand (read+write) misses
1756system.l2c.demand_misses::cpu0.data 387990 # number of demand (read+write) misses
1757system.l2c.demand_misses::cpu1.inst 1501 # number of demand (read+write) misses
1758system.l2c.demand_misses::cpu1.data 7837 # number of demand (read+write) misses
1759system.l2c.demand_misses::total 411183 # number of demand (read+write) misses
1760system.l2c.overall_misses::cpu0.inst 13855 # number of overall misses
1761system.l2c.overall_misses::cpu0.data 387990 # number of overall misses
1762system.l2c.overall_misses::cpu1.inst 1501 # number of overall misses
1763system.l2c.overall_misses::cpu1.data 7837 # number of overall misses
1764system.l2c.overall_misses::total 411183 # number of overall misses
1765system.l2c.ReadReq_miss_latency::cpu0.inst 1053790500 # number of ReadReq miss cycles
1766system.l2c.ReadReq_miss_latency::cpu0.data 17926629500 # number of ReadReq miss cycles
1767system.l2c.ReadReq_miss_latency::cpu1.inst 116949250 # number of ReadReq miss cycles
1768system.l2c.ReadReq_miss_latency::cpu1.data 69771500 # number of ReadReq miss cycles
1769system.l2c.ReadReq_miss_latency::total 19167140750 # number of ReadReq miss cycles
1770system.l2c.UpgradeReq_miss_latency::cpu0.data 1289954 # number of UpgradeReq miss cycles
1771system.l2c.UpgradeReq_miss_latency::cpu1.data 4510297 # number of UpgradeReq miss cycles
1772system.l2c.UpgradeReq_miss_latency::total 5800251 # number of UpgradeReq miss cycles
1773system.l2c.SCUpgradeReq_miss_latency::cpu0.data 801966 # number of SCUpgradeReq miss cycles
1774system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70497 # number of SCUpgradeReq miss cycles
1775system.l2c.SCUpgradeReq_miss_latency::total 872463 # number of SCUpgradeReq miss cycles
1776system.l2c.ReadExReq_miss_latency::cpu0.data 9554653251 # number of ReadExReq miss cycles
1777system.l2c.ReadExReq_miss_latency::cpu1.data 752768967 # number of ReadExReq miss cycles
1778system.l2c.ReadExReq_miss_latency::total 10307422218 # number of ReadExReq miss cycles
1779system.l2c.demand_miss_latency::cpu0.inst 1053790500 # number of demand (read+write) miss cycles
1780system.l2c.demand_miss_latency::cpu0.data 27481282751 # number of demand (read+write) miss cycles
1781system.l2c.demand_miss_latency::cpu1.inst 116949250 # number of demand (read+write) miss cycles
1782system.l2c.demand_miss_latency::cpu1.data 822540467 # number of demand (read+write) miss cycles
1783system.l2c.demand_miss_latency::total 29474562968 # number of demand (read+write) miss cycles
1784system.l2c.overall_miss_latency::cpu0.inst 1053790500 # number of overall miss cycles
1785system.l2c.overall_miss_latency::cpu0.data 27481282751 # number of overall miss cycles
1786system.l2c.overall_miss_latency::cpu1.inst 116949250 # number of overall miss cycles
1787system.l2c.overall_miss_latency::cpu1.data 822540467 # number of overall miss cycles
1788system.l2c.overall_miss_latency::total 29474562968 # number of overall miss cycles
1789system.l2c.ReadReq_accesses::cpu0.inst 915105 # number of ReadReq accesses(hits+misses)
1790system.l2c.ReadReq_accesses::cpu0.data 1016244 # number of ReadReq accesses(hits+misses)
1791system.l2c.ReadReq_accesses::cpu1.inst 205546 # number of ReadReq accesses(hits+misses)
1792system.l2c.ReadReq_accesses::cpu1.data 63647 # number of ReadReq accesses(hits+misses)
1793system.l2c.ReadReq_accesses::total 2200542 # number of ReadReq accesses(hits+misses)
1794system.l2c.Writeback_accesses::writebacks 822515 # number of Writeback accesses(hits+misses)
1795system.l2c.Writeback_accesses::total 822515 # number of Writeback accesses(hits+misses)
1796system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses)
1797system.l2c.UpgradeReq_accesses::cpu1.data 1379 # number of UpgradeReq accesses(hits+misses)
1798system.l2c.UpgradeReq_accesses::total 4254 # number of UpgradeReq accesses(hits+misses)
1799system.l2c.SCUpgradeReq_accesses::cpu0.data 431 # number of SCUpgradeReq accesses(hits+misses)
1800system.l2c.SCUpgradeReq_accesses::cpu1.data 444 # number of SCUpgradeReq accesses(hits+misses)
1801system.l2c.SCUpgradeReq_accesses::total 875 # number of SCUpgradeReq accesses(hits+misses)
1802system.l2c.ReadExReq_accesses::cpu0.data 272430 # number of ReadExReq accesses(hits+misses)
1803system.l2c.ReadExReq_accesses::cpu1.data 28280 # number of ReadExReq accesses(hits+misses)
1804system.l2c.ReadExReq_accesses::total 300710 # number of ReadExReq accesses(hits+misses)
1805system.l2c.demand_accesses::cpu0.inst 915105 # number of demand (read+write) accesses
1806system.l2c.demand_accesses::cpu0.data 1288674 # number of demand (read+write) accesses
1807system.l2c.demand_accesses::cpu1.inst 205546 # number of demand (read+write) accesses
1808system.l2c.demand_accesses::cpu1.data 91927 # number of demand (read+write) accesses
1809system.l2c.demand_accesses::total 2501252 # number of demand (read+write) accesses
1810system.l2c.overall_accesses::cpu0.inst 915105 # number of overall (read+write) accesses
1811system.l2c.overall_accesses::cpu0.data 1288674 # number of overall (read+write) accesses
1812system.l2c.overall_accesses::cpu1.inst 205546 # number of overall (read+write) accesses
1813system.l2c.overall_accesses::cpu1.data 91927 # number of overall (read+write) accesses
1814system.l2c.overall_accesses::total 2501252 # number of overall (read+write) accesses
1815system.l2c.ReadReq_miss_rate::cpu0.inst 0.015140 # miss rate for ReadReq accesses
1816system.l2c.ReadReq_miss_rate::cpu0.data 0.268784 # miss rate for ReadReq accesses
1817system.l2c.ReadReq_miss_rate::cpu1.inst 0.007303 # miss rate for ReadReq accesses
1818system.l2c.ReadReq_miss_rate::cpu1.data 0.012318 # miss rate for ReadReq accesses
1819system.l2c.ReadReq_miss_rate::total 0.131463 # miss rate for ReadReq accesses
1820system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939478 # miss rate for UpgradeReq accesses
1821system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828861 # miss rate for UpgradeReq accesses
1822system.l2c.UpgradeReq_miss_rate::total 0.903620 # miss rate for UpgradeReq accesses
1823system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.883991 # miss rate for SCUpgradeReq accesses
1824system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.936937 # miss rate for SCUpgradeReq accesses
1825system.l2c.SCUpgradeReq_miss_rate::total 0.910857 # miss rate for SCUpgradeReq accesses
1826system.l2c.ReadExReq_miss_rate::cpu0.data 0.421539 # miss rate for ReadExReq accesses
1827system.l2c.ReadExReq_miss_rate::cpu1.data 0.249399 # miss rate for ReadExReq accesses
1828system.l2c.ReadExReq_miss_rate::total 0.405351 # miss rate for ReadExReq accesses
1829system.l2c.demand_miss_rate::cpu0.inst 0.015140 # miss rate for demand accesses
1830system.l2c.demand_miss_rate::cpu0.data 0.301077 # miss rate for demand accesses
1831system.l2c.demand_miss_rate::cpu1.inst 0.007303 # miss rate for demand accesses
1832system.l2c.demand_miss_rate::cpu1.data 0.085252 # miss rate for demand accesses
1833system.l2c.demand_miss_rate::total 0.164391 # miss rate for demand accesses
1834system.l2c.overall_miss_rate::cpu0.inst 0.015140 # miss rate for overall accesses
1835system.l2c.overall_miss_rate::cpu0.data 0.301077 # miss rate for overall accesses
1836system.l2c.overall_miss_rate::cpu1.inst 0.007303 # miss rate for overall accesses
1837system.l2c.overall_miss_rate::cpu1.data 0.085252 # miss rate for overall accesses
1838system.l2c.overall_miss_rate::total 0.164391 # miss rate for overall accesses
1839system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76058.498737 # average ReadReq miss latency
1840system.l2c.ReadReq_avg_miss_latency::cpu0.data 65629.249497 # average ReadReq miss latency
1841system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77914.223851 # average ReadReq miss latency
1842system.l2c.ReadReq_avg_miss_latency::cpu1.data 88994.260204 # average ReadReq miss latency
1843system.l2c.ReadReq_avg_miss_latency::total 66255.801272 # average ReadReq miss latency
1844system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 477.583858 # average UpgradeReq miss latency
1845system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3946.016623 # average UpgradeReq miss latency
1846system.l2c.UpgradeReq_avg_miss_latency::total 1508.910250 # average UpgradeReq miss latency
1847system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.897638 # average SCUpgradeReq miss latency
1848system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 169.463942 # average SCUpgradeReq miss latency
1849system.l2c.SCUpgradeReq_avg_miss_latency::total 1094.683814 # average SCUpgradeReq miss latency
1850system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83199.697414 # average ReadExReq miss latency
1851system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106730.322841 # average ReadExReq miss latency
1852system.l2c.ReadExReq_avg_miss_latency::total 84561.231720 # average ReadExReq miss latency
1853system.l2c.demand_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency
1854system.l2c.demand_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency
1855system.l2c.demand_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency
1856system.l2c.demand_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency
1857system.l2c.demand_avg_miss_latency::total 71682.348171 # average overall miss latency
1858system.l2c.overall_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency
1859system.l2c.overall_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency
1860system.l2c.overall_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency
1861system.l2c.overall_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency
1862system.l2c.overall_avg_miss_latency::total 71682.348171 # average overall miss latency
1863system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1864system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1865system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1866system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1867system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1868system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1869system.l2c.fast_writes 0 # number of fast writes performed
1870system.l2c.cache_copies 0 # number of cache copies performed
1871system.l2c.writebacks::writebacks 81684 # number of writebacks
1872system.l2c.writebacks::total 81684 # number of writebacks
1873system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits
1874system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
1875system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
1876system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
1877system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits
1878system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
1879system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
1880system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
1881system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits
1882system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
1883system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
1884system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
1885system.l2c.ReadReq_mshr_misses::cpu0.inst 13842 # number of ReadReq MSHR misses
1886system.l2c.ReadReq_mshr_misses::cpu0.data 273149 # number of ReadReq MSHR misses
1887system.l2c.ReadReq_mshr_misses::cpu1.inst 1497 # number of ReadReq MSHR misses
1888system.l2c.ReadReq_mshr_misses::cpu1.data 784 # number of ReadReq MSHR misses
1889system.l2c.ReadReq_mshr_misses::total 289272 # number of ReadReq MSHR misses
1890system.l2c.UpgradeReq_mshr_misses::cpu0.data 2701 # number of UpgradeReq MSHR misses
1891system.l2c.UpgradeReq_mshr_misses::cpu1.data 1143 # number of UpgradeReq MSHR misses
1892system.l2c.UpgradeReq_mshr_misses::total 3844 # number of UpgradeReq MSHR misses
1893system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 381 # number of SCUpgradeReq MSHR misses
1894system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 416 # number of SCUpgradeReq MSHR misses
1895system.l2c.SCUpgradeReq_mshr_misses::total 797 # number of SCUpgradeReq MSHR misses
1896system.l2c.ReadExReq_mshr_misses::cpu0.data 114840 # number of ReadExReq MSHR misses
1897system.l2c.ReadExReq_mshr_misses::cpu1.data 7053 # number of ReadExReq MSHR misses
1898system.l2c.ReadExReq_mshr_misses::total 121893 # number of ReadExReq MSHR misses
1899system.l2c.demand_mshr_misses::cpu0.inst 13842 # number of demand (read+write) MSHR misses
1900system.l2c.demand_mshr_misses::cpu0.data 387989 # number of demand (read+write) MSHR misses
1901system.l2c.demand_mshr_misses::cpu1.inst 1497 # number of demand (read+write) MSHR misses
1902system.l2c.demand_mshr_misses::cpu1.data 7837 # number of demand (read+write) MSHR misses
1903system.l2c.demand_mshr_misses::total 411165 # number of demand (read+write) MSHR misses
1904system.l2c.overall_mshr_misses::cpu0.inst 13842 # number of overall MSHR misses
1905system.l2c.overall_mshr_misses::cpu0.data 387989 # number of overall MSHR misses
1906system.l2c.overall_mshr_misses::cpu1.inst 1497 # number of overall MSHR misses
1907system.l2c.overall_mshr_misses::cpu1.data 7837 # number of overall MSHR misses
1908system.l2c.overall_mshr_misses::total 411165 # number of overall MSHR misses
1909system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 878413500 # number of ReadReq MSHR miss cycles
1910system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14522738500 # number of ReadReq MSHR miss cycles
1911system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 97828500 # number of ReadReq MSHR miss cycles
1912system.l2c.ReadReq_mshr_miss_latency::cpu1.data 60106500 # number of ReadReq MSHR miss cycles
1913system.l2c.ReadReq_mshr_miss_latency::total 15559087000 # number of ReadReq MSHR miss cycles
1914system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27191193 # number of UpgradeReq MSHR miss cycles
1915system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11450632 # number of UpgradeReq MSHR miss cycles
1916system.l2c.UpgradeReq_mshr_miss_latency::total 38641825 # number of UpgradeReq MSHR miss cycles
1917system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3833377 # number of SCUpgradeReq MSHR miss cycles
1918system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4164911 # number of SCUpgradeReq MSHR miss cycles
1919system.l2c.SCUpgradeReq_mshr_miss_latency::total 7998288 # number of SCUpgradeReq MSHR miss cycles
1920system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8153414747 # number of ReadExReq MSHR miss cycles
1921system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 665986031 # number of ReadExReq MSHR miss cycles
1922system.l2c.ReadExReq_mshr_miss_latency::total 8819400778 # number of ReadExReq MSHR miss cycles
1923system.l2c.demand_mshr_miss_latency::cpu0.inst 878413500 # number of demand (read+write) MSHR miss cycles
1924system.l2c.demand_mshr_miss_latency::cpu0.data 22676153247 # number of demand (read+write) MSHR miss cycles
1925system.l2c.demand_mshr_miss_latency::cpu1.inst 97828500 # number of demand (read+write) MSHR miss cycles
1926system.l2c.demand_mshr_miss_latency::cpu1.data 726092531 # number of demand (read+write) MSHR miss cycles
1927system.l2c.demand_mshr_miss_latency::total 24378487778 # number of demand (read+write) MSHR miss cycles
1928system.l2c.overall_mshr_miss_latency::cpu0.inst 878413500 # number of overall MSHR miss cycles
1929system.l2c.overall_mshr_miss_latency::cpu0.data 22676153247 # number of overall MSHR miss cycles
1930system.l2c.overall_mshr_miss_latency::cpu1.inst 97828500 # number of overall MSHR miss cycles
1931system.l2c.overall_mshr_miss_latency::cpu1.data 726092531 # number of overall MSHR miss cycles
1932system.l2c.overall_mshr_miss_latency::total 24378487778 # number of overall MSHR miss cycles
1933system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366462500 # number of ReadReq MSHR uncacheable cycles
1934system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23156500 # number of ReadReq MSHR uncacheable cycles
1935system.l2c.ReadReq_mshr_uncacheable_latency::total 1389619000 # number of ReadReq MSHR uncacheable cycles
1936system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2015759500 # number of WriteReq MSHR uncacheable cycles
1937system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 582978000 # number of WriteReq MSHR uncacheable cycles
1938system.l2c.WriteReq_mshr_uncacheable_latency::total 2598737500 # number of WriteReq MSHR uncacheable cycles
1939system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3382222000 # number of overall MSHR uncacheable cycles
1940system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606134500 # number of overall MSHR uncacheable cycles
1941system.l2c.overall_mshr_uncacheable_latency::total 3988356500 # number of overall MSHR uncacheable cycles
1942system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for ReadReq accesses
1943system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268783 # mshr miss rate for ReadReq accesses
1944system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for ReadReq accesses
1945system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012318 # mshr miss rate for ReadReq accesses
1946system.l2c.ReadReq_mshr_miss_rate::total 0.131455 # mshr miss rate for ReadReq accesses
1947system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939478 # mshr miss rate for UpgradeReq accesses
1948system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828861 # mshr miss rate for UpgradeReq accesses
1949system.l2c.UpgradeReq_mshr_miss_rate::total 0.903620 # mshr miss rate for UpgradeReq accesses
1950system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.883991 # mshr miss rate for SCUpgradeReq accesses
1951system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.936937 # mshr miss rate for SCUpgradeReq accesses
1952system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.910857 # mshr miss rate for SCUpgradeReq accesses
1953system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421539 # mshr miss rate for ReadExReq accesses
1954system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249399 # mshr miss rate for ReadExReq accesses
1955system.l2c.ReadExReq_mshr_miss_rate::total 0.405351 # mshr miss rate for ReadExReq accesses
1956system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for demand accesses
1957system.l2c.demand_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for demand accesses
1958system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for demand accesses
1959system.l2c.demand_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for demand accesses
1960system.l2c.demand_mshr_miss_rate::total 0.164384 # mshr miss rate for demand accesses
1961system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for overall accesses
1962system.l2c.overall_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for overall accesses
1963system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for overall accesses
1964system.l2c.overall_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for overall accesses
1965system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses
1966system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency
1967system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency
1968system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency
1969system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency
1970system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency
1971system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency
1972system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency
1973system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency
1974system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency
1975system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency
1976system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency
1977system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency
1978system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency
1979system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency
1980system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency
1981system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency
1982system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency
1983system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency
1984system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency
1985system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency
1986system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency
1987system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency
1988system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency
1989system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency
1990system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1991system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1992system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1993system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1994system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1995system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1996system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1997system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1998system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1999system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2000system.membus.trans_dist::ReadReq 296649 # Transaction distribution
2001system.membus.trans_dist::ReadResp 296568 # Transaction distribution
2002system.membus.trans_dist::WriteReq 12984 # Transaction distribution
2003system.membus.trans_dist::WriteResp 12984 # Transaction distribution
2004system.membus.trans_dist::Writeback 123204 # Transaction distribution
2005system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
2006system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
2007system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution
2008system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution
2009system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution
2010system.membus.trans_dist::ReadExReq 121989 # Transaction distribution
2011system.membus.trans_dist::ReadExResp 121610 # Transaction distribution
2012system.membus.trans_dist::BadAddressError 81 # Transaction distribution
2013system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes)
2014system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes)
2015system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes)
2016system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes)
2017system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes)
2018system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes)
2019system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes)
2020system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes)
2021system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes)
2022system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes)
2023system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
2024system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
2025system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes)
2026system.membus.snoops 10884 # Total snoops (count)
2027system.membus.snoop_fanout::samples 591178 # Request fanout histogram
2028system.membus.snoop_fanout::mean 1 # Request fanout histogram
2029system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2030system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2031system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2032system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram
2033system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2034system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2035system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2036system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2037system.membus.snoop_fanout::total 591178 # Request fanout histogram
2038system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks)
2039system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2040system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks)
2041system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2042system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks)
2043system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2044system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks)
2045system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
2046system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks)
2047system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2048system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution
2049system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution
2050system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution
2051system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution
2052system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution
2053system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution
2054system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution
2055system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution
2056system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution
2057system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution
2058system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution
2059system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution
2060system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes)
2061system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes)
2062system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes)
2063system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes)
2064system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes)
2065system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes)
2066system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes)
2067system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes)
2068system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes)
2069system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes)
2070system.toL2Bus.snoops 73699 # Total snoops (count)
2071system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram
2072system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram
2073system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram
2074system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2075system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2076system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2077system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2078system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram
2079system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram
2080system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2081system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2082system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2083system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram
2084system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks)
2085system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
2086system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks)
2087system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2088system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks)
2089system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
2090system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks)
2091system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
2092system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks)
2093system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2094system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks)
2095system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2096system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2097system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2098system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2099system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2100system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2101system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2102system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 17 unchanged lines hidden (view full) ---

2120system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2121system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2122system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2123system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2124system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2125system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
2126system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2127system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2128system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed
2129system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed
2130system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl
2131system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl
2132system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl
2133system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl
2134system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl
2135system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl
2136system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl
2137system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
2138system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl
2139system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl
2140system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl
2141system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl
2142system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl
2143system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl
2144system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl
2145system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl
2146system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl
2147system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl
2148system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl
2149system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
2150system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2151system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2152system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl
2153system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl
2154system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed
2155system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed
2156system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed
2157system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed
2158system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed
2159system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed
2160system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed
2161system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed
2162system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed
2163system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed
2164system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed
2165system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed
2166system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed
2167system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed
2168system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed
2169system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed
2170system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed
2171system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed
2172system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed
2173system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed
2174system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed
2175system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed
2176system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed
2177system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed
2178system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed
2179system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed
2180system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed
2181system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed
2182system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed
2183system.cpu0.kern.syscall::total 232 # number of syscalls executed
2184system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2185system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed
2186system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
2187system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
2188system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed
2189system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed
2190system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed
2191system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed
2192system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed
2193system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed
2194system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed
2195system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed
2196system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed
2197system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed
2198system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed
2199system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed
2200system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed
2201system.cpu0.kern.callpal::total 170980 # number of callpals executed
2202system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches
2203system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches
2204system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2205system.cpu0.kern.mode_good::kernel 1354
2206system.cpu0.kern.mode_good::user 1355
2207system.cpu0.kern.mode_good::idle 0
2208system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches
2209system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2210system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2211system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches
2212system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode
2213system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode
2214system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2215system.cpu0.kern.swap_context 3574 # number of times the context was actually changed
2216system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2217system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed
2218system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed
2219system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl
2220system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl
2221system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl
2222system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl
2223system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl
2224system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl
2225system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl
2226system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl
2227system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl
2228system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl
2229system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl
2230system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl
2231system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl
2232system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl
2233system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl
2234system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl
2235system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2236system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2237system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl
2238system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl
2239system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed
2240system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed
2241system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed
2242system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed
2243system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed
2244system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed
2245system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed
2246system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed
2247system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed
2248system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed
2249system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed
2250system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed
2251system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed
2252system.cpu1.kern.syscall::total 94 # number of syscalls executed
2253system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2254system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed
2255system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
2256system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed
2257system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed
2258system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed
2259system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed
2260system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed
2261system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed
2262system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed
2263system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed
2264system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed
2265system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed
2266system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed
2267system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
2268system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2269system.cpu1.kern.callpal::total 46833 # number of callpals executed
2270system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches
2271system.cpu1.kern.mode_switch::user 384 # number of protection mode switches
2272system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches
2273system.cpu1.kern.mode_good::kernel 574
2274system.cpu1.kern.mode_good::user 384
2275system.cpu1.kern.mode_good::idle 190
2276system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches
2277system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2278system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches
2279system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches
2280system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode
2281system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode
2282system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode
2283system.cpu1.kern.swap_context 990 # number of times the context was actually changed
2284
2285---------- End Simulation Statistics ----------