1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.903338 # Number of seconds simulated
4sim_ticks 1903338216000 # Number of ticks simulated
5final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 100362 # Simulator instruction rate (inst/s)
8host_op_rate 100362 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3404824916 # Simulator tick rate (ticks/s)
10host_mem_usage 359096 # Number of bytes of host memory used
11host_seconds 559.01 # Real time elapsed on the host
12sim_insts 56103611 # Number of instructions simulated
13sim_ops 56103611 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory
25system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory
32system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory
33system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 452659 # Number of read requests accepted
52system.physmem.writeReqs 123811 # Number of write requests accepted
53system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue
57system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 28542 # Per bank write bursts
64system.physmem.perBankRdBursts::1 28115 # Per bank write bursts
65system.physmem.perBankRdBursts::2 28449 # Per bank write bursts
66system.physmem.perBankRdBursts::3 28319 # Per bank write bursts
67system.physmem.perBankRdBursts::4 28001 # Per bank write bursts
68system.physmem.perBankRdBursts::5 28388 # Per bank write bursts
69system.physmem.perBankRdBursts::6 28437 # Per bank write bursts
70system.physmem.perBankRdBursts::7 28681 # Per bank write bursts
71system.physmem.perBankRdBursts::8 28670 # Per bank write bursts
72system.physmem.perBankRdBursts::9 28576 # Per bank write bursts
73system.physmem.perBankRdBursts::10 28034 # Per bank write bursts
74system.physmem.perBankRdBursts::11 27899 # Per bank write bursts
75system.physmem.perBankRdBursts::12 27884 # Per bank write bursts
76system.physmem.perBankRdBursts::13 28245 # Per bank write bursts
77system.physmem.perBankRdBursts::14 28268 # Per bank write bursts
78system.physmem.perBankRdBursts::15 28092 # Per bank write bursts
79system.physmem.perBankWrBursts::0 8222 # Per bank write bursts
80system.physmem.perBankWrBursts::1 7571 # Per bank write bursts
81system.physmem.perBankWrBursts::2 7821 # Per bank write bursts
82system.physmem.perBankWrBursts::3 7782 # Per bank write bursts
83system.physmem.perBankWrBursts::4 7428 # Per bank write bursts
84system.physmem.perBankWrBursts::5 7859 # Per bank write bursts
85system.physmem.perBankWrBursts::6 7924 # Per bank write bursts
86system.physmem.perBankWrBursts::7 7992 # Per bank write bursts
87system.physmem.perBankWrBursts::8 7912 # Per bank write bursts
88system.physmem.perBankWrBursts::9 7920 # Per bank write bursts
89system.physmem.perBankWrBursts::10 7418 # Per bank write bursts
90system.physmem.perBankWrBursts::11 7297 # Per bank write bursts
91system.physmem.perBankWrBursts::12 7319 # Per bank write bursts
92system.physmem.perBankWrBursts::13 7829 # Per bank write bursts
93system.physmem.perBankWrBursts::14 7922 # Per bank write bursts
94system.physmem.perBankWrBursts::15 7585 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
97system.physmem.totGap 1903333578000 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 452659 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 123811 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see
176system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation
177system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation
178system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation
179system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation
180system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation
361system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation
362system.physmem.totQLat 8783315250 # Total ticks spent queuing
363system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM
364system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers
365system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks
366system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst
367system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst
368system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
369system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst
370system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s
371system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s
372system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s
373system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s
374system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
375system.physmem.busUtil 0.15 # Data bus utilization in percentage
376system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
377system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
378system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
379system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing
380system.physmem.readRowHits 430734 # Number of row buffer hits during reads
381system.physmem.writeRowHits 98547 # Number of row buffer hits during writes
382system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads
383system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes
384system.physmem.avgGap 3301704.47 # Average gap between requests
385system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined
386system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
387system.membus.throughput 19439855 # Throughput (bytes/s)
388system.membus.trans_dist::ReadReq 296479 # Transaction distribution
389system.membus.trans_dist::ReadResp 296230 # Transaction distribution
390system.membus.trans_dist::WriteReq 12351 # Transaction distribution
391system.membus.trans_dist::WriteResp 12351 # Transaction distribution
392system.membus.trans_dist::Writeback 123811 # Transaction distribution
393system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution
394system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution
395system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution
396system.membus.trans_dist::ReadExReq 164353 # Transaction distribution
397system.membus.trans_dist::ReadExResp 164224 # Transaction distribution
398system.membus.trans_dist::BadAddressError 249 # Transaction distribution
399system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes)
400system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes)
401system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes)
402system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes)
403system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes)
404system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes)
405system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes)
406system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes)
407system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes)
408system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes)
409system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes)
410system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes)
411system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes)
412system.membus.data_through_bus 36962282 # Total data (bytes)
413system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes)
414system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks)
415system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
416system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks)
417system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
418system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks)
419system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
420system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks)
421system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
422system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks)
423system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
424system.l2c.tags.replacements 345713 # number of replacements
425system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use
426system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks.
427system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks.
428system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks.
429system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit.
430system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor
431system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor
432system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor
433system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor
434system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor
435system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy
436system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy
437system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy
438system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy
439system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy
440system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy
441system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits
442system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits
443system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits
444system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits
445system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits
446system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits
447system.l2c.Writeback_hits::total 840492 # number of Writeback hits
448system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
449system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits
450system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits
451system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
452system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits
453system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits
454system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits
455system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits
456system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits
457system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits
458system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits
459system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits
460system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits
461system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits
462system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits
463system.l2c.overall_hits::cpu0.data 716459 # number of overall hits
464system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits
465system.l2c.overall_hits::cpu1.data 293999 # number of overall hits
466system.l2c.overall_hits::total 2078562 # number of overall hits
467system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses
468system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses
469system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses
470system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses
471system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses
472system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses
473system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses
474system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses
475system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses
476system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses
477system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses
478system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses
479system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses
480system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses
481system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses
482system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses
483system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses
484system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses
485system.l2c.demand_misses::total 411955 # number of demand (read+write) misses
486system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses
487system.l2c.overall_misses::cpu0.data 380800 # number of overall misses
488system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses
489system.l2c.overall_misses::cpu1.data 15863 # number of overall misses
490system.l2c.overall_misses::total 411955 # number of overall misses
491system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles
492system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles
493system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles
494system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles
495system.l2c.ReadReq_miss_latency::total 19081681477 # number of ReadReq miss cycles
496system.l2c.UpgradeReq_miss_latency::cpu0.data 842965 # number of UpgradeReq miss cycles
497system.l2c.UpgradeReq_miss_latency::cpu1.data 1256946 # number of UpgradeReq miss cycles
498system.l2c.UpgradeReq_miss_latency::total 2099911 # number of UpgradeReq miss cycles
499system.l2c.SCUpgradeReq_miss_latency::cpu0.data 221993 # number of SCUpgradeReq miss cycles
500system.l2c.SCUpgradeReq_miss_latency::cpu1.data 116495 # number of SCUpgradeReq miss cycles
501system.l2c.SCUpgradeReq_miss_latency::total 338488 # number of SCUpgradeReq miss cycles
502system.l2c.ReadExReq_miss_latency::cpu0.data 8947158383 # number of ReadExReq miss cycles
503system.l2c.ReadExReq_miss_latency::cpu1.data 1452475204 # number of ReadExReq miss cycles
504system.l2c.ReadExReq_miss_latency::total 10399633587 # number of ReadExReq miss cycles
505system.l2c.demand_miss_latency::cpu0.inst 929054999 # number of demand (read+write) miss cycles
506system.l2c.demand_miss_latency::cpu0.data 26640619633 # number of demand (read+write) miss cycles
507system.l2c.demand_miss_latency::cpu1.inst 314236981 # number of demand (read+write) miss cycles
508system.l2c.demand_miss_latency::cpu1.data 1597403451 # number of demand (read+write) miss cycles
509system.l2c.demand_miss_latency::total 29481315064 # number of demand (read+write) miss cycles
510system.l2c.overall_miss_latency::cpu0.inst 929054999 # number of overall miss cycles
511system.l2c.overall_miss_latency::cpu0.data 26640619633 # number of overall miss cycles
512system.l2c.overall_miss_latency::cpu1.inst 314236981 # number of overall miss cycles
513system.l2c.overall_miss_latency::cpu1.data 1597403451 # number of overall miss cycles
514system.l2c.overall_miss_latency::total 29481315064 # number of overall miss cycles
515system.l2c.ReadReq_accesses::cpu0.inst 766133 # number of ReadReq accesses(hits+misses)
516system.l2c.ReadReq_accesses::cpu0.data 844445 # number of ReadReq accesses(hits+misses)
517system.l2c.ReadReq_accesses::cpu1.inst 317263 # number of ReadReq accesses(hits+misses)
518system.l2c.ReadReq_accesses::cpu1.data 251444 # number of ReadReq accesses(hits+misses)
519system.l2c.ReadReq_accesses::total 2179285 # number of ReadReq accesses(hits+misses)
520system.l2c.Writeback_accesses::writebacks 840492 # number of Writeback accesses(hits+misses)
521system.l2c.Writeback_accesses::total 840492 # number of Writeback accesses(hits+misses)
522system.l2c.UpgradeReq_accesses::cpu0.data 2695 # number of UpgradeReq accesses(hits+misses)
523system.l2c.UpgradeReq_accesses::cpu1.data 661 # number of UpgradeReq accesses(hits+misses)
524system.l2c.UpgradeReq_accesses::total 3356 # number of UpgradeReq accesses(hits+misses)
525system.l2c.SCUpgradeReq_accesses::cpu0.data 95 # number of SCUpgradeReq accesses(hits+misses)
526system.l2c.SCUpgradeReq_accesses::cpu1.data 140 # number of SCUpgradeReq accesses(hits+misses)
527system.l2c.SCUpgradeReq_accesses::total 235 # number of SCUpgradeReq accesses(hits+misses)
528system.l2c.ReadExReq_accesses::cpu0.data 252814 # number of ReadExReq accesses(hits+misses)
529system.l2c.ReadExReq_accesses::cpu1.data 58418 # number of ReadExReq accesses(hits+misses)
530system.l2c.ReadExReq_accesses::total 311232 # number of ReadExReq accesses(hits+misses)
531system.l2c.demand_accesses::cpu0.inst 766133 # number of demand (read+write) accesses
532system.l2c.demand_accesses::cpu0.data 1097259 # number of demand (read+write) accesses
533system.l2c.demand_accesses::cpu1.inst 317263 # number of demand (read+write) accesses
534system.l2c.demand_accesses::cpu1.data 309862 # number of demand (read+write) accesses
535system.l2c.demand_accesses::total 2490517 # number of demand (read+write) accesses
536system.l2c.overall_accesses::cpu0.inst 766133 # number of overall (read+write) accesses
537system.l2c.overall_accesses::cpu0.data 1097259 # number of overall (read+write) accesses
538system.l2c.overall_accesses::cpu1.inst 317263 # number of overall (read+write) accesses
539system.l2c.overall_accesses::cpu1.data 309862 # number of overall (read+write) accesses
540system.l2c.overall_accesses::total 2490517 # number of overall (read+write) accesses
541system.l2c.ReadReq_miss_rate::cpu0.inst 0.015123 # miss rate for ReadReq accesses
542system.l2c.ReadReq_miss_rate::cpu0.data 0.322175 # miss rate for ReadReq accesses
543system.l2c.ReadReq_miss_rate::cpu1.inst 0.011681 # miss rate for ReadReq accesses
544system.l2c.ReadReq_miss_rate::cpu1.data 0.007059 # miss rate for ReadReq accesses
545system.l2c.ReadReq_miss_rate::total 0.132670 # miss rate for ReadReq accesses
546system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951763 # miss rate for UpgradeReq accesses
547system.l2c.UpgradeReq_miss_rate::cpu1.data 0.888048 # miss rate for UpgradeReq accesses
548system.l2c.UpgradeReq_miss_rate::total 0.939213 # miss rate for UpgradeReq accesses
549system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.610526 # miss rate for SCUpgradeReq accesses
550system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.764286 # miss rate for SCUpgradeReq accesses
551system.l2c.SCUpgradeReq_miss_rate::total 0.702128 # miss rate for SCUpgradeReq accesses
552system.l2c.ReadExReq_miss_rate::cpu0.data 0.430123 # miss rate for ReadExReq accesses
553system.l2c.ReadExReq_miss_rate::cpu1.data 0.241159 # miss rate for ReadExReq accesses
554system.l2c.ReadExReq_miss_rate::total 0.394654 # miss rate for ReadExReq accesses
555system.l2c.demand_miss_rate::cpu0.inst 0.015123 # miss rate for demand accesses
556system.l2c.demand_miss_rate::cpu0.data 0.347047 # miss rate for demand accesses
557system.l2c.demand_miss_rate::cpu1.inst 0.011681 # miss rate for demand accesses
558system.l2c.demand_miss_rate::cpu1.data 0.051194 # miss rate for demand accesses
559system.l2c.demand_miss_rate::total 0.165409 # miss rate for demand accesses
560system.l2c.overall_miss_rate::cpu0.inst 0.015123 # miss rate for overall accesses
561system.l2c.overall_miss_rate::cpu0.data 0.347047 # miss rate for overall accesses
562system.l2c.overall_miss_rate::cpu1.inst 0.011681 # miss rate for overall accesses
563system.l2c.overall_miss_rate::cpu1.data 0.051194 # miss rate for overall accesses
564system.l2c.overall_miss_rate::total 0.165409 # miss rate for overall accesses
565system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80187.726480 # average ReadReq miss latency
566system.l2c.ReadReq_avg_miss_latency::cpu0.data 65035.382950 # average ReadReq miss latency
567system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84791.414193 # average ReadReq miss latency
568system.l2c.ReadReq_avg_miss_latency::cpu1.data 81649.716620 # average ReadReq miss latency
569system.l2c.ReadReq_avg_miss_latency::total 65997.805376 # average ReadReq miss latency
570system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 328.641326 # average UpgradeReq miss latency
571system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2141.304940 # average UpgradeReq miss latency
572system.l2c.UpgradeReq_avg_miss_latency::total 666.215419 # average UpgradeReq miss latency
573system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3827.465517 # average SCUpgradeReq miss latency
574system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1088.738318 # average SCUpgradeReq miss latency
575system.l2c.SCUpgradeReq_avg_miss_latency::total 2051.442424 # average SCUpgradeReq miss latency
576system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82279.530104 # average ReadExReq miss latency
577system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103100.170642 # average ReadExReq miss latency
578system.l2c.ReadExReq_avg_miss_latency::total 84667.575141 # average ReadExReq miss latency
579system.l2c.demand_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
580system.l2c.demand_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
581system.l2c.demand_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
582system.l2c.demand_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
583system.l2c.demand_avg_miss_latency::total 71564.406462 # average overall miss latency
584system.l2c.overall_avg_miss_latency::cpu0.inst 80187.726480 # average overall miss latency
585system.l2c.overall_avg_miss_latency::cpu0.data 69959.610381 # average overall miss latency
586system.l2c.overall_avg_miss_latency::cpu1.inst 84791.414193 # average overall miss latency
587system.l2c.overall_avg_miss_latency::cpu1.data 100699.959087 # average overall miss latency
588system.l2c.overall_avg_miss_latency::total 71564.406462 # average overall miss latency
589system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
590system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
591system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
592system.l2c.blocked::no_targets 0 # number of cycles access was blocked
593system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
594system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
595system.l2c.fast_writes 0 # number of fast writes performed
596system.l2c.cache_copies 0 # number of cache copies performed
597system.l2c.writebacks::writebacks 82291 # number of writebacks
598system.l2c.writebacks::total 82291 # number of writebacks
599system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits
600system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
601system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits
602system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
603system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
604system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
605system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
606system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
607system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
608system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
609system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
610system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
611system.l2c.ReadReq_mshr_misses::cpu0.inst 11579 # number of ReadReq MSHR misses
612system.l2c.ReadReq_mshr_misses::cpu0.data 272058 # number of ReadReq MSHR misses
613system.l2c.ReadReq_mshr_misses::cpu1.inst 3696 # number of ReadReq MSHR misses
614system.l2c.ReadReq_mshr_misses::cpu1.data 1775 # number of ReadReq MSHR misses
615system.l2c.ReadReq_mshr_misses::total 289108 # number of ReadReq MSHR misses
616system.l2c.UpgradeReq_mshr_misses::cpu0.data 2565 # number of UpgradeReq MSHR misses
617system.l2c.UpgradeReq_mshr_misses::cpu1.data 587 # number of UpgradeReq MSHR misses
618system.l2c.UpgradeReq_mshr_misses::total 3152 # number of UpgradeReq MSHR misses
619system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 58 # number of SCUpgradeReq MSHR misses
620system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 107 # number of SCUpgradeReq MSHR misses
621system.l2c.SCUpgradeReq_mshr_misses::total 165 # number of SCUpgradeReq MSHR misses
622system.l2c.ReadExReq_mshr_misses::cpu0.data 108741 # number of ReadExReq MSHR misses
623system.l2c.ReadExReq_mshr_misses::cpu1.data 14088 # number of ReadExReq MSHR misses
624system.l2c.ReadExReq_mshr_misses::total 122829 # number of ReadExReq MSHR misses
625system.l2c.demand_mshr_misses::cpu0.inst 11579 # number of demand (read+write) MSHR misses
626system.l2c.demand_mshr_misses::cpu0.data 380799 # number of demand (read+write) MSHR misses
627system.l2c.demand_mshr_misses::cpu1.inst 3696 # number of demand (read+write) MSHR misses
628system.l2c.demand_mshr_misses::cpu1.data 15863 # number of demand (read+write) MSHR misses
629system.l2c.demand_mshr_misses::total 411937 # number of demand (read+write) MSHR misses
630system.l2c.overall_mshr_misses::cpu0.inst 11579 # number of overall MSHR misses
631system.l2c.overall_mshr_misses::cpu0.data 380799 # number of overall MSHR misses
632system.l2c.overall_mshr_misses::cpu1.inst 3696 # number of overall MSHR misses
633system.l2c.overall_mshr_misses::cpu1.data 15863 # number of overall MSHR misses
634system.l2c.overall_mshr_misses::total 411937 # number of overall MSHR misses
635system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 782519751 # number of ReadReq MSHR miss cycles
636system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14298950750 # number of ReadReq MSHR miss cycles
637system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 266998019 # number of ReadReq MSHR miss cycles
638system.l2c.ReadReq_mshr_miss_latency::cpu1.data 147305751 # number of ReadReq MSHR miss cycles
639system.l2c.ReadReq_mshr_miss_latency::total 15495774271 # number of ReadReq MSHR miss cycles
640system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25723531 # number of UpgradeReq MSHR miss cycles
641system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5884082 # number of UpgradeReq MSHR miss cycles
642system.l2c.UpgradeReq_mshr_miss_latency::total 31607613 # number of UpgradeReq MSHR miss cycles
643system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 641556 # number of SCUpgradeReq MSHR miss cycles
644system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1072106 # number of SCUpgradeReq MSHR miss cycles
645system.l2c.SCUpgradeReq_mshr_miss_latency::total 1713662 # number of SCUpgradeReq MSHR miss cycles
646system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7614105115 # number of ReadExReq MSHR miss cycles
647system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1279019296 # number of ReadExReq MSHR miss cycles
648system.l2c.ReadExReq_mshr_miss_latency::total 8893124411 # number of ReadExReq MSHR miss cycles
649system.l2c.demand_mshr_miss_latency::cpu0.inst 782519751 # number of demand (read+write) MSHR miss cycles
650system.l2c.demand_mshr_miss_latency::cpu0.data 21913055865 # number of demand (read+write) MSHR miss cycles
651system.l2c.demand_mshr_miss_latency::cpu1.inst 266998019 # number of demand (read+write) MSHR miss cycles
652system.l2c.demand_mshr_miss_latency::cpu1.data 1426325047 # number of demand (read+write) MSHR miss cycles
653system.l2c.demand_mshr_miss_latency::total 24388898682 # number of demand (read+write) MSHR miss cycles
654system.l2c.overall_mshr_miss_latency::cpu0.inst 782519751 # number of overall MSHR miss cycles
655system.l2c.overall_mshr_miss_latency::cpu0.data 21913055865 # number of overall MSHR miss cycles
656system.l2c.overall_mshr_miss_latency::cpu1.inst 266998019 # number of overall MSHR miss cycles
657system.l2c.overall_mshr_miss_latency::cpu1.data 1426325047 # number of overall MSHR miss cycles
658system.l2c.overall_mshr_miss_latency::total 24388898682 # number of overall MSHR miss cycles
659system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 931434500 # number of ReadReq MSHR uncacheable cycles
660system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 458421000 # number of ReadReq MSHR uncacheable cycles
661system.l2c.ReadReq_mshr_uncacheable_latency::total 1389855500 # number of ReadReq MSHR uncacheable cycles
662system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1577498000 # number of WriteReq MSHR uncacheable cycles
663system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 884169000 # number of WriteReq MSHR uncacheable cycles
664system.l2c.WriteReq_mshr_uncacheable_latency::total 2461667000 # number of WriteReq MSHR uncacheable cycles
665system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2508932500 # number of overall MSHR uncacheable cycles
666system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1342590000 # number of overall MSHR uncacheable cycles
667system.l2c.overall_mshr_uncacheable_latency::total 3851522500 # number of overall MSHR uncacheable cycles
668system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for ReadReq accesses
669system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.322174 # mshr miss rate for ReadReq accesses
670system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for ReadReq accesses
671system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007059 # mshr miss rate for ReadReq accesses
672system.l2c.ReadReq_mshr_miss_rate::total 0.132662 # mshr miss rate for ReadReq accesses
673system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951763 # mshr miss rate for UpgradeReq accesses
674system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.888048 # mshr miss rate for UpgradeReq accesses
675system.l2c.UpgradeReq_mshr_miss_rate::total 0.939213 # mshr miss rate for UpgradeReq accesses
676system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.610526 # mshr miss rate for SCUpgradeReq accesses
677system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.764286 # mshr miss rate for SCUpgradeReq accesses
678system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702128 # mshr miss rate for SCUpgradeReq accesses
679system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430123 # mshr miss rate for ReadExReq accesses
680system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241159 # mshr miss rate for ReadExReq accesses
681system.l2c.ReadExReq_mshr_miss_rate::total 0.394654 # mshr miss rate for ReadExReq accesses
682system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for demand accesses
683system.l2c.demand_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for demand accesses
684system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for demand accesses
685system.l2c.demand_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for demand accesses
686system.l2c.demand_mshr_miss_rate::total 0.165402 # mshr miss rate for demand accesses
687system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015114 # mshr miss rate for overall accesses
688system.l2c.overall_mshr_miss_rate::cpu0.data 0.347046 # mshr miss rate for overall accesses
689system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011650 # mshr miss rate for overall accesses
690system.l2c.overall_mshr_miss_rate::cpu1.data 0.051194 # mshr miss rate for overall accesses
691system.l2c.overall_mshr_miss_rate::total 0.165402 # mshr miss rate for overall accesses
692system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average ReadReq mshr miss latency
693system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52558.464555 # average ReadReq mshr miss latency
694system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average ReadReq mshr miss latency
695system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82989.155493 # average ReadReq mshr miss latency
696system.l2c.ReadReq_avg_mshr_miss_latency::total 53598.566179 # average ReadReq mshr miss latency
697system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.667057 # average UpgradeReq mshr miss latency
698system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.989779 # average UpgradeReq mshr miss latency
699system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.796003 # average UpgradeReq mshr miss latency
700system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 11061.310345 # average SCUpgradeReq mshr miss latency
701system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.682243 # average SCUpgradeReq mshr miss latency
702system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10385.830303 # average SCUpgradeReq mshr miss latency
703system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70020.554483 # average ReadExReq mshr miss latency
704system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90787.854628 # average ReadExReq mshr miss latency
705system.l2c.ReadExReq_avg_mshr_miss_latency::total 72402.481588 # average ReadExReq mshr miss latency
706system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
707system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
708system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
709system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
710system.l2c.demand_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
711system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67580.944037 # average overall mshr miss latency
712system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57544.940677 # average overall mshr miss latency
713system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72239.723755 # average overall mshr miss latency
714system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89915.214461 # average overall mshr miss latency
715system.l2c.overall_avg_mshr_miss_latency::total 59205.409279 # average overall mshr miss latency
716system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
717system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
718system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
719system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
720system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
721system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
722system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
723system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
724system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
725system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
726system.iocache.tags.replacements 41695 # number of replacements
727system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use
728system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
729system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
730system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
731system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit.
732system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor
733system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy
734system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy
735system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
736system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
737system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
738system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
739system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
740system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
741system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
742system.iocache.overall_misses::total 41727 # number of overall misses
743system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles
744system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles
745system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles
746system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles
747system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles
748system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles
749system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles
750system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles
751system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
752system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
753system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
754system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
755system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
756system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
757system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
758system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
759system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
760system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
761system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
762system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
763system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
764system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
765system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
766system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
767system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency
768system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency
769system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency
770system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency
771system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
772system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency
773system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
774system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency
775system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked
776system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
777system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked
778system.iocache.blocked::no_targets 0 # number of cycles access was blocked
779system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked
780system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
781system.iocache.fast_writes 0 # number of fast writes performed
782system.iocache.cache_copies 0 # number of cache copies performed
783system.iocache.writebacks::writebacks 41520 # number of writebacks
784system.iocache.writebacks::total 41520 # number of writebacks
785system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
786system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
787system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
788system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
789system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
790system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
791system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
792system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
793system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles
794system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles
795system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles
796system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles
797system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles
798system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles
799system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles
800system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles
801system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
802system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
803system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
804system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
805system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
806system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
807system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
808system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
809system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency
810system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency
811system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency
812system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency
813system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
814system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
815system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
816system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
817system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
818system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
819system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
820system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
821system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
822system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
823system.disk0.dma_write_txs 395 # Number of DMA write transactions.
824system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
825system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
826system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
827system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
828system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
829system.disk2.dma_write_txs 1 # Number of DMA write transactions.
830system.cpu0.branchPred.lookups 11006012 # Number of BP lookups
831system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted
832system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect
833system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups
834system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits
835system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
836system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage
837system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target.
838system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions.
839system.cpu0.dtb.fetch_hits 0 # ITB hits
840system.cpu0.dtb.fetch_misses 0 # ITB misses
841system.cpu0.dtb.fetch_acv 0 # ITB acv
842system.cpu0.dtb.fetch_accesses 0 # ITB accesses
843system.cpu0.dtb.read_hits 7888949 # DTB read hits
844system.cpu0.dtb.read_misses 30101 # DTB read misses
845system.cpu0.dtb.read_acv 574 # DTB read access violations
846system.cpu0.dtb.read_accesses 665608 # DTB read accesses
847system.cpu0.dtb.write_hits 5247941 # DTB write hits
848system.cpu0.dtb.write_misses 8093 # DTB write misses
849system.cpu0.dtb.write_acv 365 # DTB write access violations
850system.cpu0.dtb.write_accesses 232480 # DTB write accesses
851system.cpu0.dtb.data_hits 13136890 # DTB hits
852system.cpu0.dtb.data_misses 38194 # DTB misses
853system.cpu0.dtb.data_acv 939 # DTB access violations
854system.cpu0.dtb.data_accesses 898088 # DTB accesses
855system.cpu0.itb.fetch_hits 973403 # ITB hits
856system.cpu0.itb.fetch_misses 31216 # ITB misses
857system.cpu0.itb.fetch_acv 1004 # ITB acv
858system.cpu0.itb.fetch_accesses 1004619 # ITB accesses
859system.cpu0.itb.read_hits 0 # DTB read hits
860system.cpu0.itb.read_misses 0 # DTB read misses
861system.cpu0.itb.read_acv 0 # DTB read access violations
862system.cpu0.itb.read_accesses 0 # DTB read accesses
863system.cpu0.itb.write_hits 0 # DTB write hits
864system.cpu0.itb.write_misses 0 # DTB write misses
865system.cpu0.itb.write_acv 0 # DTB write access violations
866system.cpu0.itb.write_accesses 0 # DTB write accesses
867system.cpu0.itb.data_hits 0 # DTB hits
868system.cpu0.itb.data_misses 0 # DTB misses
869system.cpu0.itb.data_acv 0 # DTB access violations
870system.cpu0.itb.data_accesses 0 # DTB accesses
871system.cpu0.numCycles 104578589 # number of cpu cycles simulated
872system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
873system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
874system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss
875system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed
876system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered
877system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken
878system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked
879system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing
880system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked
881system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
882system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps
883system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions
884system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
885system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched
886system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed
887system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total)
888system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total)
889system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total)
890system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
891system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total)
892system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total)
893system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total)
894system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total)
895system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total)
896system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total)
897system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total)
898system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total)
899system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total)
900system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
901system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
902system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
903system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total)
904system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle
905system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle
906system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle
907system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked
908system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running
909system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking
910system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing
911system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch
912system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction
913system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode
914system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode
915system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing
916system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle
917system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking
918system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst
919system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running
920system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking
921system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename
922system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full
923system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full
924system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full
925system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed
926system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made
927system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups
928system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups
929system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed
930system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing
931system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed
932system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed
933system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer
934system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit.
935system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit.
936system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads.
937system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores.
938system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec)
939system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ
940system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued
941system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued
942system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling
943system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph
944system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed
945system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle
946system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle
947system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle
948system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
949system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle
950system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle
951system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle
952system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle
953system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle
954system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle
955system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle
956system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle
957system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle
958system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
959system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
960system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
961system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle
962system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
963system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available
964system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available
965system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available
966system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available
967system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available
968system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available
969system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available
970system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available
971system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
972system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available
973system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available
974system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available
975system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available
976system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available
977system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available
978system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available
979system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available
980system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available
981system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available
982system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available
983system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available
984system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available
985system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available
986system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available
987system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available
988system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available
989system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available
990system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available
991system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
992system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available
993system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available
994system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
995system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
996system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
997system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued
998system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued
999system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
1000system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued
1001system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued
1002system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued
1003system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued
1004system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued
1005system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
1006system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
1007system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
1008system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
1009system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
1010system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
1011system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
1012system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
1013system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
1014system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
1015system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
1016system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
1017system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
1018system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
1019system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
1020system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
1021system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
1022system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
1023system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
1024system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
1025system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
1026system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued
1027system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued
1028system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued
1029system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1030system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued
1031system.cpu0.iq.rate 0.435588 # Inst issue rate
1032system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested
1033system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst)
1034system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads
1035system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes
1036system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses
1037system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads
1038system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes
1039system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses
1040system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses
1041system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses
1042system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores
1043system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1044system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed
1045system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed
1046system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations
1047system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed
1048system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1049system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1050system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled
1051system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked
1052system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1053system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing
1054system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking
1055system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking
1056system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ
1057system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch
1058system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions
1059system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions
1060system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions
1061system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall
1062system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall
1063system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations
1064system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly
1065system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly
1066system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute
1067system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions
1068system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed
1069system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute
1070system.cpu0.iew.exec_swp 0 # number of swp insts executed
1071system.cpu0.iew.exec_nop 2802690 # number of nop insts executed
1072system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed
1073system.cpu0.iew.exec_branches 7146234 # Number of branches executed
1074system.cpu0.iew.exec_stores 5267829 # Number of stores executed
1075system.cpu0.iew.exec_rate 0.432362 # Inst execution rate
1076system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit
1077system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back
1078system.cpu0.iew.wb_producers 22315831 # num instructions producing a value
1079system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value
1080system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1081system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle
1082system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back
1083system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1084system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit
1085system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards
1086system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted
1087system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle
1088system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle
1089system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle
1090system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1091system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle
1092system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle
1093system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle
1094system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle
1095system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle
1096system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle
1097system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle
1098system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle
1099system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle
1100system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1101system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1102system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1103system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle
1104system.cpu0.commit.committedInsts 45343202 # Number of instructions committed
1105system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed
1106system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
1107system.cpu0.commit.refs 12347358 # Number of memory references committed
1108system.cpu0.commit.loads 7249545 # Number of loads committed
1109system.cpu0.commit.membars 175312 # Number of memory barriers committed
1110system.cpu0.commit.branches 6808554 # Number of branches committed
1111system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions.
1112system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions.
1113system.cpu0.commit.function_calls 564734 # Number of function calls committed.
1114system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached
1115system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
1116system.cpu0.rob.rob_reads 114710793 # The number of ROB reads
1117system.cpu0.rob.rob_writes 102749676 # The number of ROB writes
1118system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself
1119system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling
1120system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1121system.cpu0.committedInsts 42781436 # Number of Instructions Simulated
1122system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated
1123system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated
1124system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction
1125system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads
1126system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle
1127system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads
1128system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads
1129system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes
1130system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads
1131system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes
1132system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads
1133system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes
1134system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1135system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1136system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1137system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1138system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1139system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1140system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1141system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

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1157system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1158system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1159system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1160system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1161system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1162system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1163system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1164system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1165system.toL2Bus.throughput 112873708 # Throughput (bytes/s)
1166system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution
1167system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution
1168system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution
1169system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution
1170system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution
1171system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution
1172system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution
1173system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution
1174system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution
1175system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution
1176system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution
1177system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes)
1178system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes)
1179system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes)
1180system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes)
1181system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes)
1182system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes)
1183system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes)
1184system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes)
1185system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes)
1186system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes)
1187system.toL2Bus.data_through_bus 213236842 # Total data (bytes)
1188system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes)
1189system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks)
1190system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
1191system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks)
1192system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1193system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks)
1194system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1195system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks)
1196system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
1197system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks)
1198system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
1199system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks)
1200system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
1201system.iobus.throughput 1434231 # Throughput (bytes/s)
1202system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
1203system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
1204system.iobus.trans_dist::WriteReq 53903 # Transaction distribution
1205system.iobus.trans_dist::WriteResp 53903 # Transaction distribution
1206system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes)
1207system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1208system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1209system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1210system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1211system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1212system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
1213system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1214system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1215system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1216system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1217system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1218system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes)
1219system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
1220system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
1221system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes)
1222system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes)
1223system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1224system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1225system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1226system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1227system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1228system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
1229system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1230system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1231system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1232system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1233system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1234system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes)
1235system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
1236system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
1237system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes)
1238system.iobus.data_through_bus 2729826 # Total data (bytes)
1239system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks)
1240system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1241system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1242system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1243system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1244system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1245system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1246system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1247system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1248system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1249system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1250system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1251system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
1252system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1253system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1254system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1255system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1256system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1257system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1258system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1259system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1260system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1261system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks)
1262system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1263system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1264system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1265system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks)
1266system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1267system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks)
1268system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1269system.cpu0.icache.tags.replacements 765570 # number of replacements
1270system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use
1271system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks.
1272system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks.
1273system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks.
1274system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit.
1275system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor
1276system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy
1277system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy
1278system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits
1279system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits
1280system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits
1281system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits
1282system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits
1283system.cpu0.icache.overall_hits::total 6090993 # number of overall hits
1284system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses
1285system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses
1286system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses
1287system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses
1288system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses
1289system.cpu0.icache.overall_misses::total 805033 # number of overall misses
1290system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles
1291system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles
1292system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles
1293system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles
1294system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles
1295system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles
1296system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses)
1297system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses)
1298system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses
1299system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses
1300system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses
1301system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses
1302system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses
1303system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses
1304system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses
1305system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses
1306system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses
1307system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses
1308system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency
1309system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency
1310system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
1311system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency
1312system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency
1313system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency
1314system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked
1315system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1316system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked
1317system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1318system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked
1319system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1320system.cpu0.icache.fast_writes 0 # number of fast writes performed
1321system.cpu0.icache.cache_copies 0 # number of cache copies performed
1322system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits
1323system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits
1324system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits
1325system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits
1326system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits
1327system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits
1328system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses
1329system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses
1330system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses
1331system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses
1332system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses
1333system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses
1334system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles
1335system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles
1336system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles
1337system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles
1338system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles
1339system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles
1340system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses
1341system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses
1342system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses
1343system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses
1344system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses
1345system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses
1346system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency
1347system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency
1348system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
1349system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
1350system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency
1351system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency
1352system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1353system.cpu0.dcache.tags.replacements 1099493 # number of replacements
1354system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use
1355system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks.
1356system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks.
1357system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks.
1358system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit.
1359system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor
1360system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy
1361system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy
1362system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits
1363system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits
1364system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits
1365system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits
1366system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits
1367system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits
1368system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits
1369system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits
1370system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits
1371system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits
1372system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits
1373system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits
1374system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses
1375system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses
1376system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses
1377system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses
1378system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses
1379system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses
1380system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses
1381system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses
1382system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses
1383system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses
1384system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses
1385system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses
1386system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles
1387system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles
1388system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles
1389system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles
1390system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles
1391system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles
1392system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles
1393system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles
1394system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles
1395system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles
1396system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles
1397system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles
1398system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses)
1399system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses)
1400system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses)
1401system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses)
1402system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses)
1403system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses)
1404system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses)
1405system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses)
1406system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses
1407system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses
1408system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses
1409system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses
1410system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses
1411system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses
1412system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses
1413system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses
1414system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses
1415system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses
1416system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses
1417system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses
1418system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses
1419system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses
1420system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses
1421system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses
1422system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency
1423system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency
1424system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency
1425system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency
1426system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency
1427system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency
1428system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency
1429system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency
1430system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
1431system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency
1432system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency
1433system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency
1434system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked
1435system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked
1436system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked
1437system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
1438system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked
1439system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked
1440system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1441system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1442system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks
1443system.cpu0.dcache.writebacks::total 594718 # number of writebacks
1444system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits
1445system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits
1446system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits
1447system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits
1448system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits
1449system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits
1450system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits
1451system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits
1452system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits
1453system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits
1454system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses
1455system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses
1456system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses
1457system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses
1458system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses
1459system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses
1460system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses
1461system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses
1462system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses
1463system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses
1464system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses
1465system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses
1466system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles
1467system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles
1468system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles
1469system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles
1470system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles
1471system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles
1472system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles
1473system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles
1474system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles
1475system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles
1476system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles
1477system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles
1478system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles
1479system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles
1480system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles
1481system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles
1482system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles
1483system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles
1484system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses
1485system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses
1486system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses
1487system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses
1488system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses
1489system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses
1490system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses
1491system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses
1492system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses
1493system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses
1494system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses
1495system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses
1496system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency
1497system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency
1498system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency
1499system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency
1500system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency
1501system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency
1502system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency
1503system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency
1504system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
1505system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
1506system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
1507system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
1508system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1509system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1510system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1511system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1512system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1513system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1514system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1515system.cpu1.branchPred.lookups 3875512 # Number of BP lookups
1516system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted
1517system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect
1518system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups
1519system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits
1520system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1521system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage
1522system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target.
1523system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions.
1524system.cpu1.dtb.fetch_hits 0 # ITB hits
1525system.cpu1.dtb.fetch_misses 0 # ITB misses
1526system.cpu1.dtb.fetch_acv 0 # ITB acv
1527system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1528system.cpu1.dtb.read_hits 2756439 # DTB read hits
1529system.cpu1.dtb.read_misses 11971 # DTB read misses
1530system.cpu1.dtb.read_acv 6 # DTB read access violations
1531system.cpu1.dtb.read_accesses 281635 # DTB read accesses
1532system.cpu1.dtb.write_hits 1697476 # DTB write hits
1533system.cpu1.dtb.write_misses 2261 # DTB write misses
1534system.cpu1.dtb.write_acv 35 # DTB write access violations
1535system.cpu1.dtb.write_accesses 106637 # DTB write accesses
1536system.cpu1.dtb.data_hits 4453915 # DTB hits
1537system.cpu1.dtb.data_misses 14232 # DTB misses
1538system.cpu1.dtb.data_acv 41 # DTB access violations
1539system.cpu1.dtb.data_accesses 388272 # DTB accesses
1540system.cpu1.itb.fetch_hits 435796 # ITB hits
1541system.cpu1.itb.fetch_misses 5916 # ITB misses
1542system.cpu1.itb.fetch_acv 132 # ITB acv
1543system.cpu1.itb.fetch_accesses 441712 # ITB accesses
1544system.cpu1.itb.read_hits 0 # DTB read hits
1545system.cpu1.itb.read_misses 0 # DTB read misses
1546system.cpu1.itb.read_acv 0 # DTB read access violations
1547system.cpu1.itb.read_accesses 0 # DTB read accesses
1548system.cpu1.itb.write_hits 0 # DTB write hits
1549system.cpu1.itb.write_misses 0 # DTB write misses
1550system.cpu1.itb.write_acv 0 # DTB write access violations
1551system.cpu1.itb.write_accesses 0 # DTB write accesses
1552system.cpu1.itb.data_hits 0 # DTB hits
1553system.cpu1.itb.data_misses 0 # DTB misses
1554system.cpu1.itb.data_acv 0 # DTB access violations
1555system.cpu1.itb.data_accesses 0 # DTB accesses
1556system.cpu1.numCycles 25703316 # number of cpu cycles simulated
1557system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1558system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1559system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss
1560system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed
1561system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered
1562system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken
1563system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked
1564system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing
1565system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked
1566system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1567system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps
1568system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions
1569system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR
1570system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched
1571system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed
1572system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total)
1573system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total)
1574system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total)
1575system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1576system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total)
1577system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total)
1578system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total)
1579system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total)
1580system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total)
1581system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total)
1582system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total)
1583system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total)
1584system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total)
1585system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1586system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1587system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1588system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total)
1589system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle
1590system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle
1591system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle
1592system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked
1593system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running
1594system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking
1595system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing
1596system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch
1597system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction
1598system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode
1599system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode
1600system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing
1601system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle
1602system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking
1603system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst
1604system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running
1605system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking
1606system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename
1607system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
1608system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full
1609system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full
1610system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed
1611system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made
1612system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups
1613system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups
1614system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed
1615system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing
1616system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed
1617system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed
1618system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer
1619system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit.
1620system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit.
1621system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads.
1622system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores.
1623system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec)
1624system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ
1625system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued
1626system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued
1627system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling
1628system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph
1629system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed
1630system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle
1631system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle
1632system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle
1633system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1634system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle
1635system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle
1636system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle
1637system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle
1638system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle
1639system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle
1640system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle
1641system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle
1642system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle
1643system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1644system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1645system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1646system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle
1647system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1648system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available
1649system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available
1650system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available
1651system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available
1652system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available
1653system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available
1654system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available
1655system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available
1656system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
1657system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available
1658system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available
1659system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available
1660system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available
1661system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available
1662system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available
1663system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available
1664system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available
1665system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available
1666system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available
1667system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available
1668system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available
1669system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available
1670system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available
1671system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available
1672system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available
1673system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available
1674system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available
1675system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available
1676system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
1677system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available
1678system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available
1679system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1680system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1681system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
1682system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued
1683system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued
1684system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued
1685system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued
1686system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued
1687system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued
1688system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued
1689system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued
1690system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
1691system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
1692system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
1693system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
1694system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
1695system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
1696system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
1697system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
1698system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
1699system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
1700system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
1701system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
1702system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
1703system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
1704system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
1705system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
1706system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
1707system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
1708system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
1709system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
1710system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
1711system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued
1712system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued
1713system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued
1714system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1715system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued
1716system.cpu1.iq.rate 0.563522 # Inst issue rate
1717system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested
1718system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst)
1719system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads
1720system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes
1721system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses
1722system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads
1723system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes
1724system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses
1725system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses
1726system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses
1727system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores
1728system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1729system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed
1730system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed
1731system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations
1732system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed
1733system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1734system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1735system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled
1736system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked
1737system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1738system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing
1739system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking
1740system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking
1741system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ
1742system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch
1743system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions
1744system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions
1745system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions
1746system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall
1747system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall
1748system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations
1749system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly
1750system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly
1751system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute
1752system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions
1753system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed
1754system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute
1755system.cpu1.iew.exec_swp 0 # number of swp insts executed
1756system.cpu1.iew.exec_nop 875756 # number of nop insts executed
1757system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed
1758system.cpu1.iew.exec_branches 2254475 # Number of branches executed
1759system.cpu1.iew.exec_stores 1705604 # Number of stores executed
1760system.cpu1.iew.exec_rate 0.558247 # Inst execution rate
1761system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit
1762system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back
1763system.cpu1.iew.wb_producers 6903248 # num instructions producing a value
1764system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value
1765system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1766system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle
1767system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back
1768system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1769system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit
1770system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards
1771system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted
1772system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle
1773system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle
1774system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle
1775system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1776system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle
1777system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle
1778system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle
1779system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle
1780system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle
1781system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle
1782system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle
1783system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle
1784system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle
1785system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1786system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1787system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1788system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle
1789system.cpu1.commit.committedInsts 14096266 # Number of instructions committed
1790system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed
1791system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1792system.cpu1.commit.refs 4123576 # Number of memory references committed
1793system.cpu1.commit.loads 2500439 # Number of loads committed
1794system.cpu1.commit.membars 61456 # Number of memory barriers committed
1795system.cpu1.commit.branches 2105755 # Number of branches committed
1796system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions.
1797system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions.
1798system.cpu1.commit.function_calls 225813 # Number of function calls committed.
1799system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached
1800system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1801system.cpu1.rob.rob_reads 38521772 # The number of ROB reads
1802system.cpu1.rob.rob_writes 33194220 # The number of ROB writes
1803system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself
1804system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling
1805system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1806system.cpu1.committedInsts 13322175 # Number of Instructions Simulated
1807system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated
1808system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated
1809system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction
1810system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads
1811system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle
1812system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads
1813system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads
1814system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes
1815system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads
1816system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes
1817system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads
1818system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes
1819system.cpu1.icache.tags.replacements 316719 # number of replacements
1820system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use
1821system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks.
1822system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks.
1823system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks.
1824system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit.
1825system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor
1826system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy
1827system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy
1828system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits
1829system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits
1830system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits
1831system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits
1832system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits
1833system.cpu1.icache.overall_hits::total 1849767 # number of overall hits
1834system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses
1835system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses
1836system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses
1837system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses
1838system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses
1839system.cpu1.icache.overall_misses::total 331536 # number of overall misses
1840system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles
1841system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles
1842system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles
1843system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles
1844system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles
1845system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles
1846system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses)
1847system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses)
1848system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses
1849system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses
1850system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses
1851system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses
1852system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses
1853system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses
1854system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses
1855system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses
1856system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses
1857system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses
1858system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency
1859system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency
1860system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
1861system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency
1862system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
1863system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency
1864system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked
1865system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1866system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked
1867system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1868system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked
1869system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1870system.cpu1.icache.fast_writes 0 # number of fast writes performed
1871system.cpu1.icache.cache_copies 0 # number of cache copies performed
1872system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits
1873system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits
1874system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits
1875system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits
1876system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits
1877system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits
1878system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses
1879system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses
1880system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses
1881system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses
1882system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses
1883system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses
1884system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles
1885system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles
1886system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles
1887system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles
1888system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles
1889system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles
1890system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses
1891system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses
1892system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses
1893system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses
1894system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses
1895system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses
1896system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency
1897system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency
1898system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
1899system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
1900system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
1901system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
1902system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1903system.cpu1.dcache.tags.replacements 323504 # number of replacements
1904system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use
1905system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks.
1906system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks.
1907system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks.
1908system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit.
1909system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor
1910system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy
1911system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy
1912system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits
1913system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits
1914system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits
1915system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits
1916system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits
1917system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits
1918system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits
1919system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits
1920system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits
1921system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits
1922system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits
1923system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits
1924system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses
1925system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses
1926system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses
1927system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses
1928system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses
1929system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses
1930system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses
1931system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses
1932system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses
1933system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses
1934system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses
1935system.cpu1.dcache.overall_misses::total 816274 # number of overall misses
1936system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles
1937system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles
1938system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # number of WriteReq miss cycles
1939system.cpu1.dcache.WriteReq_miss_latency::total 13547153677 # number of WriteReq miss cycles
1940system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 112298247 # number of LoadLockedReq miss cycles
1941system.cpu1.dcache.LoadLockedReq_miss_latency::total 112298247 # number of LoadLockedReq miss cycles
1942system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5736606 # number of StoreCondReq miss cycles
1943system.cpu1.dcache.StoreCondReq_miss_latency::total 5736606 # number of StoreCondReq miss cycles
1944system.cpu1.dcache.demand_miss_latency::cpu1.data 20834123377 # number of demand (read+write) miss cycles
1945system.cpu1.dcache.demand_miss_latency::total 20834123377 # number of demand (read+write) miss cycles
1946system.cpu1.dcache.overall_miss_latency::cpu1.data 20834123377 # number of overall miss cycles
1947system.cpu1.dcache.overall_miss_latency::total 20834123377 # number of overall miss cycles
1948system.cpu1.dcache.ReadReq_accesses::cpu1.data 2557049 # number of ReadReq accesses(hits+misses)
1949system.cpu1.dcache.ReadReq_accesses::total 2557049 # number of ReadReq accesses(hits+misses)
1950system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses)
1951system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses)
1952system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses)
1953system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses)
1954system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses)
1955system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses)
1956system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses
1957system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses
1958system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses
1959system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses
1960system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # miss rate for ReadReq accesses
1961system.cpu1.dcache.ReadReq_miss_rate::total 0.182849 # miss rate for ReadReq accesses
1962system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222006 # miss rate for WriteReq accesses
1963system.cpu1.dcache.WriteReq_miss_rate::total 0.222006 # miss rate for WriteReq accesses
1964system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157248 # miss rate for LoadLockedReq accesses
1965system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157248 # miss rate for LoadLockedReq accesses
1966system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.017309 # miss rate for StoreCondReq accesses
1967system.cpu1.dcache.StoreCondReq_miss_rate::total 0.017309 # miss rate for StoreCondReq accesses
1968system.cpu1.dcache.demand_miss_rate::cpu1.data 0.197749 # miss rate for demand accesses
1969system.cpu1.dcache.demand_miss_rate::total 0.197749 # miss rate for demand accesses
1970system.cpu1.dcache.overall_miss_rate::cpu1.data 0.197749 # miss rate for overall accesses
1971system.cpu1.dcache.overall_miss_rate::total 0.197749 # miss rate for overall accesses
1972system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069 # average ReadReq miss latency
1973system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069 # average ReadReq miss latency
1974system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476 # average WriteReq miss latency
1975system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476 # average WriteReq miss latency
1976system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934 # average LoadLockedReq miss latency
1977system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934 # average LoadLockedReq miss latency
1978system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7335.813299 # average StoreCondReq miss latency
1979system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7335.813299 # average StoreCondReq miss latency
1980system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
1981system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570 # average overall miss latency
1982system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570 # average overall miss latency
1983system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570 # average overall miss latency
1984system.cpu1.dcache.blocked_cycles::no_mshrs 423453 # number of cycles access was blocked
1985system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1986system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked
1987system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1988system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked
1989system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1990system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1991system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1992system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks
1993system.cpu1.dcache.writebacks::total 245774 # number of writebacks
1994system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits
1995system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits
1996system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits
1997system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits
1998system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits
1999system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits
2000system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits
2001system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits
2002system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits
2003system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits
2004system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses
2005system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses
2006system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses
2007system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses
2008system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses
2009system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses
2010system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses
2011system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses
2012system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses
2013system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses
2014system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses
2015system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses
2016system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles
2017system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles
2018system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles
2019system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles
2020system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles
2021system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles
2022system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles
2023system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles
2024system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles
2025system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles
2026system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles
2027system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles
2028system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles
2029system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles
2030system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles
2031system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles
2032system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles
2033system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles
2034system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses
2035system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses
2036system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses
2037system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses
2038system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses
2039system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses
2040system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses
2041system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses
2042system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses
2043system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses
2044system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses
2045system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses
2046system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency
2047system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency
2048system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency
2049system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency
2050system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency
2051system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency
2052system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency
2053system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency
2054system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
2055system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
2056system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
2057system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
2058system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2059system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2060system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2061system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2062system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2063system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2064system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2065system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2066system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed
2067system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed
2068system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl
2069system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl
2070system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl
2071system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl
2072system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl
2073system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl
2074system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl
2075system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl
2076system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl
2077system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl
2078system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl
2079system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl
2080system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl
2081system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl
2082system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl
2083system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl
2084system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl
2085system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl
2086system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl
2087system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
2088system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2089system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2090system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl
2091system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl
2092system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed
2093system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed
2094system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed
2095system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed
2096system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed
2097system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed
2098system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed
2099system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed
2100system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed
2101system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed
2102system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed
2103system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed
2104system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed
2105system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed
2106system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed
2107system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed
2108system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed
2109system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed
2110system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed
2111system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed
2112system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed
2113system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed
2114system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed
2115system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed
2116system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed
2117system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed
2118system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed
2119system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed
2120system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
2121system.cpu0.kern.syscall::total 225 # number of syscalls executed
2122system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2123system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed
2124system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
2125system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
2126system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
2127system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed
2128system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed
2129system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed
2130system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed
2131system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed
2132system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed
2133system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed
2134system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed
2135system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
2136system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed
2137system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed
2138system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
2139system.cpu0.kern.callpal::total 151247 # number of callpals executed
2140system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches
2141system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches
2142system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2143system.cpu0.kern.mode_good::kernel 1342
2144system.cpu0.kern.mode_good::user 1343
2145system.cpu0.kern.mode_good::idle 0
2146system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches
2147system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2148system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2149system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches
2150system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode
2151system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode
2152system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2153system.cpu0.kern.swap_context 3011 # number of times the context was actually changed
2154system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2155system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed
2156system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed
2157system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl
2158system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl
2159system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl
2160system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl
2161system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl
2162system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl
2163system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl
2164system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl
2165system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl
2166system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl
2167system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl
2168system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl
2169system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl
2170system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl
2171system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl
2172system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl
2173system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2174system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2175system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl
2176system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl
2177system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
2178system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
2179system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
2180system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed
2181system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed
2182system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed
2183system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed
2184system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed
2185system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed
2186system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed
2187system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed
2188system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed
2189system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
2190system.cpu1.kern.syscall::total 101 # number of syscalls executed
2191system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2192system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed
2193system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
2194system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
2195system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed
2196system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed
2197system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed
2198system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed
2199system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed
2200system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed
2201system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed
2202system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed
2203system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed
2204system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed
2205system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
2206system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2207system.cpu1.kern.callpal::total 65000 # number of callpals executed
2208system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches
2209system.cpu1.kern.mode_switch::user 397 # number of protection mode switches
2210system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
2211system.cpu1.kern.mode_good::kernel 463
2212system.cpu1.kern.mode_good::user 397
2213system.cpu1.kern.mode_good::idle 66
2214system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches
2215system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2216system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
2217system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches
2218system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode
2219system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode
2220system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode
2221system.cpu1.kern.swap_context 1229 # number of times the context was actually changed
2222
2223---------- End Simulation Statistics ----------