1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.921764 # Number of seconds simulated
4sim_ticks 1921763645000 # Number of ticks simulated
5final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 133766 # Simulator instruction rate (inst/s)
8host_op_rate 133766 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4532754153 # Simulator tick rate (ticks/s)
10host_mem_usage 384052 # Number of bytes of host memory used
11host_seconds 423.97 # Real time elapsed on the host
12sim_insts 56713315 # Number of instructions simulated
13sim_ops 56713315 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 410427 # Number of read requests accepted
54system.physmem.writeReqs 123049 # Number of write requests accepted
55system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
59system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25500 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25969 # Per bank write bursts
67system.physmem.perBankRdBursts::2 26011 # Per bank write bursts
68system.physmem.perBankRdBursts::3 25727 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25508 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25811 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25519 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25160 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25451 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25839 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25659 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25030 # Per bank write bursts
77system.physmem.perBankRdBursts::12 26076 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25978 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25473 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25600 # Per bank write bursts
81system.physmem.perBankWrBursts::0 8066 # Per bank write bursts
82system.physmem.perBankWrBursts::1 8046 # Per bank write bursts
83system.physmem.perBankWrBursts::2 8027 # Per bank write bursts
84system.physmem.perBankWrBursts::3 7668 # Per bank write bursts
85system.physmem.perBankWrBursts::4 7376 # Per bank write bursts
86system.physmem.perBankWrBursts::5 7761 # Per bank write bursts
87system.physmem.perBankWrBursts::6 7583 # Per bank write bursts
88system.physmem.perBankWrBursts::7 6991 # Per bank write bursts
89system.physmem.perBankWrBursts::8 7326 # Per bank write bursts
90system.physmem.perBankWrBursts::9 7600 # Per bank write bursts
91system.physmem.perBankWrBursts::10 7532 # Per bank write bursts
92system.physmem.perBankWrBursts::11 7413 # Per bank write bursts
93system.physmem.perBankWrBursts::12 7962 # Per bank write bursts
94system.physmem.perBankWrBursts::13 8267 # Per bank write bursts
95system.physmem.perBankWrBursts::14 7722 # Per bank write bursts
96system.physmem.perBankWrBursts::15 7694 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 18 # Number of times write queue was full causing retry
99system.physmem.totGap 1921759329500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 410427 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 123049 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see

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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 6758 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 8174 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 8527 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 9653 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 8822 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 9133 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 8229 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 8839 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 6881 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 6896 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 6046 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 371 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 229 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 237 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 181 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 77 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 72 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 65305 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 522.687084 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 319.252168 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 410.914363 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 14928 22.86% 22.86% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 73.956561 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2834.723442 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 5545 99.95% 99.95% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads
274system.physmem.totQLat 4465229000 # Total ticks spent queuing
275system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM
276system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers
277system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst
278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
279system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst
280system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s
281system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
282system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s
283system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
285system.physmem.busUtil 0.14 # Data bus utilization in percentage
286system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
288system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing
289system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing
290system.physmem.readRowHits 369445 # Number of row buffer hits during reads
291system.physmem.writeRowHits 98595 # Number of row buffer hits during writes
292system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads
293system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes
294system.physmem.avgGap 3602335.12 # Average gap between requests
295system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined
296system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ)
297system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ)
298system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ)
299system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ)
300system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ)
301system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ)
302system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ)
303system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ)
304system.physmem_0.averagePower 670.590642 # Core power per rank (mW)
305system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states
306system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states
307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
308system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states
309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
310system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ)
311system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ)
312system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ)
313system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ)
314system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ)
315system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ)
316system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ)
317system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ)
318system.physmem_1.averagePower 670.579840 # Core power per rank (mW)
319system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states
320system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states
321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
322system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states
323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
324system.cpu0.branchPred.lookups 16172722 # Number of BP lookups
325system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted
326system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect
327system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups
328system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits
329system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
330system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage
331system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target.
332system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions.
333system.cpu_clk_domain.clock 500 # Clock period in ticks
334system.cpu0.dtb.fetch_hits 0 # ITB hits
335system.cpu0.dtb.fetch_misses 0 # ITB misses
336system.cpu0.dtb.fetch_acv 0 # ITB acv
337system.cpu0.dtb.fetch_accesses 0 # ITB accesses
338system.cpu0.dtb.read_hits 9178933 # DTB read hits
339system.cpu0.dtb.read_misses 32423 # DTB read misses
340system.cpu0.dtb.read_acv 530 # DTB read access violations
341system.cpu0.dtb.read_accesses 683199 # DTB read accesses
342system.cpu0.dtb.write_hits 5878949 # DTB write hits
343system.cpu0.dtb.write_misses 7260 # DTB write misses
344system.cpu0.dtb.write_acv 384 # DTB write access violations
345system.cpu0.dtb.write_accesses 235377 # DTB write accesses
346system.cpu0.dtb.data_hits 15057882 # DTB hits
347system.cpu0.dtb.data_misses 39683 # DTB misses
348system.cpu0.dtb.data_acv 914 # DTB access violations
349system.cpu0.dtb.data_accesses 918576 # DTB accesses
350system.cpu0.itb.fetch_hits 1433805 # ITB hits
351system.cpu0.itb.fetch_misses 20098 # ITB misses
352system.cpu0.itb.fetch_acv 602 # ITB acv
353system.cpu0.itb.fetch_accesses 1453903 # ITB accesses
354system.cpu0.itb.read_hits 0 # DTB read hits
355system.cpu0.itb.read_misses 0 # DTB read misses
356system.cpu0.itb.read_acv 0 # DTB read access violations
357system.cpu0.itb.read_accesses 0 # DTB read accesses
358system.cpu0.itb.write_hits 0 # DTB write hits
359system.cpu0.itb.write_misses 0 # DTB write misses
360system.cpu0.itb.write_acv 0 # DTB write access violations
361system.cpu0.itb.write_accesses 0 # DTB write accesses
362system.cpu0.itb.data_hits 0 # DTB hits
363system.cpu0.itb.data_misses 0 # DTB misses
364system.cpu0.itb.data_acv 0 # DTB access violations
365system.cpu0.itb.data_accesses 0 # DTB accesses
366system.cpu0.numCycles 146988157 # number of cpu cycles simulated
367system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
368system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
369system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss
370system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed
371system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered
372system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken
373system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked
374system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing
375system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb
376system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
377system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps
378system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions
379system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR
380system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched
381system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed
382system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
383system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total)
384system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total)
385system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total)
386system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
387system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total)
388system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total)
389system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total)
390system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total)
391system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total)
392system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total)
393system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total)
394system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total)
395system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total)
396system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
397system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
398system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
399system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total)
400system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle
401system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle
402system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle
403system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked
404system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running
405system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking
406system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing
407system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch
408system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction
409system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode
410system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode
411system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing
412system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle
413system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking
414system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst
415system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running
416system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking
417system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename
418system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full
419system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full
420system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full
421system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full
422system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed
423system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made
424system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups
425system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups
426system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed
427system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing
428system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed
429system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed
430system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer
431system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit.
432system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit.
433system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads.
434system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores.
435system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec)
436system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ
437system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued
438system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued
439system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling
440system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph
441system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed
442system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle
443system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle
444system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle
445system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
446system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle
447system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle
448system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle
449system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle
450system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle
451system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle
452system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle
453system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle
454system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle
455system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
456system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
457system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
458system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle
459system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
460system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available
461system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available
462system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available
463system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available
464system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available
465system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available
466system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available
467system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available
468system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available
469system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available
470system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available
471system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available
472system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available
473system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available
474system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available
475system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available
476system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available
477system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available
478system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available
479system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available
480system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available
481system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available
482system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available
483system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available
484system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available
485system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available
486system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available
487system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available
488system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available
489system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available
490system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available
491system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
492system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
493system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued
494system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued
495system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued
496system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued
497system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued
498system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued
499system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued
500system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued
501system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued
502system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued
503system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued
504system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued
505system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued
506system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued
507system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued
508system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued
509system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued
510system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued
511system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued
512system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued
513system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued
514system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued
515system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued
516system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued
517system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued
518system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued
519system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued
520system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued
521system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued
522system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued
523system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued
524system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued
525system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued
526system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
527system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued
528system.cpu0.iq.rate 0.355242 # Inst issue rate
529system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested
530system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst)
531system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads
532system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes
533system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses
534system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads
535system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes
536system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses
537system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses
538system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses
539system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores
540system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
541system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed
542system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed
543system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations
544system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed
545system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
546system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
547system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled
548system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked
549system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
550system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing
551system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking
552system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking
553system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ
554system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch
555system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions
556system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions
557system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions
558system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall
559system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall
560system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations
561system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly
562system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly
563system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute
564system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions
565system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed
566system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute
567system.cpu0.iew.exec_swp 0 # number of swp insts executed
568system.cpu0.iew.exec_nop 3376381 # number of nop insts executed
569system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed
570system.cpu0.iew.exec_branches 8213447 # Number of branches executed
571system.cpu0.iew.exec_stores 5899836 # Number of stores executed
572system.cpu0.iew.exec_rate 0.351823 # Inst execution rate
573system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit
574system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back
575system.cpu0.iew.wb_producers 26321891 # num instructions producing a value
576system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value
577system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
578system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle
579system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back
580system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
581system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit
582system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards
583system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted
584system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle
585system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle
586system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle
587system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
588system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle
589system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle
590system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle
591system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle
592system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle
593system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle
594system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle
595system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle
596system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle
597system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
598system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
599system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
600system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle
601system.cpu0.commit.committedInsts 51342045 # Number of instructions committed
602system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed
603system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
604system.cpu0.commit.refs 13846709 # Number of memory references committed
605system.cpu0.commit.loads 8192690 # Number of loads committed
606system.cpu0.commit.membars 198882 # Number of memory barriers committed
607system.cpu0.commit.branches 7762297 # Number of branches committed
608system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions.
609system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions.
610system.cpu0.commit.function_calls 657143 # Number of function calls committed.
611system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction
612system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction
613system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction
614system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction
615system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction
616system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction
617system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction
618system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction
619system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction
620system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction
621system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction
622system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction
623system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction
624system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction
625system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction
626system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction
627system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction
628system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction
629system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction
630system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction
631system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction
632system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction
633system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction
634system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction
635system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction
636system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction
637system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction
638system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction
639system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction
640system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction
641system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction
642system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction
643system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction
644system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
645system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction
646system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached
647system.cpu0.rob.rob_reads 195675599 # The number of ROB reads
648system.cpu0.rob.rob_writes 117488366 # The number of ROB writes
649system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself
650system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling
651system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
652system.cpu0.committedInsts 48394452 # Number of Instructions Simulated
653system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated
654system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction
655system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads
656system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle
657system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads
658system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads
659system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes
660system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads
661system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes
662system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads
663system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes
664system.cpu0.dcache.tags.replacements 1282830 # number of replacements
665system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use
666system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks.
667system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks.
668system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks.
669system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit.
670system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor
671system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy
672system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy
673system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
674system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
675system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
676system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
677system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
678system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses
679system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses
680system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits
681system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits
682system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits
683system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits
684system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits
685system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits
686system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits
687system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits
688system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits
689system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits
690system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits
691system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits
692system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses
693system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses
694system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses
695system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses
696system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses
697system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses
698system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses
699system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses
700system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses
701system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses
702system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses
703system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses
704system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles
705system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles
706system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles
707system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles
708system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles
709system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles
710system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles
711system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles
712system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles
713system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles
714system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles
715system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles
716system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses)
717system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses)
718system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses)
719system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses)
720system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses)
721system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses)
722system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses)
723system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses)
724system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses
725system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses
726system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses
727system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses
728system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses
729system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses
730system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses
731system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses
732system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses
733system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses
734system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses
735system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses
736system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses
737system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses
738system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses
739system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses
740system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency
741system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency
742system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency
743system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency
744system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency
745system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency
746system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency
747system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency
748system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency
749system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency
750system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency
751system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency
752system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked
753system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked
754system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked
755system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked
756system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked
757system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked
758system.cpu0.dcache.fast_writes 0 # number of fast writes performed
759system.cpu0.dcache.cache_copies 0 # number of cache copies performed
760system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks
761system.cpu0.dcache.writebacks::total 756224 # number of writebacks
762system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits
763system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits
764system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits
765system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits
766system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits
767system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits
768system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits
769system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits
770system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits
771system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits
772system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses
773system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses
774system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses
775system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses
776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses
777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses
778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses
779system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses
780system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses
781system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses
782system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses
783system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses
784system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable
785system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable
786system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable
787system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable
788system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses
789system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses
790system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles
791system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles
792system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles
793system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles
794system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles
795system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles
796system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles
797system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles
798system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles
799system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles
800system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles
801system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles
802system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles
803system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles
804system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles
805system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles
806system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles
807system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles
808system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses
809system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses
810system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses
811system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses
812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses
813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses
814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses
815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses
816system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses
817system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses
818system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses
819system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses
820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency
821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency
822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency
823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency
824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency
825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency
826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency
827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency
828system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency
829system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency
830system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency
831system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency
832system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency
833system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency
834system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency
835system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency
836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency
837system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency
838system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
839system.cpu0.icache.tags.replacements 909478 # number of replacements
840system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use
841system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks.
842system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks.
843system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks.
844system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit.
845system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor
846system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy
847system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy
848system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
849system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
850system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
851system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id
852system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
853system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses
854system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses
855system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits
856system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits
857system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits
858system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits
859system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits
860system.cpu0.icache.overall_hits::total 7170024 # number of overall hits
861system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses
862system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses
863system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses
864system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses
865system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses
866system.cpu0.icache.overall_misses::total 955631 # number of overall misses
867system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles
868system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles
869system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles
870system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles
871system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles
872system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles
873system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses)
874system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses)
875system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses
876system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses
877system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses
878system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses
879system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses
880system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses
881system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses
882system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses
883system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses
884system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses
885system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency
886system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency
887system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency
888system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency
889system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency
890system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency
891system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked
892system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
893system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked
894system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
895system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked
896system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
897system.cpu0.icache.fast_writes 0 # number of fast writes performed
898system.cpu0.icache.cache_copies 0 # number of cache copies performed
899system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits
900system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits
901system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits
902system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits
903system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits
904system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits
905system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses
906system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses
907system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses
908system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses
909system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses
910system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses
911system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles
912system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles
913system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles
914system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles
915system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles
916system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles
917system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses
918system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses
919system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses
920system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses
921system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses
922system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses
923system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency
924system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency
925system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency
926system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency
927system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency
928system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency
929system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
930system.cpu1.branchPred.lookups 3566695 # Number of BP lookups
931system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted
932system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect
933system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups
934system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits
935system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
936system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage
937system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target.
938system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions.
939system.cpu1.dtb.fetch_hits 0 # ITB hits
940system.cpu1.dtb.fetch_misses 0 # ITB misses
941system.cpu1.dtb.fetch_acv 0 # ITB acv
942system.cpu1.dtb.fetch_accesses 0 # ITB accesses
943system.cpu1.dtb.read_hits 1880373 # DTB read hits
944system.cpu1.dtb.read_misses 9576 # DTB read misses
945system.cpu1.dtb.read_acv 6 # DTB read access violations
946system.cpu1.dtb.read_accesses 286028 # DTB read accesses
947system.cpu1.dtb.write_hits 1172828 # DTB write hits
948system.cpu1.dtb.write_misses 2034 # DTB write misses
949system.cpu1.dtb.write_acv 35 # DTB write access violations
950system.cpu1.dtb.write_accesses 108538 # DTB write accesses
951system.cpu1.dtb.data_hits 3053201 # DTB hits
952system.cpu1.dtb.data_misses 11610 # DTB misses
953system.cpu1.dtb.data_acv 41 # DTB access violations
954system.cpu1.dtb.data_accesses 394566 # DTB accesses
955system.cpu1.itb.fetch_hits 516269 # ITB hits
956system.cpu1.itb.fetch_misses 4737 # ITB misses
957system.cpu1.itb.fetch_acv 64 # ITB acv
958system.cpu1.itb.fetch_accesses 521006 # ITB accesses
959system.cpu1.itb.read_hits 0 # DTB read hits
960system.cpu1.itb.read_misses 0 # DTB read misses
961system.cpu1.itb.read_acv 0 # DTB read access violations
962system.cpu1.itb.read_accesses 0 # DTB read accesses
963system.cpu1.itb.write_hits 0 # DTB write hits
964system.cpu1.itb.write_misses 0 # DTB write misses
965system.cpu1.itb.write_acv 0 # DTB write access violations
966system.cpu1.itb.write_accesses 0 # DTB write accesses
967system.cpu1.itb.data_hits 0 # DTB hits
968system.cpu1.itb.data_misses 0 # DTB misses
969system.cpu1.itb.data_acv 0 # DTB access violations
970system.cpu1.itb.data_accesses 0 # DTB accesses
971system.cpu1.numCycles 14959639 # number of cpu cycles simulated
972system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
973system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
974system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss
975system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed
976system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered
977system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken
978system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked
979system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing
980system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb
981system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
982system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps
983system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions
984system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
985system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched
986system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed
987system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total)
988system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total)
989system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total)
990system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
991system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total)
992system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total)
993system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total)
994system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total)
995system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total)
996system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total)
997system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total)
998system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total)
999system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total)
1000system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1001system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1002system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
1003system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total)
1004system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle
1005system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle
1006system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle
1007system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked
1008system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running
1009system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking
1010system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing
1011system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch
1012system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction
1013system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode
1014system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode
1015system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing
1016system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle
1017system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking
1018system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst
1019system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running
1020system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking
1021system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename
1022system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full
1023system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full
1024system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full
1025system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full
1026system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed
1027system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made
1028system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups
1029system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups
1030system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed
1031system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing
1032system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed
1033system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed
1034system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer
1035system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit.
1036system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit.
1037system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads.
1038system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores.
1039system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec)
1040system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ
1041system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued
1042system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued
1043system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling
1044system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph
1045system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed
1046system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle
1047system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle
1048system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle
1049system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1050system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle
1051system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle
1052system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle
1053system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle
1054system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle
1055system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle
1056system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle
1057system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle
1058system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle
1059system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1060system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1061system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1062system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle
1063system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1064system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available
1065system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available
1066system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available
1067system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available
1068system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available
1069system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available
1070system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available
1071system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available
1072system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available
1073system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available
1074system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available
1075system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available
1076system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available
1077system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available
1078system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available
1079system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available
1080system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available
1081system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available
1082system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available
1083system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available
1084system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available
1085system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available
1086system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available
1087system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available
1088system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available
1089system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available
1090system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available
1091system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available
1092system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available
1093system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available
1094system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available
1095system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1096system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1097system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
1098system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued
1099system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued
1100system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued
1101system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued
1102system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued
1103system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued
1104system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued
1105system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued
1106system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
1107system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
1108system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
1109system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
1110system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
1111system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
1112system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
1113system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
1114system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
1115system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
1116system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
1117system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
1118system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
1119system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
1120system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
1121system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
1122system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
1123system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued
1124system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
1125system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
1126system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
1127system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued
1128system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued
1129system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued
1130system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1131system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued
1132system.cpu1.iq.rate 0.609112 # Inst issue rate
1133system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested
1134system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst)
1135system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads
1136system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes
1137system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses
1138system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads
1139system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes
1140system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses
1141system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses
1142system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses
1143system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores
1144system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1145system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed
1146system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed
1147system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations
1148system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed
1149system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1150system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1151system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled
1152system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked
1153system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1154system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing
1155system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking
1156system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking
1157system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ
1158system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch
1159system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions
1160system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions
1161system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions
1162system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall
1163system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall
1164system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations
1165system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly
1166system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly
1167system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute
1168system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions
1169system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed
1170system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute
1171system.cpu1.iew.exec_swp 0 # number of swp insts executed
1172system.cpu1.iew.exec_nop 516366 # number of nop insts executed
1173system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed
1174system.cpu1.iew.exec_branches 1335580 # Number of branches executed
1175system.cpu1.iew.exec_stores 1180544 # Number of stores executed
1176system.cpu1.iew.exec_rate 0.601481 # Inst execution rate
1177system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit
1178system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back
1179system.cpu1.iew.wb_producers 4235192 # num instructions producing a value
1180system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value
1181system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1182system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle
1183system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back
1184system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1185system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit
1186system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards
1187system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted
1188system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle
1189system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle
1190system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle
1191system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1192system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle
1193system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle
1194system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle
1195system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle
1196system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle
1197system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle
1198system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle
1199system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle
1200system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle
1201system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1202system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1203system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1204system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle
1205system.cpu1.commit.committedInsts 8743092 # Number of instructions committed
1206system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed
1207system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1208system.cpu1.commit.refs 2784903 # Number of memory references committed
1209system.cpu1.commit.loads 1665249 # Number of loads committed
1210system.cpu1.commit.membars 42287 # Number of memory barriers committed
1211system.cpu1.commit.branches 1247450 # Number of branches committed
1212system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions.
1213system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions.
1214system.cpu1.commit.function_calls 139604 # Number of function calls committed.
1215system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction
1216system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction
1217system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction
1218system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction
1219system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction
1220system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction
1221system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction
1222system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction
1223system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction
1224system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction
1225system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction
1226system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction
1227system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction
1228system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction
1229system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction
1230system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction
1231system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction
1232system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction
1233system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction
1234system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction
1235system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction
1236system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction
1237system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction
1238system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction
1239system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction
1240system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction
1241system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction
1242system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction
1243system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction
1244system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction
1245system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction
1246system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction
1247system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction
1248system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1249system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction
1250system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached
1251system.cpu1.rob.rob_reads 23719092 # The number of ROB reads
1252system.cpu1.rob.rob_writes 20805392 # The number of ROB writes
1253system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself
1254system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling
1255system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1256system.cpu1.committedInsts 8318863 # Number of Instructions Simulated
1257system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated
1258system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction
1259system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads
1260system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle
1261system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads
1262system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads
1263system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes
1264system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads
1265system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes
1266system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads
1267system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes
1268system.cpu1.dcache.tags.replacements 98586 # number of replacements
1269system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use
1270system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks.
1271system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks.
1272system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks.
1273system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit.
1274system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor
1275system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy
1276system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy
1277system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
1278system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
1279system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id
1280system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses
1281system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses
1282system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits
1283system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits
1284system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits
1285system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits
1286system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits
1287system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits
1288system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits
1289system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits
1290system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits
1291system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits
1292system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits
1293system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits
1294system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses
1295system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses
1296system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses
1297system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses
1298system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses
1299system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses
1300system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses
1301system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses
1302system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses
1303system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses
1304system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses
1305system.cpu1.dcache.overall_misses::total 379686 # number of overall misses
1306system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles
1307system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles
1308system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles
1309system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles
1310system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles
1311system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles
1312system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles
1313system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles
1314system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles
1315system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles
1316system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles
1317system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles
1318system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses)
1319system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses)
1320system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses)
1321system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses)
1322system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses)
1323system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses)
1324system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses)
1325system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses)
1326system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses
1327system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses
1328system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses
1329system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses
1330system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses
1331system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses
1332system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses
1333system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses
1334system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses
1335system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses
1336system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses
1337system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses
1338system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses
1339system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses
1340system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses
1341system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses
1342system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency
1343system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency
1344system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency
1345system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency
1346system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency
1347system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency
1348system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency
1349system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency
1350system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency
1351system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency
1352system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency
1353system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency
1354system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked
1355system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked
1356system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked
1357system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked
1358system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked
1359system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked
1360system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1361system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1362system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks
1363system.cpu1.dcache.writebacks::total 63787 # number of writebacks
1364system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits
1365system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits
1366system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits
1367system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits
1368system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits
1369system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits
1370system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits
1371system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits
1372system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits
1373system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits
1374system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses
1375system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses
1376system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses
1377system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses
1378system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses
1379system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses
1380system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses
1381system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses
1382system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses
1383system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses
1384system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses
1385system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses
1386system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable
1387system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable
1388system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable
1389system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable
1390system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses
1391system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses
1392system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles
1393system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles
1394system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles
1395system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles
1396system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles
1397system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles
1398system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles
1399system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles
1400system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles
1401system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles
1402system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles
1403system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles
1404system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles
1405system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles
1406system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles
1407system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles
1408system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles
1409system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles
1410system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses
1411system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses
1412system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses
1413system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses
1414system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses
1415system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses
1416system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses
1417system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses
1418system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses
1419system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses
1420system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses
1421system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses
1422system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency
1423system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency
1424system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency
1425system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency
1426system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency
1427system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency
1428system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency
1429system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency
1430system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency
1431system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency
1432system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency
1433system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency
1434system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency
1435system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency
1436system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency
1437system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency
1438system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency
1439system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency
1440system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1441system.cpu1.icache.tags.replacements 222828 # number of replacements
1442system.cpu1.icache.tags.tagsinuse 467.348174 # Cycle average of tags in use
1443system.cpu1.icache.tags.total_refs 1300089 # Total number of references to valid blocks.
1444system.cpu1.icache.tags.sampled_refs 223338 # Sample count of references to valid blocks.
1445system.cpu1.icache.tags.avg_refs 5.821172 # Average number of references to valid blocks.
1446system.cpu1.icache.tags.warmup_cycle 1895764140500 # Cycle when the warmup percentage was hit.
1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.348174 # Average occupied blocks per requestor
1448system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912789 # Average percentage of cache occupancy
1449system.cpu1.icache.tags.occ_percent::total 0.912789 # Average percentage of cache occupancy
1450system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
1451system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id
1452system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
1453system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses
1454system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses
1455system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits
1456system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits
1457system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits
1458system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits
1459system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits
1460system.cpu1.icache.overall_hits::total 1300089 # number of overall hits
1461system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses
1462system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses
1463system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses
1464system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses
1465system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses
1466system.cpu1.icache.overall_misses::total 230461 # number of overall misses
1467system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles
1468system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles
1469system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles
1470system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles
1471system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles
1472system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles
1473system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses)
1474system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses)
1475system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses
1476system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses
1477system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses
1478system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses
1479system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses
1480system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses
1481system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses
1482system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses
1483system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses
1484system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses
1485system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency
1486system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency
1487system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency
1488system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency
1489system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency
1490system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency
1491system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked
1492system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1493system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked
1494system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1495system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked
1496system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1497system.cpu1.icache.fast_writes 0 # number of fast writes performed
1498system.cpu1.icache.cache_copies 0 # number of cache copies performed
1499system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits
1500system.cpu1.icache.ReadReq_mshr_hits::total 7062 # number of ReadReq MSHR hits
1501system.cpu1.icache.demand_mshr_hits::cpu1.inst 7062 # number of demand (read+write) MSHR hits
1502system.cpu1.icache.demand_mshr_hits::total 7062 # number of demand (read+write) MSHR hits
1503system.cpu1.icache.overall_mshr_hits::cpu1.inst 7062 # number of overall MSHR hits
1504system.cpu1.icache.overall_mshr_hits::total 7062 # number of overall MSHR hits
1505system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223399 # number of ReadReq MSHR misses
1506system.cpu1.icache.ReadReq_mshr_misses::total 223399 # number of ReadReq MSHR misses
1507system.cpu1.icache.demand_mshr_misses::cpu1.inst 223399 # number of demand (read+write) MSHR misses
1508system.cpu1.icache.demand_mshr_misses::total 223399 # number of demand (read+write) MSHR misses
1509system.cpu1.icache.overall_mshr_misses::cpu1.inst 223399 # number of overall MSHR misses
1510system.cpu1.icache.overall_mshr_misses::total 223399 # number of overall MSHR misses
1511system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles
1512system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles
1513system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles
1514system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles
1515system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles
1516system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles
1517system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses
1518system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses
1519system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses
1520system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses
1521system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses
1522system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses
1523system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency
1524system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency
1525system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency
1526system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency
1527system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency
1528system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency
1529system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1530system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1531system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1532system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1533system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1534system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1535system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1536system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1537system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1538system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1539system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1540system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1541system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1542system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
1543system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
1544system.iobus.trans_dist::WriteReq 54607 # Transaction distribution
1545system.iobus.trans_dist::WriteResp 54607 # Transaction distribution
1546system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes)
1547system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
1548system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1549system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1550system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1551system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1552system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
1553system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1554system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1555system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1556system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1557system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1558system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes)
1559system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
1560system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
1561system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes)
1562system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes)
1563system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
1564system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1565system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1566system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1567system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1568system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
1569system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1570system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1571system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1572system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1573system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1574system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes)
1575system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
1576system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
1577system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes)
1578system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks)
1579system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1580system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
1581system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1582system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1583system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1584system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1585system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1586system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1587system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1588system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1589system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1590system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
1591system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1592system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1593system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1594system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1595system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1596system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1597system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1598system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1599system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1600system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks)
1601system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1602system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1603system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1604system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks)
1605system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1606system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks)
1607system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1608system.iocache.tags.replacements 41696 # number of replacements
1609system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use
1610system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1611system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks.
1612system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1613system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit.
1614system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor
1615system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy
1616system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy
1617system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1618system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1619system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1620system.iocache.tags.tag_accesses 375552 # Number of tag accesses
1621system.iocache.tags.data_accesses 375552 # Number of data accesses
1622system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
1623system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
1624system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1625system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1626system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
1627system.iocache.demand_misses::total 176 # number of demand (read+write) misses
1628system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
1629system.iocache.overall_misses::total 176 # number of overall misses
1630system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles
1631system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles
1632system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles
1633system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles
1634system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles
1635system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles
1636system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles
1637system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles
1638system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
1639system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
1640system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1641system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1642system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
1643system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
1644system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
1645system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
1646system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1647system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1648system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1649system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1650system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1651system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1652system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1653system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1654system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency
1655system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency
1656system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency
1657system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency
1658system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency
1659system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency
1660system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency
1661system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency
1662system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked
1663system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1664system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
1665system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1666system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked
1667system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1668system.iocache.fast_writes 0 # number of fast writes performed
1669system.iocache.cache_copies 0 # number of cache copies performed
1670system.iocache.writebacks::writebacks 41520 # number of writebacks
1671system.iocache.writebacks::total 41520 # number of writebacks
1672system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
1673system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
1674system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1675system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1676system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
1677system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
1678system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
1679system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
1680system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles
1681system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles
1682system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # number of WriteLineReq MSHR miss cycles
1683system.iocache.WriteLineReq_mshr_miss_latency::total 3350397858 # number of WriteLineReq MSHR miss cycles
1684system.iocache.demand_mshr_miss_latency::tsunami.ide 13449883 # number of demand (read+write) MSHR miss cycles
1685system.iocache.demand_mshr_miss_latency::total 13449883 # number of demand (read+write) MSHR miss cycles
1686system.iocache.overall_mshr_miss_latency::tsunami.ide 13449883 # number of overall MSHR miss cycles
1687system.iocache.overall_mshr_miss_latency::total 13449883 # number of overall MSHR miss cycles
1688system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1689system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1690system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1691system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1692system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1693system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1694system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1695system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1696system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency
1697system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency
1698system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency
1699system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency
1700system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency
1701system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency
1702system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency
1703system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency
1704system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1705system.l2c.tags.replacements 344948 # number of replacements
1706system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use
1707system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks.
1708system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks.
1709system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks.
1710system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit.
1711system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor
1712system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor
1713system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor
1714system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor
1715system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor
1716system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy
1717system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy
1718system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy
1719system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy
1720system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy
1721system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy
1722system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id
1723system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
1724system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id
1725system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id
1726system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id
1727system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id
1728system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id
1729system.l2c.tags.tag_accesses 38374495 # Number of tag accesses
1730system.l2c.tags.data_accesses 38374495 # Number of data accesses
1731system.l2c.Writeback_hits::writebacks 820011 # number of Writeback hits
1732system.l2c.Writeback_hits::total 820011 # number of Writeback hits
1733system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits
1734system.l2c.UpgradeReq_hits::cpu1.data 256 # number of UpgradeReq hits
1735system.l2c.UpgradeReq_hits::total 437 # number of UpgradeReq hits
1736system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits
1737system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits
1738system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits
1739system.l2c.ReadExReq_hits::cpu0.data 155441 # number of ReadExReq hits
1740system.l2c.ReadExReq_hits::cpu1.data 22735 # number of ReadExReq hits
1741system.l2c.ReadExReq_hits::total 178176 # number of ReadExReq hits
1742system.l2c.ReadCleanReq_hits::cpu0.inst 896343 # number of ReadCleanReq hits
1743system.l2c.ReadCleanReq_hits::cpu1.inst 221742 # number of ReadCleanReq hits
1744system.l2c.ReadCleanReq_hits::total 1118085 # number of ReadCleanReq hits
1745system.l2c.ReadSharedReq_hits::cpu0.data 736901 # number of ReadSharedReq hits
1746system.l2c.ReadSharedReq_hits::cpu1.data 66152 # number of ReadSharedReq hits
1747system.l2c.ReadSharedReq_hits::total 803053 # number of ReadSharedReq hits
1748system.l2c.demand_hits::cpu0.inst 896343 # number of demand (read+write) hits
1749system.l2c.demand_hits::cpu0.data 892342 # number of demand (read+write) hits
1750system.l2c.demand_hits::cpu1.inst 221742 # number of demand (read+write) hits
1751system.l2c.demand_hits::cpu1.data 88887 # number of demand (read+write) hits
1752system.l2c.demand_hits::total 2099314 # number of demand (read+write) hits
1753system.l2c.overall_hits::cpu0.inst 896343 # number of overall hits
1754system.l2c.overall_hits::cpu0.data 892342 # number of overall hits
1755system.l2c.overall_hits::cpu1.inst 221742 # number of overall hits
1756system.l2c.overall_hits::cpu1.data 88887 # number of overall hits
1757system.l2c.overall_hits::total 2099314 # number of overall hits
1758system.l2c.UpgradeReq_misses::cpu0.data 2756 # number of UpgradeReq misses
1759system.l2c.UpgradeReq_misses::cpu1.data 1092 # number of UpgradeReq misses
1760system.l2c.UpgradeReq_misses::total 3848 # number of UpgradeReq misses
1761system.l2c.SCUpgradeReq_misses::cpu0.data 412 # number of SCUpgradeReq misses
1762system.l2c.SCUpgradeReq_misses::cpu1.data 449 # number of SCUpgradeReq misses
1763system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses
1764system.l2c.ReadExReq_misses::cpu0.data 114759 # number of ReadExReq misses
1765system.l2c.ReadExReq_misses::cpu1.data 7322 # number of ReadExReq misses
1766system.l2c.ReadExReq_misses::total 122081 # number of ReadExReq misses
1767system.l2c.ReadCleanReq_misses::cpu0.inst 13662 # number of ReadCleanReq misses
1768system.l2c.ReadCleanReq_misses::cpu1.inst 1628 # number of ReadCleanReq misses
1769system.l2c.ReadCleanReq_misses::total 15290 # number of ReadCleanReq misses
1770system.l2c.ReadSharedReq_misses::cpu0.data 272997 # number of ReadSharedReq misses
1771system.l2c.ReadSharedReq_misses::cpu1.data 824 # number of ReadSharedReq misses
1772system.l2c.ReadSharedReq_misses::total 273821 # number of ReadSharedReq misses
1773system.l2c.demand_misses::cpu0.inst 13662 # number of demand (read+write) misses
1774system.l2c.demand_misses::cpu0.data 387756 # number of demand (read+write) misses
1775system.l2c.demand_misses::cpu1.inst 1628 # number of demand (read+write) misses
1776system.l2c.demand_misses::cpu1.data 8146 # number of demand (read+write) misses
1777system.l2c.demand_misses::total 411192 # number of demand (read+write) misses
1778system.l2c.overall_misses::cpu0.inst 13662 # number of overall misses
1779system.l2c.overall_misses::cpu0.data 387756 # number of overall misses
1780system.l2c.overall_misses::cpu1.inst 1628 # number of overall misses
1781system.l2c.overall_misses::cpu1.data 8146 # number of overall misses
1782system.l2c.overall_misses::total 411192 # number of overall misses
1783system.l2c.UpgradeReq_miss_latency::cpu0.data 3749500 # number of UpgradeReq miss cycles
1784system.l2c.UpgradeReq_miss_latency::cpu1.data 17004000 # number of UpgradeReq miss cycles
1785system.l2c.UpgradeReq_miss_latency::total 20753500 # number of UpgradeReq miss cycles
1786system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2598000 # number of SCUpgradeReq miss cycles
1787system.l2c.SCUpgradeReq_miss_latency::cpu1.data 405500 # number of SCUpgradeReq miss cycles
1788system.l2c.SCUpgradeReq_miss_latency::total 3003500 # number of SCUpgradeReq miss cycles
1789system.l2c.ReadExReq_miss_latency::cpu0.data 15999286000 # number of ReadExReq miss cycles
1790system.l2c.ReadExReq_miss_latency::cpu1.data 1158590000 # number of ReadExReq miss cycles
1791system.l2c.ReadExReq_miss_latency::total 17157876000 # number of ReadExReq miss cycles
1792system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1831463500 # number of ReadCleanReq miss cycles
1793system.l2c.ReadCleanReq_miss_latency::cpu1.inst 221176500 # number of ReadCleanReq miss cycles
1794system.l2c.ReadCleanReq_miss_latency::total 2052640000 # number of ReadCleanReq miss cycles
1795system.l2c.ReadSharedReq_miss_latency::cpu0.data 33895753500 # number of ReadSharedReq miss cycles
1796system.l2c.ReadSharedReq_miss_latency::cpu1.data 116047500 # number of ReadSharedReq miss cycles
1797system.l2c.ReadSharedReq_miss_latency::total 34011801000 # number of ReadSharedReq miss cycles
1798system.l2c.demand_miss_latency::cpu0.inst 1831463500 # number of demand (read+write) miss cycles
1799system.l2c.demand_miss_latency::cpu0.data 49895039500 # number of demand (read+write) miss cycles
1800system.l2c.demand_miss_latency::cpu1.inst 221176500 # number of demand (read+write) miss cycles
1801system.l2c.demand_miss_latency::cpu1.data 1274637500 # number of demand (read+write) miss cycles
1802system.l2c.demand_miss_latency::total 53222317000 # number of demand (read+write) miss cycles
1803system.l2c.overall_miss_latency::cpu0.inst 1831463500 # number of overall miss cycles
1804system.l2c.overall_miss_latency::cpu0.data 49895039500 # number of overall miss cycles
1805system.l2c.overall_miss_latency::cpu1.inst 221176500 # number of overall miss cycles
1806system.l2c.overall_miss_latency::cpu1.data 1274637500 # number of overall miss cycles
1807system.l2c.overall_miss_latency::total 53222317000 # number of overall miss cycles
1808system.l2c.Writeback_accesses::writebacks 820011 # number of Writeback accesses(hits+misses)
1809system.l2c.Writeback_accesses::total 820011 # number of Writeback accesses(hits+misses)
1810system.l2c.UpgradeReq_accesses::cpu0.data 2937 # number of UpgradeReq accesses(hits+misses)
1811system.l2c.UpgradeReq_accesses::cpu1.data 1348 # number of UpgradeReq accesses(hits+misses)
1812system.l2c.UpgradeReq_accesses::total 4285 # number of UpgradeReq accesses(hits+misses)
1813system.l2c.SCUpgradeReq_accesses::cpu0.data 461 # number of SCUpgradeReq accesses(hits+misses)
1814system.l2c.SCUpgradeReq_accesses::cpu1.data 475 # number of SCUpgradeReq accesses(hits+misses)
1815system.l2c.SCUpgradeReq_accesses::total 936 # number of SCUpgradeReq accesses(hits+misses)
1816system.l2c.ReadExReq_accesses::cpu0.data 270200 # number of ReadExReq accesses(hits+misses)
1817system.l2c.ReadExReq_accesses::cpu1.data 30057 # number of ReadExReq accesses(hits+misses)
1818system.l2c.ReadExReq_accesses::total 300257 # number of ReadExReq accesses(hits+misses)
1819system.l2c.ReadCleanReq_accesses::cpu0.inst 910005 # number of ReadCleanReq accesses(hits+misses)
1820system.l2c.ReadCleanReq_accesses::cpu1.inst 223370 # number of ReadCleanReq accesses(hits+misses)
1821system.l2c.ReadCleanReq_accesses::total 1133375 # number of ReadCleanReq accesses(hits+misses)
1822system.l2c.ReadSharedReq_accesses::cpu0.data 1009898 # number of ReadSharedReq accesses(hits+misses)
1823system.l2c.ReadSharedReq_accesses::cpu1.data 66976 # number of ReadSharedReq accesses(hits+misses)
1824system.l2c.ReadSharedReq_accesses::total 1076874 # number of ReadSharedReq accesses(hits+misses)
1825system.l2c.demand_accesses::cpu0.inst 910005 # number of demand (read+write) accesses
1826system.l2c.demand_accesses::cpu0.data 1280098 # number of demand (read+write) accesses
1827system.l2c.demand_accesses::cpu1.inst 223370 # number of demand (read+write) accesses
1828system.l2c.demand_accesses::cpu1.data 97033 # number of demand (read+write) accesses
1829system.l2c.demand_accesses::total 2510506 # number of demand (read+write) accesses
1830system.l2c.overall_accesses::cpu0.inst 910005 # number of overall (read+write) accesses
1831system.l2c.overall_accesses::cpu0.data 1280098 # number of overall (read+write) accesses
1832system.l2c.overall_accesses::cpu1.inst 223370 # number of overall (read+write) accesses
1833system.l2c.overall_accesses::cpu1.data 97033 # number of overall (read+write) accesses
1834system.l2c.overall_accesses::total 2510506 # number of overall (read+write) accesses
1835system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938372 # miss rate for UpgradeReq accesses
1836system.l2c.UpgradeReq_miss_rate::cpu1.data 0.810089 # miss rate for UpgradeReq accesses
1837system.l2c.UpgradeReq_miss_rate::total 0.898016 # miss rate for UpgradeReq accesses
1838system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.893709 # miss rate for SCUpgradeReq accesses
1839system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945263 # miss rate for SCUpgradeReq accesses
1840system.l2c.SCUpgradeReq_miss_rate::total 0.919872 # miss rate for SCUpgradeReq accesses
1841system.l2c.ReadExReq_miss_rate::cpu0.data 0.424719 # miss rate for ReadExReq accesses
1842system.l2c.ReadExReq_miss_rate::cpu1.data 0.243604 # miss rate for ReadExReq accesses
1843system.l2c.ReadExReq_miss_rate::total 0.406588 # miss rate for ReadExReq accesses
1844system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015013 # miss rate for ReadCleanReq accesses
1845system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007288 # miss rate for ReadCleanReq accesses
1846system.l2c.ReadCleanReq_miss_rate::total 0.013491 # miss rate for ReadCleanReq accesses
1847system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.270321 # miss rate for ReadSharedReq accesses
1848system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.012303 # miss rate for ReadSharedReq accesses
1849system.l2c.ReadSharedReq_miss_rate::total 0.254274 # miss rate for ReadSharedReq accesses
1850system.l2c.demand_miss_rate::cpu0.inst 0.015013 # miss rate for demand accesses
1851system.l2c.demand_miss_rate::cpu0.data 0.302911 # miss rate for demand accesses
1852system.l2c.demand_miss_rate::cpu1.inst 0.007288 # miss rate for demand accesses
1853system.l2c.demand_miss_rate::cpu1.data 0.083951 # miss rate for demand accesses
1854system.l2c.demand_miss_rate::total 0.163788 # miss rate for demand accesses
1855system.l2c.overall_miss_rate::cpu0.inst 0.015013 # miss rate for overall accesses
1856system.l2c.overall_miss_rate::cpu0.data 0.302911 # miss rate for overall accesses
1857system.l2c.overall_miss_rate::cpu1.inst 0.007288 # miss rate for overall accesses
1858system.l2c.overall_miss_rate::cpu1.data 0.083951 # miss rate for overall accesses
1859system.l2c.overall_miss_rate::total 0.163788 # miss rate for overall accesses
1860system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1360.486212 # average UpgradeReq miss latency
1861system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15571.428571 # average UpgradeReq miss latency
1862system.l2c.UpgradeReq_avg_miss_latency::total 5393.321206 # average UpgradeReq miss latency
1863system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6305.825243 # average SCUpgradeReq miss latency
1864system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 903.118040 # average SCUpgradeReq miss latency
1865system.l2c.SCUpgradeReq_avg_miss_latency::total 3488.385598 # average SCUpgradeReq miss latency
1866system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139416.394357 # average ReadExReq miss latency
1867system.l2c.ReadExReq_avg_miss_latency::cpu1.data 158234.089047 # average ReadExReq miss latency
1868system.l2c.ReadExReq_avg_miss_latency::total 140545.015195 # average ReadExReq miss latency
1869system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 134055.299371 # average ReadCleanReq miss latency
1870system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135857.800983 # average ReadCleanReq miss latency
1871system.l2c.ReadCleanReq_avg_miss_latency::total 134247.220405 # average ReadCleanReq miss latency
1872system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124161.633644 # average ReadSharedReq miss latency
1873system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140834.344660 # average ReadSharedReq miss latency
1874system.l2c.ReadSharedReq_avg_miss_latency::total 124211.806253 # average ReadSharedReq miss latency
1875system.l2c.demand_avg_miss_latency::cpu0.inst 134055.299371 # average overall miss latency
1876system.l2c.demand_avg_miss_latency::cpu0.data 128676.382828 # average overall miss latency
1877system.l2c.demand_avg_miss_latency::cpu1.inst 135857.800983 # average overall miss latency
1878system.l2c.demand_avg_miss_latency::cpu1.data 156474.036337 # average overall miss latency
1879system.l2c.demand_avg_miss_latency::total 129434.222942 # average overall miss latency
1880system.l2c.overall_avg_miss_latency::cpu0.inst 134055.299371 # average overall miss latency
1881system.l2c.overall_avg_miss_latency::cpu0.data 128676.382828 # average overall miss latency
1882system.l2c.overall_avg_miss_latency::cpu1.inst 135857.800983 # average overall miss latency
1883system.l2c.overall_avg_miss_latency::cpu1.data 156474.036337 # average overall miss latency
1884system.l2c.overall_avg_miss_latency::total 129434.222942 # average overall miss latency
1885system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1886system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1887system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1888system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1889system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1890system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1891system.l2c.fast_writes 0 # number of fast writes performed
1892system.l2c.cache_copies 0 # number of cache copies performed
1893system.l2c.writebacks::writebacks 81529 # number of writebacks
1894system.l2c.writebacks::total 81529 # number of writebacks
1895system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
1896system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits
1897system.l2c.ReadCleanReq_mshr_hits::total 19 # number of ReadCleanReq MSHR hits
1898system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
1899system.l2c.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits
1900system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
1901system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
1902system.l2c.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits
1903system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
1904system.l2c.CleanEvict_mshr_misses::writebacks 355 # number of CleanEvict MSHR misses
1905system.l2c.CleanEvict_mshr_misses::total 355 # number of CleanEvict MSHR misses
1906system.l2c.UpgradeReq_mshr_misses::cpu0.data 2756 # number of UpgradeReq MSHR misses
1907system.l2c.UpgradeReq_mshr_misses::cpu1.data 1092 # number of UpgradeReq MSHR misses
1908system.l2c.UpgradeReq_mshr_misses::total 3848 # number of UpgradeReq MSHR misses
1909system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 412 # number of SCUpgradeReq MSHR misses
1910system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 449 # number of SCUpgradeReq MSHR misses
1911system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses
1912system.l2c.ReadExReq_mshr_misses::cpu0.data 114759 # number of ReadExReq MSHR misses
1913system.l2c.ReadExReq_mshr_misses::cpu1.data 7322 # number of ReadExReq MSHR misses
1914system.l2c.ReadExReq_mshr_misses::total 122081 # number of ReadExReq MSHR misses
1915system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13661 # number of ReadCleanReq MSHR misses
1916system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1610 # number of ReadCleanReq MSHR misses
1917system.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses
1918system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272997 # number of ReadSharedReq MSHR misses
1919system.l2c.ReadSharedReq_mshr_misses::cpu1.data 824 # number of ReadSharedReq MSHR misses
1920system.l2c.ReadSharedReq_mshr_misses::total 273821 # number of ReadSharedReq MSHR misses
1921system.l2c.demand_mshr_misses::cpu0.inst 13661 # number of demand (read+write) MSHR misses
1922system.l2c.demand_mshr_misses::cpu0.data 387756 # number of demand (read+write) MSHR misses
1923system.l2c.demand_mshr_misses::cpu1.inst 1610 # number of demand (read+write) MSHR misses
1924system.l2c.demand_mshr_misses::cpu1.data 8146 # number of demand (read+write) MSHR misses
1925system.l2c.demand_mshr_misses::total 411173 # number of demand (read+write) MSHR misses
1926system.l2c.overall_mshr_misses::cpu0.inst 13661 # number of overall MSHR misses
1927system.l2c.overall_mshr_misses::cpu0.data 387756 # number of overall MSHR misses
1928system.l2c.overall_mshr_misses::cpu1.inst 1610 # number of overall MSHR misses
1929system.l2c.overall_mshr_misses::cpu1.data 8146 # number of overall MSHR misses
1930system.l2c.overall_mshr_misses::total 411173 # number of overall MSHR misses
1931system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable
1932system.l2c.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable
1933system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable
1934system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable
1935system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable
1936system.l2c.WriteReq_mshr_uncacheable::total 13055 # number of WriteReq MSHR uncacheable
1937system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses
1938system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses
1939system.l2c.overall_mshr_uncacheable_misses::total 20250 # number of overall MSHR uncacheable misses
1940system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 197825500 # number of UpgradeReq MSHR miss cycles
1941system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 78287000 # number of UpgradeReq MSHR miss cycles
1942system.l2c.UpgradeReq_mshr_miss_latency::total 276112500 # number of UpgradeReq MSHR miss cycles
1943system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29369500 # number of SCUpgradeReq MSHR miss cycles
1944system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32234000 # number of SCUpgradeReq MSHR miss cycles
1945system.l2c.SCUpgradeReq_mshr_miss_latency::total 61603500 # number of SCUpgradeReq MSHR miss cycles
1946system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14851696000 # number of ReadExReq MSHR miss cycles
1947system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1085370000 # number of ReadExReq MSHR miss cycles
1948system.l2c.ReadExReq_mshr_miss_latency::total 15937066000 # number of ReadExReq MSHR miss cycles
1949system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1694708500 # number of ReadCleanReq MSHR miss cycles
1950system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 202919000 # number of ReadCleanReq MSHR miss cycles
1951system.l2c.ReadCleanReq_mshr_miss_latency::total 1897627500 # number of ReadCleanReq MSHR miss cycles
1952system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31174991500 # number of ReadSharedReq MSHR miss cycles
1953system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 107807500 # number of ReadSharedReq MSHR miss cycles
1954system.l2c.ReadSharedReq_mshr_miss_latency::total 31282799000 # number of ReadSharedReq MSHR miss cycles
1955system.l2c.demand_mshr_miss_latency::cpu0.inst 1694708500 # number of demand (read+write) MSHR miss cycles
1956system.l2c.demand_mshr_miss_latency::cpu0.data 46026687500 # number of demand (read+write) MSHR miss cycles
1957system.l2c.demand_mshr_miss_latency::cpu1.inst 202919000 # number of demand (read+write) MSHR miss cycles
1958system.l2c.demand_mshr_miss_latency::cpu1.data 1193177500 # number of demand (read+write) MSHR miss cycles
1959system.l2c.demand_mshr_miss_latency::total 49117492500 # number of demand (read+write) MSHR miss cycles
1960system.l2c.overall_mshr_miss_latency::cpu0.inst 1694708500 # number of overall MSHR miss cycles
1961system.l2c.overall_mshr_miss_latency::cpu0.data 46026687500 # number of overall MSHR miss cycles
1962system.l2c.overall_mshr_miss_latency::cpu1.inst 202919000 # number of overall MSHR miss cycles
1963system.l2c.overall_mshr_miss_latency::cpu1.data 1193177500 # number of overall MSHR miss cycles
1964system.l2c.overall_mshr_miss_latency::total 49117492500 # number of overall MSHR miss cycles
1965system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1394464000 # number of ReadReq MSHR uncacheable cycles
1966system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 26594500 # number of ReadReq MSHR uncacheable cycles
1967system.l2c.ReadReq_mshr_uncacheable_latency::total 1421058500 # number of ReadReq MSHR uncacheable cycles
1968system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2057508000 # number of WriteReq MSHR uncacheable cycles
1969system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 612939000 # number of WriteReq MSHR uncacheable cycles
1970system.l2c.WriteReq_mshr_uncacheable_latency::total 2670447000 # number of WriteReq MSHR uncacheable cycles
1971system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3451972000 # number of overall MSHR uncacheable cycles
1972system.l2c.overall_mshr_uncacheable_latency::cpu1.data 639533500 # number of overall MSHR uncacheable cycles
1973system.l2c.overall_mshr_uncacheable_latency::total 4091505500 # number of overall MSHR uncacheable cycles
1974system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1975system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1976system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938372 # mshr miss rate for UpgradeReq accesses
1977system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.810089 # mshr miss rate for UpgradeReq accesses
1978system.l2c.UpgradeReq_mshr_miss_rate::total 0.898016 # mshr miss rate for UpgradeReq accesses
1979system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.893709 # mshr miss rate for SCUpgradeReq accesses
1980system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945263 # mshr miss rate for SCUpgradeReq accesses
1981system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.919872 # mshr miss rate for SCUpgradeReq accesses
1982system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424719 # mshr miss rate for ReadExReq accesses
1983system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.243604 # mshr miss rate for ReadExReq accesses
1984system.l2c.ReadExReq_mshr_miss_rate::total 0.406588 # mshr miss rate for ReadExReq accesses
1985system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for ReadCleanReq accesses
1986system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for ReadCleanReq accesses
1987system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013474 # mshr miss rate for ReadCleanReq accesses
1988system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270321 # mshr miss rate for ReadSharedReq accesses
1989system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses
1990system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses
1991system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses
1992system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses
1993system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses
1994system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses
1995system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses
1996system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses
1997system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses
1998system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses
1999system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses
2000system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses
2001system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency
2002system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency
2003system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency
2004system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency
2005system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency
2006system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency
2007system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency
2008system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency
2009system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency
2010system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency
2011system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency
2012system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency
2013system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency
2014system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency
2015system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency
2016system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency
2017system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency
2018system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency
2019system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency
2020system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency
2021system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency
2022system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency
2023system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency
2024system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency
2025system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency
2026system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency
2027system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency
2028system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency
2029system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency
2030system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency
2031system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency
2032system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency
2033system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency
2034system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency
2035system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2036system.membus.trans_dist::ReadReq 7195 # Transaction distribution
2037system.membus.trans_dist::ReadResp 296388 # Transaction distribution
2038system.membus.trans_dist::WriteReq 13055 # Transaction distribution
2039system.membus.trans_dist::WriteResp 13055 # Transaction distribution
2040system.membus.trans_dist::Writeback 123049 # Transaction distribution
2041system.membus.trans_dist::CleanEvict 262884 # Transaction distribution
2042system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution
2043system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution
2044system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution
2045system.membus.trans_dist::ReadExReq 122086 # Transaction distribution
2046system.membus.trans_dist::ReadExResp 121678 # Transaction distribution
2047system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution
2048system.membus.trans_dist::BadAddressError 75 # Transaction distribution
2049system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
2050system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
2051system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes)
2052system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes)
2053system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes)
2054system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes)
2055system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes)
2056system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes)
2057system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes)
2058system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes)
2059system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes)
2060system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes)
2061system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
2062system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
2063system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes)
2064system.membus.snoops 11781 # Total snoops (count)
2065system.membus.snoop_fanout::samples 875308 # Request fanout histogram
2066system.membus.snoop_fanout::mean 1 # Request fanout histogram
2067system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2068system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2069system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2070system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram
2071system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2072system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2073system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2074system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2075system.membus.snoop_fanout::total 875308 # Request fanout histogram
2076system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks)
2077system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2078system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks)
2079system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2080system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks)
2081system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2082system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks)
2083system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2084system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks)
2085system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2086system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter.
2087system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2088system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2089system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter.
2090system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2091system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2092system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution
2093system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution
2094system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution
2095system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution
2096system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution
2097system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution
2098system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution
2099system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution
2100system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution
2101system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution
2102system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution
2103system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution
2104system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution
2105system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution
2106system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
2107system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes)
2108system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes)
2109system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes)
2110system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes)
2111system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes)
2112system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes)
2113system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes)
2114system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes)
2115system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes)
2116system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes)
2117system.toL2Bus.snoops 462162 # Total snoops (count)
2118system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram
2119system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram
2120system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram
2121system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2122system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram
2123system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram
2124system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram
2125system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram
2126system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
2127system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2128system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2129system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
2130system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram
2131system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks)
2132system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2133system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks)
2134system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2135system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks)
2136system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2137system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks)
2138system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2139system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks)
2140system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2141system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks)
2142system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2143system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2144system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2145system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2146system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2147system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2148system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2149system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 17 unchanged lines hidden (view full) ---

2167system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2168system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2169system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2170system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2171system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2172system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
2173system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2174system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2175system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed
2176system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed
2177system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl
2178system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl
2179system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl
2180system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl
2181system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl
2182system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl
2183system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl
2184system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
2185system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl
2186system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl
2187system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl
2188system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl
2189system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl
2190system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl
2191system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl
2192system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl
2193system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl
2194system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl
2195system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl
2196system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
2197system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2198system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2199system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl
2200system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl
2201system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed
2202system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed
2203system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed
2204system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed
2205system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed
2206system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed
2207system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed
2208system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed
2209system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed
2210system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed
2211system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed
2212system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed
2213system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed
2214system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed
2215system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed
2216system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed
2217system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed
2218system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed
2219system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed
2220system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed
2221system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed
2222system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed
2223system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed
2224system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed
2225system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed
2226system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed
2227system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed
2228system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
2229system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
2230system.cpu0.kern.syscall::total 228 # number of syscalls executed
2231system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2232system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed
2233system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
2234system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
2235system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
2236system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed
2237system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed
2238system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
2239system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed
2240system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed
2241system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
2242system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed
2243system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed
2244system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
2245system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed
2246system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed
2247system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed
2248system.cpu0.kern.callpal::total 169199 # number of callpals executed
2249system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches
2250system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches
2251system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2252system.cpu0.kern.mode_good::kernel 1346
2253system.cpu0.kern.mode_good::user 1347
2254system.cpu0.kern.mode_good::idle 0
2255system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches
2256system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2257system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2258system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches
2259system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode
2260system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode
2261system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2262system.cpu0.kern.swap_context 3534 # number of times the context was actually changed
2263system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2264system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed
2265system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed
2266system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl
2267system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl
2268system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl
2269system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl
2270system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl
2271system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl
2272system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl
2273system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl
2274system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl
2275system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl
2276system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl
2277system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl
2278system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl
2279system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl
2280system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl
2281system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl
2282system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2283system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2284system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl
2285system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl
2286system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed
2287system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed
2288system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed
2289system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed
2290system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed
2291system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed
2292system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed
2293system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed
2294system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed
2295system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed
2296system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed
2297system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed
2298system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed
2299system.cpu1.kern.syscall::total 98 # number of syscalls executed
2300system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2301system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed
2302system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed
2303system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed
2304system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed
2305system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed
2306system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed
2307system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed
2308system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed
2309system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed
2310system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed
2311system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed
2312system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed
2313system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed
2314system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
2315system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2316system.cpu1.kern.callpal::total 48843 # number of callpals executed
2317system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches
2318system.cpu1.kern.mode_switch::user 392 # number of protection mode switches
2319system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches
2320system.cpu1.kern.mode_good::kernel 600
2321system.cpu1.kern.mode_good::user 392
2322system.cpu1.kern.mode_good::idle 208
2323system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches
2324system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2325system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches
2326system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches
2327system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode
2328system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode
2329system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode
2330system.cpu1.kern.swap_context 1057 # number of times the context was actually changed
2331
2332---------- End Simulation Statistics ----------