1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.901187 # Number of seconds simulated
4sim_ticks 1901187238000 # Number of ticks simulated
5final_tick 1901187238000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 164685 # Simulator instruction rate (inst/s)
8host_op_rate 164685 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5473626023 # Simulator tick rate (ticks/s)
10host_mem_usage 324480 # Number of bytes of host memory used
11host_seconds 347.34 # Real time elapsed on the host
12sim_insts 57201060 # Number of instructions simulated
13sim_ops 57201060 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 886592 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24764800 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 96384 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 525056 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26273792 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 886592 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 96384 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 982976 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7873024 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7873024 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 13853 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 386950 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 1506 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 8204 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 410528 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 123016 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 123016 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 466336 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 13025966 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 50697 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 276173 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13819676 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 466336 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 50697 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 517033 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 4141109 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 4141109 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 4141109 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 466336 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 13025966 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 50697 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 276173 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17960785 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 410528 # Number of read requests accepted
54system.physmem.writeReqs 164568 # Number of write requests accepted
55system.physmem.readBursts 410528 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 164568 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26267072 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue
59system.physmem.bytesWritten 10385920 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26273792 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 10532352 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 6311 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25881 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25672 # Per bank write bursts
67system.physmem.perBankRdBursts::2 26260 # Per bank write bursts
68system.physmem.perBankRdBursts::3 25757 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25283 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25202 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25755 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25257 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25550 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25721 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25770 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25804 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25810 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25881 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25644 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25176 # Per bank write bursts
81system.physmem.perBankWrBursts::0 10943 # Per bank write bursts
82system.physmem.perBankWrBursts::1 9789 # Per bank write bursts
83system.physmem.perBankWrBursts::2 10222 # Per bank write bursts
84system.physmem.perBankWrBursts::3 9625 # Per bank write bursts
85system.physmem.perBankWrBursts::4 9290 # Per bank write bursts
86system.physmem.perBankWrBursts::5 9560 # Per bank write bursts
87system.physmem.perBankWrBursts::6 10277 # Per bank write bursts
88system.physmem.perBankWrBursts::7 9346 # Per bank write bursts
89system.physmem.perBankWrBursts::8 9649 # Per bank write bursts
90system.physmem.perBankWrBursts::9 9784 # Per bank write bursts
91system.physmem.perBankWrBursts::10 9978 # Per bank write bursts
92system.physmem.perBankWrBursts::11 10113 # Per bank write bursts
93system.physmem.perBankWrBursts::12 11182 # Per bank write bursts
94system.physmem.perBankWrBursts::13 11629 # Per bank write bursts
95system.physmem.perBankWrBursts::14 10712 # Per bank write bursts
96system.physmem.perBankWrBursts::15 10181 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
99system.physmem.totGap 1901182789000 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 410528 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 164568 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 317417 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 40637 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 43118 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 9157 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 11 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see

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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 4105 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 5616 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 7559 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 9457 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 10999 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 11504 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 12419 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 12067 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 12285 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 10644 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 9571 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 9646 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 7484 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 7228 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 7108 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 6742 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 373 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 372 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 267 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 242 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 190 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 196 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 67066 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 546.521218 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 334.319778 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 419.846112 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 14858 22.15% 22.15% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 11363 16.94% 39.10% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5157 7.69% 46.79% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 2935 4.38% 51.16% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2350 3.50% 54.67% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1701 2.54% 57.20% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1587 2.37% 59.57% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1704 2.54% 62.11% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 25411 37.89% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 67066 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 6000 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 68.402667 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2725.840527 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 5997 99.95% 99.95% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 6000 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 6000 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 27.046667 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 20.651184 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 33.190276 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-23 4953 82.55% 82.55% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-31 193 3.22% 85.77% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::32-39 289 4.82% 90.58% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::40-47 50 0.83% 91.42% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-55 96 1.60% 93.02% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::56-63 44 0.73% 93.75% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::64-71 19 0.32% 94.07% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::72-79 8 0.13% 94.20% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::80-87 23 0.38% 94.58% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::88-95 10 0.17% 94.75% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::96-103 13 0.22% 94.97% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::104-111 6 0.10% 95.07% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::112-119 7 0.12% 95.18% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::120-127 5 0.08% 95.27% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::128-135 20 0.33% 95.60% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::136-143 38 0.63% 96.23% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::144-151 17 0.28% 96.52% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::152-159 12 0.20% 96.72% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::160-167 91 1.52% 98.23% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::168-175 43 0.72% 98.95% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::176-183 17 0.28% 99.23% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::184-191 19 0.32% 99.55% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::192-199 8 0.13% 99.68% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::200-207 2 0.03% 99.72% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::208-215 9 0.15% 99.87% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::272-279 2 0.03% 100.00% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::total 6000 # Writes before turning the bus around for reads
267system.physmem.totQLat 3893190750 # Total ticks spent queuing
268system.physmem.totMemAccLat 11588622000 # Total ticks spent from burst creation until serviced by the DRAM
269system.physmem.totBusLat 2052115000 # Total ticks spent in databus transfers
270system.physmem.avgQLat 9485.80 # Average queueing delay per DRAM burst
271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
272system.physmem.avgMemAccLat 28235.80 # Average memory access latency per DRAM burst
273system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s
274system.physmem.avgWrBW 5.46 # Average achieved write bandwidth in MiByte/s
275system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s
276system.physmem.avgWrBWSys 5.54 # Average system write bandwidth in MiByte/s
277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
278system.physmem.busUtil 0.15 # Data bus utilization in percentage
279system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
280system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
281system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing
282system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing
283system.physmem.readRowHits 370176 # Number of row buffer hits during reads
284system.physmem.writeRowHits 135461 # Number of row buffer hits during writes
285system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads
286system.physmem.writeRowHitRate 83.46 # Row buffer hit rate for writes
287system.physmem.avgGap 3305852.92 # Average gap between requests
288system.physmem.pageHitRate 88.29 # Row buffer hit rate, read and write combined
289system.physmem.memoryStateTime::IDLE 1800384684500 # Time in different power states
290system.physmem.memoryStateTime::REF 63484720000 # Time in different power states
291system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
292system.physmem.memoryStateTime::ACT 37315104250 # Time in different power states
293system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
294system.physmem.actEnergy::0 252216720 # Energy for activate commands per rank (pJ)
295system.physmem.actEnergy::1 254802240 # Energy for activate commands per rank (pJ)
296system.physmem.preEnergy::0 137618250 # Energy for precharge commands per rank (pJ)
297system.physmem.preEnergy::1 139029000 # Energy for precharge commands per rank (pJ)
298system.physmem.readEnergy::0 1599522600 # Energy for read commands per rank (pJ)
299system.physmem.readEnergy::1 1601776800 # Energy for read commands per rank (pJ)
300system.physmem.writeEnergy::0 512256960 # Energy for write commands per rank (pJ)
301system.physmem.writeEnergy::1 539317440 # Energy for write commands per rank (pJ)
302system.physmem.refreshEnergy::0 124176112320 # Energy for refresh commands per rank (pJ)
303system.physmem.refreshEnergy::1 124176112320 # Energy for refresh commands per rank (pJ)
304system.physmem.actBackEnergy::0 57055460715 # Energy for active background per rank (pJ)
305system.physmem.actBackEnergy::1 57001965930 # Energy for active background per rank (pJ)
306system.physmem.preBackEnergy::0 1090662047250 # Energy for precharge background per rank (pJ)
307system.physmem.preBackEnergy::1 1090708972500 # Energy for precharge background per rank (pJ)
308system.physmem.totalEnergy::0 1274395234815 # Total energy per rank (pJ)
309system.physmem.totalEnergy::1 1274421976230 # Total energy per rank (pJ)
310system.physmem.averagePower::0 670.316446 # Core power per rank (mW)
311system.physmem.averagePower::1 670.330512 # Core power per rank (mW)
312system.cpu0.branchPred.lookups 15024669 # Number of BP lookups
313system.cpu0.branchPred.condPredicted 13090822 # Number of conditional branches predicted
314system.cpu0.branchPred.condIncorrect 302150 # Number of conditional branches incorrect
315system.cpu0.branchPred.BTBLookups 9266199 # Number of BTB lookups
316system.cpu0.branchPred.BTBHits 5129053 # Number of BTB hits
317system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
318system.cpu0.branchPred.BTBHitPct 55.352286 # BTB Hit Percentage
319system.cpu0.branchPred.usedRAS 762066 # Number of times the RAS was used to get a target.
320system.cpu0.branchPred.RASInCorrect 14857 # Number of incorrect RAS predictions.
321system.cpu_clk_domain.clock 500 # Clock period in ticks
322system.cpu0.dtb.fetch_hits 0 # ITB hits
323system.cpu0.dtb.fetch_misses 0 # ITB misses
324system.cpu0.dtb.fetch_acv 0 # ITB acv
325system.cpu0.dtb.fetch_accesses 0 # ITB accesses
326system.cpu0.dtb.read_hits 8699665 # DTB read hits
327system.cpu0.dtb.read_misses 31652 # DTB read misses
328system.cpu0.dtb.read_acv 518 # DTB read access violations
329system.cpu0.dtb.read_accesses 684964 # DTB read accesses
330system.cpu0.dtb.write_hits 5527628 # DTB write hits
331system.cpu0.dtb.write_misses 7312 # DTB write misses
332system.cpu0.dtb.write_acv 384 # DTB write access violations
333system.cpu0.dtb.write_accesses 236678 # DTB write accesses
334system.cpu0.dtb.data_hits 14227293 # DTB hits
335system.cpu0.dtb.data_misses 38964 # DTB misses
336system.cpu0.dtb.data_acv 902 # DTB access violations
337system.cpu0.dtb.data_accesses 921642 # DTB accesses
338system.cpu0.itb.fetch_hits 1360805 # ITB hits
339system.cpu0.itb.fetch_misses 29325 # ITB misses
340system.cpu0.itb.fetch_acv 623 # ITB acv
341system.cpu0.itb.fetch_accesses 1390130 # ITB accesses
342system.cpu0.itb.read_hits 0 # DTB read hits
343system.cpu0.itb.read_misses 0 # DTB read misses
344system.cpu0.itb.read_acv 0 # DTB read access violations
345system.cpu0.itb.read_accesses 0 # DTB read accesses
346system.cpu0.itb.write_hits 0 # DTB write hits
347system.cpu0.itb.write_misses 0 # DTB write misses
348system.cpu0.itb.write_acv 0 # DTB write access violations
349system.cpu0.itb.write_accesses 0 # DTB write accesses
350system.cpu0.itb.data_hits 0 # DTB hits
351system.cpu0.itb.data_misses 0 # DTB misses
352system.cpu0.itb.data_acv 0 # DTB access violations
353system.cpu0.itb.data_accesses 0 # DTB accesses
354system.cpu0.numCycles 108792579 # number of cpu cycles simulated
355system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
356system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
357system.cpu0.fetch.icacheStallCycles 24480610 # Number of cycles fetch is stalled on an Icache miss
358system.cpu0.fetch.Insts 66921510 # Number of instructions fetch has processed
359system.cpu0.fetch.Branches 15024669 # Number of branches that fetch encountered
360system.cpu0.fetch.predictedBranches 5891119 # Number of branches that fetch has predicted taken
361system.cpu0.fetch.Cycles 76960209 # Number of cycles fetch has run and was not squashing or blocked
362system.cpu0.fetch.SquashCycles 1006918 # Number of cycles fetch has spent squashing
363system.cpu0.fetch.TlbCycles 587 # Number of cycles fetch has spent waiting for tlb
364system.cpu0.fetch.MiscStallCycles 30320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
365system.cpu0.fetch.PendingTrapStallCycles 1459024 # Number of stall cycles due to pending traps
366system.cpu0.fetch.PendingQuiesceStallCycles 459440 # Number of stall cycles due to pending quiesce instructions
367system.cpu0.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR
368system.cpu0.fetch.CacheLines 7808182 # Number of cache lines fetched
369system.cpu0.fetch.IcacheSquashes 214478 # Number of outstanding Icache misses that were squashed
370system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
371system.cpu0.fetch.rateDist::samples 103893877 # Number of instructions fetched each cycle (Total)
372system.cpu0.fetch.rateDist::mean 0.644133 # Number of instructions fetched each cycle (Total)
373system.cpu0.fetch.rateDist::stdev 1.944480 # Number of instructions fetched each cycle (Total)
374system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
375system.cpu0.fetch.rateDist::0 91308838 87.89% 87.89% # Number of instructions fetched each cycle (Total)
376system.cpu0.fetch.rateDist::1 814381 0.78% 88.67% # Number of instructions fetched each cycle (Total)
377system.cpu0.fetch.rateDist::2 1763801 1.70% 90.37% # Number of instructions fetched each cycle (Total)
378system.cpu0.fetch.rateDist::3 741690 0.71% 91.08% # Number of instructions fetched each cycle (Total)
379system.cpu0.fetch.rateDist::4 2523255 2.43% 93.51% # Number of instructions fetched each cycle (Total)
380system.cpu0.fetch.rateDist::5 561128 0.54% 94.05% # Number of instructions fetched each cycle (Total)
381system.cpu0.fetch.rateDist::6 635570 0.61% 94.66% # Number of instructions fetched each cycle (Total)
382system.cpu0.fetch.rateDist::7 719335 0.69% 95.35% # Number of instructions fetched each cycle (Total)
383system.cpu0.fetch.rateDist::8 4825879 4.65% 100.00% # Number of instructions fetched each cycle (Total)
384system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
385system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
386system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
387system.cpu0.fetch.rateDist::total 103893877 # Number of instructions fetched each cycle (Total)
388system.cpu0.fetch.branchRate 0.138104 # Number of branch fetches per cycle
389system.cpu0.fetch.rate 0.615129 # Number of inst fetches per cycle
390system.cpu0.decode.IdleCycles 19900832 # Number of cycles decode is idle
391system.cpu0.decode.BlockedCycles 73745257 # Number of cycles decode is blocked
392system.cpu0.decode.RunCycles 8046257 # Number of cycles decode is running
393system.cpu0.decode.UnblockCycles 1730950 # Number of cycles decode is unblocking
394system.cpu0.decode.SquashCycles 470580 # Number of cycles decode is squashing
395system.cpu0.decode.BranchResolved 495026 # Number of times decode resolved a branch
396system.cpu0.decode.BranchMispred 33344 # Number of times decode detected a branch misprediction
397system.cpu0.decode.DecodedInsts 58913691 # Number of instructions handled by decode
398system.cpu0.decode.SquashedInsts 103815 # Number of squashed instructions handled by decode
399system.cpu0.rename.SquashCycles 470580 # Number of cycles rename is squashing
400system.cpu0.rename.IdleCycles 20722206 # Number of cycles rename is idle
401system.cpu0.rename.BlockCycles 48316669 # Number of cycles rename is blocking
402system.cpu0.rename.serializeStallCycles 17970373 # count of cycles rename stalled for serializing inst
403system.cpu0.rename.RunCycles 8856068 # Number of cycles rename is running
404system.cpu0.rename.UnblockCycles 7557979 # Number of cycles rename is unblocking
405system.cpu0.rename.RenamedInsts 56901533 # Number of instructions processed by rename
406system.cpu0.rename.ROBFullEvents 202703 # Number of times rename has blocked due to ROB full
407system.cpu0.rename.IQFullEvents 2015999 # Number of times rename has blocked due to IQ full
408system.cpu0.rename.LQFullEvents 141191 # Number of times rename has blocked due to LQ full
409system.cpu0.rename.SQFullEvents 3736855 # Number of times rename has blocked due to SQ full
410system.cpu0.rename.RenamedOperands 38160864 # Number of destination operands rename has renamed
411system.cpu0.rename.RenameLookups 69501237 # Number of register rename lookups that rename has made
412system.cpu0.rename.int_rename_lookups 69376844 # Number of integer rename lookups
413system.cpu0.rename.fp_rename_lookups 115358 # Number of floating rename lookups
414system.cpu0.rename.CommittedMaps 33567232 # Number of HB maps that are committed
415system.cpu0.rename.UndoneMaps 4593624 # Number of HB maps that are undone due to squashing
416system.cpu0.rename.serializingInsts 1365129 # count of serializing insts renamed
417system.cpu0.rename.tempSerializingInsts 198221 # count of temporary serializing insts renamed
418system.cpu0.rename.skidInsts 12480015 # count of insts added to the skid buffer
419system.cpu0.memDep0.insertedLoads 8824182 # Number of loads inserted to the mem dependence unit.
420system.cpu0.memDep0.insertedStores 5791367 # Number of stores inserted to the mem dependence unit.
421system.cpu0.memDep0.conflictingLoads 1299957 # Number of conflicting loads.
422system.cpu0.memDep0.conflictingStores 953544 # Number of conflicting stores.
423system.cpu0.iq.iqInstsAdded 50831435 # Number of instructions added to the IQ (excludes non-spec)
424system.cpu0.iq.iqNonSpecInstsAdded 1735186 # Number of non-speculative instructions added to the IQ
425system.cpu0.iq.iqInstsIssued 49951846 # Number of instructions issued
426system.cpu0.iq.iqSquashedInstsIssued 52661 # Number of squashed instructions issued
427system.cpu0.iq.iqSquashedInstsExamined 5989483 # Number of squashed instructions iterated over during squash; mainly for profiling
428system.cpu0.iq.iqSquashedOperandsExamined 2856975 # Number of squashed operands that are examined and possibly removed from graph
429system.cpu0.iq.iqSquashedNonSpecRemoved 1193961 # Number of squashed non-spec instructions that were removed
430system.cpu0.iq.issued_per_cycle::samples 103893877 # Number of insts issued each cycle
431system.cpu0.iq.issued_per_cycle::mean 0.480797 # Number of insts issued each cycle
432system.cpu0.iq.issued_per_cycle::stdev 1.214404 # Number of insts issued each cycle
433system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
434system.cpu0.iq.issued_per_cycle::0 83240383 80.12% 80.12% # Number of insts issued each cycle
435system.cpu0.iq.issued_per_cycle::1 8994841 8.66% 88.78% # Number of insts issued each cycle
436system.cpu0.iq.issued_per_cycle::2 3729897 3.59% 92.37% # Number of insts issued each cycle
437system.cpu0.iq.issued_per_cycle::3 2662216 2.56% 94.93% # Number of insts issued each cycle
438system.cpu0.iq.issued_per_cycle::4 2692674 2.59% 97.52% # Number of insts issued each cycle
439system.cpu0.iq.issued_per_cycle::5 1272103 1.22% 98.75% # Number of insts issued each cycle
440system.cpu0.iq.issued_per_cycle::6 842802 0.81% 99.56% # Number of insts issued each cycle
441system.cpu0.iq.issued_per_cycle::7 349148 0.34% 99.89% # Number of insts issued each cycle
442system.cpu0.iq.issued_per_cycle::8 109813 0.11% 100.00% # Number of insts issued each cycle
443system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
444system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
445system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
446system.cpu0.iq.issued_per_cycle::total 103893877 # Number of insts issued each cycle
447system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
448system.cpu0.iq.fu_full::IntAlu 174329 19.02% 19.02% # attempts to use FU when none available
449system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available
450system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available
451system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available
452system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available
453system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available
454system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available
455system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available
456system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
457system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available
458system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available
459system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available
460system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available
461system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available
462system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available
463system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available
464system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available
465system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available
466system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available
467system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available
468system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available
469system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available
470system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available
471system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available
472system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available
473system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available
474system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available
475system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available
476system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available
477system.cpu0.iq.fu_full::MemRead 437335 47.71% 66.72% # attempts to use FU when none available
478system.cpu0.iq.fu_full::MemWrite 305033 33.28% 100.00% # attempts to use FU when none available
479system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
480system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
481system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued
482system.cpu0.iq.FU_type_0::IntAlu 34481483 69.03% 69.04% # Type of FU issued
483system.cpu0.iq.FU_type_0::IntMult 54630 0.11% 69.15% # Type of FU issued
484system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued
485system.cpu0.iq.FU_type_0::FloatAdd 27712 0.06% 69.20% # Type of FU issued
486system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued
487system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued
488system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued
489system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.21% # Type of FU issued
490system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued
491system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued
492system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued
493system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued
494system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued
495system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued
496system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued
497system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued
498system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued
499system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued
500system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued
501system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued
502system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued
503system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued
504system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued
505system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued
506system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued
507system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued
508system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued
509system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued
510system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued
511system.cpu0.iq.FU_type_0::MemRead 9019851 18.06% 87.26% # Type of FU issued
512system.cpu0.iq.FU_type_0::MemWrite 5598402 11.21% 98.47% # Type of FU issued
513system.cpu0.iq.FU_type_0::IprAccess 764115 1.53% 100.00% # Type of FU issued
514system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
515system.cpu0.iq.FU_type_0::total 49951846 # Type of FU issued
516system.cpu0.iq.rate 0.459148 # Inst issue rate
517system.cpu0.iq.fu_busy_cnt 916697 # FU busy when requested
518system.cpu0.iq.fu_busy_rate 0.018352 # FU busy rate (busy events/executed inst)
519system.cpu0.iq.int_inst_queue_reads 204260867 # Number of integer instruction queue reads
520system.cpu0.iq.int_inst_queue_writes 58336070 # Number of integer instruction queue writes
521system.cpu0.iq.int_inst_queue_wakeup_accesses 48679612 # Number of integer instruction queue wakeup accesses
522system.cpu0.iq.fp_inst_queue_reads 506059 # Number of floating instruction queue reads
523system.cpu0.iq.fp_inst_queue_writes 237571 # Number of floating instruction queue writes
524system.cpu0.iq.fp_inst_queue_wakeup_accesses 232415 # Number of floating instruction queue wakeup accesses
525system.cpu0.iq.int_alu_accesses 50592327 # Number of integer alu accesses
526system.cpu0.iq.fp_alu_accesses 272446 # Number of floating point alu accesses
527system.cpu0.iew.lsq.thread0.forwLoads 560089 # Number of loads that had data forwarded from stores
528system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
529system.cpu0.iew.lsq.thread0.squashedLoads 1038811 # Number of loads squashed
530system.cpu0.iew.lsq.thread0.ignoredResponses 4304 # Number of memory responses ignored because the instruction is squashed
531system.cpu0.iew.lsq.thread0.memOrderViolation 17864 # Number of memory ordering violations
532system.cpu0.iew.lsq.thread0.squashedStores 487331 # Number of stores squashed
533system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
534system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
535system.cpu0.iew.lsq.thread0.rescheduledLoads 18869 # Number of loads that were rescheduled
536system.cpu0.iew.lsq.thread0.cacheBlocked 349661 # Number of times an access to memory failed due to the cache being blocked
537system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
538system.cpu0.iew.iewSquashCycles 470580 # Number of cycles IEW is squashing
539system.cpu0.iew.iewBlockCycles 44276704 # Number of cycles IEW is blocking
540system.cpu0.iew.iewUnblockCycles 1577501 # Number of cycles IEW is unblocking
541system.cpu0.iew.iewDispatchedInsts 55768983 # Number of instructions dispatched to IQ
542system.cpu0.iew.iewDispSquashedInsts 120052 # Number of squashed instructions skipped by dispatch
543system.cpu0.iew.iewDispLoadInsts 8824182 # Number of dispatched load instructions
544system.cpu0.iew.iewDispStoreInsts 5791367 # Number of dispatched store instructions
545system.cpu0.iew.iewDispNonSpecInsts 1533608 # Number of dispatched non-speculative instructions
546system.cpu0.iew.iewIQFullEvents 47079 # Number of times the IQ has become full, causing a stall
547system.cpu0.iew.iewLSQFullEvents 1307470 # Number of times the LSQ has become full, causing a stall
548system.cpu0.iew.memOrderViolationEvents 17864 # Number of memory order violations
549system.cpu0.iew.predictedTakenIncorrect 152204 # Number of branches that were predicted taken incorrectly
550system.cpu0.iew.predictedNotTakenIncorrect 328517 # Number of branches that were predicted not taken incorrectly
551system.cpu0.iew.branchMispredicts 480721 # Number of branch mispredicts detected at execute
552system.cpu0.iew.iewExecutedInsts 49479281 # Number of executed instructions
553system.cpu0.iew.iewExecLoadInsts 8753036 # Number of load instructions executed
554system.cpu0.iew.iewExecSquashedInsts 472564 # Number of squashed instructions skipped in execute
555system.cpu0.iew.exec_swp 0 # number of swp insts executed
556system.cpu0.iew.exec_nop 3202362 # number of nop insts executed
557system.cpu0.iew.exec_refs 14301032 # number of memory reference insts executed
558system.cpu0.iew.exec_branches 7879408 # Number of branches executed
559system.cpu0.iew.exec_stores 5547996 # Number of stores executed
560system.cpu0.iew.exec_rate 0.454804 # Inst execution rate
561system.cpu0.iew.wb_sent 49022541 # cumulative count of insts sent to commit
562system.cpu0.iew.wb_count 48912027 # cumulative count of insts written-back
563system.cpu0.iew.wb_producers 25297454 # num instructions producing a value
564system.cpu0.iew.wb_consumers 34938196 # num instructions consuming a value
565system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
566system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle
567system.cpu0.iew.wb_fanout 0.724063 # average fanout of values written-back
568system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
569system.cpu0.commit.commitSquashedInsts 6548409 # The number of squashed insts skipped by commit
570system.cpu0.commit.commitNonSpecStalls 541225 # The number of times commit has been forced to stall to communicate backwards
571system.cpu0.commit.branchMispredicts 440159 # The number of times a branch was mispredicted
572system.cpu0.commit.committed_per_cycle::samples 102738863 # Number of insts commited each cycle
573system.cpu0.commit.committed_per_cycle::mean 0.478033 # Number of insts commited each cycle
574system.cpu0.commit.committed_per_cycle::stdev 1.411836 # Number of insts commited each cycle
575system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
576system.cpu0.commit.committed_per_cycle::0 85310078 83.04% 83.04% # Number of insts commited each cycle
577system.cpu0.commit.committed_per_cycle::1 6928869 6.74% 89.78% # Number of insts commited each cycle
578system.cpu0.commit.committed_per_cycle::2 3804927 3.70% 93.48% # Number of insts commited each cycle
579system.cpu0.commit.committed_per_cycle::3 2004533 1.95% 95.43% # Number of insts commited each cycle
580system.cpu0.commit.committed_per_cycle::4 1514323 1.47% 96.91% # Number of insts commited each cycle
581system.cpu0.commit.committed_per_cycle::5 555844 0.54% 97.45% # Number of insts commited each cycle
582system.cpu0.commit.committed_per_cycle::6 414883 0.40% 97.85% # Number of insts commited each cycle
583system.cpu0.commit.committed_per_cycle::7 408778 0.40% 98.25% # Number of insts commited each cycle
584system.cpu0.commit.committed_per_cycle::8 1796628 1.75% 100.00% # Number of insts commited each cycle
585system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
586system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
587system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
588system.cpu0.commit.committed_per_cycle::total 102738863 # Number of insts commited each cycle
589system.cpu0.commit.committedInsts 49112602 # Number of instructions committed
590system.cpu0.commit.committedOps 49112602 # Number of ops (including micro ops) committed
591system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
592system.cpu0.commit.refs 13089407 # Number of memory references committed
593system.cpu0.commit.loads 7785371 # Number of loads committed
594system.cpu0.commit.membars 183023 # Number of memory barriers committed
595system.cpu0.commit.branches 7443994 # Number of branches committed
596system.cpu0.commit.fp_insts 229281 # Number of committed floating point instructions.
597system.cpu0.commit.int_insts 45524861 # Number of committed integer instructions.
598system.cpu0.commit.function_calls 617737 # Number of function calls committed.
599system.cpu0.commit.op_class_0::No_OpClass 2801788 5.70% 5.70% # Class of committed instruction
600system.cpu0.commit.op_class_0::IntAlu 32185758 65.53% 71.24% # Class of committed instruction
601system.cpu0.commit.op_class_0::IntMult 53394 0.11% 71.35% # Class of committed instruction
602system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.35% # Class of committed instruction
603system.cpu0.commit.op_class_0::FloatAdd 27239 0.06% 71.40% # Class of committed instruction
604system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.40% # Class of committed instruction
605system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.40% # Class of committed instruction
606system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.40% # Class of committed instruction
607system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.41% # Class of committed instruction
608system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.41% # Class of committed instruction
609system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.41% # Class of committed instruction
610system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.41% # Class of committed instruction
611system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.41% # Class of committed instruction
612system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.41% # Class of committed instruction
613system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.41% # Class of committed instruction
614system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.41% # Class of committed instruction
615system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.41% # Class of committed instruction
616system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.41% # Class of committed instruction
617system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.41% # Class of committed instruction
618system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.41% # Class of committed instruction
619system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.41% # Class of committed instruction
620system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.41% # Class of committed instruction
621system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.41% # Class of committed instruction
622system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.41% # Class of committed instruction
623system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.41% # Class of committed instruction
624system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.41% # Class of committed instruction
625system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.41% # Class of committed instruction
626system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.41% # Class of committed instruction
627system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.41% # Class of committed instruction
628system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.41% # Class of committed instruction
629system.cpu0.commit.op_class_0::MemRead 7968394 16.22% 87.63% # Class of committed instruction
630system.cpu0.commit.op_class_0::MemWrite 5310031 10.81% 98.44% # Class of committed instruction
631system.cpu0.commit.op_class_0::IprAccess 764115 1.56% 100.00% # Class of committed instruction
632system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
633system.cpu0.commit.op_class_0::total 49112602 # Class of committed instruction
634system.cpu0.commit.bw_lim_events 1796628 # number cycles where commit BW limit reached
635system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
636system.cpu0.rob.rob_reads 156399894 # The number of ROB reads
637system.cpu0.rob.rob_writes 112470885 # The number of ROB writes
638system.cpu0.timesIdled 448982 # Number of times that the entire CPU went into an idle state and unscheduled itself
639system.cpu0.idleCycles 4898702 # Total number of cycles that the CPU has spent unscheduled due to idling
640system.cpu0.quiesceCycles 3693581898 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
641system.cpu0.committedInsts 46314581 # Number of Instructions Simulated
642system.cpu0.committedOps 46314581 # Number of Ops (including micro ops) Simulated
643system.cpu0.cpi 2.348992 # CPI: Cycles Per Instruction
644system.cpu0.cpi_total 2.348992 # CPI: Total CPI of All Threads
645system.cpu0.ipc 0.425715 # IPC: Instructions Per Cycle
646system.cpu0.ipc_total 0.425715 # IPC: Total IPC of All Threads
647system.cpu0.int_regfile_reads 65241971 # number of integer regfile reads
648system.cpu0.int_regfile_writes 35484902 # number of integer regfile writes
649system.cpu0.fp_regfile_reads 114300 # number of floating regfile reads
650system.cpu0.fp_regfile_writes 114851 # number of floating regfile writes
651system.cpu0.misc_regfile_reads 1680980 # number of misc regfile reads
652system.cpu0.misc_regfile_writes 762179 # number of misc regfile writes
653system.cpu0.dcache.tags.replacements 1226061 # number of replacements
654system.cpu0.dcache.tags.tagsinuse 505.967877 # Cycle average of tags in use
655system.cpu0.dcache.tags.total_refs 9972327 # Total number of references to valid blocks.
656system.cpu0.dcache.tags.sampled_refs 1226573 # Sample count of references to valid blocks.
657system.cpu0.dcache.tags.avg_refs 8.130235 # Average number of references to valid blocks.
658system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit.
659system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.967877 # Average occupied blocks per requestor
660system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988219 # Average percentage of cache occupancy
661system.cpu0.dcache.tags.occ_percent::total 0.988219 # Average percentage of cache occupancy
662system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
663system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id
664system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
665system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
666system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
667system.cpu0.dcache.tags.tag_accesses 53849509 # Number of tag accesses
668system.cpu0.dcache.tags.data_accesses 53849509 # Number of data accesses
669system.cpu0.dcache.ReadReq_hits::cpu0.data 6192446 # number of ReadReq hits
670system.cpu0.dcache.ReadReq_hits::total 6192446 # number of ReadReq hits
671system.cpu0.dcache.WriteReq_hits::cpu0.data 3442531 # number of WriteReq hits
672system.cpu0.dcache.WriteReq_hits::total 3442531 # number of WriteReq hits
673system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150135 # number of LoadLockedReq hits
674system.cpu0.dcache.LoadLockedReq_hits::total 150135 # number of LoadLockedReq hits
675system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172107 # number of StoreCondReq hits
676system.cpu0.dcache.StoreCondReq_hits::total 172107 # number of StoreCondReq hits
677system.cpu0.dcache.demand_hits::cpu0.data 9634977 # number of demand (read+write) hits
678system.cpu0.dcache.demand_hits::total 9634977 # number of demand (read+write) hits
679system.cpu0.dcache.overall_hits::cpu0.data 9634977 # number of overall hits
680system.cpu0.dcache.overall_hits::total 9634977 # number of overall hits
681system.cpu0.dcache.ReadReq_misses::cpu0.data 1501821 # number of ReadReq misses
682system.cpu0.dcache.ReadReq_misses::total 1501821 # number of ReadReq misses
683system.cpu0.dcache.WriteReq_misses::cpu0.data 1669841 # number of WriteReq misses
684system.cpu0.dcache.WriteReq_misses::total 1669841 # number of WriteReq misses
685system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19141 # number of LoadLockedReq misses
686system.cpu0.dcache.LoadLockedReq_misses::total 19141 # number of LoadLockedReq misses
687system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4636 # number of StoreCondReq misses
688system.cpu0.dcache.StoreCondReq_misses::total 4636 # number of StoreCondReq misses
689system.cpu0.dcache.demand_misses::cpu0.data 3171662 # number of demand (read+write) misses
690system.cpu0.dcache.demand_misses::total 3171662 # number of demand (read+write) misses
691system.cpu0.dcache.overall_misses::cpu0.data 3171662 # number of overall misses
692system.cpu0.dcache.overall_misses::total 3171662 # number of overall misses
693system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39101656628 # number of ReadReq miss cycles
694system.cpu0.dcache.ReadReq_miss_latency::total 39101656628 # number of ReadReq miss cycles
695system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78115764371 # number of WriteReq miss cycles
696system.cpu0.dcache.WriteReq_miss_latency::total 78115764371 # number of WriteReq miss cycles
697system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 290102987 # number of LoadLockedReq miss cycles
698system.cpu0.dcache.LoadLockedReq_miss_latency::total 290102987 # number of LoadLockedReq miss cycles
699system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35172730 # number of StoreCondReq miss cycles
700system.cpu0.dcache.StoreCondReq_miss_latency::total 35172730 # number of StoreCondReq miss cycles
701system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999 # number of demand (read+write) miss cycles
702system.cpu0.dcache.demand_miss_latency::total 117217420999 # number of demand (read+write) miss cycles
703system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999 # number of overall miss cycles
704system.cpu0.dcache.overall_miss_latency::total 117217420999 # number of overall miss cycles
705system.cpu0.dcache.ReadReq_accesses::cpu0.data 7694267 # number of ReadReq accesses(hits+misses)
706system.cpu0.dcache.ReadReq_accesses::total 7694267 # number of ReadReq accesses(hits+misses)
707system.cpu0.dcache.WriteReq_accesses::cpu0.data 5112372 # number of WriteReq accesses(hits+misses)
708system.cpu0.dcache.WriteReq_accesses::total 5112372 # number of WriteReq accesses(hits+misses)
709system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169276 # number of LoadLockedReq accesses(hits+misses)
710system.cpu0.dcache.LoadLockedReq_accesses::total 169276 # number of LoadLockedReq accesses(hits+misses)
711system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176743 # number of StoreCondReq accesses(hits+misses)
712system.cpu0.dcache.StoreCondReq_accesses::total 176743 # number of StoreCondReq accesses(hits+misses)
713system.cpu0.dcache.demand_accesses::cpu0.data 12806639 # number of demand (read+write) accesses
714system.cpu0.dcache.demand_accesses::total 12806639 # number of demand (read+write) accesses
715system.cpu0.dcache.overall_accesses::cpu0.data 12806639 # number of overall (read+write) accesses
716system.cpu0.dcache.overall_accesses::total 12806639 # number of overall (read+write) accesses
717system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195187 # miss rate for ReadReq accesses
718system.cpu0.dcache.ReadReq_miss_rate::total 0.195187 # miss rate for ReadReq accesses
719system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.326627 # miss rate for WriteReq accesses
720system.cpu0.dcache.WriteReq_miss_rate::total 0.326627 # miss rate for WriteReq accesses
721system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113076 # miss rate for LoadLockedReq accesses
722system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113076 # miss rate for LoadLockedReq accesses
723system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026230 # miss rate for StoreCondReq accesses
724system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026230 # miss rate for StoreCondReq accesses
725system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247658 # miss rate for demand accesses
726system.cpu0.dcache.demand_miss_rate::total 0.247658 # miss rate for demand accesses
727system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247658 # miss rate for overall accesses
728system.cpu0.dcache.overall_miss_rate::total 0.247658 # miss rate for overall accesses
729system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183 # average ReadReq miss latency
730system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183 # average ReadReq miss latency
731system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748 # average WriteReq miss latency
732system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748 # average WriteReq miss latency
733system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018 # average LoadLockedReq miss latency
734system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018 # average LoadLockedReq miss latency
735system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7586.870147 # average StoreCondReq miss latency
736system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7586.870147 # average StoreCondReq miss latency
737system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency
738system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841 # average overall miss latency
739system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency
740system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841 # average overall miss latency
741system.cpu0.dcache.blocked_cycles::no_mshrs 3837622 # number of cycles access was blocked
742system.cpu0.dcache.blocked_cycles::no_targets 3343 # number of cycles access was blocked
743system.cpu0.dcache.blocked::no_mshrs 160954 # number of cycles access was blocked
744system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked
745system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.842974 # average number of cycles each access was blocked
746system.cpu0.dcache.avg_blocked_cycles::no_targets 37.561798 # average number of cycles each access was blocked
747system.cpu0.dcache.fast_writes 0 # number of fast writes performed
748system.cpu0.dcache.cache_copies 0 # number of cache copies performed
749system.cpu0.dcache.writebacks::writebacks 711843 # number of writebacks
750system.cpu0.dcache.writebacks::total 711843 # number of writebacks
751system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 520027 # number of ReadReq MSHR hits
752system.cpu0.dcache.ReadReq_mshr_hits::total 520027 # number of ReadReq MSHR hits
753system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1419840 # number of WriteReq MSHR hits
754system.cpu0.dcache.WriteReq_mshr_hits::total 1419840 # number of WriteReq MSHR hits
755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4544 # number of LoadLockedReq MSHR hits
756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4544 # number of LoadLockedReq MSHR hits
757system.cpu0.dcache.demand_mshr_hits::cpu0.data 1939867 # number of demand (read+write) MSHR hits
758system.cpu0.dcache.demand_mshr_hits::total 1939867 # number of demand (read+write) MSHR hits
759system.cpu0.dcache.overall_mshr_hits::cpu0.data 1939867 # number of overall MSHR hits
760system.cpu0.dcache.overall_mshr_hits::total 1939867 # number of overall MSHR hits
761system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 981794 # number of ReadReq MSHR misses
762system.cpu0.dcache.ReadReq_mshr_misses::total 981794 # number of ReadReq MSHR misses
763system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 250001 # number of WriteReq MSHR misses
764system.cpu0.dcache.WriteReq_mshr_misses::total 250001 # number of WriteReq MSHR misses
765system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14597 # number of LoadLockedReq MSHR misses
766system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14597 # number of LoadLockedReq MSHR misses
767system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4636 # number of StoreCondReq MSHR misses
768system.cpu0.dcache.StoreCondReq_mshr_misses::total 4636 # number of StoreCondReq MSHR misses
769system.cpu0.dcache.demand_mshr_misses::cpu0.data 1231795 # number of demand (read+write) MSHR misses
770system.cpu0.dcache.demand_mshr_misses::total 1231795 # number of demand (read+write) MSHR misses
771system.cpu0.dcache.overall_mshr_misses::cpu0.data 1231795 # number of overall MSHR misses
772system.cpu0.dcache.overall_mshr_misses::total 1231795 # number of overall MSHR misses
773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27071690424 # number of ReadReq MSHR miss cycles
774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27071690424 # number of ReadReq MSHR miss cycles
775system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11368022018 # number of WriteReq MSHR miss cycles
776system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11368022018 # number of WriteReq MSHR miss cycles
777system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148174261 # number of LoadLockedReq MSHR miss cycles
778system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148174261 # number of LoadLockedReq MSHR miss cycles
779system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25899270 # number of StoreCondReq MSHR miss cycles
780system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25899270 # number of StoreCondReq MSHR miss cycles
781system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38439712442 # number of demand (read+write) MSHR miss cycles
782system.cpu0.dcache.demand_mshr_miss_latency::total 38439712442 # number of demand (read+write) MSHR miss cycles
783system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38439712442 # number of overall MSHR miss cycles
784system.cpu0.dcache.overall_mshr_miss_latency::total 38439712442 # number of overall MSHR miss cycles
785system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458085000 # number of ReadReq MSHR uncacheable cycles
786system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458085000 # number of ReadReq MSHR uncacheable cycles
787system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2211101998 # number of WriteReq MSHR uncacheable cycles
788system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2211101998 # number of WriteReq MSHR uncacheable cycles
789system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3669186998 # number of overall MSHR uncacheable cycles
790system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3669186998 # number of overall MSHR uncacheable cycles
791system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127601 # mshr miss rate for ReadReq accesses
792system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127601 # mshr miss rate for ReadReq accesses
793system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048901 # mshr miss rate for WriteReq accesses
794system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048901 # mshr miss rate for WriteReq accesses
795system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086232 # mshr miss rate for LoadLockedReq accesses
796system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086232 # mshr miss rate for LoadLockedReq accesses
797system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026230 # mshr miss rate for StoreCondReq accesses
798system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026230 # mshr miss rate for StoreCondReq accesses
799system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for demand accesses
800system.cpu0.dcache.demand_mshr_miss_rate::total 0.096184 # mshr miss rate for demand accesses
801system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for overall accesses
802system.cpu0.dcache.overall_mshr_miss_rate::total 0.096184 # mshr miss rate for overall accesses
803system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154 # average ReadReq mshr miss latency
804system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154 # average ReadReq mshr miss latency
805system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184 # average WriteReq mshr miss latency
806system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184 # average WriteReq mshr miss latency
807system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810 # average LoadLockedReq mshr miss latency
808system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810 # average LoadLockedReq mshr miss latency
809system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5586.555220 # average StoreCondReq mshr miss latency
810system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5586.555220 # average StoreCondReq mshr miss latency
811system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency
812system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency
813system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency
814system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency
815system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
816system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
817system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
818system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
819system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
820system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
821system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
822system.cpu0.icache.tags.replacements 821620 # number of replacements
823system.cpu0.icache.tags.tagsinuse 509.585426 # Cycle average of tags in use
824system.cpu0.icache.tags.total_refs 6946118 # Total number of references to valid blocks.
825system.cpu0.icache.tags.sampled_refs 822130 # Sample count of references to valid blocks.
826system.cpu0.icache.tags.avg_refs 8.448929 # Average number of references to valid blocks.
827system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit.
828system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.585426 # Average occupied blocks per requestor
829system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995284 # Average percentage of cache occupancy
830system.cpu0.icache.tags.occ_percent::total 0.995284 # Average percentage of cache occupancy
831system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
832system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
833system.cpu0.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
834system.cpu0.icache.tags.age_task_id_blocks_1024::2 431 # Occupied blocks per task id
835system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
836system.cpu0.icache.tags.tag_accesses 8630516 # Number of tag accesses
837system.cpu0.icache.tags.data_accesses 8630516 # Number of data accesses
838system.cpu0.icache.ReadReq_hits::cpu0.inst 6946118 # number of ReadReq hits
839system.cpu0.icache.ReadReq_hits::total 6946118 # number of ReadReq hits
840system.cpu0.icache.demand_hits::cpu0.inst 6946118 # number of demand (read+write) hits
841system.cpu0.icache.demand_hits::total 6946118 # number of demand (read+write) hits
842system.cpu0.icache.overall_hits::cpu0.inst 6946118 # number of overall hits
843system.cpu0.icache.overall_hits::total 6946118 # number of overall hits
844system.cpu0.icache.ReadReq_misses::cpu0.inst 862061 # number of ReadReq misses
845system.cpu0.icache.ReadReq_misses::total 862061 # number of ReadReq misses
846system.cpu0.icache.demand_misses::cpu0.inst 862061 # number of demand (read+write) misses
847system.cpu0.icache.demand_misses::total 862061 # number of demand (read+write) misses
848system.cpu0.icache.overall_misses::cpu0.inst 862061 # number of overall misses
849system.cpu0.icache.overall_misses::total 862061 # number of overall misses
850system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12338398473 # number of ReadReq miss cycles
851system.cpu0.icache.ReadReq_miss_latency::total 12338398473 # number of ReadReq miss cycles
852system.cpu0.icache.demand_miss_latency::cpu0.inst 12338398473 # number of demand (read+write) miss cycles
853system.cpu0.icache.demand_miss_latency::total 12338398473 # number of demand (read+write) miss cycles
854system.cpu0.icache.overall_miss_latency::cpu0.inst 12338398473 # number of overall miss cycles
855system.cpu0.icache.overall_miss_latency::total 12338398473 # number of overall miss cycles
856system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808179 # number of ReadReq accesses(hits+misses)
857system.cpu0.icache.ReadReq_accesses::total 7808179 # number of ReadReq accesses(hits+misses)
858system.cpu0.icache.demand_accesses::cpu0.inst 7808179 # number of demand (read+write) accesses
859system.cpu0.icache.demand_accesses::total 7808179 # number of demand (read+write) accesses
860system.cpu0.icache.overall_accesses::cpu0.inst 7808179 # number of overall (read+write) accesses
861system.cpu0.icache.overall_accesses::total 7808179 # number of overall (read+write) accesses
862system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110405 # miss rate for ReadReq accesses
863system.cpu0.icache.ReadReq_miss_rate::total 0.110405 # miss rate for ReadReq accesses
864system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110405 # miss rate for demand accesses
865system.cpu0.icache.demand_miss_rate::total 0.110405 # miss rate for demand accesses
866system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110405 # miss rate for overall accesses
867system.cpu0.icache.overall_miss_rate::total 0.110405 # miss rate for overall accesses
868system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478 # average ReadReq miss latency
869system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478 # average ReadReq miss latency
870system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency
871system.cpu0.icache.demand_avg_miss_latency::total 14312.674478 # average overall miss latency
872system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency
873system.cpu0.icache.overall_avg_miss_latency::total 14312.674478 # average overall miss latency
874system.cpu0.icache.blocked_cycles::no_mshrs 4878 # number of cycles access was blocked
875system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
876system.cpu0.icache.blocked::no_mshrs 185 # number of cycles access was blocked
877system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
878system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.367568 # average number of cycles each access was blocked
879system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
880system.cpu0.icache.fast_writes 0 # number of fast writes performed
881system.cpu0.icache.cache_copies 0 # number of cache copies performed
882system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39724 # number of ReadReq MSHR hits
883system.cpu0.icache.ReadReq_mshr_hits::total 39724 # number of ReadReq MSHR hits
884system.cpu0.icache.demand_mshr_hits::cpu0.inst 39724 # number of demand (read+write) MSHR hits
885system.cpu0.icache.demand_mshr_hits::total 39724 # number of demand (read+write) MSHR hits
886system.cpu0.icache.overall_mshr_hits::cpu0.inst 39724 # number of overall MSHR hits
887system.cpu0.icache.overall_mshr_hits::total 39724 # number of overall MSHR hits
888system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 822337 # number of ReadReq MSHR misses
889system.cpu0.icache.ReadReq_mshr_misses::total 822337 # number of ReadReq MSHR misses
890system.cpu0.icache.demand_mshr_misses::cpu0.inst 822337 # number of demand (read+write) MSHR misses
891system.cpu0.icache.demand_mshr_misses::total 822337 # number of demand (read+write) MSHR misses
892system.cpu0.icache.overall_mshr_misses::cpu0.inst 822337 # number of overall MSHR misses
893system.cpu0.icache.overall_mshr_misses::total 822337 # number of overall MSHR misses
894system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10177943027 # number of ReadReq MSHR miss cycles
895system.cpu0.icache.ReadReq_mshr_miss_latency::total 10177943027 # number of ReadReq MSHR miss cycles
896system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10177943027 # number of demand (read+write) MSHR miss cycles
897system.cpu0.icache.demand_mshr_miss_latency::total 10177943027 # number of demand (read+write) MSHR miss cycles
898system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10177943027 # number of overall MSHR miss cycles
899system.cpu0.icache.overall_mshr_miss_latency::total 10177943027 # number of overall MSHR miss cycles
900system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for ReadReq accesses
901system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105317 # mshr miss rate for ReadReq accesses
902system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for demand accesses
903system.cpu0.icache.demand_mshr_miss_rate::total 0.105317 # mshr miss rate for demand accesses
904system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for overall accesses
905system.cpu0.icache.overall_mshr_miss_rate::total 0.105317 # mshr miss rate for overall accesses
906system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average ReadReq mshr miss latency
907system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616 # average ReadReq mshr miss latency
908system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency
909system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency
910system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency
911system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency
912system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
913system.cpu1.branchPred.lookups 4575539 # Number of BP lookups
914system.cpu1.branchPred.condPredicted 4011453 # Number of conditional branches predicted
915system.cpu1.branchPred.condIncorrect 80159 # Number of conditional branches incorrect
916system.cpu1.branchPred.BTBLookups 2846769 # Number of BTB lookups
917system.cpu1.branchPred.BTBHits 1118608 # Number of BTB hits
918system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
919system.cpu1.branchPred.BTBHitPct 39.293950 # BTB Hit Percentage
920system.cpu1.branchPred.usedRAS 219011 # Number of times the RAS was used to get a target.
921system.cpu1.branchPred.RASInCorrect 6943 # Number of incorrect RAS predictions.
922system.cpu1.dtb.fetch_hits 0 # ITB hits
923system.cpu1.dtb.fetch_misses 0 # ITB misses
924system.cpu1.dtb.fetch_acv 0 # ITB acv
925system.cpu1.dtb.fetch_accesses 0 # ITB accesses
926system.cpu1.dtb.read_hits 2376918 # DTB read hits
927system.cpu1.dtb.read_misses 9978 # DTB read misses
928system.cpu1.dtb.read_acv 5 # DTB read access violations
929system.cpu1.dtb.read_accesses 290947 # DTB read accesses
930system.cpu1.dtb.write_hits 1576285 # DTB write hits
931system.cpu1.dtb.write_misses 2026 # DTB write misses
932system.cpu1.dtb.write_acv 38 # DTB write access violations
933system.cpu1.dtb.write_accesses 109535 # DTB write accesses
934system.cpu1.dtb.data_hits 3953203 # DTB hits
935system.cpu1.dtb.data_misses 12004 # DTB misses
936system.cpu1.dtb.data_acv 43 # DTB access violations
937system.cpu1.dtb.data_accesses 400482 # DTB accesses
938system.cpu1.itb.fetch_hits 602928 # ITB hits
939system.cpu1.itb.fetch_misses 5576 # ITB misses
940system.cpu1.itb.fetch_acv 51 # ITB acv
941system.cpu1.itb.fetch_accesses 608504 # ITB accesses
942system.cpu1.itb.read_hits 0 # DTB read hits
943system.cpu1.itb.read_misses 0 # DTB read misses
944system.cpu1.itb.read_acv 0 # DTB read access violations
945system.cpu1.itb.read_accesses 0 # DTB read accesses
946system.cpu1.itb.write_hits 0 # DTB write hits
947system.cpu1.itb.write_misses 0 # DTB write misses
948system.cpu1.itb.write_acv 0 # DTB write access violations
949system.cpu1.itb.write_accesses 0 # DTB write accesses
950system.cpu1.itb.data_hits 0 # DTB hits
951system.cpu1.itb.data_misses 0 # DTB misses
952system.cpu1.itb.data_acv 0 # DTB access violations
953system.cpu1.itb.data_accesses 0 # DTB accesses
954system.cpu1.numCycles 18735029 # number of cpu cycles simulated
955system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
956system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
957system.cpu1.fetch.icacheStallCycles 8327481 # Number of cycles fetch is stalled on an Icache miss
958system.cpu1.fetch.Insts 17619609 # Number of instructions fetch has processed
959system.cpu1.fetch.Branches 4575539 # Number of branches that fetch encountered
960system.cpu1.fetch.predictedBranches 1337619 # Number of branches that fetch has predicted taken
961system.cpu1.fetch.Cycles 9079051 # Number of cycles fetch has run and was not squashing or blocked
962system.cpu1.fetch.SquashCycles 321428 # Number of cycles fetch has spent squashing
963system.cpu1.fetch.MiscStallCycles 26636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
964system.cpu1.fetch.PendingTrapStallCycles 222369 # Number of stall cycles due to pending traps
965system.cpu1.fetch.PendingQuiesceStallCycles 65129 # Number of stall cycles due to pending quiesce instructions
966system.cpu1.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR
967system.cpu1.fetch.CacheLines 1934705 # Number of cache lines fetched
968system.cpu1.fetch.IcacheSquashes 65647 # Number of outstanding Icache misses that were squashed
969system.cpu1.fetch.rateDist::samples 17881393 # Number of instructions fetched each cycle (Total)
970system.cpu1.fetch.rateDist::mean 0.985360 # Number of instructions fetched each cycle (Total)
971system.cpu1.fetch.rateDist::stdev 2.396691 # Number of instructions fetched each cycle (Total)
972system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
973system.cpu1.fetch.rateDist::0 14806869 82.81% 82.81% # Number of instructions fetched each cycle (Total)
974system.cpu1.fetch.rateDist::1 203122 1.14% 83.94% # Number of instructions fetched each cycle (Total)
975system.cpu1.fetch.rateDist::2 303524 1.70% 85.64% # Number of instructions fetched each cycle (Total)
976system.cpu1.fetch.rateDist::3 223355 1.25% 86.89% # Number of instructions fetched each cycle (Total)
977system.cpu1.fetch.rateDist::4 384843 2.15% 89.04% # Number of instructions fetched each cycle (Total)
978system.cpu1.fetch.rateDist::5 149669 0.84% 89.88% # Number of instructions fetched each cycle (Total)
979system.cpu1.fetch.rateDist::6 166893 0.93% 90.81% # Number of instructions fetched each cycle (Total)
980system.cpu1.fetch.rateDist::7 294645 1.65% 92.46% # Number of instructions fetched each cycle (Total)
981system.cpu1.fetch.rateDist::8 1348473 7.54% 100.00% # Number of instructions fetched each cycle (Total)
982system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
983system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
984system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
985system.cpu1.fetch.rateDist::total 17881393 # Number of instructions fetched each cycle (Total)
986system.cpu1.fetch.branchRate 0.244224 # Number of branch fetches per cycle
987system.cpu1.fetch.rate 0.940463 # Number of inst fetches per cycle
988system.cpu1.decode.IdleCycles 6834927 # Number of cycles decode is idle
989system.cpu1.decode.BlockedCycles 8400269 # Number of cycles decode is blocked
990system.cpu1.decode.RunCycles 2240291 # Number of cycles decode is running
991system.cpu1.decode.UnblockCycles 252863 # Number of cycles decode is unblocking
992system.cpu1.decode.SquashCycles 153042 # Number of cycles decode is squashing
993system.cpu1.decode.BranchResolved 134285 # Number of times decode resolved a branch
994system.cpu1.decode.BranchMispred 7749 # Number of times decode detected a branch misprediction
995system.cpu1.decode.DecodedInsts 14408505 # Number of instructions handled by decode
996system.cpu1.decode.SquashedInsts 25621 # Number of squashed instructions handled by decode
997system.cpu1.rename.SquashCycles 153042 # Number of cycles rename is squashing
998system.cpu1.rename.IdleCycles 7012697 # Number of cycles rename is idle
999system.cpu1.rename.BlockCycles 586426 # Number of cycles rename is blocking
1000system.cpu1.rename.serializeStallCycles 6840794 # count of cycles rename stalled for serializing inst
1001system.cpu1.rename.RunCycles 2316099 # Number of cycles rename is running
1002system.cpu1.rename.UnblockCycles 972333 # Number of cycles rename is unblocking
1003system.cpu1.rename.RenamedInsts 13683407 # Number of instructions processed by rename
1004system.cpu1.rename.ROBFullEvents 9781 # Number of times rename has blocked due to ROB full
1005system.cpu1.rename.IQFullEvents 69005 # Number of times rename has blocked due to IQ full
1006system.cpu1.rename.LQFullEvents 16467 # Number of times rename has blocked due to LQ full
1007system.cpu1.rename.SQFullEvents 367791 # Number of times rename has blocked due to SQ full
1008system.cpu1.rename.RenamedOperands 8910587 # Number of destination operands rename has renamed
1009system.cpu1.rename.RenameLookups 16181694 # Number of register rename lookups that rename has made
1010system.cpu1.rename.int_rename_lookups 16097130 # Number of integer rename lookups
1011system.cpu1.rename.fp_rename_lookups 77675 # Number of floating rename lookups
1012system.cpu1.rename.CommittedMaps 7724005 # Number of HB maps that are committed
1013system.cpu1.rename.UndoneMaps 1186582 # Number of HB maps that are undone due to squashing
1014system.cpu1.rename.serializingInsts 556647 # count of serializing insts renamed
1015system.cpu1.rename.tempSerializingInsts 57942 # count of temporary serializing insts renamed
1016system.cpu1.rename.skidInsts 2323703 # count of insts added to the skid buffer
1017system.cpu1.memDep0.insertedLoads 2456737 # Number of loads inserted to the mem dependence unit.
1018system.cpu1.memDep0.insertedStores 1657029 # Number of stores inserted to the mem dependence unit.
1019system.cpu1.memDep0.conflictingLoads 275399 # Number of conflicting loads.
1020system.cpu1.memDep0.conflictingStores 155321 # Number of conflicting stores.
1021system.cpu1.iq.iqInstsAdded 12021391 # Number of instructions added to the IQ (excludes non-spec)
1022system.cpu1.iq.iqNonSpecInstsAdded 653222 # Number of non-speculative instructions added to the IQ
1023system.cpu1.iq.iqInstsIssued 11806375 # Number of instructions issued
1024system.cpu1.iq.iqSquashedInstsIssued 22216 # Number of squashed instructions issued
1025system.cpu1.iq.iqSquashedInstsExamined 1705669 # Number of squashed instructions iterated over during squash; mainly for profiling
1026system.cpu1.iq.iqSquashedOperandsExamined 770229 # Number of squashed operands that are examined and possibly removed from graph
1027system.cpu1.iq.iqSquashedNonSpecRemoved 468205 # Number of squashed non-spec instructions that were removed
1028system.cpu1.iq.issued_per_cycle::samples 17881393 # Number of insts issued each cycle
1029system.cpu1.iq.issued_per_cycle::mean 0.660260 # Number of insts issued each cycle
1030system.cpu1.iq.issued_per_cycle::stdev 1.377042 # Number of insts issued each cycle
1031system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1032system.cpu1.iq.issued_per_cycle::0 12935770 72.34% 72.34% # Number of insts issued each cycle
1033system.cpu1.iq.issued_per_cycle::1 2198264 12.29% 84.64% # Number of insts issued each cycle
1034system.cpu1.iq.issued_per_cycle::2 914656 5.12% 89.75% # Number of insts issued each cycle
1035system.cpu1.iq.issued_per_cycle::3 630896 3.53% 93.28% # Number of insts issued each cycle
1036system.cpu1.iq.issued_per_cycle::4 572849 3.20% 96.48% # Number of insts issued each cycle
1037system.cpu1.iq.issued_per_cycle::5 314457 1.76% 98.24% # Number of insts issued each cycle
1038system.cpu1.iq.issued_per_cycle::6 208202 1.16% 99.41% # Number of insts issued each cycle
1039system.cpu1.iq.issued_per_cycle::7 77174 0.43% 99.84% # Number of insts issued each cycle
1040system.cpu1.iq.issued_per_cycle::8 29125 0.16% 100.00% # Number of insts issued each cycle
1041system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1042system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1043system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
1044system.cpu1.iq.issued_per_cycle::total 17881393 # Number of insts issued each cycle
1045system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1046system.cpu1.iq.fu_full::IntAlu 23808 8.12% 8.12% # attempts to use FU when none available
1047system.cpu1.iq.fu_full::IntMult 0 0.00% 8.12% # attempts to use FU when none available
1048system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.12% # attempts to use FU when none available
1049system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.12% # attempts to use FU when none available
1050system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.12% # attempts to use FU when none available
1051system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.12% # attempts to use FU when none available
1052system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.12% # attempts to use FU when none available
1053system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.12% # attempts to use FU when none available
1054system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.12% # attempts to use FU when none available
1055system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.12% # attempts to use FU when none available
1056system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.12% # attempts to use FU when none available
1057system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.12% # attempts to use FU when none available
1058system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.12% # attempts to use FU when none available
1059system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.12% # attempts to use FU when none available
1060system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.12% # attempts to use FU when none available
1061system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.12% # attempts to use FU when none available
1062system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.12% # attempts to use FU when none available
1063system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.12% # attempts to use FU when none available
1064system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.12% # attempts to use FU when none available
1065system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.12% # attempts to use FU when none available
1066system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.12% # attempts to use FU when none available
1067system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.12% # attempts to use FU when none available
1068system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.12% # attempts to use FU when none available
1069system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.12% # attempts to use FU when none available
1070system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.12% # attempts to use FU when none available
1071system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.12% # attempts to use FU when none available
1072system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.12% # attempts to use FU when none available
1073system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.12% # attempts to use FU when none available
1074system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.12% # attempts to use FU when none available
1075system.cpu1.iq.fu_full::MemRead 159009 54.21% 62.33% # attempts to use FU when none available
1076system.cpu1.iq.fu_full::MemWrite 110483 37.67% 100.00% # attempts to use FU when none available
1077system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1078system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1079system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued
1080system.cpu1.iq.FU_type_0::IntAlu 7355530 62.30% 62.33% # Type of FU issued
1081system.cpu1.iq.FU_type_0::IntMult 19854 0.17% 62.50% # Type of FU issued
1082system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued
1083system.cpu1.iq.FU_type_0::FloatAdd 12327 0.10% 62.60% # Type of FU issued
1084system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
1085system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
1086system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
1087system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.62% # Type of FU issued
1088system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.62% # Type of FU issued
1089system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.62% # Type of FU issued
1090system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.62% # Type of FU issued
1091system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.62% # Type of FU issued
1092system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.62% # Type of FU issued
1093system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.62% # Type of FU issued
1094system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.62% # Type of FU issued
1095system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.62% # Type of FU issued
1096system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.62% # Type of FU issued
1097system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.62% # Type of FU issued
1098system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.62% # Type of FU issued
1099system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.62% # Type of FU issued
1100system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.62% # Type of FU issued
1101system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.62% # Type of FU issued
1102system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.62% # Type of FU issued
1103system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.62% # Type of FU issued
1104system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.62% # Type of FU issued
1105system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.62% # Type of FU issued
1106system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.62% # Type of FU issued
1107system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.62% # Type of FU issued
1108system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.62% # Type of FU issued
1109system.cpu1.iq.FU_type_0::MemRead 2486397 21.06% 83.68% # Type of FU issued
1110system.cpu1.iq.FU_type_0::MemWrite 1602376 13.57% 97.25% # Type of FU issued
1111system.cpu1.iq.FU_type_0::IprAccess 324614 2.75% 100.00% # Type of FU issued
1112system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1113system.cpu1.iq.FU_type_0::total 11806375 # Type of FU issued
1114system.cpu1.iq.rate 0.630176 # Inst issue rate
1115system.cpu1.iq.fu_busy_cnt 293300 # FU busy when requested
1116system.cpu1.iq.fu_busy_rate 0.024843 # FU busy rate (busy events/executed inst)
1117system.cpu1.iq.int_inst_queue_reads 41494201 # Number of integer instruction queue reads
1118system.cpu1.iq.int_inst_queue_writes 14236824 # Number of integer instruction queue writes
1119system.cpu1.iq.int_inst_queue_wakeup_accesses 11389686 # Number of integer instruction queue wakeup accesses
1120system.cpu1.iq.fp_inst_queue_reads 315458 # Number of floating instruction queue reads
1121system.cpu1.iq.fp_inst_queue_writes 147457 # Number of floating instruction queue writes
1122system.cpu1.iq.fp_inst_queue_wakeup_accesses 145351 # Number of floating instruction queue wakeup accesses
1123system.cpu1.iq.int_alu_accesses 11926347 # Number of integer alu accesses
1124system.cpu1.iq.fp_alu_accesses 169810 # Number of floating point alu accesses
1125system.cpu1.iew.lsq.thread0.forwLoads 115792 # Number of loads that had data forwarded from stores
1126system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1127system.cpu1.iew.lsq.thread0.squashedLoads 308768 # Number of loads squashed
1128system.cpu1.iew.lsq.thread0.ignoredResponses 1081 # Number of memory responses ignored because the instruction is squashed
1129system.cpu1.iew.lsq.thread0.memOrderViolation 4102 # Number of memory ordering violations
1130system.cpu1.iew.lsq.thread0.squashedStores 143102 # Number of stores squashed
1131system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1132system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1133system.cpu1.iew.lsq.thread0.rescheduledLoads 395 # Number of loads that were rescheduled
1134system.cpu1.iew.lsq.thread0.cacheBlocked 55406 # Number of times an access to memory failed due to the cache being blocked
1135system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1136system.cpu1.iew.iewSquashCycles 153042 # Number of cycles IEW is squashing
1137system.cpu1.iew.iewBlockCycles 303896 # Number of cycles IEW is blocking
1138system.cpu1.iew.iewUnblockCycles 248843 # Number of cycles IEW is unblocking
1139system.cpu1.iew.iewDispatchedInsts 13398271 # Number of instructions dispatched to IQ
1140system.cpu1.iew.iewDispSquashedInsts 36703 # Number of squashed instructions skipped by dispatch
1141system.cpu1.iew.iewDispLoadInsts 2456737 # Number of dispatched load instructions
1142system.cpu1.iew.iewDispStoreInsts 1657029 # Number of dispatched store instructions
1143system.cpu1.iew.iewDispNonSpecInsts 586577 # Number of dispatched non-speculative instructions
1144system.cpu1.iew.iewIQFullEvents 4501 # Number of times the IQ has become full, causing a stall
1145system.cpu1.iew.iewLSQFullEvents 243181 # Number of times the LSQ has become full, causing a stall
1146system.cpu1.iew.memOrderViolationEvents 4102 # Number of memory order violations
1147system.cpu1.iew.predictedTakenIncorrect 36741 # Number of branches that were predicted taken incorrectly
1148system.cpu1.iew.predictedNotTakenIncorrect 118067 # Number of branches that were predicted not taken incorrectly
1149system.cpu1.iew.branchMispredicts 154808 # Number of branch mispredicts detected at execute
1150system.cpu1.iew.iewExecutedInsts 11654930 # Number of executed instructions
1151system.cpu1.iew.iewExecLoadInsts 2396476 # Number of load instructions executed
1152system.cpu1.iew.iewExecSquashedInsts 151445 # Number of squashed instructions skipped in execute
1153system.cpu1.iew.exec_swp 0 # number of swp insts executed
1154system.cpu1.iew.exec_nop 723658 # number of nop insts executed
1155system.cpu1.iew.exec_refs 3982565 # number of memory reference insts executed
1156system.cpu1.iew.exec_branches 1739472 # Number of branches executed
1157system.cpu1.iew.exec_stores 1586089 # Number of stores executed
1158system.cpu1.iew.exec_rate 0.622093 # Inst execution rate
1159system.cpu1.iew.wb_sent 11565622 # cumulative count of insts sent to commit
1160system.cpu1.iew.wb_count 11535037 # cumulative count of insts written-back
1161system.cpu1.iew.wb_producers 5422471 # num instructions producing a value
1162system.cpu1.iew.wb_consumers 7736628 # num instructions consuming a value
1163system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1164system.cpu1.iew.wb_rate 0.615694 # insts written-back per cycle
1165system.cpu1.iew.wb_fanout 0.700883 # average fanout of values written-back
1166system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1167system.cpu1.commit.commitSquashedInsts 1839025 # The number of squashed insts skipped by commit
1168system.cpu1.commit.commitNonSpecStalls 185017 # The number of times commit has been forced to stall to communicate backwards
1169system.cpu1.commit.branchMispredicts 142916 # The number of times a branch was mispredicted
1170system.cpu1.commit.committed_per_cycle::samples 17538839 # Number of insts commited each cycle
1171system.cpu1.commit.committed_per_cycle::mean 0.655077 # Number of insts commited each cycle
1172system.cpu1.commit.committed_per_cycle::stdev 1.643008 # Number of insts commited each cycle
1173system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1174system.cpu1.commit.committed_per_cycle::0 13431880 76.58% 76.58% # Number of insts commited each cycle
1175system.cpu1.commit.committed_per_cycle::1 1875136 10.69% 87.27% # Number of insts commited each cycle
1176system.cpu1.commit.committed_per_cycle::2 688221 3.92% 91.20% # Number of insts commited each cycle
1177system.cpu1.commit.committed_per_cycle::3 418119 2.38% 93.58% # Number of insts commited each cycle
1178system.cpu1.commit.committed_per_cycle::4 312509 1.78% 95.36% # Number of insts commited each cycle
1179system.cpu1.commit.committed_per_cycle::5 131127 0.75% 96.11% # Number of insts commited each cycle
1180system.cpu1.commit.committed_per_cycle::6 110360 0.63% 96.74% # Number of insts commited each cycle
1181system.cpu1.commit.committed_per_cycle::7 156367 0.89% 97.63% # Number of insts commited each cycle
1182system.cpu1.commit.committed_per_cycle::8 415120 2.37% 100.00% # Number of insts commited each cycle
1183system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1184system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1185system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1186system.cpu1.commit.committed_per_cycle::total 17538839 # Number of insts commited each cycle
1187system.cpu1.commit.committedInsts 11489295 # Number of instructions committed
1188system.cpu1.commit.committedOps 11489295 # Number of ops (including micro ops) committed
1189system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1190system.cpu1.commit.refs 3661896 # Number of memory references committed
1191system.cpu1.commit.loads 2147969 # Number of loads committed
1192system.cpu1.commit.membars 61867 # Number of memory barriers committed
1193system.cpu1.commit.branches 1640602 # Number of branches committed
1194system.cpu1.commit.fp_insts 143665 # Number of committed floating point instructions.
1195system.cpu1.commit.int_insts 10598150 # Number of committed integer instructions.
1196system.cpu1.commit.function_calls 183822 # Number of function calls committed.
1197system.cpu1.commit.op_class_0::No_OpClass 606334 5.28% 5.28% # Class of committed instruction
1198system.cpu1.commit.op_class_0::IntAlu 6800030 59.19% 64.46% # Class of committed instruction
1199system.cpu1.commit.op_class_0::IntMult 19654 0.17% 64.63% # Class of committed instruction
1200system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.63% # Class of committed instruction
1201system.cpu1.commit.op_class_0::FloatAdd 12323 0.11% 64.74% # Class of committed instruction
1202system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction
1203system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction
1204system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction
1205system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction
1206system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction
1207system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction
1208system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction
1209system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction
1210system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction
1211system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction
1212system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction

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1219system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction
1220system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction
1221system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction
1222system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction
1223system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction
1224system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction
1225system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction
1226system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction
1227system.cpu1.commit.op_class_0::MemRead 2209836 19.23% 83.99% # Class of committed instruction
1228system.cpu1.commit.op_class_0::MemWrite 1514745 13.18% 97.17% # Class of committed instruction
1229system.cpu1.commit.op_class_0::IprAccess 324614 2.83% 100.00% # Class of committed instruction
1230system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1231system.cpu1.commit.op_class_0::total 11489295 # Class of committed instruction
1232system.cpu1.commit.bw_lim_events 415120 # number cycles where commit BW limit reached
1233system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1234system.cpu1.rob.rob_reads 30366198 # The number of ROB reads
1235system.cpu1.rob.rob_writes 26995045 # The number of ROB writes
1236system.cpu1.timesIdled 163095 # Number of times that the entire CPU went into an idle state and unscheduled itself
1237system.cpu1.idleCycles 853636 # Total number of cycles that the CPU has spent unscheduled due to idling
1238system.cpu1.quiesceCycles 3782985916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1239system.cpu1.committedInsts 10886479 # Number of Instructions Simulated
1240system.cpu1.committedOps 10886479 # Number of Ops (including micro ops) Simulated
1241system.cpu1.cpi 1.720945 # CPI: Cycles Per Instruction
1242system.cpu1.cpi_total 1.720945 # CPI: Total CPI of All Threads
1243system.cpu1.ipc 0.581076 # IPC: Instructions Per Cycle
1244system.cpu1.ipc_total 0.581076 # IPC: Total IPC of All Threads
1245system.cpu1.int_regfile_reads 14951888 # number of integer regfile reads
1246system.cpu1.int_regfile_writes 8155185 # number of integer regfile writes
1247system.cpu1.fp_regfile_reads 77020 # number of floating regfile reads
1248system.cpu1.fp_regfile_writes 77068 # number of floating regfile writes
1249system.cpu1.misc_regfile_reads 1117526 # number of misc regfile reads
1250system.cpu1.misc_regfile_writes 276759 # number of misc regfile writes
1251system.cpu1.dcache.tags.replacements 138501 # number of replacements
1252system.cpu1.dcache.tags.tagsinuse 492.617684 # Cycle average of tags in use
1253system.cpu1.dcache.tags.total_refs 3193598 # Total number of references to valid blocks.
1254system.cpu1.dcache.tags.sampled_refs 138812 # Sample count of references to valid blocks.
1255system.cpu1.dcache.tags.avg_refs 23.006642 # Average number of references to valid blocks.
1256system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit.
1257system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.617684 # Average occupied blocks per requestor
1258system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962144 # Average percentage of cache occupancy
1259system.cpu1.dcache.tags.occ_percent::total 0.962144 # Average percentage of cache occupancy
1260system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
1261system.cpu1.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
1262system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
1263system.cpu1.dcache.tags.tag_accesses 15087685 # Number of tag accesses
1264system.cpu1.dcache.tags.data_accesses 15087685 # Number of data accesses
1265system.cpu1.dcache.ReadReq_hits::cpu1.data 1906947 # number of ReadReq hits
1266system.cpu1.dcache.ReadReq_hits::total 1906947 # number of ReadReq hits
1267system.cpu1.dcache.WriteReq_hits::cpu1.data 1195571 # number of WriteReq hits
1268system.cpu1.dcache.WriteReq_hits::total 1195571 # number of WriteReq hits
1269system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 44901 # number of LoadLockedReq hits
1270system.cpu1.dcache.LoadLockedReq_hits::total 44901 # number of LoadLockedReq hits
1271system.cpu1.dcache.StoreCondReq_hits::cpu1.data 43886 # number of StoreCondReq hits
1272system.cpu1.dcache.StoreCondReq_hits::total 43886 # number of StoreCondReq hits
1273system.cpu1.dcache.demand_hits::cpu1.data 3102518 # number of demand (read+write) hits
1274system.cpu1.dcache.demand_hits::total 3102518 # number of demand (read+write) hits
1275system.cpu1.dcache.overall_hits::cpu1.data 3102518 # number of overall hits
1276system.cpu1.dcache.overall_hits::total 3102518 # number of overall hits
1277system.cpu1.dcache.ReadReq_misses::cpu1.data 266692 # number of ReadReq misses
1278system.cpu1.dcache.ReadReq_misses::total 266692 # number of ReadReq misses
1279system.cpu1.dcache.WriteReq_misses::cpu1.data 262982 # number of WriteReq misses
1280system.cpu1.dcache.WriteReq_misses::total 262982 # number of WriteReq misses
1281system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8052 # number of LoadLockedReq misses
1282system.cpu1.dcache.LoadLockedReq_misses::total 8052 # number of LoadLockedReq misses
1283system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4916 # number of StoreCondReq misses
1284system.cpu1.dcache.StoreCondReq_misses::total 4916 # number of StoreCondReq misses
1285system.cpu1.dcache.demand_misses::cpu1.data 529674 # number of demand (read+write) misses
1286system.cpu1.dcache.demand_misses::total 529674 # number of demand (read+write) misses
1287system.cpu1.dcache.overall_misses::cpu1.data 529674 # number of overall misses
1288system.cpu1.dcache.overall_misses::total 529674 # number of overall misses
1289system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4020623652 # number of ReadReq miss cycles
1290system.cpu1.dcache.ReadReq_miss_latency::total 4020623652 # number of ReadReq miss cycles
1291system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8531401983 # number of WriteReq miss cycles
1292system.cpu1.dcache.WriteReq_miss_latency::total 8531401983 # number of WriteReq miss cycles
1293system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 76759992 # number of LoadLockedReq miss cycles
1294system.cpu1.dcache.LoadLockedReq_miss_latency::total 76759992 # number of LoadLockedReq miss cycles
1295system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36344731 # number of StoreCondReq miss cycles
1296system.cpu1.dcache.StoreCondReq_miss_latency::total 36344731 # number of StoreCondReq miss cycles
1297system.cpu1.dcache.demand_miss_latency::cpu1.data 12552025635 # number of demand (read+write) miss cycles
1298system.cpu1.dcache.demand_miss_latency::total 12552025635 # number of demand (read+write) miss cycles
1299system.cpu1.dcache.overall_miss_latency::cpu1.data 12552025635 # number of overall miss cycles
1300system.cpu1.dcache.overall_miss_latency::total 12552025635 # number of overall miss cycles
1301system.cpu1.dcache.ReadReq_accesses::cpu1.data 2173639 # number of ReadReq accesses(hits+misses)
1302system.cpu1.dcache.ReadReq_accesses::total 2173639 # number of ReadReq accesses(hits+misses)
1303system.cpu1.dcache.WriteReq_accesses::cpu1.data 1458553 # number of WriteReq accesses(hits+misses)
1304system.cpu1.dcache.WriteReq_accesses::total 1458553 # number of WriteReq accesses(hits+misses)
1305system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 52953 # number of LoadLockedReq accesses(hits+misses)
1306system.cpu1.dcache.LoadLockedReq_accesses::total 52953 # number of LoadLockedReq accesses(hits+misses)
1307system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 48802 # number of StoreCondReq accesses(hits+misses)
1308system.cpu1.dcache.StoreCondReq_accesses::total 48802 # number of StoreCondReq accesses(hits+misses)
1309system.cpu1.dcache.demand_accesses::cpu1.data 3632192 # number of demand (read+write) accesses
1310system.cpu1.dcache.demand_accesses::total 3632192 # number of demand (read+write) accesses
1311system.cpu1.dcache.overall_accesses::cpu1.data 3632192 # number of overall (read+write) accesses
1312system.cpu1.dcache.overall_accesses::total 3632192 # number of overall (read+write) accesses
1313system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122694 # miss rate for ReadReq accesses
1314system.cpu1.dcache.ReadReq_miss_rate::total 0.122694 # miss rate for ReadReq accesses
1315system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.180303 # miss rate for WriteReq accesses
1316system.cpu1.dcache.WriteReq_miss_rate::total 0.180303 # miss rate for WriteReq accesses
1317system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152059 # miss rate for LoadLockedReq accesses
1318system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152059 # miss rate for LoadLockedReq accesses
1319system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100734 # miss rate for StoreCondReq accesses
1320system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100734 # miss rate for StoreCondReq accesses
1321system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145828 # miss rate for demand accesses
1322system.cpu1.dcache.demand_miss_rate::total 0.145828 # miss rate for demand accesses
1323system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145828 # miss rate for overall accesses
1324system.cpu1.dcache.overall_miss_rate::total 0.145828 # miss rate for overall accesses
1325system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484 # average ReadReq miss latency
1326system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484 # average ReadReq miss latency
1327system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107 # average WriteReq miss latency
1328system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107 # average WriteReq miss latency
1329system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9533.034277 # average LoadLockedReq miss latency
1330system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9533.034277 # average LoadLockedReq miss latency
1331system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7393.151139 # average StoreCondReq miss latency
1332system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7393.151139 # average StoreCondReq miss latency
1333system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency
1334system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522 # average overall miss latency
1335system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency
1336system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522 # average overall miss latency
1337system.cpu1.dcache.blocked_cycles::no_mshrs 379144 # number of cycles access was blocked
1338system.cpu1.dcache.blocked_cycles::no_targets 215 # number of cycles access was blocked
1339system.cpu1.dcache.blocked::no_mshrs 18342 # number of cycles access was blocked
1340system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked
1341system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.670810 # average number of cycles each access was blocked
1342system.cpu1.dcache.avg_blocked_cycles::no_targets 23.888889 # average number of cycles each access was blocked
1343system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1344system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1345system.cpu1.dcache.writebacks::writebacks 93139 # number of writebacks
1346system.cpu1.dcache.writebacks::total 93139 # number of writebacks
1347system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 164682 # number of ReadReq MSHR hits
1348system.cpu1.dcache.ReadReq_mshr_hits::total 164682 # number of ReadReq MSHR hits
1349system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 213530 # number of WriteReq MSHR hits
1350system.cpu1.dcache.WriteReq_mshr_hits::total 213530 # number of WriteReq MSHR hits
1351system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits
1352system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits
1353system.cpu1.dcache.demand_mshr_hits::cpu1.data 378212 # number of demand (read+write) MSHR hits
1354system.cpu1.dcache.demand_mshr_hits::total 378212 # number of demand (read+write) MSHR hits
1355system.cpu1.dcache.overall_mshr_hits::cpu1.data 378212 # number of overall MSHR hits
1356system.cpu1.dcache.overall_mshr_hits::total 378212 # number of overall MSHR hits
1357system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 102010 # number of ReadReq MSHR misses
1358system.cpu1.dcache.ReadReq_mshr_misses::total 102010 # number of ReadReq MSHR misses
1359system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 49452 # number of WriteReq MSHR misses
1360system.cpu1.dcache.WriteReq_mshr_misses::total 49452 # number of WriteReq MSHR misses
1361system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7397 # number of LoadLockedReq MSHR misses
1362system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7397 # number of LoadLockedReq MSHR misses
1363system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4916 # number of StoreCondReq MSHR misses
1364system.cpu1.dcache.StoreCondReq_mshr_misses::total 4916 # number of StoreCondReq MSHR misses
1365system.cpu1.dcache.demand_mshr_misses::cpu1.data 151462 # number of demand (read+write) MSHR misses
1366system.cpu1.dcache.demand_mshr_misses::total 151462 # number of demand (read+write) MSHR misses
1367system.cpu1.dcache.overall_mshr_misses::cpu1.data 151462 # number of overall MSHR misses
1368system.cpu1.dcache.overall_mshr_misses::total 151462 # number of overall MSHR misses
1369system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1194457513 # number of ReadReq MSHR miss cycles
1370system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1194457513 # number of ReadReq MSHR miss cycles
1371system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1312928589 # number of WriteReq MSHR miss cycles
1372system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1312928589 # number of WriteReq MSHR miss cycles
1373system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54001007 # number of LoadLockedReq MSHR miss cycles
1374system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54001007 # number of LoadLockedReq MSHR miss cycles
1375system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26510269 # number of StoreCondReq MSHR miss cycles
1376system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26510269 # number of StoreCondReq MSHR miss cycles
1377system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2507386102 # number of demand (read+write) MSHR miss cycles
1378system.cpu1.dcache.demand_mshr_miss_latency::total 2507386102 # number of demand (read+write) MSHR miss cycles
1379system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2507386102 # number of overall MSHR miss cycles
1380system.cpu1.dcache.overall_mshr_miss_latency::total 2507386102 # number of overall MSHR miss cycles
1381system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24847500 # number of ReadReq MSHR uncacheable cycles
1382system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24847500 # number of ReadReq MSHR uncacheable cycles
1383system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 692513000 # number of WriteReq MSHR uncacheable cycles
1384system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 692513000 # number of WriteReq MSHR uncacheable cycles
1385system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717360500 # number of overall MSHR uncacheable cycles
1386system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717360500 # number of overall MSHR uncacheable cycles
1387system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046931 # mshr miss rate for ReadReq accesses
1388system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046931 # mshr miss rate for ReadReq accesses
1389system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033905 # mshr miss rate for WriteReq accesses
1390system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033905 # mshr miss rate for WriteReq accesses
1391system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139690 # mshr miss rate for LoadLockedReq accesses
1392system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139690 # mshr miss rate for LoadLockedReq accesses
1393system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100734 # mshr miss rate for StoreCondReq accesses
1394system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100734 # mshr miss rate for StoreCondReq accesses
1395system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for demand accesses
1396system.cpu1.dcache.demand_mshr_miss_rate::total 0.041700 # mshr miss rate for demand accesses
1397system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for overall accesses
1398system.cpu1.dcache.overall_mshr_miss_rate::total 0.041700 # mshr miss rate for overall accesses
1399system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812 # average ReadReq mshr miss latency
1400system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812 # average ReadReq mshr miss latency
1401system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902 # average WriteReq mshr miss latency
1402system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902 # average WriteReq mshr miss latency
1403system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7300.392997 # average LoadLockedReq mshr miss latency
1404system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7300.392997 # average LoadLockedReq mshr miss latency
1405system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5392.650325 # average StoreCondReq mshr miss latency
1406system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5392.650325 # average StoreCondReq mshr miss latency
1407system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency
1408system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency
1409system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency
1410system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency
1411system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1412system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1413system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1414system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1415system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1416system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1417system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1418system.cpu1.icache.tags.replacements 306147 # number of replacements
1419system.cpu1.icache.tags.tagsinuse 470.962529 # Cycle average of tags in use
1420system.cpu1.icache.tags.total_refs 1618659 # Total number of references to valid blocks.
1421system.cpu1.icache.tags.sampled_refs 306656 # Sample count of references to valid blocks.
1422system.cpu1.icache.tags.avg_refs 5.278419 # Average number of references to valid blocks.
1423system.cpu1.icache.tags.warmup_cycle 1878409820250 # Cycle when the warmup percentage was hit.
1424system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.962529 # Average occupied blocks per requestor
1425system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919849 # Average percentage of cache occupancy
1426system.cpu1.icache.tags.occ_percent::total 0.919849 # Average percentage of cache occupancy
1427system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
1428system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
1429system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1430system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
1431system.cpu1.icache.tags.tag_accesses 2241410 # Number of tag accesses
1432system.cpu1.icache.tags.data_accesses 2241410 # Number of data accesses
1433system.cpu1.icache.ReadReq_hits::cpu1.inst 1618659 # number of ReadReq hits
1434system.cpu1.icache.ReadReq_hits::total 1618659 # number of ReadReq hits
1435system.cpu1.icache.demand_hits::cpu1.inst 1618659 # number of demand (read+write) hits
1436system.cpu1.icache.demand_hits::total 1618659 # number of demand (read+write) hits
1437system.cpu1.icache.overall_hits::cpu1.inst 1618659 # number of overall hits
1438system.cpu1.icache.overall_hits::total 1618659 # number of overall hits
1439system.cpu1.icache.ReadReq_misses::cpu1.inst 316046 # number of ReadReq misses
1440system.cpu1.icache.ReadReq_misses::total 316046 # number of ReadReq misses
1441system.cpu1.icache.demand_misses::cpu1.inst 316046 # number of demand (read+write) misses
1442system.cpu1.icache.demand_misses::total 316046 # number of demand (read+write) misses
1443system.cpu1.icache.overall_misses::cpu1.inst 316046 # number of overall misses
1444system.cpu1.icache.overall_misses::total 316046 # number of overall misses
1445system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4251188208 # number of ReadReq miss cycles
1446system.cpu1.icache.ReadReq_miss_latency::total 4251188208 # number of ReadReq miss cycles
1447system.cpu1.icache.demand_miss_latency::cpu1.inst 4251188208 # number of demand (read+write) miss cycles
1448system.cpu1.icache.demand_miss_latency::total 4251188208 # number of demand (read+write) miss cycles
1449system.cpu1.icache.overall_miss_latency::cpu1.inst 4251188208 # number of overall miss cycles
1450system.cpu1.icache.overall_miss_latency::total 4251188208 # number of overall miss cycles
1451system.cpu1.icache.ReadReq_accesses::cpu1.inst 1934705 # number of ReadReq accesses(hits+misses)
1452system.cpu1.icache.ReadReq_accesses::total 1934705 # number of ReadReq accesses(hits+misses)
1453system.cpu1.icache.demand_accesses::cpu1.inst 1934705 # number of demand (read+write) accesses
1454system.cpu1.icache.demand_accesses::total 1934705 # number of demand (read+write) accesses
1455system.cpu1.icache.overall_accesses::cpu1.inst 1934705 # number of overall (read+write) accesses
1456system.cpu1.icache.overall_accesses::total 1934705 # number of overall (read+write) accesses
1457system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163356 # miss rate for ReadReq accesses
1458system.cpu1.icache.ReadReq_miss_rate::total 0.163356 # miss rate for ReadReq accesses
1459system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163356 # miss rate for demand accesses
1460system.cpu1.icache.demand_miss_rate::total 0.163356 # miss rate for demand accesses
1461system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163356 # miss rate for overall accesses
1462system.cpu1.icache.overall_miss_rate::total 0.163356 # miss rate for overall accesses
1463system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159 # average ReadReq miss latency
1464system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159 # average ReadReq miss latency
1465system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency
1466system.cpu1.icache.demand_avg_miss_latency::total 13451.169159 # average overall miss latency
1467system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency
1468system.cpu1.icache.overall_avg_miss_latency::total 13451.169159 # average overall miss latency
1469system.cpu1.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked
1470system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1471system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked
1472system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1473system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.307692 # average number of cycles each access was blocked
1474system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1475system.cpu1.icache.fast_writes 0 # number of fast writes performed
1476system.cpu1.icache.cache_copies 0 # number of cache copies performed
1477system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9341 # number of ReadReq MSHR hits
1478system.cpu1.icache.ReadReq_mshr_hits::total 9341 # number of ReadReq MSHR hits
1479system.cpu1.icache.demand_mshr_hits::cpu1.inst 9341 # number of demand (read+write) MSHR hits
1480system.cpu1.icache.demand_mshr_hits::total 9341 # number of demand (read+write) MSHR hits
1481system.cpu1.icache.overall_mshr_hits::cpu1.inst 9341 # number of overall MSHR hits
1482system.cpu1.icache.overall_mshr_hits::total 9341 # number of overall MSHR hits
1483system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 306705 # number of ReadReq MSHR misses
1484system.cpu1.icache.ReadReq_mshr_misses::total 306705 # number of ReadReq MSHR misses
1485system.cpu1.icache.demand_mshr_misses::cpu1.inst 306705 # number of demand (read+write) MSHR misses
1486system.cpu1.icache.demand_mshr_misses::total 306705 # number of demand (read+write) MSHR misses
1487system.cpu1.icache.overall_mshr_misses::cpu1.inst 306705 # number of overall MSHR misses
1488system.cpu1.icache.overall_mshr_misses::total 306705 # number of overall MSHR misses
1489system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3543296218 # number of ReadReq MSHR miss cycles
1490system.cpu1.icache.ReadReq_mshr_miss_latency::total 3543296218 # number of ReadReq MSHR miss cycles
1491system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3543296218 # number of demand (read+write) MSHR miss cycles
1492system.cpu1.icache.demand_mshr_miss_latency::total 3543296218 # number of demand (read+write) MSHR miss cycles
1493system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3543296218 # number of overall MSHR miss cycles
1494system.cpu1.icache.overall_mshr_miss_latency::total 3543296218 # number of overall MSHR miss cycles
1495system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for ReadReq accesses
1496system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158528 # mshr miss rate for ReadReq accesses
1497system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for demand accesses
1498system.cpu1.icache.demand_mshr_miss_rate::total 0.158528 # mshr miss rate for demand accesses
1499system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for overall accesses
1500system.cpu1.icache.overall_mshr_miss_rate::total 0.158528 # mshr miss rate for overall accesses
1501system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average ReadReq mshr miss latency
1502system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700 # average ReadReq mshr miss latency
1503system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency
1504system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency
1505system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency
1506system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency
1507system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1508system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1509system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1510system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1511system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1512system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1513system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1514system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1515system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1516system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1517system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1518system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1519system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1520system.iobus.trans_dist::ReadReq 7368 # Transaction distribution
1521system.iobus.trans_dist::ReadResp 7368 # Transaction distribution
1522system.iobus.trans_dist::WriteReq 55198 # Transaction distribution
1523system.iobus.trans_dist::WriteResp 13646 # Transaction distribution
1524system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1525system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13082 # Packet count per connected master and slave (bytes)
1526system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
1527system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1528system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1529system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1530system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1531system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
1532system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1533system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1534system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1535system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1536system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1537system.iobus.pkt_count_system.bridge.master::total 41682 # Packet count per connected master and slave (bytes)
1538system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
1539system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
1540system.iobus.pkt_count::total 125132 # Packet count per connected master and slave (bytes)
1541system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52328 # Cumulative packet size per connected master and slave (bytes)
1542system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
1543system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1544system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1545system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1546system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1547system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
1548system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1549system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1550system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1551system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1552system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1553system.iobus.pkt_size_system.bridge.master::total 78554 # Cumulative packet size per connected master and slave (bytes)
1554system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
1555system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
1556system.iobus.pkt_size::total 2740162 # Cumulative packet size per connected master and slave (bytes)
1557system.iobus.reqLayer0.occupancy 12437000 # Layer occupancy (ticks)
1558system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1559system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks)
1560system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1561system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1562system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1563system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1564system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1565system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1566system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1567system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1568system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1569system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
1570system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1571system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1572system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1573system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1574system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1575system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1576system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1577system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1578system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1579system.iobus.reqLayer29.occupancy 406224779 # Layer occupancy (ticks)
1580system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1581system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1582system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1583system.iobus.respLayer0.occupancy 28036000 # Layer occupancy (ticks)
1584system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1585system.iobus.respLayer1.occupancy 42010550 # Layer occupancy (ticks)
1586system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1587system.iocache.tags.replacements 41693 # number of replacements
1588system.iocache.tags.tagsinuse 0.465320 # Cycle average of tags in use
1589system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1590system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks.
1591system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1592system.iocache.tags.warmup_cycle 1710336865000 # Cycle when the warmup percentage was hit.
1593system.iocache.tags.occ_blocks::tsunami.ide 0.465320 # Average occupied blocks per requestor
1594system.iocache.tags.occ_percent::tsunami.ide 0.029083 # Average percentage of cache occupancy
1595system.iocache.tags.occ_percent::total 0.029083 # Average percentage of cache occupancy
1596system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1597system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
1598system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1599system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1600system.iocache.tags.data_accesses 375525 # Number of data accesses
1601system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1602system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1603system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1604system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1605system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1606system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1607system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1608system.iocache.overall_misses::total 173 # number of overall misses
1609system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles
1610system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles
1611system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13658910846 # number of WriteInvalidateReq miss cycles
1612system.iocache.WriteInvalidateReq_miss_latency::total 13658910846 # number of WriteInvalidateReq miss cycles
1613system.iocache.demand_miss_latency::tsunami.ide 21134383 # number of demand (read+write) miss cycles
1614system.iocache.demand_miss_latency::total 21134383 # number of demand (read+write) miss cycles
1615system.iocache.overall_miss_latency::tsunami.ide 21134383 # number of overall miss cycles
1616system.iocache.overall_miss_latency::total 21134383 # number of overall miss cycles
1617system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1618system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1619system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1620system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1621system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1622system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1623system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1624system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
1625system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1626system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1627system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1628system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1629system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1630system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1631system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1632system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1633system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency
1634system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency
1635system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598 # average WriteInvalidateReq miss latency
1636system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598 # average WriteInvalidateReq miss latency
1637system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency
1638system.iocache.demand_avg_miss_latency::total 122164.063584 # average overall miss latency
1639system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency
1640system.iocache.overall_avg_miss_latency::total 122164.063584 # average overall miss latency
1641system.iocache.blocked_cycles::no_mshrs 207096 # number of cycles access was blocked
1642system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1643system.iocache.blocked::no_mshrs 23572 # number of cycles access was blocked
1644system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1645system.iocache.avg_blocked_cycles::no_mshrs 8.785678 # average number of cycles each access was blocked
1646system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1647system.iocache.fast_writes 0 # number of fast writes performed
1648system.iocache.cache_copies 0 # number of cache copies performed
1649system.iocache.writebacks::writebacks 41520 # number of writebacks
1650system.iocache.writebacks::total 41520 # number of writebacks
1651system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1652system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1653system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1654system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1655system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1656system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1657system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1658system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
1659system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles
1660system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles
1661system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11498106946 # number of WriteInvalidateReq MSHR miss cycles
1662system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11498106946 # number of WriteInvalidateReq MSHR miss cycles
1663system.iocache.demand_mshr_miss_latency::tsunami.ide 12137383 # number of demand (read+write) MSHR miss cycles
1664system.iocache.demand_mshr_miss_latency::total 12137383 # number of demand (read+write) MSHR miss cycles
1665system.iocache.overall_mshr_miss_latency::tsunami.ide 12137383 # number of overall MSHR miss cycles
1666system.iocache.overall_mshr_miss_latency::total 12137383 # number of overall MSHR miss cycles
1667system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1668system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1669system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1670system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1671system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1672system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1673system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1674system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1675system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency
1676system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency
1677system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382 # average WriteInvalidateReq mshr miss latency
1678system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382 # average WriteInvalidateReq mshr miss latency
1679system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency
1680system.iocache.demand_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency
1681system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency
1682system.iocache.overall_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency
1683system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1684system.l2c.tags.replacements 345011 # number of replacements
1685system.l2c.tags.tagsinuse 65255.839207 # Cycle average of tags in use
1686system.l2c.tags.total_refs 2587062 # Total number of references to valid blocks.
1687system.l2c.tags.sampled_refs 410177 # Sample count of references to valid blocks.
1688system.l2c.tags.avg_refs 6.307184 # Average number of references to valid blocks.
1689system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit.
1690system.l2c.tags.occ_blocks::writebacks 53401.606938 # Average occupied blocks per requestor
1691system.l2c.tags.occ_blocks::cpu0.inst 5320.695867 # Average occupied blocks per requestor
1692system.l2c.tags.occ_blocks::cpu0.data 6228.167915 # Average occupied blocks per requestor
1693system.l2c.tags.occ_blocks::cpu1.inst 214.693065 # Average occupied blocks per requestor
1694system.l2c.tags.occ_blocks::cpu1.data 90.675422 # Average occupied blocks per requestor
1695system.l2c.tags.occ_percent::writebacks 0.814844 # Average percentage of cache occupancy
1696system.l2c.tags.occ_percent::cpu0.inst 0.081187 # Average percentage of cache occupancy
1697system.l2c.tags.occ_percent::cpu0.data 0.095034 # Average percentage of cache occupancy
1698system.l2c.tags.occ_percent::cpu1.inst 0.003276 # Average percentage of cache occupancy
1699system.l2c.tags.occ_percent::cpu1.data 0.001384 # Average percentage of cache occupancy
1700system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy
1701system.l2c.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id
1702system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
1703system.l2c.tags.age_task_id_blocks_1024::1 2663 # Occupied blocks per task id
1704system.l2c.tags.age_task_id_blocks_1024::2 5629 # Occupied blocks per task id
1705system.l2c.tags.age_task_id_blocks_1024::3 5286 # Occupied blocks per task id
1706system.l2c.tags.age_task_id_blocks_1024::4 51350 # Occupied blocks per task id
1707system.l2c.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id
1708system.l2c.tags.tag_accesses 27100727 # Number of tag accesses
1709system.l2c.tags.data_accesses 27100727 # Number of data accesses
1710system.l2c.ReadReq_hits::cpu0.inst 808308 # number of ReadReq hits
1711system.l2c.ReadReq_hits::cpu0.data 697381 # number of ReadReq hits
1712system.l2c.ReadReq_hits::cpu1.inst 305176 # number of ReadReq hits
1713system.l2c.ReadReq_hits::cpu1.data 93224 # number of ReadReq hits
1714system.l2c.ReadReq_hits::total 1904089 # number of ReadReq hits
1715system.l2c.Writeback_hits::writebacks 804982 # number of Writeback hits
1716system.l2c.Writeback_hits::total 804982 # number of Writeback hits
1717system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits
1718system.l2c.UpgradeReq_hits::cpu1.data 430 # number of UpgradeReq hits
1719system.l2c.UpgradeReq_hits::total 602 # number of UpgradeReq hits
1720system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits
1721system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
1722system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits
1723system.l2c.ReadExReq_hits::cpu0.data 137834 # number of ReadExReq hits
1724system.l2c.ReadExReq_hits::cpu1.data 34568 # number of ReadExReq hits
1725system.l2c.ReadExReq_hits::total 172402 # number of ReadExReq hits
1726system.l2c.demand_hits::cpu0.inst 808308 # number of demand (read+write) hits
1727system.l2c.demand_hits::cpu0.data 835215 # number of demand (read+write) hits
1728system.l2c.demand_hits::cpu1.inst 305176 # number of demand (read+write) hits
1729system.l2c.demand_hits::cpu1.data 127792 # number of demand (read+write) hits
1730system.l2c.demand_hits::total 2076491 # number of demand (read+write) hits
1731system.l2c.overall_hits::cpu0.inst 808308 # number of overall hits
1732system.l2c.overall_hits::cpu0.data 835215 # number of overall hits
1733system.l2c.overall_hits::cpu1.inst 305176 # number of overall hits
1734system.l2c.overall_hits::cpu1.data 127792 # number of overall hits
1735system.l2c.overall_hits::total 2076491 # number of overall hits
1736system.l2c.ReadReq_misses::cpu0.inst 13868 # number of ReadReq misses
1737system.l2c.ReadReq_misses::cpu0.data 273214 # number of ReadReq misses
1738system.l2c.ReadReq_misses::cpu1.inst 1510 # number of ReadReq misses
1739system.l2c.ReadReq_misses::cpu1.data 835 # number of ReadReq misses
1740system.l2c.ReadReq_misses::total 289427 # number of ReadReq misses
1741system.l2c.UpgradeReq_misses::cpu0.data 2863 # number of UpgradeReq misses
1742system.l2c.UpgradeReq_misses::cpu1.data 1520 # number of UpgradeReq misses
1743system.l2c.UpgradeReq_misses::total 4383 # number of UpgradeReq misses
1744system.l2c.SCUpgradeReq_misses::cpu0.data 730 # number of SCUpgradeReq misses
1745system.l2c.SCUpgradeReq_misses::cpu1.data 742 # number of SCUpgradeReq misses
1746system.l2c.SCUpgradeReq_misses::total 1472 # number of SCUpgradeReq misses
1747system.l2c.ReadExReq_misses::cpu0.data 114473 # number of ReadExReq misses
1748system.l2c.ReadExReq_misses::cpu1.data 7452 # number of ReadExReq misses
1749system.l2c.ReadExReq_misses::total 121925 # number of ReadExReq misses
1750system.l2c.demand_misses::cpu0.inst 13868 # number of demand (read+write) misses
1751system.l2c.demand_misses::cpu0.data 387687 # number of demand (read+write) misses
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1753system.l2c.demand_misses::cpu1.data 8287 # number of demand (read+write) misses
1754system.l2c.demand_misses::total 411352 # number of demand (read+write) misses
1755system.l2c.overall_misses::cpu0.inst 13868 # number of overall misses
1756system.l2c.overall_misses::cpu0.data 387687 # number of overall misses
1757system.l2c.overall_misses::cpu1.inst 1510 # number of overall misses
1758system.l2c.overall_misses::cpu1.data 8287 # number of overall misses
1759system.l2c.overall_misses::total 411352 # number of overall misses
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1761system.l2c.ReadReq_miss_latency::cpu0.data 17940986000 # number of ReadReq miss cycles
1762system.l2c.ReadReq_miss_latency::cpu1.inst 121354750 # number of ReadReq miss cycles
1763system.l2c.ReadReq_miss_latency::cpu1.data 74847500 # number of ReadReq miss cycles
1764system.l2c.ReadReq_miss_latency::total 19201570000 # number of ReadReq miss cycles
1765system.l2c.UpgradeReq_miss_latency::cpu0.data 1318455 # number of UpgradeReq miss cycles
1766system.l2c.UpgradeReq_miss_latency::cpu1.data 8321116 # number of UpgradeReq miss cycles
1767system.l2c.UpgradeReq_miss_latency::total 9639571 # number of UpgradeReq miss cycles
1768system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1217948 # number of SCUpgradeReq miss cycles
1769system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209991 # number of SCUpgradeReq miss cycles
1770system.l2c.SCUpgradeReq_miss_latency::total 1427939 # number of SCUpgradeReq miss cycles
1771system.l2c.ReadExReq_miss_latency::cpu0.data 9484677078 # number of ReadExReq miss cycles
1772system.l2c.ReadExReq_miss_latency::cpu1.data 797025966 # number of ReadExReq miss cycles
1773system.l2c.ReadExReq_miss_latency::total 10281703044 # number of ReadExReq miss cycles
1774system.l2c.demand_miss_latency::cpu0.inst 1064381750 # number of demand (read+write) miss cycles
1775system.l2c.demand_miss_latency::cpu0.data 27425663078 # number of demand (read+write) miss cycles
1776system.l2c.demand_miss_latency::cpu1.inst 121354750 # number of demand (read+write) miss cycles
1777system.l2c.demand_miss_latency::cpu1.data 871873466 # number of demand (read+write) miss cycles
1778system.l2c.demand_miss_latency::total 29483273044 # number of demand (read+write) miss cycles
1779system.l2c.overall_miss_latency::cpu0.inst 1064381750 # number of overall miss cycles
1780system.l2c.overall_miss_latency::cpu0.data 27425663078 # number of overall miss cycles
1781system.l2c.overall_miss_latency::cpu1.inst 121354750 # number of overall miss cycles
1782system.l2c.overall_miss_latency::cpu1.data 871873466 # number of overall miss cycles
1783system.l2c.overall_miss_latency::total 29483273044 # number of overall miss cycles
1784system.l2c.ReadReq_accesses::cpu0.inst 822176 # number of ReadReq accesses(hits+misses)
1785system.l2c.ReadReq_accesses::cpu0.data 970595 # number of ReadReq accesses(hits+misses)
1786system.l2c.ReadReq_accesses::cpu1.inst 306686 # number of ReadReq accesses(hits+misses)
1787system.l2c.ReadReq_accesses::cpu1.data 94059 # number of ReadReq accesses(hits+misses)
1788system.l2c.ReadReq_accesses::total 2193516 # number of ReadReq accesses(hits+misses)
1789system.l2c.Writeback_accesses::writebacks 804982 # number of Writeback accesses(hits+misses)
1790system.l2c.Writeback_accesses::total 804982 # number of Writeback accesses(hits+misses)
1791system.l2c.UpgradeReq_accesses::cpu0.data 3035 # number of UpgradeReq accesses(hits+misses)
1792system.l2c.UpgradeReq_accesses::cpu1.data 1950 # number of UpgradeReq accesses(hits+misses)
1793system.l2c.UpgradeReq_accesses::total 4985 # number of UpgradeReq accesses(hits+misses)
1794system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses)
1795system.l2c.SCUpgradeReq_accesses::cpu1.data 763 # number of SCUpgradeReq accesses(hits+misses)
1796system.l2c.SCUpgradeReq_accesses::total 1544 # number of SCUpgradeReq accesses(hits+misses)
1797system.l2c.ReadExReq_accesses::cpu0.data 252307 # number of ReadExReq accesses(hits+misses)
1798system.l2c.ReadExReq_accesses::cpu1.data 42020 # number of ReadExReq accesses(hits+misses)
1799system.l2c.ReadExReq_accesses::total 294327 # number of ReadExReq accesses(hits+misses)
1800system.l2c.demand_accesses::cpu0.inst 822176 # number of demand (read+write) accesses
1801system.l2c.demand_accesses::cpu0.data 1222902 # number of demand (read+write) accesses
1802system.l2c.demand_accesses::cpu1.inst 306686 # number of demand (read+write) accesses
1803system.l2c.demand_accesses::cpu1.data 136079 # number of demand (read+write) accesses
1804system.l2c.demand_accesses::total 2487843 # number of demand (read+write) accesses
1805system.l2c.overall_accesses::cpu0.inst 822176 # number of overall (read+write) accesses
1806system.l2c.overall_accesses::cpu0.data 1222902 # number of overall (read+write) accesses
1807system.l2c.overall_accesses::cpu1.inst 306686 # number of overall (read+write) accesses
1808system.l2c.overall_accesses::cpu1.data 136079 # number of overall (read+write) accesses
1809system.l2c.overall_accesses::total 2487843 # number of overall (read+write) accesses
1810system.l2c.ReadReq_miss_rate::cpu0.inst 0.016867 # miss rate for ReadReq accesses
1811system.l2c.ReadReq_miss_rate::cpu0.data 0.281491 # miss rate for ReadReq accesses
1812system.l2c.ReadReq_miss_rate::cpu1.inst 0.004924 # miss rate for ReadReq accesses
1813system.l2c.ReadReq_miss_rate::cpu1.data 0.008877 # miss rate for ReadReq accesses
1814system.l2c.ReadReq_miss_rate::total 0.131947 # miss rate for ReadReq accesses
1815system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943328 # miss rate for UpgradeReq accesses
1816system.l2c.UpgradeReq_miss_rate::cpu1.data 0.779487 # miss rate for UpgradeReq accesses
1817system.l2c.UpgradeReq_miss_rate::total 0.879238 # miss rate for UpgradeReq accesses
1818system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934699 # miss rate for SCUpgradeReq accesses
1819system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.972477 # miss rate for SCUpgradeReq accesses
1820system.l2c.SCUpgradeReq_miss_rate::total 0.953368 # miss rate for SCUpgradeReq accesses
1821system.l2c.ReadExReq_miss_rate::cpu0.data 0.453705 # miss rate for ReadExReq accesses
1822system.l2c.ReadExReq_miss_rate::cpu1.data 0.177344 # miss rate for ReadExReq accesses
1823system.l2c.ReadExReq_miss_rate::total 0.414250 # miss rate for ReadExReq accesses
1824system.l2c.demand_miss_rate::cpu0.inst 0.016867 # miss rate for demand accesses
1825system.l2c.demand_miss_rate::cpu0.data 0.317022 # miss rate for demand accesses
1826system.l2c.demand_miss_rate::cpu1.inst 0.004924 # miss rate for demand accesses
1827system.l2c.demand_miss_rate::cpu1.data 0.060898 # miss rate for demand accesses
1828system.l2c.demand_miss_rate::total 0.165345 # miss rate for demand accesses
1829system.l2c.overall_miss_rate::cpu0.inst 0.016867 # miss rate for overall accesses
1830system.l2c.overall_miss_rate::cpu0.data 0.317022 # miss rate for overall accesses
1831system.l2c.overall_miss_rate::cpu1.inst 0.004924 # miss rate for overall accesses
1832system.l2c.overall_miss_rate::cpu1.data 0.060898 # miss rate for overall accesses
1833system.l2c.overall_miss_rate::total 0.165345 # miss rate for overall accesses
1834system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76750.919383 # average ReadReq miss latency
1835system.l2c.ReadReq_avg_miss_latency::cpu0.data 65666.422658 # average ReadReq miss latency
1836system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80367.384106 # average ReadReq miss latency
1837system.l2c.ReadReq_avg_miss_latency::cpu1.data 89637.724551 # average ReadReq miss latency
1838system.l2c.ReadReq_avg_miss_latency::total 66343.395744 # average ReadReq miss latency
1839system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 460.515194 # average UpgradeReq miss latency
1840system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5474.418421 # average UpgradeReq miss latency
1841system.l2c.UpgradeReq_avg_miss_latency::total 2199.308921 # average UpgradeReq miss latency
1842system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1668.421918 # average SCUpgradeReq miss latency
1843system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 283.006739 # average SCUpgradeReq miss latency
1844system.l2c.SCUpgradeReq_avg_miss_latency::total 970.067255 # average SCUpgradeReq miss latency
1845system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82855.145563 # average ReadExReq miss latency
1846system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106954.638486 # average ReadExReq miss latency
1847system.l2c.ReadExReq_avg_miss_latency::total 84328.095501 # average ReadExReq miss latency
1848system.l2c.demand_avg_miss_latency::cpu0.inst 76750.919383 # average overall miss latency
1849system.l2c.demand_avg_miss_latency::cpu0.data 70741.766110 # average overall miss latency
1850system.l2c.demand_avg_miss_latency::cpu1.inst 80367.384106 # average overall miss latency
1851system.l2c.demand_avg_miss_latency::cpu1.data 105209.782310 # average overall miss latency
1852system.l2c.demand_avg_miss_latency::total 71674.072434 # average overall miss latency
1853system.l2c.overall_avg_miss_latency::cpu0.inst 76750.919383 # average overall miss latency
1854system.l2c.overall_avg_miss_latency::cpu0.data 70741.766110 # average overall miss latency
1855system.l2c.overall_avg_miss_latency::cpu1.inst 80367.384106 # average overall miss latency
1856system.l2c.overall_avg_miss_latency::cpu1.data 105209.782310 # average overall miss latency
1857system.l2c.overall_avg_miss_latency::total 71674.072434 # average overall miss latency
1858system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1859system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1860system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1861system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1862system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1863system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1864system.l2c.fast_writes 0 # number of fast writes performed
1865system.l2c.cache_copies 0 # number of cache copies performed
1866system.l2c.writebacks::writebacks 81496 # number of writebacks
1867system.l2c.writebacks::total 81496 # number of writebacks
1868system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits
1869system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits
1870system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
1871system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
1872system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits
1873system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
1874system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
1875system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
1876system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits
1877system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
1878system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
1879system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
1880system.l2c.ReadReq_mshr_misses::cpu0.inst 13855 # number of ReadReq MSHR misses
1881system.l2c.ReadReq_mshr_misses::cpu0.data 273213 # number of ReadReq MSHR misses
1882system.l2c.ReadReq_mshr_misses::cpu1.inst 1506 # number of ReadReq MSHR misses
1883system.l2c.ReadReq_mshr_misses::cpu1.data 835 # number of ReadReq MSHR misses
1884system.l2c.ReadReq_mshr_misses::total 289409 # number of ReadReq MSHR misses
1885system.l2c.UpgradeReq_mshr_misses::cpu0.data 2863 # number of UpgradeReq MSHR misses
1886system.l2c.UpgradeReq_mshr_misses::cpu1.data 1520 # number of UpgradeReq MSHR misses
1887system.l2c.UpgradeReq_mshr_misses::total 4383 # number of UpgradeReq MSHR misses
1888system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 730 # number of SCUpgradeReq MSHR misses
1889system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 742 # number of SCUpgradeReq MSHR misses
1890system.l2c.SCUpgradeReq_mshr_misses::total 1472 # number of SCUpgradeReq MSHR misses
1891system.l2c.ReadExReq_mshr_misses::cpu0.data 114473 # number of ReadExReq MSHR misses
1892system.l2c.ReadExReq_mshr_misses::cpu1.data 7452 # number of ReadExReq MSHR misses
1893system.l2c.ReadExReq_mshr_misses::total 121925 # number of ReadExReq MSHR misses
1894system.l2c.demand_mshr_misses::cpu0.inst 13855 # number of demand (read+write) MSHR misses
1895system.l2c.demand_mshr_misses::cpu0.data 387686 # number of demand (read+write) MSHR misses
1896system.l2c.demand_mshr_misses::cpu1.inst 1506 # number of demand (read+write) MSHR misses
1897system.l2c.demand_mshr_misses::cpu1.data 8287 # number of demand (read+write) MSHR misses
1898system.l2c.demand_mshr_misses::total 411334 # number of demand (read+write) MSHR misses
1899system.l2c.overall_mshr_misses::cpu0.inst 13855 # number of overall MSHR misses
1900system.l2c.overall_mshr_misses::cpu0.data 387686 # number of overall MSHR misses
1901system.l2c.overall_mshr_misses::cpu1.inst 1506 # number of overall MSHR misses
1902system.l2c.overall_mshr_misses::cpu1.data 8287 # number of overall MSHR misses
1903system.l2c.overall_mshr_misses::total 411334 # number of overall MSHR misses
1904system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888852750 # number of ReadReq MSHR miss cycles
1905system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14535939000 # number of ReadReq MSHR miss cycles
1906system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 102112500 # number of ReadReq MSHR miss cycles
1907system.l2c.ReadReq_mshr_miss_latency::cpu1.data 64568500 # number of ReadReq MSHR miss cycles
1908system.l2c.ReadReq_mshr_miss_latency::total 15591472750 # number of ReadReq MSHR miss cycles
1909system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28831355 # number of UpgradeReq MSHR miss cycles
1910system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15242993 # number of UpgradeReq MSHR miss cycles
1911system.l2c.UpgradeReq_mshr_miss_latency::total 44074348 # number of UpgradeReq MSHR miss cycles
1912system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7325227 # number of SCUpgradeReq MSHR miss cycles
1913system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7431733 # number of SCUpgradeReq MSHR miss cycles
1914system.l2c.SCUpgradeReq_mshr_miss_latency::total 14756960 # number of SCUpgradeReq MSHR miss cycles
1915system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8087686422 # number of ReadExReq MSHR miss cycles
1916system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 705343034 # number of ReadExReq MSHR miss cycles
1917system.l2c.ReadExReq_mshr_miss_latency::total 8793029456 # number of ReadExReq MSHR miss cycles
1918system.l2c.demand_mshr_miss_latency::cpu0.inst 888852750 # number of demand (read+write) MSHR miss cycles
1919system.l2c.demand_mshr_miss_latency::cpu0.data 22623625422 # number of demand (read+write) MSHR miss cycles
1920system.l2c.demand_mshr_miss_latency::cpu1.inst 102112500 # number of demand (read+write) MSHR miss cycles
1921system.l2c.demand_mshr_miss_latency::cpu1.data 769911534 # number of demand (read+write) MSHR miss cycles
1922system.l2c.demand_mshr_miss_latency::total 24384502206 # number of demand (read+write) MSHR miss cycles
1923system.l2c.overall_mshr_miss_latency::cpu0.inst 888852750 # number of overall MSHR miss cycles
1924system.l2c.overall_mshr_miss_latency::cpu0.data 22623625422 # number of overall MSHR miss cycles
1925system.l2c.overall_mshr_miss_latency::cpu1.inst 102112500 # number of overall MSHR miss cycles
1926system.l2c.overall_mshr_miss_latency::cpu1.data 769911534 # number of overall MSHR miss cycles
1927system.l2c.overall_mshr_miss_latency::total 24384502206 # number of overall MSHR miss cycles
1928system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366200000 # number of ReadReq MSHR uncacheable cycles
1929system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23157500 # number of ReadReq MSHR uncacheable cycles
1930system.l2c.ReadReq_mshr_uncacheable_latency::total 1389357500 # number of ReadReq MSHR uncacheable cycles
1931system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2085104000 # number of WriteReq MSHR uncacheable cycles
1932system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 652738500 # number of WriteReq MSHR uncacheable cycles
1933system.l2c.WriteReq_mshr_uncacheable_latency::total 2737842500 # number of WriteReq MSHR uncacheable cycles
1934system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3451304000 # number of overall MSHR uncacheable cycles
1935system.l2c.overall_mshr_uncacheable_latency::cpu1.data 675896000 # number of overall MSHR uncacheable cycles
1936system.l2c.overall_mshr_uncacheable_latency::total 4127200000 # number of overall MSHR uncacheable cycles
1937system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for ReadReq accesses
1938system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281490 # mshr miss rate for ReadReq accesses
1939system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for ReadReq accesses
1940system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008877 # mshr miss rate for ReadReq accesses
1941system.l2c.ReadReq_mshr_miss_rate::total 0.131938 # mshr miss rate for ReadReq accesses
1942system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943328 # mshr miss rate for UpgradeReq accesses
1943system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.779487 # mshr miss rate for UpgradeReq accesses
1944system.l2c.UpgradeReq_mshr_miss_rate::total 0.879238 # mshr miss rate for UpgradeReq accesses
1945system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934699 # mshr miss rate for SCUpgradeReq accesses
1946system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.972477 # mshr miss rate for SCUpgradeReq accesses
1947system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.953368 # mshr miss rate for SCUpgradeReq accesses
1948system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453705 # mshr miss rate for ReadExReq accesses
1949system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.177344 # mshr miss rate for ReadExReq accesses
1950system.l2c.ReadExReq_mshr_miss_rate::total 0.414250 # mshr miss rate for ReadExReq accesses
1951system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for demand accesses
1952system.l2c.demand_mshr_miss_rate::cpu0.data 0.317021 # mshr miss rate for demand accesses
1953system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for demand accesses
1954system.l2c.demand_mshr_miss_rate::cpu1.data 0.060898 # mshr miss rate for demand accesses
1955system.l2c.demand_mshr_miss_rate::total 0.165338 # mshr miss rate for demand accesses
1956system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for overall accesses
1957system.l2c.overall_mshr_miss_rate::cpu0.data 0.317021 # mshr miss rate for overall accesses
1958system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for overall accesses
1959system.l2c.overall_mshr_miss_rate::cpu1.data 0.060898 # mshr miss rate for overall accesses
1960system.l2c.overall_mshr_miss_rate::total 0.165338 # mshr miss rate for overall accesses
1961system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average ReadReq mshr miss latency
1962system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53203.687233 # average ReadReq mshr miss latency
1963system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average ReadReq mshr miss latency
1964system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77327.544910 # average ReadReq mshr miss latency
1965system.l2c.ReadReq_avg_mshr_miss_latency::total 53873.489594 # average ReadReq mshr miss latency
1966system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10070.330073 # average UpgradeReq mshr miss latency
1967system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.284868 # average UpgradeReq mshr miss latency
1968system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.749030 # average UpgradeReq mshr miss latency
1969system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.557534 # average SCUpgradeReq mshr miss latency
1970system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.812668 # average SCUpgradeReq mshr miss latency
1971system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.108696 # average SCUpgradeReq mshr miss latency
1972system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70651.476086 # average ReadExReq mshr miss latency
1973system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94651.507515 # average ReadExReq mshr miss latency
1974system.l2c.ReadExReq_avg_mshr_miss_latency::total 72118.346984 # average ReadExReq mshr miss latency
1975system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average overall mshr miss latency
1976system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58355.538817 # average overall mshr miss latency
1977system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average overall mshr miss latency
1978system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92905.941113 # average overall mshr miss latency
1979system.l2c.demand_avg_mshr_miss_latency::total 59281.513821 # average overall mshr miss latency
1980system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average overall mshr miss latency
1981system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58355.538817 # average overall mshr miss latency
1982system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average overall mshr miss latency
1983system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92905.941113 # average overall mshr miss latency
1984system.l2c.overall_avg_mshr_miss_latency::total 59281.513821 # average overall mshr miss latency
1985system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1986system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1987system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1988system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1989system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1990system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1991system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1992system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1993system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1994system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1995system.membus.trans_dist::ReadReq 296777 # Transaction distribution
1996system.membus.trans_dist::ReadResp 296698 # Transaction distribution
1997system.membus.trans_dist::WriteReq 13646 # Transaction distribution
1998system.membus.trans_dist::WriteResp 13646 # Transaction distribution
1999system.membus.trans_dist::Writeback 123016 # Transaction distribution
2000system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
2001system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
2002system.membus.trans_dist::UpgradeReq 14268 # Transaction distribution
2003system.membus.trans_dist::SCUpgradeReq 9480 # Transaction distribution
2004system.membus.trans_dist::UpgradeResp 6314 # Transaction distribution
2005system.membus.trans_dist::ReadExReq 122151 # Transaction distribution
2006system.membus.trans_dist::ReadExResp 121466 # Transaction distribution
2007system.membus.trans_dist::BadAddressError 79 # Transaction distribution
2008system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41682 # Packet count per connected master and slave (bytes)
2009system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 933549 # Packet count per connected master and slave (bytes)
2010system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes)
2011system.membus.pkt_count_system.l2c.mem_side::total 975389 # Packet count per connected master and slave (bytes)
2012system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124812 # Packet count per connected master and slave (bytes)
2013system.membus.pkt_count_system.iocache.mem_side::total 124812 # Packet count per connected master and slave (bytes)
2014system.membus.pkt_count::total 1100201 # Packet count per connected master and slave (bytes)
2015system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78554 # Cumulative packet size per connected master and slave (bytes)
2016system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31488576 # Cumulative packet size per connected master and slave (bytes)
2017system.membus.pkt_size_system.l2c.mem_side::total 31567130 # Cumulative packet size per connected master and slave (bytes)
2018system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
2019system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
2020system.membus.pkt_size::total 36884698 # Cumulative packet size per connected master and slave (bytes)
2021system.membus.snoops 18563 # Total snoops (count)
2022system.membus.snoop_fanout::samples 600049 # Request fanout histogram
2023system.membus.snoop_fanout::mean 1 # Request fanout histogram
2024system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2025system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2026system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2027system.membus.snoop_fanout::1 600049 100.00% 100.00% # Request fanout histogram
2028system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2029system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2030system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2031system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2032system.membus.snoop_fanout::total 600049 # Request fanout histogram
2033system.membus.reqLayer0.occupancy 40411498 # Layer occupancy (ticks)
2034system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2035system.membus.reqLayer1.occupancy 1927899500 # Layer occupancy (ticks)
2036system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
2037system.membus.reqLayer2.occupancy 99500 # Layer occupancy (ticks)
2038system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2039system.membus.respLayer1.occupancy 3832783452 # Layer occupancy (ticks)
2040system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
2041system.membus.respLayer2.occupancy 43159450 # Layer occupancy (ticks)
2042system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2043system.toL2Bus.trans_dist::ReadReq 2231232 # Transaction distribution
2044system.toL2Bus.trans_dist::ReadResp 2231137 # Transaction distribution
2045system.toL2Bus.trans_dist::WriteReq 13646 # Transaction distribution
2046system.toL2Bus.trans_dist::WriteResp 13646 # Transaction distribution
2047system.toL2Bus.trans_dist::Writeback 804982 # Transaction distribution
2048system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
2049system.toL2Bus.trans_dist::UpgradeReq 14411 # Transaction distribution
2050system.toL2Bus.trans_dist::SCUpgradeReq 9552 # Transaction distribution
2051system.toL2Bus.trans_dist::UpgradeResp 23963 # Transaction distribution
2052system.toL2Bus.trans_dist::ReadExReq 296031 # Transaction distribution
2053system.toL2Bus.trans_dist::ReadExResp 296031 # Transaction distribution
2054system.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution
2055system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1644513 # Packet count per connected master and slave (bytes)
2056system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3224840 # Packet count per connected master and slave (bytes)
2057system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 613391 # Packet count per connected master and slave (bytes)
2058system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 402307 # Packet count per connected master and slave (bytes)
2059system.toL2Bus.pkt_count::total 5885051 # Packet count per connected master and slave (bytes)
2060system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52619264 # Cumulative packet size per connected master and slave (bytes)
2061system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123882452 # Cumulative packet size per connected master and slave (bytes)
2062system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19627904 # Cumulative packet size per connected master and slave (bytes)
2063system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14694726 # Cumulative packet size per connected master and slave (bytes)
2064system.toL2Bus.pkt_size::total 210824346 # Cumulative packet size per connected master and slave (bytes)
2065system.toL2Bus.snoops 91368 # Total snoops (count)
2066system.toL2Bus.snoop_fanout::samples 3390565 # Request fanout histogram
2067system.toL2Bus.snoop_fanout::mean 3.012306 # Request fanout histogram
2068system.toL2Bus.snoop_fanout::stdev 0.110249 # Request fanout histogram
2069system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2070system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2071system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2072system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2073system.toL2Bus.snoop_fanout::3 3348840 98.77% 98.77% # Request fanout histogram
2074system.toL2Bus.snoop_fanout::4 41725 1.23% 100.00% # Request fanout histogram
2075system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2076system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2077system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2078system.toL2Bus.snoop_fanout::total 3390565 # Request fanout histogram
2079system.toL2Bus.reqLayer0.occupancy 4912159072 # Layer occupancy (ticks)
2080system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
2081system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks)
2082system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2083system.toL2Bus.respLayer0.occupancy 3705712969 # Layer occupancy (ticks)
2084system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
2085system.toL2Bus.respLayer1.occupancy 5664612723 # Layer occupancy (ticks)
2086system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
2087system.toL2Bus.respLayer2.occupancy 1381251781 # Layer occupancy (ticks)
2088system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
2089system.toL2Bus.respLayer3.occupancy 692182943 # Layer occupancy (ticks)
2090system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2091system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2092system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2093system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2094system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2095system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2096system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2097system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 17 unchanged lines hidden (view full) ---

2115system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2116system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2117system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2118system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2119system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2120system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
2121system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
2122system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2123system.cpu0.kern.inst.quiesce 6735 # number of quiesce instructions executed
2124system.cpu0.kern.inst.hwrei 170888 # number of hwrei instructions executed
2125system.cpu0.kern.ipl_count::0 59399 40.36% 40.36% # number of times we switched to this ipl
2126system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl
2127system.cpu0.kern.ipl_count::22 1921 1.31% 41.76% # number of times we switched to this ipl
2128system.cpu0.kern.ipl_count::30 339 0.23% 41.99% # number of times we switched to this ipl
2129system.cpu0.kern.ipl_count::31 85372 58.01% 100.00% # number of times we switched to this ipl
2130system.cpu0.kern.ipl_count::total 147162 # number of times we switched to this ipl
2131system.cpu0.kern.ipl_good::0 58699 49.14% 49.14% # number of times we switched to this ipl from a different ipl
2132system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl
2133system.cpu0.kern.ipl_good::22 1921 1.61% 50.86% # number of times we switched to this ipl from a different ipl
2134system.cpu0.kern.ipl_good::30 339 0.28% 51.14% # number of times we switched to this ipl from a different ipl
2135system.cpu0.kern.ipl_good::31 58360 48.86% 100.00% # number of times we switched to this ipl from a different ipl
2136system.cpu0.kern.ipl_good::total 119450 # number of times we switched to this ipl from a different ipl
2137system.cpu0.kern.ipl_ticks::0 1860822176500 97.88% 97.88% # number of cycles we spent at this ipl
2138system.cpu0.kern.ipl_ticks::21 61176000 0.00% 97.88% # number of cycles we spent at this ipl
2139system.cpu0.kern.ipl_ticks::22 541931500 0.03% 97.91% # number of cycles we spent at this ipl
2140system.cpu0.kern.ipl_ticks::30 152116500 0.01% 97.92% # number of cycles we spent at this ipl
2141system.cpu0.kern.ipl_ticks::31 39608995500 2.08% 100.00% # number of cycles we spent at this ipl
2142system.cpu0.kern.ipl_ticks::total 1901186396000 # number of cycles we spent at this ipl
2143system.cpu0.kern.ipl_used::0 0.988215 # fraction of swpipl calls that actually changed the ipl
2144system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
2145system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2146system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2147system.cpu0.kern.ipl_used::31 0.683596 # fraction of swpipl calls that actually changed the ipl
2148system.cpu0.kern.ipl_used::total 0.811691 # fraction of swpipl calls that actually changed the ipl
2149system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed
2150system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed
2151system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed
2152system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed
2153system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed
2154system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed
2155system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed
2156system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed
2157system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed
2158system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed
2159system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed
2160system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed
2161system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed
2162system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed
2163system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed
2164system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed
2165system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed
2166system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed
2167system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed
2168system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed
2169system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed
2170system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed
2171system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed
2172system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed
2173system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed
2174system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed
2175system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed
2176system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed
2177system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed
2178system.cpu0.kern.syscall::total 232 # number of syscalls executed
2179system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2180system.cpu0.kern.callpal::wripir 432 0.28% 0.28% # number of callpals executed
2181system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed
2182system.cpu0.kern.callpal::wrfen 1 0.00% 0.28% # number of callpals executed
2183system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.28% # number of callpals executed
2184system.cpu0.kern.callpal::swpctx 3241 2.09% 2.37% # number of callpals executed
2185system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed
2186system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed
2187system.cpu0.kern.callpal::swpipl 140334 90.29% 92.69% # number of callpals executed
2188system.cpu0.kern.callpal::rdps 6381 4.11% 96.80% # number of callpals executed
2189system.cpu0.kern.callpal::wrkgp 1 0.00% 96.80% # number of callpals executed
2190system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed
2191system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed
2192system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed
2193system.cpu0.kern.callpal::rti 4436 2.85% 99.66% # number of callpals executed
2194system.cpu0.kern.callpal::callsys 391 0.25% 99.91% # number of callpals executed
2195system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
2196system.cpu0.kern.callpal::total 155429 # number of callpals executed
2197system.cpu0.kern.mode_switch::kernel 7000 # number of protection mode switches
2198system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches
2199system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
2200system.cpu0.kern.mode_good::kernel 1354
2201system.cpu0.kern.mode_good::user 1355
2202system.cpu0.kern.mode_good::idle 0
2203system.cpu0.kern.mode_switch_good::kernel 0.193429 # fraction of useful protection mode switches
2204system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2205system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
2206system.cpu0.kern.mode_switch_good::total 0.324237 # fraction of useful protection mode switches
2207system.cpu0.kern.mode_ticks::kernel 1899184407000 99.89% 99.89% # number of ticks spent at the given mode
2208system.cpu0.kern.mode_ticks::user 2001981000 0.11% 100.00% # number of ticks spent at the given mode
2209system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
2210system.cpu0.kern.swap_context 3242 # number of times the context was actually changed
2211system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2212system.cpu1.kern.inst.quiesce 2589 # number of quiesce instructions executed
2213system.cpu1.kern.inst.hwrei 70429 # number of hwrei instructions executed
2214system.cpu1.kern.ipl_count::0 23508 38.03% 38.03% # number of times we switched to this ipl
2215system.cpu1.kern.ipl_count::22 1920 3.11% 41.14% # number of times we switched to this ipl
2216system.cpu1.kern.ipl_count::30 432 0.70% 41.84% # number of times we switched to this ipl
2217system.cpu1.kern.ipl_count::31 35949 58.16% 100.00% # number of times we switched to this ipl
2218system.cpu1.kern.ipl_count::total 61809 # number of times we switched to this ipl
2219system.cpu1.kern.ipl_good::0 22831 47.98% 47.98% # number of times we switched to this ipl from a different ipl
2220system.cpu1.kern.ipl_good::22 1920 4.04% 52.02% # number of times we switched to this ipl from a different ipl
2221system.cpu1.kern.ipl_good::30 432 0.91% 52.93% # number of times we switched to this ipl from a different ipl
2222system.cpu1.kern.ipl_good::31 22399 47.07% 100.00% # number of times we switched to this ipl from a different ipl
2223system.cpu1.kern.ipl_good::total 47582 # number of times we switched to this ipl from a different ipl
2224system.cpu1.kern.ipl_ticks::0 1869145937500 98.33% 98.33% # number of cycles we spent at this ipl
2225system.cpu1.kern.ipl_ticks::22 530408500 0.03% 98.36% # number of cycles we spent at this ipl
2226system.cpu1.kern.ipl_ticks::30 194479500 0.01% 98.37% # number of cycles we spent at this ipl
2227system.cpu1.kern.ipl_ticks::31 30989632500 1.63% 100.00% # number of cycles we spent at this ipl
2228system.cpu1.kern.ipl_ticks::total 1900860458000 # number of cycles we spent at this ipl
2229system.cpu1.kern.ipl_used::0 0.971201 # fraction of swpipl calls that actually changed the ipl
2230system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
2231system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
2232system.cpu1.kern.ipl_used::31 0.623077 # fraction of swpipl calls that actually changed the ipl
2233system.cpu1.kern.ipl_used::total 0.769823 # fraction of swpipl calls that actually changed the ipl
2234system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed
2235system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed
2236system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed
2237system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed
2238system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed
2239system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed
2240system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed
2241system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed
2242system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed
2243system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed
2244system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed
2245system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed
2246system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed
2247system.cpu1.kern.syscall::total 94 # number of syscalls executed
2248system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
2249system.cpu1.kern.callpal::wripir 339 0.53% 0.53% # number of callpals executed
2250system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed
2251system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed
2252system.cpu1.kern.callpal::swpctx 1656 2.59% 3.12% # number of callpals executed
2253system.cpu1.kern.callpal::tbi 3 0.00% 3.13% # number of callpals executed
2254system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed
2255system.cpu1.kern.callpal::swpipl 56045 87.56% 90.70% # number of callpals executed
2256system.cpu1.kern.callpal::rdps 2366 3.70% 94.40% # number of callpals executed
2257system.cpu1.kern.callpal::wrkgp 1 0.00% 94.40% # number of callpals executed
2258system.cpu1.kern.callpal::wrusp 4 0.01% 94.41% # number of callpals executed
2259system.cpu1.kern.callpal::whami 3 0.00% 94.41% # number of callpals executed
2260system.cpu1.kern.callpal::rti 3411 5.33% 99.74% # number of callpals executed
2261system.cpu1.kern.callpal::callsys 124 0.19% 99.93% # number of callpals executed
2262system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed
2263system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
2264system.cpu1.kern.callpal::total 64005 # number of callpals executed
2265system.cpu1.kern.mode_switch::kernel 1702 # number of protection mode switches
2266system.cpu1.kern.mode_switch::user 384 # number of protection mode switches
2267system.cpu1.kern.mode_switch::idle 2700 # number of protection mode switches
2268system.cpu1.kern.mode_good::kernel 740
2269system.cpu1.kern.mode_good::user 384
2270system.cpu1.kern.mode_good::idle 356
2271system.cpu1.kern.mode_switch_good::kernel 0.434783 # fraction of useful protection mode switches
2272system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
2273system.cpu1.kern.mode_switch_good::idle 0.131852 # fraction of useful protection mode switches
2274system.cpu1.kern.mode_switch_good::total 0.309235 # fraction of useful protection mode switches
2275system.cpu1.kern.mode_ticks::kernel 6130779500 0.32% 0.32% # number of ticks spent at the given mode
2276system.cpu1.kern.mode_ticks::user 692688500 0.04% 0.36% # number of ticks spent at the given mode
2277system.cpu1.kern.mode_ticks::idle 1893719133000 99.64% 100.00% # number of ticks spent at the given mode
2278system.cpu1.kern.swap_context 1657 # number of times the context was actually changed
2279
2280---------- End Simulation Statistics ----------