config.ini (9055:38f1926fb599) config.ini (9096:8971a998190a)
1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8

--- 927 unchanged lines hidden (view full) ---

936sys=system
937
938[system.iobus]
939type=NoncoherentBus
940block_size=64
941clock=1000
942header_cycles=1
943use_default_range=true
1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8

--- 927 unchanged lines hidden (view full) ---

936sys=system
937
938[system.iobus]
939type=NoncoherentBus
940block_size=64
941clock=1000
942header_cycles=1
943use_default_range=true
944width=64
944width=8
945default=system.tsunami.pciconfig.pio
946master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
947slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
948
949[system.iocache]
950type=BaseCache
951addr_ranges=0:8589934591
952assoc=8

--- 45 unchanged lines hidden (view full) ---

998
999[system.membus]
1000type=CoherentBus
1001children=badaddr_responder
1002block_size=64
1003clock=1000
1004header_cycles=1
1005use_default_range=false
945default=system.tsunami.pciconfig.pio
946master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
947slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
948
949[system.iocache]
950type=BaseCache
951addr_ranges=0:8589934591
952assoc=8

--- 45 unchanged lines hidden (view full) ---

998
999[system.membus]
1000type=CoherentBus
1001children=badaddr_responder
1002block_size=64
1003clock=1000
1004header_cycles=1
1005use_default_range=false
1006width=64
1006width=8
1007default=system.membus.badaddr_responder.pio
1008master=system.bridge.slave system.physmem.port[0]
1009slave=system.system_port system.iocache.mem_side system.l2c.mem_side
1010
1011[system.membus.badaddr_responder]
1012type=IsaFake
1013fake_mem=false
1014pio_addr=0

--- 40 unchanged lines hidden (view full) ---

1055port=3456
1056
1057[system.toL2Bus]
1058type=CoherentBus
1059block_size=64
1060clock=1000
1061header_cycles=1
1062use_default_range=false
1007default=system.membus.badaddr_responder.pio
1008master=system.bridge.slave system.physmem.port[0]
1009slave=system.system_port system.iocache.mem_side system.l2c.mem_side
1010
1011[system.membus.badaddr_responder]
1012type=IsaFake
1013fake_mem=false
1014pio_addr=0

--- 40 unchanged lines hidden (view full) ---

1055port=3456
1056
1057[system.toL2Bus]
1058type=CoherentBus
1059block_size=64
1060clock=1000
1061header_cycles=1
1062use_default_range=false
1063width=64
1063width=8
1064master=system.l2c.cpu_side
1065slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
1066
1067[system.tsunami]
1068type=Tsunami
1069children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1070intrctrl=system.intrctrl
1071system=system

--- 496 unchanged lines hidden --- 		1064master=system.l2c.cpu_side
1065slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
1066
1067[system.tsunami]
1068type=Tsunami
1069children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1070intrctrl=system.intrctrl
1071system=system

--- 496 unchanged lines hidden ---