| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 922 unchanged lines hidden (view full) --- 931image_file=/dist/m5/system/disks/linux-bigswap2.img 932read_only=true 933 934[system.intrctrl] 935type=IntrControl 936sys=system 937 938[system.iobus] | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 922 unchanged lines hidden (view full) --- 931image_file=/dist/m5/system/disks/linux-bigswap2.img 932read_only=true 933 934[system.intrctrl] 935type=IntrControl 936sys=system 937 938[system.iobus] |
| 939type=Bus | 939type=NoncoherentBus |
| 940block_size=64 | 940block_size=64 |
| 941bus_id=0 | |
| 942clock=1000 943header_cycles=1 944use_default_range=true 945width=64 946default=system.tsunami.pciconfig.pio 947master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 948slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 949 --- 43 unchanged lines hidden (view full) --- 993tgts_per_mshr=16 994trace_addr=0 995two_queue=false 996write_buffers=8 997cpu_side=system.toL2Bus.master[0] 998mem_side=system.membus.slave[2] 999 1000[system.membus] | 941clock=1000 942header_cycles=1 943use_default_range=true 944width=64 945default=system.tsunami.pciconfig.pio 946master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 947slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 948 --- 43 unchanged lines hidden (view full) --- 992tgts_per_mshr=16 993trace_addr=0 994two_queue=false 995write_buffers=8 996cpu_side=system.toL2Bus.master[0] 997mem_side=system.membus.slave[2] 998 999[system.membus] |
| 1001type=Bus | 1000type=CoherentBus |
| 1002children=badaddr_responder 1003block_size=64 | 1001children=badaddr_responder 1002block_size=64 |
| 1004bus_id=1 | |
| 1005clock=1000 1006header_cycles=1 1007use_default_range=false 1008width=64 1009default=system.membus.badaddr_responder.pio 1010master=system.bridge.slave system.physmem.port[0] 1011slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1012 --- 39 unchanged lines hidden (view full) --- 1052[system.terminal] 1053type=Terminal 1054intr_control=system.intrctrl 1055number=0 1056output=true 1057port=3456 1058 1059[system.toL2Bus] | 1003clock=1000 1004header_cycles=1 1005use_default_range=false 1006width=64 1007default=system.membus.badaddr_responder.pio 1008master=system.bridge.slave system.physmem.port[0] 1009slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1010 --- 39 unchanged lines hidden (view full) --- 1050[system.terminal] 1051type=Terminal 1052intr_control=system.intrctrl 1053number=0 1054output=true 1055port=3456 1056 1057[system.toL2Bus] |
| 1060type=Bus | 1058type=CoherentBus |
| 1061block_size=64 | 1059block_size=64 |
| 1062bus_id=0 | |
| 1063clock=1000 1064header_cycles=1 1065use_default_range=false 1066width=64 1067master=system.l2c.cpu_side 1068slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1069 1070[system.tsunami] --- 500 unchanged lines hidden --- | 1060clock=1000 1061header_cycles=1 1062use_default_range=false 1063width=64 1064master=system.l2c.cpu_side 1065slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1066 1067[system.tsunami] --- 500 unchanged lines hidden --- |