config.ini (11570:4aac82f10951) config.ini (11680:b4d943429dc6)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

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20eventq_index=0
21exit_on_work_items=false
22init_param=0
23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
24kernel_addr_check=true
25load_addr_mask=1099511627775
26load_offset=0
27mem_mode=timing
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 11 unchanged lines hidden (view full) ---

20eventq_index=0
21exit_on_work_items=false
22init_param=0
23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
24kernel_addr_check=true
25load_addr_mask=1099511627775
26load_offset=0
27mem_mode=timing
28mem_ranges=0:134217727
28mem_ranges=0:134217727:0:0:0:0
29memories=system.physmem
30mmap_using_noreserve=false
31multi_thread=false
32num_work_ids=16
33p_state_clk_gate_bins=20
34p_state_clk_gate_max=1000000000000
35p_state_clk_gate_min=1000
36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal

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55clk_domain=system.clk_domain
56default_p_state=UNDEFINED
57delay=50000
58eventq_index=0
59p_state_clk_gate_bins=20
60p_state_clk_gate_max=1000000000000
61p_state_clk_gate_min=1000
62power_model=Null
29memories=system.physmem
30mmap_using_noreserve=false
31multi_thread=false
32num_work_ids=16
33p_state_clk_gate_bins=20
34p_state_clk_gate_max=1000000000000
35p_state_clk_gate_min=1000
36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal

--- 18 unchanged lines hidden (view full) ---

55clk_domain=system.clk_domain
56default_p_state=UNDEFINED
57delay=50000
58eventq_index=0
59p_state_clk_gate_bins=20
60p_state_clk_gate_max=1000000000000
61p_state_clk_gate_min=1000
62power_model=Null
63ranges=8796093022208:18446744073709551615
63ranges=8796093022208:18446744073709551615:0:0:0:0
64req_size=16
65resp_size=16
66master=system.iobus.slave[0]
67slave=system.membus.master[0]
68
69[system.clk_domain]
70type=SrcClockDomain
71clock=1000

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189localHistoryTableSize=2048
190localPredictorSize=2048
191numThreads=1
192useIndirect=true
193
194[system.cpu0.dcache]
195type=Cache
196children=tags
64req_size=16
65resp_size=16
66master=system.iobus.slave[0]
67slave=system.membus.master[0]
68
69[system.clk_domain]
70type=SrcClockDomain
71clock=1000

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189localHistoryTableSize=2048
190localPredictorSize=2048
191numThreads=1
192useIndirect=true
193
194[system.cpu0.dcache]
195type=Cache
196children=tags
197addr_ranges=0:18446744073709551615
197addr_ranges=0:18446744073709551615:0:0:0:0
198assoc=4
199clk_domain=system.cpu_clk_domain
200clusivity=mostly_incl
201default_p_state=UNDEFINED
202demand_mshr_reserve=1
203eventq_index=0
204hit_latency=2
205is_read_only=false

--- 341 unchanged lines hidden (view full) ---

547eventq_index=0
548opClass=IprAccess
549opLat=3
550pipelined=false
551
552[system.cpu0.icache]
553type=Cache
554children=tags
198assoc=4
199clk_domain=system.cpu_clk_domain
200clusivity=mostly_incl
201default_p_state=UNDEFINED
202demand_mshr_reserve=1
203eventq_index=0
204hit_latency=2
205is_read_only=false

--- 341 unchanged lines hidden (view full) ---

547eventq_index=0
548opClass=IprAccess
549opLat=3
550pipelined=false
551
552[system.cpu0.icache]
553type=Cache
554children=tags
555addr_ranges=0:18446744073709551615
555addr_ranges=0:18446744073709551615:0:0:0:0
556assoc=1
557clk_domain=system.cpu_clk_domain
558clusivity=mostly_incl
559default_p_state=UNDEFINED
560demand_mshr_reserve=1
561eventq_index=0
562hit_latency=2
563is_read_only=true

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728localHistoryTableSize=2048
729localPredictorSize=2048
730numThreads=1
731useIndirect=true
732
733[system.cpu1.dcache]
734type=Cache
735children=tags
556assoc=1
557clk_domain=system.cpu_clk_domain
558clusivity=mostly_incl
559default_p_state=UNDEFINED
560demand_mshr_reserve=1
561eventq_index=0
562hit_latency=2
563is_read_only=true

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728localHistoryTableSize=2048
729localPredictorSize=2048
730numThreads=1
731useIndirect=true
732
733[system.cpu1.dcache]
734type=Cache
735children=tags
736addr_ranges=0:18446744073709551615
736addr_ranges=0:18446744073709551615:0:0:0:0
737assoc=4
738clk_domain=system.cpu_clk_domain
739clusivity=mostly_incl
740default_p_state=UNDEFINED
741demand_mshr_reserve=1
742eventq_index=0
743hit_latency=2
744is_read_only=false

--- 341 unchanged lines hidden (view full) ---

1086eventq_index=0
1087opClass=IprAccess
1088opLat=3
1089pipelined=false
1090
1091[system.cpu1.icache]
1092type=Cache
1093children=tags
737assoc=4
738clk_domain=system.cpu_clk_domain
739clusivity=mostly_incl
740default_p_state=UNDEFINED
741demand_mshr_reserve=1
742eventq_index=0
743hit_latency=2
744is_read_only=false

--- 341 unchanged lines hidden (view full) ---

1086eventq_index=0
1087opClass=IprAccess
1088opLat=3
1089pipelined=false
1090
1091[system.cpu1.icache]
1092type=Cache
1093children=tags
1094addr_ranges=0:18446744073709551615
1094addr_ranges=0:18446744073709551615:0:0:0:0
1095assoc=1
1096clk_domain=system.cpu_clk_domain
1097clusivity=mostly_incl
1098default_p_state=UNDEFINED
1099demand_mshr_reserve=1
1100eventq_index=0
1101hit_latency=2
1102is_read_only=true

--- 131 unchanged lines hidden (view full) ---

1234use_default_range=false
1235width=16
1236master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
1237slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
1238
1239[system.iocache]
1240type=Cache
1241children=tags
1095assoc=1
1096clk_domain=system.cpu_clk_domain
1097clusivity=mostly_incl
1098default_p_state=UNDEFINED
1099demand_mshr_reserve=1
1100eventq_index=0
1101hit_latency=2
1102is_read_only=true

--- 131 unchanged lines hidden (view full) ---

1234use_default_range=false
1235width=16
1236master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
1237slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
1238
1239[system.iocache]
1240type=Cache
1241children=tags
1242addr_ranges=0:134217727
1242addr_ranges=0:134217727:0:0:0:0
1243assoc=8
1244clk_domain=system.clk_domain
1245clusivity=mostly_incl
1246default_p_state=UNDEFINED
1247demand_mshr_reserve=1
1248eventq_index=0
1249hit_latency=50
1250is_read_only=false

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1280p_state_clk_gate_min=1000
1281power_model=Null
1282sequential_access=false
1283size=1024
1284
1285[system.l2c]
1286type=Cache
1287children=tags
1243assoc=8
1244clk_domain=system.clk_domain
1245clusivity=mostly_incl
1246default_p_state=UNDEFINED
1247demand_mshr_reserve=1
1248eventq_index=0
1249hit_latency=50
1250is_read_only=false

--- 29 unchanged lines hidden (view full) ---

1280p_state_clk_gate_min=1000
1281power_model=Null
1282sequential_access=false
1283size=1024
1284
1285[system.l2c]
1286type=Cache
1287children=tags
1288addr_ranges=0:18446744073709551615
1288addr_ranges=0:18446744073709551615:0:0:0:0
1289assoc=8
1290clk_domain=system.cpu_clk_domain
1291clusivity=mostly_incl
1292default_p_state=UNDEFINED
1293demand_mshr_reserve=1
1294eventq_index=0
1295hit_latency=20
1296is_read_only=false

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1378type=SnoopFilter
1379eventq_index=0
1380lookup_latency=1
1381max_capacity=8388608
1382system=system
1383
1384[system.physmem]
1385type=DRAMCtrl
1289assoc=8
1290clk_domain=system.cpu_clk_domain
1291clusivity=mostly_incl
1292default_p_state=UNDEFINED
1293demand_mshr_reserve=1
1294eventq_index=0
1295hit_latency=20
1296is_read_only=false

--- 81 unchanged lines hidden (view full) ---

1378type=SnoopFilter
1379eventq_index=0
1380lookup_latency=1
1381max_capacity=8388608
1382system=system
1383
1384[system.physmem]
1385type=DRAMCtrl
1386IDD0=0.075000
1386IDD0=0.055000
1387IDD02=0.000000
1387IDD02=0.000000
1388IDD2N=0.050000
1388IDD2N=0.032000
1389IDD2N2=0.000000
1390IDD2P0=0.000000
1391IDD2P02=0.000000
1389IDD2N2=0.000000
1390IDD2P0=0.000000
1391IDD2P02=0.000000
1392IDD2P1=0.000000
1392IDD2P1=0.032000
1393IDD2P12=0.000000
1393IDD2P12=0.000000
1394IDD3N=0.057000
1394IDD3N=0.038000
1395IDD3N2=0.000000
1396IDD3P0=0.000000
1397IDD3P02=0.000000
1395IDD3N2=0.000000
1396IDD3P0=0.000000
1397IDD3P02=0.000000
1398IDD3P1=0.000000
1398IDD3P1=0.038000
1399IDD3P12=0.000000
1399IDD3P12=0.000000
1400IDD4R=0.187000
1400IDD4R=0.157000
1401IDD4R2=0.000000
1401IDD4R2=0.000000
1402IDD4W=0.165000
1402IDD4W=0.125000
1403IDD4W2=0.000000
1403IDD4W2=0.000000
1404IDD5=0.220000
1404IDD5=0.235000
1405IDD52=0.000000
1405IDD52=0.000000
1406IDD6=0.000000
1406IDD6=0.020000
1407IDD62=0.000000
1408VDD=1.500000
1409VDD2=0.000000
1410activation_limit=4
1411addr_mapping=RoRaBaCoCh
1412bank_groups_per_rank=0
1413banks_per_rank=8
1414burst_length=8
1415channels=1
1416clk_domain=system.clk_domain
1417conf_table_reported=true
1418default_p_state=UNDEFINED
1419device_bus_width=8
1420device_rowbuffer_size=1024
1421device_size=536870912
1422devices_per_rank=8
1423dll=true
1424eventq_index=0
1425in_addr_map=true
1407IDD62=0.000000
1408VDD=1.500000
1409VDD2=0.000000
1410activation_limit=4
1411addr_mapping=RoRaBaCoCh
1412bank_groups_per_rank=0
1413banks_per_rank=8
1414burst_length=8
1415channels=1
1416clk_domain=system.clk_domain
1417conf_table_reported=true
1418default_p_state=UNDEFINED
1419device_bus_width=8
1420device_rowbuffer_size=1024
1421device_size=536870912
1422devices_per_rank=8
1423dll=true
1424eventq_index=0
1425in_addr_map=true
1426kvm_map=true
1426max_accesses_per_row=16
1427mem_sched_policy=frfcfs
1428min_writes_per_switch=16
1429null=false
1430p_state_clk_gate_bins=20
1431p_state_clk_gate_max=1000000000000
1432p_state_clk_gate_min=1000
1433page_policy=open_adaptive
1434power_model=Null
1427max_accesses_per_row=16
1428mem_sched_policy=frfcfs
1429min_writes_per_switch=16
1430null=false
1431p_state_clk_gate_bins=20
1432p_state_clk_gate_max=1000000000000
1433p_state_clk_gate_min=1000
1434page_policy=open_adaptive
1435power_model=Null
1435range=0:134217727
1436range=0:134217727:0:0:0:0
1436ranks_per_channel=2
1437read_buffer_size=32
1438static_backend_latency=10000
1439static_frontend_latency=10000
1440tBURST=5000
1441tCCD_L=0
1442tCK=1250
1443tCL=13750

--- 5 unchanged lines hidden (view full) ---

1449tRP=13750
1450tRRD=6000
1451tRRD_L=0
1452tRTP=7500
1453tRTW=2500
1454tWR=15000
1455tWTR=7500
1456tXAW=30000
1437ranks_per_channel=2
1438read_buffer_size=32
1439static_backend_latency=10000
1440static_frontend_latency=10000
1441tBURST=5000
1442tCCD_L=0
1443tCK=1250
1444tCL=13750

--- 5 unchanged lines hidden (view full) ---

1450tRP=13750
1451tRRD=6000
1452tRRD_L=0
1453tRTP=7500
1454tRTW=2500
1455tWR=15000
1456tWTR=7500
1457tXAW=30000
1457tXP=0
1458tXP=6000
1458tXPDLL=0
1459tXPDLL=0
1459tXS=0
1460tXS=270000
1460tXSDLL=0
1461write_buffer_size=64
1462write_high_thresh_perc=85
1463write_low_thresh_perc=50
1464port=system.membus.master[1]
1465
1466[system.simple_disk]
1467type=SimpleDisk

--- 803 unchanged lines hidden --- 		1461tXSDLL=0
1462write_buffer_size=64
1463write_high_thresh_perc=85
1464write_low_thresh_perc=50
1465port=system.membus.master[1]
1466
1467[system.simple_disk]
1468type=SimpleDisk

--- 803 unchanged lines hidden ---