| config.ini (10315:9e02c14446bb) | config.ini (10451:3a87241adfb8) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 76 unchanged lines hidden (view full) --- 85decodeWidth=8 86dispatchWidth=8 87do_checkpoint_insts=true 88do_quiesce=true 89do_statistics_insts=true 90dtb=system.cpu0.dtb 91eventq_index=0 92fetchBufferSize=64 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 76 unchanged lines hidden (view full) --- 85decodeWidth=8 86dispatchWidth=8 87do_checkpoint_insts=true 88do_quiesce=true 89do_statistics_insts=true 90dtb=system.cpu0.dtb 91eventq_index=0 92fetchBufferSize=64 |
| 93fetchQueueSize=32 |
|
| 93fetchToDecodeDelay=1 94fetchTrapLatency=1 95fetchWidth=8 96forwardComSize=5 97fuPool=system.cpu0.fuPool 98function_trace=false 99function_trace_start=0 100iewToCommitDelay=1 --- 36 unchanged lines hidden (view full) --- 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu0.tracer 144trapLatency=13 | 94fetchToDecodeDelay=1 95fetchTrapLatency=1 96fetchWidth=8 97forwardComSize=5 98fuPool=system.cpu0.fuPool 99function_trace=false 100function_trace_start=0 101iewToCommitDelay=1 --- 36 unchanged lines hidden (view full) --- 138smtROBThreshold=100 139socket_id=0 140squashWidth=8 141store_set_clear_period=250000 142switched_out=false 143system=system 144tracer=system.cpu0.tracer 145trapLatency=13 |
| 145wbDepth=1 | |
| 146wbWidth=8 147workload= 148dcache_port=system.cpu0.dcache.cpu_side 149icache_port=system.cpu0.icache.cpu_side 150 151[system.cpu0.branchPred] 152type=BranchPredictor 153BTBEntries=4096 --- 437 unchanged lines hidden (view full) --- 591decodeWidth=8 592dispatchWidth=8 593do_checkpoint_insts=true 594do_quiesce=true 595do_statistics_insts=true 596dtb=system.cpu1.dtb 597eventq_index=0 598fetchBufferSize=64 | 146wbWidth=8 147workload= 148dcache_port=system.cpu0.dcache.cpu_side 149icache_port=system.cpu0.icache.cpu_side 150 151[system.cpu0.branchPred] 152type=BranchPredictor 153BTBEntries=4096 --- 437 unchanged lines hidden (view full) --- 591decodeWidth=8 592dispatchWidth=8 593do_checkpoint_insts=true 594do_quiesce=true 595do_statistics_insts=true 596dtb=system.cpu1.dtb 597eventq_index=0 598fetchBufferSize=64 |
| 599fetchQueueSize=32 |
|
| 599fetchToDecodeDelay=1 600fetchTrapLatency=1 601fetchWidth=8 602forwardComSize=5 603fuPool=system.cpu1.fuPool 604function_trace=false 605function_trace_start=0 606iewToCommitDelay=1 --- 36 unchanged lines hidden (view full) --- 643smtROBThreshold=100 644socket_id=0 645squashWidth=8 646store_set_clear_period=250000 647switched_out=false 648system=system 649tracer=system.cpu1.tracer 650trapLatency=13 | 600fetchToDecodeDelay=1 601fetchTrapLatency=1 602fetchWidth=8 603forwardComSize=5 604fuPool=system.cpu1.fuPool 605function_trace=false 606function_trace_start=0 607iewToCommitDelay=1 --- 36 unchanged lines hidden (view full) --- 644smtROBThreshold=100 645socket_id=0 646squashWidth=8 647store_set_clear_period=250000 648switched_out=false 649system=system 650tracer=system.cpu1.tracer 651trapLatency=13 |
| 651wbDepth=1 | |
| 652wbWidth=8 653workload= 654dcache_port=system.cpu1.dcache.cpu_side 655icache_port=system.cpu1.icache.cpu_side 656 657[system.cpu1.branchPred] 658type=BranchPredictor 659BTBEntries=4096 --- 474 unchanged lines hidden (view full) --- 1134transition_latency=100000000 1135 1136[system.intrctrl] 1137type=IntrControl 1138eventq_index=0 1139sys=system 1140 1141[system.iobus] | 652wbWidth=8 653workload= 654dcache_port=system.cpu1.dcache.cpu_side 655icache_port=system.cpu1.icache.cpu_side 656 657[system.cpu1.branchPred] 658type=BranchPredictor 659BTBEntries=4096 --- 474 unchanged lines hidden (view full) --- 1134transition_latency=100000000 1135 1136[system.intrctrl] 1137type=IntrControl 1138eventq_index=0 1139sys=system 1140 1141[system.iobus] |
| 1142type=NoncoherentBus | 1142type=NoncoherentXBar |
| 1143clk_domain=system.clk_domain 1144eventq_index=0 1145header_cycles=1 1146use_default_range=true 1147width=8 1148default=system.tsunami.pciconfig.pio 1149master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 1150slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma --- 64 unchanged lines hidden (view full) --- 1215block_size=64 1216clk_domain=system.cpu_clk_domain 1217eventq_index=0 1218hit_latency=20 1219sequential_access=false 1220size=4194304 1221 1222[system.membus] | 1143clk_domain=system.clk_domain 1144eventq_index=0 1145header_cycles=1 1146use_default_range=true 1147width=8 1148default=system.tsunami.pciconfig.pio 1149master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 1150slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma --- 64 unchanged lines hidden (view full) --- 1215block_size=64 1216clk_domain=system.cpu_clk_domain 1217eventq_index=0 1218hit_latency=20 1219sequential_access=false 1220size=4194304 1221 1222[system.membus] |
| 1223type=CoherentBus | 1223type=CoherentXBar |
| 1224children=badaddr_responder 1225clk_domain=system.clk_domain 1226eventq_index=0 1227header_cycles=1 | 1224children=badaddr_responder 1225clk_domain=system.clk_domain 1226eventq_index=0 1227header_cycles=1 |
| 1228snoop_filter=Null |
|
| 1228system=system 1229use_default_range=false 1230width=8 1231default=system.membus.badaddr_responder.pio 1232master=system.bridge.slave system.physmem.port 1233slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1234 1235[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 1247ret_data8=255 1248system=system 1249update_data=false 1250warn_access= 1251pio=system.membus.default 1252 1253[system.physmem] 1254type=DRAMCtrl | 1229system=system 1230use_default_range=false 1231width=8 1232default=system.membus.badaddr_responder.pio 1233master=system.bridge.slave system.physmem.port 1234slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1235 1236[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 1248ret_data8=255 1249system=system 1250update_data=false 1251warn_access= 1252pio=system.membus.default 1253 1254[system.physmem] 1255type=DRAMCtrl |
| 1256IDD0=0.075000 1257IDD02=0.000000 1258IDD2N=0.050000 1259IDD2N2=0.000000 1260IDD2P0=0.000000 1261IDD2P02=0.000000 1262IDD2P1=0.000000 1263IDD2P12=0.000000 1264IDD3N=0.057000 1265IDD3N2=0.000000 1266IDD3P0=0.000000 1267IDD3P02=0.000000 1268IDD3P1=0.000000 1269IDD3P12=0.000000 1270IDD4R=0.187000 1271IDD4R2=0.000000 1272IDD4W=0.165000 1273IDD4W2=0.000000 1274IDD5=0.220000 1275IDD52=0.000000 1276IDD6=0.000000 1277IDD62=0.000000 1278VDD=1.500000 1279VDD2=0.000000 |
|
| 1255activation_limit=4 1256addr_mapping=RoRaBaChCo | 1280activation_limit=4 1281addr_mapping=RoRaBaChCo |
| 1282bank_groups_per_rank=0 |
|
| 1257banks_per_rank=8 1258burst_length=8 1259channels=1 1260clk_domain=system.clk_domain 1261conf_table_reported=true 1262device_bus_width=8 1263device_rowbuffer_size=1024 1264devices_per_rank=8 | 1283banks_per_rank=8 1284burst_length=8 1285channels=1 1286clk_domain=system.clk_domain 1287conf_table_reported=true 1288device_bus_width=8 1289device_rowbuffer_size=1024 1290devices_per_rank=8 |
| 1291dll=true |
|
| 1265eventq_index=0 1266in_addr_map=true 1267max_accesses_per_row=16 1268mem_sched_policy=frfcfs 1269min_writes_per_switch=16 1270null=false 1271page_policy=open_adaptive 1272range=0:134217727 1273ranks_per_channel=2 1274read_buffer_size=32 1275static_backend_latency=10000 1276static_frontend_latency=10000 1277tBURST=5000 | 1292eventq_index=0 1293in_addr_map=true 1294max_accesses_per_row=16 1295mem_sched_policy=frfcfs 1296min_writes_per_switch=16 1297null=false 1298page_policy=open_adaptive 1299range=0:134217727 1300ranks_per_channel=2 1301read_buffer_size=32 1302static_backend_latency=10000 1303static_frontend_latency=10000 1304tBURST=5000 |
| 1305tCCD_L=0 |
|
| 1278tCK=1250 1279tCL=13750 | 1306tCK=1250 1307tCL=13750 |
| 1308tCS=2500 |
|
| 1280tRAS=35000 1281tRCD=13750 1282tREFI=7800000 1283tRFC=260000 1284tRP=13750 1285tRRD=6000 | 1309tRAS=35000 1310tRCD=13750 1311tREFI=7800000 1312tRFC=260000 1313tRP=13750 1314tRRD=6000 |
| 1315tRRD_L=0 |
|
| 1286tRTP=7500 1287tRTW=2500 1288tWR=15000 1289tWTR=7500 1290tXAW=30000 | 1316tRTP=7500 1317tRTW=2500 1318tWR=15000 1319tWTR=7500 1320tXAW=30000 |
| 1321tXP=0 1322tXPDLL=0 1323tXS=0 1324tXSDLL=0 |
|
| 1291write_buffer_size=64 1292write_high_thresh_perc=85 1293write_low_thresh_perc=50 1294port=system.membus.master[1] 1295 1296[system.simple_disk] 1297type=SimpleDisk 1298children=disk --- 11 unchanged lines hidden (view full) --- 1310type=Terminal 1311eventq_index=0 1312intr_control=system.intrctrl 1313number=0 1314output=true 1315port=3456 1316 1317[system.toL2Bus] | 1325write_buffer_size=64 1326write_high_thresh_perc=85 1327write_low_thresh_perc=50 1328port=system.membus.master[1] 1329 1330[system.simple_disk] 1331type=SimpleDisk 1332children=disk --- 11 unchanged lines hidden (view full) --- 1344type=Terminal 1345eventq_index=0 1346intr_control=system.intrctrl 1347number=0 1348output=true 1349port=3456 1350 1351[system.toL2Bus] |
| 1318type=CoherentBus | 1352type=CoherentXBar |
| 1319clk_domain=system.cpu_clk_domain 1320eventq_index=0 1321header_cycles=1 | 1353clk_domain=system.cpu_clk_domain 1354eventq_index=0 1355header_cycles=1 |
| 1356snoop_filter=Null |
|
| 1322system=system 1323use_default_range=false 1324width=8 1325master=system.l2c.cpu_side 1326slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1327 1328[system.tsunami] 1329type=Tsunami --- 52 unchanged lines hidden (view full) --- 1382ClassCode=2 1383Command=0 1384DeviceID=34 1385ExpansionROM=0 1386HeaderType=0 1387InterruptLine=30 1388InterruptPin=1 1389LatencyTimer=0 | 1357system=system 1358use_default_range=false 1359width=8 1360master=system.l2c.cpu_side 1361slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1362 1363[system.tsunami] 1364type=Tsunami --- 52 unchanged lines hidden (view full) --- 1417ClassCode=2 1418Command=0 1419DeviceID=34 1420ExpansionROM=0 1421HeaderType=0 1422InterruptLine=30 1423InterruptPin=1 1424LatencyTimer=0 |
| 1425LegacyIOBase=0 |
|
| 1390MSICAPBaseOffset=0 1391MSICAPCapId=0 1392MSICAPMaskBits=0 1393MSICAPMsgAddr=0 1394MSICAPMsgCtrl=0 1395MSICAPMsgData=0 1396MSICAPMsgUpperAddr=0 1397MSICAPNextCapability=0 --- 439 unchanged lines hidden (view full) --- 1837ClassCode=1 1838Command=0 1839DeviceID=28945 1840ExpansionROM=0 1841HeaderType=0 1842InterruptLine=31 1843InterruptPin=1 1844LatencyTimer=0 | 1426MSICAPBaseOffset=0 1427MSICAPCapId=0 1428MSICAPMaskBits=0 1429MSICAPMsgAddr=0 1430MSICAPMsgCtrl=0 1431MSICAPMsgData=0 1432MSICAPMsgUpperAddr=0 1433MSICAPNextCapability=0 --- 439 unchanged lines hidden (view full) --- 1873ClassCode=1 1874Command=0 1875DeviceID=28945 1876ExpansionROM=0 1877HeaderType=0 1878InterruptLine=31 1879InterruptPin=1 1880LatencyTimer=0 |
| 1881LegacyIOBase=0 |
|
| 1845MSICAPBaseOffset=0 1846MSICAPCapId=0 1847MSICAPMaskBits=0 1848MSICAPMsgAddr=0 1849MSICAPMsgCtrl=0 1850MSICAPMsgData=0 1851MSICAPMsgUpperAddr=0 1852MSICAPNextCapability=0 --- 100 unchanged lines hidden --- | 1882MSICAPBaseOffset=0 1883MSICAPCapId=0 1884MSICAPMaskBits=0 1885MSICAPMsgAddr=0 1886MSICAPMsgCtrl=0 1887MSICAPMsgData=0 1888MSICAPMsgUpperAddr=0 1889MSICAPNextCapability=0 --- 100 unchanged lines hidden --- |