| 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
| 5full_system=true |
| 6sim_quantum=0 |
| 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
| 18console=/scratch/nilay/GEM5/system/binaries/console 19eventq_index=0 |
| 20init_param=0 |
| 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux |
| 22load_addr_mask=1099511627775 23mem_mode=timing 24mem_ranges=0:134217727 25memories=system.physmem 26num_work_ids=16 |
| 27pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal |
| 28readfile=tests/halt.sh 29symbolfile= 30system_rev=1024 31system_type=34 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clk_domain=system.clk_domain 44delay=50000 |
| 45eventq_index=0 |
| 46ranges=8796093022208:18446744073709551615 47req_size=16 48resp_size=16 49master=system.iobus.slave[0] 50slave=system.membus.master[0] 51 52[system.clk_domain] 53type=SrcClockDomain 54clock=1000 |
| 55eventq_index=0 |
| 56voltage_domain=system.voltage_domain 57 58[system.cpu0] 59type=DerivO3CPU 60children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 61LFSTSize=1024 62LQEntries=32 63LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 79decodeToFetchDelay=1 80decodeToRenameDelay=1 81decodeWidth=8 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu0.dtb |
| 87eventq_index=0 88fetchBufferSize=64 |
| 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 145 146[system.cpu0.branchPred] 147type=BranchPredictor 148BTBEntries=4096 149BTBTagSize=16 150RASSize=16 151choiceCtrBits=2 152choicePredictorSize=8192 |
| 153eventq_index=0 |
| 154globalCtrBits=2 155globalPredictorSize=8192 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=1 161predType=tournament 162 163[system.cpu0.dcache] 164type=BaseCache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=4 168clk_domain=system.cpu_clk_domain |
| 169eventq_index=0 |
| 170forward_snoops=true 171hit_latency=2 172is_top_level=true 173max_miss_count=0 174mshrs=4 175prefetch_on_access=false 176prefetcher=Null 177response_latency=2 --- 6 unchanged lines hidden (view full) --- 184cpu_side=system.cpu0.dcache_port 185mem_side=system.toL2Bus.slave[1] 186 187[system.cpu0.dcache.tags] 188type=LRU 189assoc=4 190block_size=64 191clk_domain=system.cpu_clk_domain |
| 192eventq_index=0 |
| 193hit_latency=2 194size=32768 195 196[system.cpu0.dtb] 197type=AlphaTLB |
| 198eventq_index=0 |
| 199size=64 200 201[system.cpu0.fuPool] 202type=FUPool 203children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 204FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 |
| 205eventq_index=0 |
| 206 207[system.cpu0.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6 |
| 211eventq_index=0 |
| 212opList=system.cpu0.fuPool.FUList0.opList 213 214[system.cpu0.fuPool.FUList0.opList] 215type=OpDesc |
| 216eventq_index=0 |
| 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu0.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 |
| 225eventq_index=0 |
| 226opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 227 228[system.cpu0.fuPool.FUList1.opList0] 229type=OpDesc |
| 230eventq_index=0 |
| 231issueLat=1 232opClass=IntMult 233opLat=3 234 235[system.cpu0.fuPool.FUList1.opList1] 236type=OpDesc |
| 237eventq_index=0 |
| 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu0.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 |
| 246eventq_index=0 |
| 247opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 248 249[system.cpu0.fuPool.FUList2.opList0] 250type=OpDesc |
| 251eventq_index=0 |
| 252issueLat=1 253opClass=FloatAdd 254opLat=2 255 256[system.cpu0.fuPool.FUList2.opList1] 257type=OpDesc |
| 258eventq_index=0 |
| 259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu0.fuPool.FUList2.opList2] 264type=OpDesc |
| 265eventq_index=0 |
| 266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu0.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2 |
| 274eventq_index=0 |
| 275opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 276 277[system.cpu0.fuPool.FUList3.opList0] 278type=OpDesc |
| 279eventq_index=0 |
| 280issueLat=1 281opClass=FloatMult 282opLat=4 283 284[system.cpu0.fuPool.FUList3.opList1] 285type=OpDesc |
| 286eventq_index=0 |
| 287issueLat=12 288opClass=FloatDiv 289opLat=12 290 291[system.cpu0.fuPool.FUList3.opList2] 292type=OpDesc |
| 293eventq_index=0 |
| 294issueLat=24 295opClass=FloatSqrt 296opLat=24 297 298[system.cpu0.fuPool.FUList4] 299type=FUDesc 300children=opList 301count=0 |
| 302eventq_index=0 |
| 303opList=system.cpu0.fuPool.FUList4.opList 304 305[system.cpu0.fuPool.FUList4.opList] 306type=OpDesc |
| 307eventq_index=0 |
| 308issueLat=1 309opClass=MemRead 310opLat=1 311 312[system.cpu0.fuPool.FUList5] 313type=FUDesc 314children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 315count=4 |
| 316eventq_index=0 |
| 317opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 318 319[system.cpu0.fuPool.FUList5.opList00] 320type=OpDesc |
| 321eventq_index=0 |
| 322issueLat=1 323opClass=SimdAdd 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList01] 327type=OpDesc |
| 328eventq_index=0 |
| 329issueLat=1 330opClass=SimdAddAcc 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList02] 334type=OpDesc |
| 335eventq_index=0 |
| 336issueLat=1 337opClass=SimdAlu 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList03] 341type=OpDesc |
| 342eventq_index=0 |
| 343issueLat=1 344opClass=SimdCmp 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList04] 348type=OpDesc |
| 349eventq_index=0 |
| 350issueLat=1 351opClass=SimdCvt 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList05] 355type=OpDesc |
| 356eventq_index=0 |
| 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList06] 362type=OpDesc |
| 363eventq_index=0 |
| 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList07] 369type=OpDesc |
| 370eventq_index=0 |
| 371issueLat=1 372opClass=SimdMultAcc 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList08] 376type=OpDesc |
| 377eventq_index=0 |
| 378issueLat=1 379opClass=SimdShift 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList09] 383type=OpDesc |
| 384eventq_index=0 |
| 385issueLat=1 386opClass=SimdShiftAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList10] 390type=OpDesc |
| 391eventq_index=0 |
| 392issueLat=1 393opClass=SimdSqrt 394opLat=1 395 396[system.cpu0.fuPool.FUList5.opList11] 397type=OpDesc |
| 398eventq_index=0 |
| 399issueLat=1 400opClass=SimdFloatAdd 401opLat=1 402 403[system.cpu0.fuPool.FUList5.opList12] 404type=OpDesc |
| 405eventq_index=0 |
| 406issueLat=1 407opClass=SimdFloatAlu 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList13] 411type=OpDesc |
| 412eventq_index=0 |
| 413issueLat=1 414opClass=SimdFloatCmp 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList14] 418type=OpDesc |
| 419eventq_index=0 |
| 420issueLat=1 421opClass=SimdFloatCvt 422opLat=1 423 424[system.cpu0.fuPool.FUList5.opList15] 425type=OpDesc |
| 426eventq_index=0 |
| 427issueLat=1 428opClass=SimdFloatDiv 429opLat=1 430 431[system.cpu0.fuPool.FUList5.opList16] 432type=OpDesc |
| 433eventq_index=0 |
| 434issueLat=1 435opClass=SimdFloatMisc 436opLat=1 437 438[system.cpu0.fuPool.FUList5.opList17] 439type=OpDesc |
| 440eventq_index=0 |
| 441issueLat=1 442opClass=SimdFloatMult 443opLat=1 444 445[system.cpu0.fuPool.FUList5.opList18] 446type=OpDesc |
| 447eventq_index=0 |
| 448issueLat=1 449opClass=SimdFloatMultAcc 450opLat=1 451 452[system.cpu0.fuPool.FUList5.opList19] 453type=OpDesc |
| 454eventq_index=0 |
| 455issueLat=1 456opClass=SimdFloatSqrt 457opLat=1 458 459[system.cpu0.fuPool.FUList6] 460type=FUDesc 461children=opList 462count=0 |
| 463eventq_index=0 |
| 464opList=system.cpu0.fuPool.FUList6.opList 465 466[system.cpu0.fuPool.FUList6.opList] 467type=OpDesc |
| 468eventq_index=0 |
| 469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu0.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4 |
| 477eventq_index=0 |
| 478opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 479 480[system.cpu0.fuPool.FUList7.opList0] 481type=OpDesc |
| 482eventq_index=0 |
| 483issueLat=1 484opClass=MemRead 485opLat=1 486 487[system.cpu0.fuPool.FUList7.opList1] 488type=OpDesc |
| 489eventq_index=0 |
| 490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu0.fuPool.FUList8] 495type=FUDesc 496children=opList 497count=1 |
| 498eventq_index=0 |
| 499opList=system.cpu0.fuPool.FUList8.opList 500 501[system.cpu0.fuPool.FUList8.opList] 502type=OpDesc |
| 503eventq_index=0 |
| 504issueLat=3 505opClass=IprAccess 506opLat=3 507 508[system.cpu0.icache] 509type=BaseCache 510children=tags 511addr_ranges=0:18446744073709551615 512assoc=1 513clk_domain=system.cpu_clk_domain |
| 514eventq_index=0 |
| 515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 --- 6 unchanged lines hidden (view full) --- 529cpu_side=system.cpu0.icache_port 530mem_side=system.toL2Bus.slave[0] 531 532[system.cpu0.icache.tags] 533type=LRU 534assoc=1 535block_size=64 536clk_domain=system.cpu_clk_domain |
| 537eventq_index=0 |
| 538hit_latency=2 539size=32768 540 541[system.cpu0.interrupts] 542type=AlphaInterrupts |
| 543eventq_index=0 |
| 544 545[system.cpu0.isa] 546type=AlphaISA |
| 547eventq_index=0 |
| 548 549[system.cpu0.itb] 550type=AlphaTLB |
| 551eventq_index=0 |
| 552size=48 553 554[system.cpu0.tracer] 555type=ExeTracer |
| 556eventq_index=0 |
| 557 558[system.cpu1] 559type=DerivO3CPU 560children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 561LFSTSize=1024 562LQEntries=32 563LSQCheckLoads=true 564LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 579decodeToFetchDelay=1 580decodeToRenameDelay=1 581decodeWidth=8 582dispatchWidth=8 583do_checkpoint_insts=true 584do_quiesce=true 585do_statistics_insts=true 586dtb=system.cpu1.dtb |
| 587eventq_index=0 588fetchBufferSize=64 |
| 589fetchToDecodeDelay=1 590fetchTrapLatency=1 591fetchWidth=8 592forwardComSize=5 593fuPool=system.cpu1.fuPool 594function_trace=false 595function_trace_start=0 596iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 645 646[system.cpu1.branchPred] 647type=BranchPredictor 648BTBEntries=4096 649BTBTagSize=16 650RASSize=16 651choiceCtrBits=2 652choicePredictorSize=8192 |
| 653eventq_index=0 |
| 654globalCtrBits=2 655globalPredictorSize=8192 656instShiftAmt=2 657localCtrBits=2 658localHistoryTableSize=2048 659localPredictorSize=2048 660numThreads=1 661predType=tournament 662 663[system.cpu1.dcache] 664type=BaseCache 665children=tags 666addr_ranges=0:18446744073709551615 667assoc=4 668clk_domain=system.cpu_clk_domain |
| 669eventq_index=0 |
| 670forward_snoops=true 671hit_latency=2 672is_top_level=true 673max_miss_count=0 674mshrs=4 675prefetch_on_access=false 676prefetcher=Null 677response_latency=2 --- 6 unchanged lines hidden (view full) --- 684cpu_side=system.cpu1.dcache_port 685mem_side=system.toL2Bus.slave[3] 686 687[system.cpu1.dcache.tags] 688type=LRU 689assoc=4 690block_size=64 691clk_domain=system.cpu_clk_domain |
| 692eventq_index=0 |
| 693hit_latency=2 694size=32768 695 696[system.cpu1.dtb] 697type=AlphaTLB |
| 698eventq_index=0 |
| 699size=64 700 701[system.cpu1.fuPool] 702type=FUPool 703children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 704FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 |
| 705eventq_index=0 |
| 706 707[system.cpu1.fuPool.FUList0] 708type=FUDesc 709children=opList 710count=6 |
| 711eventq_index=0 |
| 712opList=system.cpu1.fuPool.FUList0.opList 713 714[system.cpu1.fuPool.FUList0.opList] 715type=OpDesc |
| 716eventq_index=0 |
| 717issueLat=1 718opClass=IntAlu 719opLat=1 720 721[system.cpu1.fuPool.FUList1] 722type=FUDesc 723children=opList0 opList1 724count=2 |
| 725eventq_index=0 |
| 726opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 727 728[system.cpu1.fuPool.FUList1.opList0] 729type=OpDesc |
| 730eventq_index=0 |
| 731issueLat=1 732opClass=IntMult 733opLat=3 734 735[system.cpu1.fuPool.FUList1.opList1] 736type=OpDesc |
| 737eventq_index=0 |
| 738issueLat=19 739opClass=IntDiv 740opLat=20 741 742[system.cpu1.fuPool.FUList2] 743type=FUDesc 744children=opList0 opList1 opList2 745count=4 |
| 746eventq_index=0 |
| 747opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 748 749[system.cpu1.fuPool.FUList2.opList0] 750type=OpDesc |
| 751eventq_index=0 |
| 752issueLat=1 753opClass=FloatAdd 754opLat=2 755 756[system.cpu1.fuPool.FUList2.opList1] 757type=OpDesc |
| 758eventq_index=0 |
| 759issueLat=1 760opClass=FloatCmp 761opLat=2 762 763[system.cpu1.fuPool.FUList2.opList2] 764type=OpDesc |
| 765eventq_index=0 |
| 766issueLat=1 767opClass=FloatCvt 768opLat=2 769 770[system.cpu1.fuPool.FUList3] 771type=FUDesc 772children=opList0 opList1 opList2 773count=2 |
| 774eventq_index=0 |
| 775opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 776 777[system.cpu1.fuPool.FUList3.opList0] 778type=OpDesc |
| 779eventq_index=0 |
| 780issueLat=1 781opClass=FloatMult 782opLat=4 783 784[system.cpu1.fuPool.FUList3.opList1] 785type=OpDesc |
| 786eventq_index=0 |
| 787issueLat=12 788opClass=FloatDiv 789opLat=12 790 791[system.cpu1.fuPool.FUList3.opList2] 792type=OpDesc |
| 793eventq_index=0 |
| 794issueLat=24 795opClass=FloatSqrt 796opLat=24 797 798[system.cpu1.fuPool.FUList4] 799type=FUDesc 800children=opList 801count=0 |
| 802eventq_index=0 |
| 803opList=system.cpu1.fuPool.FUList4.opList 804 805[system.cpu1.fuPool.FUList4.opList] 806type=OpDesc |
| 807eventq_index=0 |
| 808issueLat=1 809opClass=MemRead 810opLat=1 811 812[system.cpu1.fuPool.FUList5] 813type=FUDesc 814children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 815count=4 |
| 816eventq_index=0 |
| 817opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 818 819[system.cpu1.fuPool.FUList5.opList00] 820type=OpDesc |
| 821eventq_index=0 |
| 822issueLat=1 823opClass=SimdAdd 824opLat=1 825 826[system.cpu1.fuPool.FUList5.opList01] 827type=OpDesc |
| 828eventq_index=0 |
| 829issueLat=1 830opClass=SimdAddAcc 831opLat=1 832 833[system.cpu1.fuPool.FUList5.opList02] 834type=OpDesc |
| 835eventq_index=0 |
| 836issueLat=1 837opClass=SimdAlu 838opLat=1 839 840[system.cpu1.fuPool.FUList5.opList03] 841type=OpDesc |
| 842eventq_index=0 |
| 843issueLat=1 844opClass=SimdCmp 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList04] 848type=OpDesc |
| 849eventq_index=0 |
| 850issueLat=1 851opClass=SimdCvt 852opLat=1 853 854[system.cpu1.fuPool.FUList5.opList05] 855type=OpDesc |
| 856eventq_index=0 |
| 857issueLat=1 858opClass=SimdMisc 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList06] 862type=OpDesc |
| 863eventq_index=0 |
| 864issueLat=1 865opClass=SimdMult 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList07] 869type=OpDesc |
| 870eventq_index=0 |
| 871issueLat=1 872opClass=SimdMultAcc 873opLat=1 874 875[system.cpu1.fuPool.FUList5.opList08] 876type=OpDesc |
| 877eventq_index=0 |
| 878issueLat=1 879opClass=SimdShift 880opLat=1 881 882[system.cpu1.fuPool.FUList5.opList09] 883type=OpDesc |
| 884eventq_index=0 |
| 885issueLat=1 886opClass=SimdShiftAcc 887opLat=1 888 889[system.cpu1.fuPool.FUList5.opList10] 890type=OpDesc |
| 891eventq_index=0 |
| 892issueLat=1 893opClass=SimdSqrt 894opLat=1 895 896[system.cpu1.fuPool.FUList5.opList11] 897type=OpDesc |
| 898eventq_index=0 |
| 899issueLat=1 900opClass=SimdFloatAdd 901opLat=1 902 903[system.cpu1.fuPool.FUList5.opList12] 904type=OpDesc |
| 905eventq_index=0 |
| 906issueLat=1 907opClass=SimdFloatAlu 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList13] 911type=OpDesc |
| 912eventq_index=0 |
| 913issueLat=1 914opClass=SimdFloatCmp 915opLat=1 916 917[system.cpu1.fuPool.FUList5.opList14] 918type=OpDesc |
| 919eventq_index=0 |
| 920issueLat=1 921opClass=SimdFloatCvt 922opLat=1 923 924[system.cpu1.fuPool.FUList5.opList15] 925type=OpDesc |
| 926eventq_index=0 |
| 927issueLat=1 928opClass=SimdFloatDiv 929opLat=1 930 931[system.cpu1.fuPool.FUList5.opList16] 932type=OpDesc |
| 933eventq_index=0 |
| 934issueLat=1 935opClass=SimdFloatMisc 936opLat=1 937 938[system.cpu1.fuPool.FUList5.opList17] 939type=OpDesc |
| 940eventq_index=0 |
| 941issueLat=1 942opClass=SimdFloatMult 943opLat=1 944 945[system.cpu1.fuPool.FUList5.opList18] 946type=OpDesc |
| 947eventq_index=0 |
| 948issueLat=1 949opClass=SimdFloatMultAcc 950opLat=1 951 952[system.cpu1.fuPool.FUList5.opList19] 953type=OpDesc |
| 954eventq_index=0 |
| 955issueLat=1 956opClass=SimdFloatSqrt 957opLat=1 958 959[system.cpu1.fuPool.FUList6] 960type=FUDesc 961children=opList 962count=0 |
| 963eventq_index=0 |
| 964opList=system.cpu1.fuPool.FUList6.opList 965 966[system.cpu1.fuPool.FUList6.opList] 967type=OpDesc |
| 968eventq_index=0 |
| 969issueLat=1 970opClass=MemWrite 971opLat=1 972 973[system.cpu1.fuPool.FUList7] 974type=FUDesc 975children=opList0 opList1 976count=4 |
| 977eventq_index=0 |
| 978opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 979 980[system.cpu1.fuPool.FUList7.opList0] 981type=OpDesc |
| 982eventq_index=0 |
| 983issueLat=1 984opClass=MemRead 985opLat=1 986 987[system.cpu1.fuPool.FUList7.opList1] 988type=OpDesc |
| 989eventq_index=0 |
| 990issueLat=1 991opClass=MemWrite 992opLat=1 993 994[system.cpu1.fuPool.FUList8] 995type=FUDesc 996children=opList 997count=1 |
| 998eventq_index=0 |
| 999opList=system.cpu1.fuPool.FUList8.opList 1000 1001[system.cpu1.fuPool.FUList8.opList] 1002type=OpDesc |
| 1003eventq_index=0 |
| 1004issueLat=3 1005opClass=IprAccess 1006opLat=3 1007 1008[system.cpu1.icache] 1009type=BaseCache 1010children=tags 1011addr_ranges=0:18446744073709551615 1012assoc=1 1013clk_domain=system.cpu_clk_domain |
| 1014eventq_index=0 |
| 1015forward_snoops=true 1016hit_latency=2 1017is_top_level=true 1018max_miss_count=0 1019mshrs=4 1020prefetch_on_access=false 1021prefetcher=Null 1022response_latency=2 --- 6 unchanged lines hidden (view full) --- 1029cpu_side=system.cpu1.icache_port 1030mem_side=system.toL2Bus.slave[2] 1031 1032[system.cpu1.icache.tags] 1033type=LRU 1034assoc=1 1035block_size=64 1036clk_domain=system.cpu_clk_domain |
| 1037eventq_index=0 |
| 1038hit_latency=2 1039size=32768 1040 1041[system.cpu1.interrupts] 1042type=AlphaInterrupts |
| 1043eventq_index=0 |
| 1044 1045[system.cpu1.isa] 1046type=AlphaISA |
| 1047eventq_index=0 |
| 1048 1049[system.cpu1.itb] 1050type=AlphaTLB |
| 1051eventq_index=0 |
| 1052size=48 1053 1054[system.cpu1.tracer] 1055type=ExeTracer |
| 1056eventq_index=0 |
| 1057 1058[system.cpu_clk_domain] 1059type=SrcClockDomain 1060clock=500 |
| 1061eventq_index=0 |
| 1062voltage_domain=system.voltage_domain 1063 1064[system.disk0] 1065type=IdeDisk 1066children=image 1067delay=1000000 1068driveID=master |
| 1069eventq_index=0 |
| 1070image=system.disk0.image 1071 1072[system.disk0.image] 1073type=CowDiskImage 1074children=child 1075child=system.disk0.image.child |
| 1076eventq_index=0 |
| 1077image_file= 1078read_only=false 1079table_size=65536 1080 1081[system.disk0.image.child] 1082type=RawDiskImage |
| 1083eventq_index=0 1084image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
| 1085read_only=true 1086 1087[system.disk2] 1088type=IdeDisk 1089children=image 1090delay=1000000 1091driveID=master |
| 1092eventq_index=0 |
| 1093image=system.disk2.image 1094 1095[system.disk2.image] 1096type=CowDiskImage 1097children=child 1098child=system.disk2.image.child |
| 1099eventq_index=0 |
| 1100image_file= 1101read_only=false 1102table_size=65536 1103 1104[system.disk2.image.child] 1105type=RawDiskImage |
| 1106eventq_index=0 1107image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img |
| 1108read_only=true 1109 1110[system.intrctrl] 1111type=IntrControl |
| 1112eventq_index=0 |
| 1113sys=system 1114 1115[system.iobus] 1116type=NoncoherentBus 1117clk_domain=system.clk_domain |
| 1118eventq_index=0 |
| 1119header_cycles=1 1120use_default_range=true 1121width=8 1122default=system.tsunami.pciconfig.pio 1123master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 1124slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1125 1126[system.iocache] 1127type=BaseCache 1128children=tags 1129addr_ranges=0:134217727 1130assoc=8 1131clk_domain=system.clk_domain |
| 1132eventq_index=0 |
| 1133forward_snoops=false 1134hit_latency=50 1135is_top_level=true 1136max_miss_count=0 1137mshrs=20 1138prefetch_on_access=false 1139prefetcher=Null 1140response_latency=50 --- 6 unchanged lines hidden (view full) --- 1147cpu_side=system.iobus.master[29] 1148mem_side=system.membus.slave[2] 1149 1150[system.iocache.tags] 1151type=LRU 1152assoc=8 1153block_size=64 1154clk_domain=system.clk_domain |
| 1155eventq_index=0 |
| 1156hit_latency=50 1157size=1024 1158 1159[system.l2c] 1160type=BaseCache 1161children=tags 1162addr_ranges=0:18446744073709551615 1163assoc=8 1164clk_domain=system.cpu_clk_domain |
| 1165eventq_index=0 |
| 1166forward_snoops=true 1167hit_latency=20 1168is_top_level=false 1169max_miss_count=0 1170mshrs=20 1171prefetch_on_access=false 1172prefetcher=Null 1173response_latency=20 --- 6 unchanged lines hidden (view full) --- 1180cpu_side=system.toL2Bus.master[0] 1181mem_side=system.membus.slave[1] 1182 1183[system.l2c.tags] 1184type=LRU 1185assoc=8 1186block_size=64 1187clk_domain=system.cpu_clk_domain |
| 1188eventq_index=0 |
| 1189hit_latency=20 1190size=4194304 1191 1192[system.membus] 1193type=CoherentBus 1194children=badaddr_responder 1195clk_domain=system.clk_domain |
| 1196eventq_index=0 |
| 1197header_cycles=1 1198system=system 1199use_default_range=false 1200width=8 1201default=system.membus.badaddr_responder.pio 1202master=system.bridge.slave system.physmem.port 1203slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1204 1205[system.membus.badaddr_responder] 1206type=IsaFake 1207clk_domain=system.clk_domain |
| 1208eventq_index=0 |
| 1209fake_mem=false 1210pio_addr=0 1211pio_latency=100000 1212pio_size=8 1213ret_bad_addr=true 1214ret_data16=65535 1215ret_data32=4294967295 1216ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 1227banks_per_rank=8 1228burst_length=8 1229channels=1 1230clk_domain=system.clk_domain 1231conf_table_reported=true 1232device_bus_width=8 1233device_rowbuffer_size=1024 1234devices_per_rank=8 |
| 1235eventq_index=0 |
| 1236in_addr_map=true 1237mem_sched_policy=frfcfs 1238null=false 1239page_policy=open 1240range=0:134217727 1241ranks_per_channel=2 1242read_buffer_size=32 1243static_backend_latency=10000 1244static_frontend_latency=10000 1245tBURST=5000 1246tCL=13750 |
| 1247tRAS=35000 |
| 1248tRCD=13750 1249tREFI=7800000 1250tRFC=300000 1251tRP=13750 |
| 1252tRRD=6250 |
| 1253tWTR=7500 1254tXAW=40000 1255write_buffer_size=32 |
| 1256write_high_thresh_perc=70 1257write_low_thresh_perc=0 |
| 1258port=system.membus.master[1] 1259 1260[system.simple_disk] 1261type=SimpleDisk 1262children=disk 1263disk=system.simple_disk.disk |
| 1264eventq_index=0 |
| 1265system=system 1266 1267[system.simple_disk.disk] 1268type=RawDiskImage |
| 1269eventq_index=0 1270image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
| 1271read_only=true 1272 1273[system.terminal] 1274type=Terminal |
| 1275eventq_index=0 |
| 1276intr_control=system.intrctrl 1277number=0 1278output=true 1279port=3456 1280 1281[system.toL2Bus] 1282type=CoherentBus 1283clk_domain=system.cpu_clk_domain |
| 1284eventq_index=0 |
| 1285header_cycles=1 1286system=system 1287use_default_range=false 1288width=8 1289master=system.l2c.cpu_side 1290slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1291 1292[system.tsunami] 1293type=Tsunami 1294children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart |
| 1295eventq_index=0 |
| 1296intrctrl=system.intrctrl 1297system=system 1298 1299[system.tsunami.backdoor] 1300type=AlphaBackdoor 1301clk_domain=system.clk_domain 1302cpu=system.cpu0 1303disk=system.simple_disk |
| 1304eventq_index=0 |
| 1305pio_addr=8804682956800 1306pio_latency=100000 1307platform=system.tsunami 1308system=system 1309terminal=system.terminal 1310pio=system.iobus.master[24] 1311 1312[system.tsunami.cchip] 1313type=TsunamiCChip 1314clk_domain=system.clk_domain |
| 1315eventq_index=0 |
| 1316pio_addr=8803072344064 1317pio_latency=100000 1318system=system 1319tsunami=system.tsunami 1320pio=system.iobus.master[0] 1321 1322[system.tsunami.ethernet] 1323type=NSGigE --- 12 unchanged lines hidden (view full) --- 1336BAR4=0 1337BAR4LegacyIO=false 1338BAR4Size=0 1339BAR5=0 1340BAR5LegacyIO=false 1341BAR5Size=0 1342BIST=0 1343CacheLineSize=0 |
| 1344CapabilityPtr=0 |
| 1345CardbusCIS=0 1346ClassCode=2 1347Command=0 1348DeviceID=34 1349ExpansionROM=0 1350HeaderType=0 1351InterruptLine=30 1352InterruptPin=1 1353LatencyTimer=0 |
| 1354MSICAPBaseOffset=0 1355MSICAPCapId=0 1356MSICAPMaskBits=0 1357MSICAPMsgAddr=0 1358MSICAPMsgCtrl=0 1359MSICAPMsgData=0 1360MSICAPMsgUpperAddr=0 1361MSICAPNextCapability=0 1362MSICAPPendingBits=0 1363MSIXCAPBaseOffset=0 1364MSIXCAPCapId=0 1365MSIXCAPNextCapability=0 1366MSIXMsgCtrl=0 1367MSIXPbaOffset=0 1368MSIXTableOffset=0 |
| 1369MaximumLatency=52 1370MinimumGrant=176 |
| 1371PMCAPBaseOffset=0 1372PMCAPCapId=0 1373PMCAPCapabilities=0 1374PMCAPCtrlStatus=0 1375PMCAPNextCapability=0 1376PXCAPBaseOffset=0 1377PXCAPCapId=0 1378PXCAPCapabilities=0 1379PXCAPDevCap2=0 1380PXCAPDevCapabilities=0 1381PXCAPDevCtrl=0 1382PXCAPDevCtrl2=0 1383PXCAPDevStatus=0 1384PXCAPLinkCap=0 1385PXCAPLinkCtrl=0 1386PXCAPLinkStatus=0 1387PXCAPNextCapability=0 |
| 1388ProgIF=0 1389Revision=0 1390Status=656 1391SubClassCode=0 1392SubsystemID=0 1393SubsystemVendorID=0 1394VendorID=4107 1395clk_domain=system.clk_domain 1396config_latency=20000 1397dma_data_free=false 1398dma_desc_free=false 1399dma_no_allocate=true 1400dma_read_delay=0 1401dma_read_factor=0 1402dma_write_delay=0 1403dma_write_factor=0 |
| 1404eventq_index=0 |
| 1405hardware_address=00:90:00:00:00:01 1406intr_delay=10000000 1407pci_bus=0 1408pci_dev=1 1409pci_func=0 1410pio_latency=30000 1411platform=system.tsunami 1412rss=false --- 7 unchanged lines hidden (view full) --- 1420tx_thread=false 1421config=system.iobus.master[28] 1422dma=system.iobus.slave[2] 1423pio=system.iobus.master[27] 1424 1425[system.tsunami.fake_OROM] 1426type=IsaFake 1427clk_domain=system.clk_domain |
| 1428eventq_index=0 |
| 1429fake_mem=false 1430pio_addr=8796093677568 1431pio_latency=100000 1432pio_size=393216 1433ret_bad_addr=false 1434ret_data16=65535 1435ret_data32=4294967295 1436ret_data64=18446744073709551615 1437ret_data8=255 1438system=system 1439update_data=false 1440warn_access= 1441pio=system.iobus.master[8] 1442 1443[system.tsunami.fake_ata0] 1444type=IsaFake 1445clk_domain=system.clk_domain |
| 1446eventq_index=0 |
| 1447fake_mem=false 1448pio_addr=8804615848432 1449pio_latency=100000 1450pio_size=8 1451ret_bad_addr=false 1452ret_data16=65535 1453ret_data32=4294967295 1454ret_data64=18446744073709551615 1455ret_data8=255 1456system=system 1457update_data=false 1458warn_access= 1459pio=system.iobus.master[19] 1460 1461[system.tsunami.fake_ata1] 1462type=IsaFake 1463clk_domain=system.clk_domain |
| 1464eventq_index=0 |
| 1465fake_mem=false 1466pio_addr=8804615848304 1467pio_latency=100000 1468pio_size=8 1469ret_bad_addr=false 1470ret_data16=65535 1471ret_data32=4294967295 1472ret_data64=18446744073709551615 1473ret_data8=255 1474system=system 1475update_data=false 1476warn_access= 1477pio=system.iobus.master[20] 1478 1479[system.tsunami.fake_pnp_addr] 1480type=IsaFake 1481clk_domain=system.clk_domain |
| 1482eventq_index=0 |
| 1483fake_mem=false 1484pio_addr=8804615848569 1485pio_latency=100000 1486pio_size=8 1487ret_bad_addr=false 1488ret_data16=65535 1489ret_data32=4294967295 1490ret_data64=18446744073709551615 1491ret_data8=255 1492system=system 1493update_data=false 1494warn_access= 1495pio=system.iobus.master[9] 1496 1497[system.tsunami.fake_pnp_read0] 1498type=IsaFake 1499clk_domain=system.clk_domain |
| 1500eventq_index=0 |
| 1501fake_mem=false 1502pio_addr=8804615848451 1503pio_latency=100000 1504pio_size=8 1505ret_bad_addr=false 1506ret_data16=65535 1507ret_data32=4294967295 1508ret_data64=18446744073709551615 1509ret_data8=255 1510system=system 1511update_data=false 1512warn_access= 1513pio=system.iobus.master[11] 1514 1515[system.tsunami.fake_pnp_read1] 1516type=IsaFake 1517clk_domain=system.clk_domain |
| 1518eventq_index=0 |
| 1519fake_mem=false 1520pio_addr=8804615848515 1521pio_latency=100000 1522pio_size=8 1523ret_bad_addr=false 1524ret_data16=65535 1525ret_data32=4294967295 1526ret_data64=18446744073709551615 1527ret_data8=255 1528system=system 1529update_data=false 1530warn_access= 1531pio=system.iobus.master[12] 1532 1533[system.tsunami.fake_pnp_read2] 1534type=IsaFake 1535clk_domain=system.clk_domain |
| 1536eventq_index=0 |
| 1537fake_mem=false 1538pio_addr=8804615848579 1539pio_latency=100000 1540pio_size=8 1541ret_bad_addr=false 1542ret_data16=65535 1543ret_data32=4294967295 1544ret_data64=18446744073709551615 1545ret_data8=255 1546system=system 1547update_data=false 1548warn_access= 1549pio=system.iobus.master[13] 1550 1551[system.tsunami.fake_pnp_read3] 1552type=IsaFake 1553clk_domain=system.clk_domain |
| 1554eventq_index=0 |
| 1555fake_mem=false 1556pio_addr=8804615848643 1557pio_latency=100000 1558pio_size=8 1559ret_bad_addr=false 1560ret_data16=65535 1561ret_data32=4294967295 1562ret_data64=18446744073709551615 1563ret_data8=255 1564system=system 1565update_data=false 1566warn_access= 1567pio=system.iobus.master[14] 1568 1569[system.tsunami.fake_pnp_read4] 1570type=IsaFake 1571clk_domain=system.clk_domain |
| 1572eventq_index=0 |
| 1573fake_mem=false 1574pio_addr=8804615848707 1575pio_latency=100000 1576pio_size=8 1577ret_bad_addr=false 1578ret_data16=65535 1579ret_data32=4294967295 1580ret_data64=18446744073709551615 1581ret_data8=255 1582system=system 1583update_data=false 1584warn_access= 1585pio=system.iobus.master[15] 1586 1587[system.tsunami.fake_pnp_read5] 1588type=IsaFake 1589clk_domain=system.clk_domain |
| 1590eventq_index=0 |
| 1591fake_mem=false 1592pio_addr=8804615848771 1593pio_latency=100000 1594pio_size=8 1595ret_bad_addr=false 1596ret_data16=65535 1597ret_data32=4294967295 1598ret_data64=18446744073709551615 1599ret_data8=255 1600system=system 1601update_data=false 1602warn_access= 1603pio=system.iobus.master[16] 1604 1605[system.tsunami.fake_pnp_read6] 1606type=IsaFake 1607clk_domain=system.clk_domain |
| 1608eventq_index=0 |
| 1609fake_mem=false 1610pio_addr=8804615848835 1611pio_latency=100000 1612pio_size=8 1613ret_bad_addr=false 1614ret_data16=65535 1615ret_data32=4294967295 1616ret_data64=18446744073709551615 1617ret_data8=255 1618system=system 1619update_data=false 1620warn_access= 1621pio=system.iobus.master[17] 1622 1623[system.tsunami.fake_pnp_read7] 1624type=IsaFake 1625clk_domain=system.clk_domain |
| 1626eventq_index=0 |
| 1627fake_mem=false 1628pio_addr=8804615848899 1629pio_latency=100000 1630pio_size=8 1631ret_bad_addr=false 1632ret_data16=65535 1633ret_data32=4294967295 1634ret_data64=18446744073709551615 1635ret_data8=255 1636system=system 1637update_data=false 1638warn_access= 1639pio=system.iobus.master[18] 1640 1641[system.tsunami.fake_pnp_write] 1642type=IsaFake 1643clk_domain=system.clk_domain |
| 1644eventq_index=0 |
| 1645fake_mem=false 1646pio_addr=8804615850617 1647pio_latency=100000 1648pio_size=8 1649ret_bad_addr=false 1650ret_data16=65535 1651ret_data32=4294967295 1652ret_data64=18446744073709551615 1653ret_data8=255 1654system=system 1655update_data=false 1656warn_access= 1657pio=system.iobus.master[10] 1658 1659[system.tsunami.fake_ppc] 1660type=IsaFake 1661clk_domain=system.clk_domain |
| 1662eventq_index=0 |
| 1663fake_mem=false 1664pio_addr=8804615848891 1665pio_latency=100000 1666pio_size=8 1667ret_bad_addr=false 1668ret_data16=65535 1669ret_data32=4294967295 1670ret_data64=18446744073709551615 1671ret_data8=255 1672system=system 1673update_data=false 1674warn_access= 1675pio=system.iobus.master[7] 1676 1677[system.tsunami.fake_sm_chip] 1678type=IsaFake 1679clk_domain=system.clk_domain |
| 1680eventq_index=0 |
| 1681fake_mem=false 1682pio_addr=8804615848816 1683pio_latency=100000 1684pio_size=8 1685ret_bad_addr=false 1686ret_data16=65535 1687ret_data32=4294967295 1688ret_data64=18446744073709551615 1689ret_data8=255 1690system=system 1691update_data=false 1692warn_access= 1693pio=system.iobus.master[2] 1694 1695[system.tsunami.fake_uart1] 1696type=IsaFake 1697clk_domain=system.clk_domain |
| 1698eventq_index=0 |
| 1699fake_mem=false 1700pio_addr=8804615848696 1701pio_latency=100000 1702pio_size=8 1703ret_bad_addr=false 1704ret_data16=65535 1705ret_data32=4294967295 1706ret_data64=18446744073709551615 1707ret_data8=255 1708system=system 1709update_data=false 1710warn_access= 1711pio=system.iobus.master[3] 1712 1713[system.tsunami.fake_uart2] 1714type=IsaFake 1715clk_domain=system.clk_domain |
| 1716eventq_index=0 |
| 1717fake_mem=false 1718pio_addr=8804615848936 1719pio_latency=100000 1720pio_size=8 1721ret_bad_addr=false 1722ret_data16=65535 1723ret_data32=4294967295 1724ret_data64=18446744073709551615 1725ret_data8=255 1726system=system 1727update_data=false 1728warn_access= 1729pio=system.iobus.master[4] 1730 1731[system.tsunami.fake_uart3] 1732type=IsaFake 1733clk_domain=system.clk_domain |
| 1734eventq_index=0 |
| 1735fake_mem=false 1736pio_addr=8804615848680 1737pio_latency=100000 1738pio_size=8 1739ret_bad_addr=false 1740ret_data16=65535 1741ret_data32=4294967295 1742ret_data64=18446744073709551615 1743ret_data8=255 1744system=system 1745update_data=false 1746warn_access= 1747pio=system.iobus.master[5] 1748 1749[system.tsunami.fake_uart4] 1750type=IsaFake 1751clk_domain=system.clk_domain |
| 1752eventq_index=0 |
| 1753fake_mem=false 1754pio_addr=8804615848944 1755pio_latency=100000 1756pio_size=8 1757ret_bad_addr=false 1758ret_data16=65535 1759ret_data32=4294967295 1760ret_data64=18446744073709551615 1761ret_data8=255 1762system=system 1763update_data=false 1764warn_access= 1765pio=system.iobus.master[6] 1766 1767[system.tsunami.fb] 1768type=BadDevice 1769clk_domain=system.clk_domain 1770devicename=FrameBuffer |
| 1771eventq_index=0 |
| 1772pio_addr=8804615848912 1773pio_latency=100000 1774system=system 1775pio=system.iobus.master[21] 1776 1777[system.tsunami.ide] 1778type=IdeController 1779BAR0=1 --- 11 unchanged lines hidden (view full) --- 1791BAR4=1 1792BAR4LegacyIO=false 1793BAR4Size=16 1794BAR5=1 1795BAR5LegacyIO=false 1796BAR5Size=0 1797BIST=0 1798CacheLineSize=0 |
| 1799CapabilityPtr=0 |
| 1800CardbusCIS=0 1801ClassCode=1 1802Command=0 1803DeviceID=28945 1804ExpansionROM=0 1805HeaderType=0 1806InterruptLine=31 1807InterruptPin=1 1808LatencyTimer=0 |
| 1809MSICAPBaseOffset=0 1810MSICAPCapId=0 1811MSICAPMaskBits=0 1812MSICAPMsgAddr=0 1813MSICAPMsgCtrl=0 1814MSICAPMsgData=0 1815MSICAPMsgUpperAddr=0 1816MSICAPNextCapability=0 1817MSICAPPendingBits=0 1818MSIXCAPBaseOffset=0 1819MSIXCAPCapId=0 1820MSIXCAPNextCapability=0 1821MSIXMsgCtrl=0 1822MSIXPbaOffset=0 1823MSIXTableOffset=0 |
| 1824MaximumLatency=0 1825MinimumGrant=0 |
| 1826PMCAPBaseOffset=0 1827PMCAPCapId=0 1828PMCAPCapabilities=0 1829PMCAPCtrlStatus=0 1830PMCAPNextCapability=0 1831PXCAPBaseOffset=0 1832PXCAPCapId=0 1833PXCAPCapabilities=0 1834PXCAPDevCap2=0 1835PXCAPDevCapabilities=0 1836PXCAPDevCtrl=0 1837PXCAPDevCtrl2=0 1838PXCAPDevStatus=0 1839PXCAPLinkCap=0 1840PXCAPLinkCtrl=0 1841PXCAPLinkStatus=0 1842PXCAPNextCapability=0 |
| 1843ProgIF=133 1844Revision=0 1845Status=640 1846SubClassCode=1 1847SubsystemID=0 1848SubsystemVendorID=0 1849VendorID=32902 1850clk_domain=system.clk_domain 1851config_latency=20000 1852ctrl_offset=0 1853disks=system.disk0 system.disk2 |
| 1854eventq_index=0 |
| 1855io_shift=0 1856pci_bus=0 1857pci_dev=0 1858pci_func=0 1859pio_latency=30000 1860platform=system.tsunami 1861system=system 1862config=system.iobus.master[26] 1863dma=system.iobus.slave[1] 1864pio=system.iobus.master[25] 1865 1866[system.tsunami.io] 1867type=TsunamiIO 1868clk_domain=system.clk_domain |
| 1869eventq_index=0 |
| 1870frequency=976562500 1871pio_addr=8804615847936 1872pio_latency=100000 1873system=system 1874time=Thu Jan 1 00:00:00 2009 1875tsunami=system.tsunami 1876year_is_bcd=false 1877pio=system.iobus.master[22] 1878 1879[system.tsunami.pchip] 1880type=TsunamiPChip 1881clk_domain=system.clk_domain |
| 1882eventq_index=0 |
| 1883pio_addr=8802535473152 1884pio_latency=100000 1885system=system 1886tsunami=system.tsunami 1887pio=system.iobus.master[1] 1888 1889[system.tsunami.pciconfig] 1890type=PciConfigAll 1891bus=0 1892clk_domain=system.clk_domain |
| 1893eventq_index=0 |
| 1894pio_addr=0 1895pio_latency=30000 1896platform=system.tsunami 1897size=16777216 1898system=system 1899pio=system.iobus.default 1900 1901[system.tsunami.uart] 1902type=Uart8250 1903clk_domain=system.clk_domain |
| 1904eventq_index=0 |
| 1905pio_addr=8804615848952 1906pio_latency=100000 1907platform=system.tsunami 1908system=system 1909terminal=system.terminal 1910pio=system.iobus.master[23] 1911 1912[system.voltage_domain] 1913type=VoltageDomain |
| 1914eventq_index=0 |
| 1915voltage=1.000000 1916 |