1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14clock=1000
|
15console=/projects/pd/randd/dist/binaries/console
| 15console=/gem5/dist/binaries/console
|
16init_param=0
| 16init_param=0
|
17kernel=/projects/pd/randd/dist/binaries/vmlinux
| 17kernel=/gem5/dist/binaries/vmlinux
|
18load_addr_mask=1099511627775 19mem_mode=timing
| 18load_addr_mask=1099511627775 19mem_mode=timing
|
| 20mem_ranges=0:134217727
|
20memories=system.physmem 21num_work_ids=16
| 21memories=system.physmem 22num_work_ids=16
|
22pal=/projects/pd/randd/dist/binaries/ts_osfpal
| 23pal=/gem5/dist/binaries/ts_osfpal
|
23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge 38clock=1000 39delay=50000 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu0] 47type=DerivO3CPU 48children=dcache dtb fuPool icache interrupts isa itb tracer 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8
| 24readfile=tests/halt.sh 25symbolfile= 26system_rev=1024 27system_type=34 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.bridge] 38type=Bridge 39clock=1000 40delay=50000 41ranges=8796093022208:18446744073709551615 42req_size=16 43resp_size=16 44master=system.iobus.slave[0] 45slave=system.membus.master[0] 46 47[system.cpu0] 48type=DerivO3CPU 49children=dcache dtb fuPool icache interrupts isa itb tracer 50BTBEntries=4096 51BTBTagSize=16 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56RASSize=16 57SQEntries=32 58SSITSize=1024 59activity=0 60backComSize=5 61cachePorts=200 62checker=Null 63choiceCtrBits=2 64choicePredictorSize=8192 65clock=500 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8
|
74defer_registration=false
| |
75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu0.interrupts 96isa=system.cpu0.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu0.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000
| 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu0.interrupts 96isa=system.cpu0.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu0.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000
|
| 134switched_out=false
|
134system=system 135tracer=system.cpu0.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu0.dcache.cpu_side 141icache_port=system.cpu0.icache.cpu_side 142 143[system.cpu0.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64 148clock=500 149forward_snoops=true
| 135system=system 136tracer=system.cpu0.tracer 137trapLatency=13 138wbDepth=1 139wbWidth=8 140workload= 141dcache_port=system.cpu0.dcache.cpu_side 142icache_port=system.cpu0.icache.cpu_side 143 144[system.cpu0.dcache] 145type=BaseCache 146addr_ranges=0:18446744073709551615 147assoc=4 148block_size=64 149clock=500 150forward_snoops=true
|
150hash_delay=1
| |
151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null
| 151hit_latency=2 152is_top_level=true 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null
|
157prioritizeRequests=false 158repl=Null
| |
159response_latency=2 160size=32768
| 157response_latency=2 158size=32768
|
161subblock_size=0
| |
162system=system 163tgts_per_mshr=20
| 159system=system 160tgts_per_mshr=20
|
164trace_addr=0
| |
165two_queue=false 166write_buffers=8 167cpu_side=system.cpu0.dcache_port 168mem_side=system.toL2Bus.slave[1] 169 170[system.cpu0.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu0.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 178 179[system.cpu0.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu0.fuPool.FUList0.opList 184 185[system.cpu0.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu0.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 196 197[system.cpu0.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu0.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu0.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 214 215[system.cpu0.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu0.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu0.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu0.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 238 239[system.cpu0.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu0.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu0.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu0.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu0.fuPool.FUList4.opList 262 263[system.cpu0.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu0.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 274 275[system.cpu0.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu0.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu0.fuPool.FUList6.opList 400 401[system.cpu0.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu0.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 412 413[system.cpu0.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu0.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu0.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu0.fuPool.FUList8.opList 430 431[system.cpu0.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu0.icache] 438type=BaseCache 439addr_ranges=0:18446744073709551615 440assoc=1 441block_size=64 442clock=500 443forward_snoops=true
| 161two_queue=false 162write_buffers=8 163cpu_side=system.cpu0.dcache_port 164mem_side=system.toL2Bus.slave[1] 165 166[system.cpu0.dtb] 167type=AlphaTLB 168size=64 169 170[system.cpu0.fuPool] 171type=FUPool 172children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 173FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 174 175[system.cpu0.fuPool.FUList0] 176type=FUDesc 177children=opList 178count=6 179opList=system.cpu0.fuPool.FUList0.opList 180 181[system.cpu0.fuPool.FUList0.opList] 182type=OpDesc 183issueLat=1 184opClass=IntAlu 185opLat=1 186 187[system.cpu0.fuPool.FUList1] 188type=FUDesc 189children=opList0 opList1 190count=2 191opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 192 193[system.cpu0.fuPool.FUList1.opList0] 194type=OpDesc 195issueLat=1 196opClass=IntMult 197opLat=3 198 199[system.cpu0.fuPool.FUList1.opList1] 200type=OpDesc 201issueLat=19 202opClass=IntDiv 203opLat=20 204 205[system.cpu0.fuPool.FUList2] 206type=FUDesc 207children=opList0 opList1 opList2 208count=4 209opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 210 211[system.cpu0.fuPool.FUList2.opList0] 212type=OpDesc 213issueLat=1 214opClass=FloatAdd 215opLat=2 216 217[system.cpu0.fuPool.FUList2.opList1] 218type=OpDesc 219issueLat=1 220opClass=FloatCmp 221opLat=2 222 223[system.cpu0.fuPool.FUList2.opList2] 224type=OpDesc 225issueLat=1 226opClass=FloatCvt 227opLat=2 228 229[system.cpu0.fuPool.FUList3] 230type=FUDesc 231children=opList0 opList1 opList2 232count=2 233opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 234 235[system.cpu0.fuPool.FUList3.opList0] 236type=OpDesc 237issueLat=1 238opClass=FloatMult 239opLat=4 240 241[system.cpu0.fuPool.FUList3.opList1] 242type=OpDesc 243issueLat=12 244opClass=FloatDiv 245opLat=12 246 247[system.cpu0.fuPool.FUList3.opList2] 248type=OpDesc 249issueLat=24 250opClass=FloatSqrt 251opLat=24 252 253[system.cpu0.fuPool.FUList4] 254type=FUDesc 255children=opList 256count=0 257opList=system.cpu0.fuPool.FUList4.opList 258 259[system.cpu0.fuPool.FUList4.opList] 260type=OpDesc 261issueLat=1 262opClass=MemRead 263opLat=1 264 265[system.cpu0.fuPool.FUList5] 266type=FUDesc 267children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 268count=4 269opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 270 271[system.cpu0.fuPool.FUList5.opList00] 272type=OpDesc 273issueLat=1 274opClass=SimdAdd 275opLat=1 276 277[system.cpu0.fuPool.FUList5.opList01] 278type=OpDesc 279issueLat=1 280opClass=SimdAddAcc 281opLat=1 282 283[system.cpu0.fuPool.FUList5.opList02] 284type=OpDesc 285issueLat=1 286opClass=SimdAlu 287opLat=1 288 289[system.cpu0.fuPool.FUList5.opList03] 290type=OpDesc 291issueLat=1 292opClass=SimdCmp 293opLat=1 294 295[system.cpu0.fuPool.FUList5.opList04] 296type=OpDesc 297issueLat=1 298opClass=SimdCvt 299opLat=1 300 301[system.cpu0.fuPool.FUList5.opList05] 302type=OpDesc 303issueLat=1 304opClass=SimdMisc 305opLat=1 306 307[system.cpu0.fuPool.FUList5.opList06] 308type=OpDesc 309issueLat=1 310opClass=SimdMult 311opLat=1 312 313[system.cpu0.fuPool.FUList5.opList07] 314type=OpDesc 315issueLat=1 316opClass=SimdMultAcc 317opLat=1 318 319[system.cpu0.fuPool.FUList5.opList08] 320type=OpDesc 321issueLat=1 322opClass=SimdShift 323opLat=1 324 325[system.cpu0.fuPool.FUList5.opList09] 326type=OpDesc 327issueLat=1 328opClass=SimdShiftAcc 329opLat=1 330 331[system.cpu0.fuPool.FUList5.opList10] 332type=OpDesc 333issueLat=1 334opClass=SimdSqrt 335opLat=1 336 337[system.cpu0.fuPool.FUList5.opList11] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatAdd 341opLat=1 342 343[system.cpu0.fuPool.FUList5.opList12] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatAlu 347opLat=1 348 349[system.cpu0.fuPool.FUList5.opList13] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatCmp 353opLat=1 354 355[system.cpu0.fuPool.FUList5.opList14] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatCvt 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList15] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatDiv 365opLat=1 366 367[system.cpu0.fuPool.FUList5.opList16] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMisc 371opLat=1 372 373[system.cpu0.fuPool.FUList5.opList17] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatMult 377opLat=1 378 379[system.cpu0.fuPool.FUList5.opList18] 380type=OpDesc 381issueLat=1 382opClass=SimdFloatMultAcc 383opLat=1 384 385[system.cpu0.fuPool.FUList5.opList19] 386type=OpDesc 387issueLat=1 388opClass=SimdFloatSqrt 389opLat=1 390 391[system.cpu0.fuPool.FUList6] 392type=FUDesc 393children=opList 394count=0 395opList=system.cpu0.fuPool.FUList6.opList 396 397[system.cpu0.fuPool.FUList6.opList] 398type=OpDesc 399issueLat=1 400opClass=MemWrite 401opLat=1 402 403[system.cpu0.fuPool.FUList7] 404type=FUDesc 405children=opList0 opList1 406count=4 407opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 408 409[system.cpu0.fuPool.FUList7.opList0] 410type=OpDesc 411issueLat=1 412opClass=MemRead 413opLat=1 414 415[system.cpu0.fuPool.FUList7.opList1] 416type=OpDesc 417issueLat=1 418opClass=MemWrite 419opLat=1 420 421[system.cpu0.fuPool.FUList8] 422type=FUDesc 423children=opList 424count=1 425opList=system.cpu0.fuPool.FUList8.opList 426 427[system.cpu0.fuPool.FUList8.opList] 428type=OpDesc 429issueLat=3 430opClass=IprAccess 431opLat=3 432 433[system.cpu0.icache] 434type=BaseCache 435addr_ranges=0:18446744073709551615 436assoc=1 437block_size=64 438clock=500 439forward_snoops=true
|
444hash_delay=1
| |
445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null
| 440hit_latency=2 441is_top_level=true 442max_miss_count=0 443mshrs=4 444prefetch_on_access=false 445prefetcher=Null
|
451prioritizeRequests=false 452repl=Null
| |
453response_latency=2 454size=32768
| 446response_latency=2 447size=32768
|
455subblock_size=0
| |
456system=system 457tgts_per_mshr=20
| 448system=system 449tgts_per_mshr=20
|
458trace_addr=0
| |
459two_queue=false 460write_buffers=8 461cpu_side=system.cpu0.icache_port 462mem_side=system.toL2Bus.slave[0] 463 464[system.cpu0.interrupts] 465type=AlphaInterrupts 466 467[system.cpu0.isa] 468type=AlphaISA 469 470[system.cpu0.itb] 471type=AlphaTLB 472size=48 473 474[system.cpu0.tracer] 475type=ExeTracer 476 477[system.cpu1] 478type=DerivO3CPU 479children=dcache dtb fuPool icache interrupts isa itb tracer 480BTBEntries=4096 481BTBTagSize=16 482LFSTSize=1024 483LQEntries=32 484LSQCheckLoads=true 485LSQDepCheckShift=4 486RASSize=16 487SQEntries=32 488SSITSize=1024 489activity=0 490backComSize=5 491cachePorts=200 492checker=Null 493choiceCtrBits=2 494choicePredictorSize=8192 495clock=500 496commitToDecodeDelay=1 497commitToFetchDelay=1 498commitToIEWDelay=1 499commitToRenameDelay=1 500commitWidth=8 501cpu_id=1 502decodeToFetchDelay=1 503decodeToRenameDelay=1 504decodeWidth=8
| 450two_queue=false 451write_buffers=8 452cpu_side=system.cpu0.icache_port 453mem_side=system.toL2Bus.slave[0] 454 455[system.cpu0.interrupts] 456type=AlphaInterrupts 457 458[system.cpu0.isa] 459type=AlphaISA 460 461[system.cpu0.itb] 462type=AlphaTLB 463size=48 464 465[system.cpu0.tracer] 466type=ExeTracer 467 468[system.cpu1] 469type=DerivO3CPU 470children=dcache dtb fuPool icache interrupts isa itb tracer 471BTBEntries=4096 472BTBTagSize=16 473LFSTSize=1024 474LQEntries=32 475LSQCheckLoads=true 476LSQDepCheckShift=4 477RASSize=16 478SQEntries=32 479SSITSize=1024 480activity=0 481backComSize=5 482cachePorts=200 483checker=Null 484choiceCtrBits=2 485choicePredictorSize=8192 486clock=500 487commitToDecodeDelay=1 488commitToFetchDelay=1 489commitToIEWDelay=1 490commitToRenameDelay=1 491commitWidth=8 492cpu_id=1 493decodeToFetchDelay=1 494decodeToRenameDelay=1 495decodeWidth=8
|
505defer_registration=false
| |
506dispatchWidth=8 507do_checkpoint_insts=true 508do_quiesce=true 509do_statistics_insts=true 510dtb=system.cpu1.dtb 511fetchToDecodeDelay=1 512fetchTrapLatency=1 513fetchWidth=8 514forwardComSize=5 515fuPool=system.cpu1.fuPool 516function_trace=false 517function_trace_start=0 518globalCtrBits=2 519globalHistoryBits=13 520globalPredictorSize=8192 521iewToCommitDelay=1 522iewToDecodeDelay=1 523iewToFetchDelay=1 524iewToRenameDelay=1 525instShiftAmt=2 526interrupts=system.cpu1.interrupts 527isa=system.cpu1.isa 528issueToExecuteDelay=1 529issueWidth=8 530itb=system.cpu1.itb 531localCtrBits=2 532localHistoryBits=11 533localHistoryTableSize=2048 534localPredictorSize=2048 535max_insts_all_threads=0 536max_insts_any_thread=0 537max_loads_all_threads=0 538max_loads_any_thread=0 539needsTSO=false 540numIQEntries=64 541numPhysFloatRegs=256 542numPhysIntRegs=256 543numROBEntries=192 544numRobs=1 545numThreads=1 546predType=tournament 547profile=0 548progress_interval=0 549renameToDecodeDelay=1 550renameToFetchDelay=1 551renameToIEWDelay=2 552renameToROBDelay=1 553renameWidth=8 554smtCommitPolicy=RoundRobin 555smtFetchPolicy=SingleThread 556smtIQPolicy=Partitioned 557smtIQThreshold=100 558smtLSQPolicy=Partitioned 559smtLSQThreshold=100 560smtNumFetchingThreads=1 561smtROBPolicy=Partitioned 562smtROBThreshold=100 563squashWidth=8 564store_set_clear_period=250000
| 496dispatchWidth=8 497do_checkpoint_insts=true 498do_quiesce=true 499do_statistics_insts=true 500dtb=system.cpu1.dtb 501fetchToDecodeDelay=1 502fetchTrapLatency=1 503fetchWidth=8 504forwardComSize=5 505fuPool=system.cpu1.fuPool 506function_trace=false 507function_trace_start=0 508globalCtrBits=2 509globalHistoryBits=13 510globalPredictorSize=8192 511iewToCommitDelay=1 512iewToDecodeDelay=1 513iewToFetchDelay=1 514iewToRenameDelay=1 515instShiftAmt=2 516interrupts=system.cpu1.interrupts 517isa=system.cpu1.isa 518issueToExecuteDelay=1 519issueWidth=8 520itb=system.cpu1.itb 521localCtrBits=2 522localHistoryBits=11 523localHistoryTableSize=2048 524localPredictorSize=2048 525max_insts_all_threads=0 526max_insts_any_thread=0 527max_loads_all_threads=0 528max_loads_any_thread=0 529needsTSO=false 530numIQEntries=64 531numPhysFloatRegs=256 532numPhysIntRegs=256 533numROBEntries=192 534numRobs=1 535numThreads=1 536predType=tournament 537profile=0 538progress_interval=0 539renameToDecodeDelay=1 540renameToFetchDelay=1 541renameToIEWDelay=2 542renameToROBDelay=1 543renameWidth=8 544smtCommitPolicy=RoundRobin 545smtFetchPolicy=SingleThread 546smtIQPolicy=Partitioned 547smtIQThreshold=100 548smtLSQPolicy=Partitioned 549smtLSQThreshold=100 550smtNumFetchingThreads=1 551smtROBPolicy=Partitioned 552smtROBThreshold=100 553squashWidth=8 554store_set_clear_period=250000
|
| 555switched_out=false
|
565system=system 566tracer=system.cpu1.tracer 567trapLatency=13 568wbDepth=1 569wbWidth=8 570workload= 571dcache_port=system.cpu1.dcache.cpu_side 572icache_port=system.cpu1.icache.cpu_side 573 574[system.cpu1.dcache] 575type=BaseCache 576addr_ranges=0:18446744073709551615 577assoc=4 578block_size=64 579clock=500 580forward_snoops=true
| 556system=system 557tracer=system.cpu1.tracer 558trapLatency=13 559wbDepth=1 560wbWidth=8 561workload= 562dcache_port=system.cpu1.dcache.cpu_side 563icache_port=system.cpu1.icache.cpu_side 564 565[system.cpu1.dcache] 566type=BaseCache 567addr_ranges=0:18446744073709551615 568assoc=4 569block_size=64 570clock=500 571forward_snoops=true
|
581hash_delay=1
| |
582hit_latency=2 583is_top_level=true 584max_miss_count=0 585mshrs=4 586prefetch_on_access=false 587prefetcher=Null
| 572hit_latency=2 573is_top_level=true 574max_miss_count=0 575mshrs=4 576prefetch_on_access=false 577prefetcher=Null
|
588prioritizeRequests=false 589repl=Null
| |
590response_latency=2 591size=32768
| 578response_latency=2 579size=32768
|
592subblock_size=0
| |
593system=system 594tgts_per_mshr=20
| 580system=system 581tgts_per_mshr=20
|
595trace_addr=0
| |
596two_queue=false 597write_buffers=8 598cpu_side=system.cpu1.dcache_port 599mem_side=system.toL2Bus.slave[3] 600 601[system.cpu1.dtb] 602type=AlphaTLB 603size=64 604 605[system.cpu1.fuPool] 606type=FUPool 607children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 608FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 609 610[system.cpu1.fuPool.FUList0] 611type=FUDesc 612children=opList 613count=6 614opList=system.cpu1.fuPool.FUList0.opList 615 616[system.cpu1.fuPool.FUList0.opList] 617type=OpDesc 618issueLat=1 619opClass=IntAlu 620opLat=1 621 622[system.cpu1.fuPool.FUList1] 623type=FUDesc 624children=opList0 opList1 625count=2 626opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 627 628[system.cpu1.fuPool.FUList1.opList0] 629type=OpDesc 630issueLat=1 631opClass=IntMult 632opLat=3 633 634[system.cpu1.fuPool.FUList1.opList1] 635type=OpDesc 636issueLat=19 637opClass=IntDiv 638opLat=20 639 640[system.cpu1.fuPool.FUList2] 641type=FUDesc 642children=opList0 opList1 opList2 643count=4 644opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 645 646[system.cpu1.fuPool.FUList2.opList0] 647type=OpDesc 648issueLat=1 649opClass=FloatAdd 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList1] 653type=OpDesc 654issueLat=1 655opClass=FloatCmp 656opLat=2 657 658[system.cpu1.fuPool.FUList2.opList2] 659type=OpDesc 660issueLat=1 661opClass=FloatCvt 662opLat=2 663 664[system.cpu1.fuPool.FUList3] 665type=FUDesc 666children=opList0 opList1 opList2 667count=2 668opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 669 670[system.cpu1.fuPool.FUList3.opList0] 671type=OpDesc 672issueLat=1 673opClass=FloatMult 674opLat=4 675 676[system.cpu1.fuPool.FUList3.opList1] 677type=OpDesc 678issueLat=12 679opClass=FloatDiv 680opLat=12 681 682[system.cpu1.fuPool.FUList3.opList2] 683type=OpDesc 684issueLat=24 685opClass=FloatSqrt 686opLat=24 687 688[system.cpu1.fuPool.FUList4] 689type=FUDesc 690children=opList 691count=0 692opList=system.cpu1.fuPool.FUList4.opList 693 694[system.cpu1.fuPool.FUList4.opList] 695type=OpDesc 696issueLat=1 697opClass=MemRead 698opLat=1 699 700[system.cpu1.fuPool.FUList5] 701type=FUDesc 702children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 703count=4 704opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 705 706[system.cpu1.fuPool.FUList5.opList00] 707type=OpDesc 708issueLat=1 709opClass=SimdAdd 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList01] 713type=OpDesc 714issueLat=1 715opClass=SimdAddAcc 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList02] 719type=OpDesc 720issueLat=1 721opClass=SimdAlu 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList03] 725type=OpDesc 726issueLat=1 727opClass=SimdCmp 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList04] 731type=OpDesc 732issueLat=1 733opClass=SimdCvt 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList05] 737type=OpDesc 738issueLat=1 739opClass=SimdMisc 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList06] 743type=OpDesc 744issueLat=1 745opClass=SimdMult 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList07] 749type=OpDesc 750issueLat=1 751opClass=SimdMultAcc 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList08] 755type=OpDesc 756issueLat=1 757opClass=SimdShift 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList09] 761type=OpDesc 762issueLat=1 763opClass=SimdShiftAcc 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList10] 767type=OpDesc 768issueLat=1 769opClass=SimdSqrt 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList11] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAdd 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList12] 779type=OpDesc 780issueLat=1 781opClass=SimdFloatAlu 782opLat=1 783 784[system.cpu1.fuPool.FUList5.opList13] 785type=OpDesc 786issueLat=1 787opClass=SimdFloatCmp 788opLat=1 789 790[system.cpu1.fuPool.FUList5.opList14] 791type=OpDesc 792issueLat=1 793opClass=SimdFloatCvt 794opLat=1 795 796[system.cpu1.fuPool.FUList5.opList15] 797type=OpDesc 798issueLat=1 799opClass=SimdFloatDiv 800opLat=1 801 802[system.cpu1.fuPool.FUList5.opList16] 803type=OpDesc 804issueLat=1 805opClass=SimdFloatMisc 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList17] 809type=OpDesc 810issueLat=1 811opClass=SimdFloatMult 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList18] 815type=OpDesc 816issueLat=1 817opClass=SimdFloatMultAcc 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList19] 821type=OpDesc 822issueLat=1 823opClass=SimdFloatSqrt 824opLat=1 825 826[system.cpu1.fuPool.FUList6] 827type=FUDesc 828children=opList 829count=0 830opList=system.cpu1.fuPool.FUList6.opList 831 832[system.cpu1.fuPool.FUList6.opList] 833type=OpDesc 834issueLat=1 835opClass=MemWrite 836opLat=1 837 838[system.cpu1.fuPool.FUList7] 839type=FUDesc 840children=opList0 opList1 841count=4 842opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 843 844[system.cpu1.fuPool.FUList7.opList0] 845type=OpDesc 846issueLat=1 847opClass=MemRead 848opLat=1 849 850[system.cpu1.fuPool.FUList7.opList1] 851type=OpDesc 852issueLat=1 853opClass=MemWrite 854opLat=1 855 856[system.cpu1.fuPool.FUList8] 857type=FUDesc 858children=opList 859count=1 860opList=system.cpu1.fuPool.FUList8.opList 861 862[system.cpu1.fuPool.FUList8.opList] 863type=OpDesc 864issueLat=3 865opClass=IprAccess 866opLat=3 867 868[system.cpu1.icache] 869type=BaseCache 870addr_ranges=0:18446744073709551615 871assoc=1 872block_size=64 873clock=500 874forward_snoops=true
| 582two_queue=false 583write_buffers=8 584cpu_side=system.cpu1.dcache_port 585mem_side=system.toL2Bus.slave[3] 586 587[system.cpu1.dtb] 588type=AlphaTLB 589size=64 590 591[system.cpu1.fuPool] 592type=FUPool 593children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 594FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 595 596[system.cpu1.fuPool.FUList0] 597type=FUDesc 598children=opList 599count=6 600opList=system.cpu1.fuPool.FUList0.opList 601 602[system.cpu1.fuPool.FUList0.opList] 603type=OpDesc 604issueLat=1 605opClass=IntAlu 606opLat=1 607 608[system.cpu1.fuPool.FUList1] 609type=FUDesc 610children=opList0 opList1 611count=2 612opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 613 614[system.cpu1.fuPool.FUList1.opList0] 615type=OpDesc 616issueLat=1 617opClass=IntMult 618opLat=3 619 620[system.cpu1.fuPool.FUList1.opList1] 621type=OpDesc 622issueLat=19 623opClass=IntDiv 624opLat=20 625 626[system.cpu1.fuPool.FUList2] 627type=FUDesc 628children=opList0 opList1 opList2 629count=4 630opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 631 632[system.cpu1.fuPool.FUList2.opList0] 633type=OpDesc 634issueLat=1 635opClass=FloatAdd 636opLat=2 637 638[system.cpu1.fuPool.FUList2.opList1] 639type=OpDesc 640issueLat=1 641opClass=FloatCmp 642opLat=2 643 644[system.cpu1.fuPool.FUList2.opList2] 645type=OpDesc 646issueLat=1 647opClass=FloatCvt 648opLat=2 649 650[system.cpu1.fuPool.FUList3] 651type=FUDesc 652children=opList0 opList1 opList2 653count=2 654opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 655 656[system.cpu1.fuPool.FUList3.opList0] 657type=OpDesc 658issueLat=1 659opClass=FloatMult 660opLat=4 661 662[system.cpu1.fuPool.FUList3.opList1] 663type=OpDesc 664issueLat=12 665opClass=FloatDiv 666opLat=12 667 668[system.cpu1.fuPool.FUList3.opList2] 669type=OpDesc 670issueLat=24 671opClass=FloatSqrt 672opLat=24 673 674[system.cpu1.fuPool.FUList4] 675type=FUDesc 676children=opList 677count=0 678opList=system.cpu1.fuPool.FUList4.opList 679 680[system.cpu1.fuPool.FUList4.opList] 681type=OpDesc 682issueLat=1 683opClass=MemRead 684opLat=1 685 686[system.cpu1.fuPool.FUList5] 687type=FUDesc 688children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 689count=4 690opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 691 692[system.cpu1.fuPool.FUList5.opList00] 693type=OpDesc 694issueLat=1 695opClass=SimdAdd 696opLat=1 697 698[system.cpu1.fuPool.FUList5.opList01] 699type=OpDesc 700issueLat=1 701opClass=SimdAddAcc 702opLat=1 703 704[system.cpu1.fuPool.FUList5.opList02] 705type=OpDesc 706issueLat=1 707opClass=SimdAlu 708opLat=1 709 710[system.cpu1.fuPool.FUList5.opList03] 711type=OpDesc 712issueLat=1 713opClass=SimdCmp 714opLat=1 715 716[system.cpu1.fuPool.FUList5.opList04] 717type=OpDesc 718issueLat=1 719opClass=SimdCvt 720opLat=1 721 722[system.cpu1.fuPool.FUList5.opList05] 723type=OpDesc 724issueLat=1 725opClass=SimdMisc 726opLat=1 727 728[system.cpu1.fuPool.FUList5.opList06] 729type=OpDesc 730issueLat=1 731opClass=SimdMult 732opLat=1 733 734[system.cpu1.fuPool.FUList5.opList07] 735type=OpDesc 736issueLat=1 737opClass=SimdMultAcc 738opLat=1 739 740[system.cpu1.fuPool.FUList5.opList08] 741type=OpDesc 742issueLat=1 743opClass=SimdShift 744opLat=1 745 746[system.cpu1.fuPool.FUList5.opList09] 747type=OpDesc 748issueLat=1 749opClass=SimdShiftAcc 750opLat=1 751 752[system.cpu1.fuPool.FUList5.opList10] 753type=OpDesc 754issueLat=1 755opClass=SimdSqrt 756opLat=1 757 758[system.cpu1.fuPool.FUList5.opList11] 759type=OpDesc 760issueLat=1 761opClass=SimdFloatAdd 762opLat=1 763 764[system.cpu1.fuPool.FUList5.opList12] 765type=OpDesc 766issueLat=1 767opClass=SimdFloatAlu 768opLat=1 769 770[system.cpu1.fuPool.FUList5.opList13] 771type=OpDesc 772issueLat=1 773opClass=SimdFloatCmp 774opLat=1 775 776[system.cpu1.fuPool.FUList5.opList14] 777type=OpDesc 778issueLat=1 779opClass=SimdFloatCvt 780opLat=1 781 782[system.cpu1.fuPool.FUList5.opList15] 783type=OpDesc 784issueLat=1 785opClass=SimdFloatDiv 786opLat=1 787 788[system.cpu1.fuPool.FUList5.opList16] 789type=OpDesc 790issueLat=1 791opClass=SimdFloatMisc 792opLat=1 793 794[system.cpu1.fuPool.FUList5.opList17] 795type=OpDesc 796issueLat=1 797opClass=SimdFloatMult 798opLat=1 799 800[system.cpu1.fuPool.FUList5.opList18] 801type=OpDesc 802issueLat=1 803opClass=SimdFloatMultAcc 804opLat=1 805 806[system.cpu1.fuPool.FUList5.opList19] 807type=OpDesc 808issueLat=1 809opClass=SimdFloatSqrt 810opLat=1 811 812[system.cpu1.fuPool.FUList6] 813type=FUDesc 814children=opList 815count=0 816opList=system.cpu1.fuPool.FUList6.opList 817 818[system.cpu1.fuPool.FUList6.opList] 819type=OpDesc 820issueLat=1 821opClass=MemWrite 822opLat=1 823 824[system.cpu1.fuPool.FUList7] 825type=FUDesc 826children=opList0 opList1 827count=4 828opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 829 830[system.cpu1.fuPool.FUList7.opList0] 831type=OpDesc 832issueLat=1 833opClass=MemRead 834opLat=1 835 836[system.cpu1.fuPool.FUList7.opList1] 837type=OpDesc 838issueLat=1 839opClass=MemWrite 840opLat=1 841 842[system.cpu1.fuPool.FUList8] 843type=FUDesc 844children=opList 845count=1 846opList=system.cpu1.fuPool.FUList8.opList 847 848[system.cpu1.fuPool.FUList8.opList] 849type=OpDesc 850issueLat=3 851opClass=IprAccess 852opLat=3 853 854[system.cpu1.icache] 855type=BaseCache 856addr_ranges=0:18446744073709551615 857assoc=1 858block_size=64 859clock=500 860forward_snoops=true
|
875hash_delay=1
| |
876hit_latency=2 877is_top_level=true 878max_miss_count=0 879mshrs=4 880prefetch_on_access=false 881prefetcher=Null
| 861hit_latency=2 862is_top_level=true 863max_miss_count=0 864mshrs=4 865prefetch_on_access=false 866prefetcher=Null
|
882prioritizeRequests=false 883repl=Null
| |
884response_latency=2 885size=32768
| 867response_latency=2 868size=32768
|
886subblock_size=0
| |
887system=system 888tgts_per_mshr=20
| 869system=system 870tgts_per_mshr=20
|
889trace_addr=0
| |
890two_queue=false 891write_buffers=8 892cpu_side=system.cpu1.icache_port 893mem_side=system.toL2Bus.slave[2] 894 895[system.cpu1.interrupts] 896type=AlphaInterrupts 897 898[system.cpu1.isa] 899type=AlphaISA 900 901[system.cpu1.itb] 902type=AlphaTLB 903size=48 904 905[system.cpu1.tracer] 906type=ExeTracer 907 908[system.disk0] 909type=IdeDisk 910children=image 911delay=1000000 912driveID=master 913image=system.disk0.image 914 915[system.disk0.image] 916type=CowDiskImage 917children=child 918child=system.disk0.image.child 919image_file= 920read_only=false 921table_size=65536 922 923[system.disk0.image.child] 924type=RawDiskImage
| 871two_queue=false 872write_buffers=8 873cpu_side=system.cpu1.icache_port 874mem_side=system.toL2Bus.slave[2] 875 876[system.cpu1.interrupts] 877type=AlphaInterrupts 878 879[system.cpu1.isa] 880type=AlphaISA 881 882[system.cpu1.itb] 883type=AlphaTLB 884size=48 885 886[system.cpu1.tracer] 887type=ExeTracer 888 889[system.disk0] 890type=IdeDisk 891children=image 892delay=1000000 893driveID=master 894image=system.disk0.image 895 896[system.disk0.image] 897type=CowDiskImage 898children=child 899child=system.disk0.image.child 900image_file= 901read_only=false 902table_size=65536 903 904[system.disk0.image.child] 905type=RawDiskImage
|
925image_file=/projects/pd/randd/dist/disks/linux-latest.img
| 906image_file=/gem5/dist/disks/linux-latest.img
|
926read_only=true 927 928[system.disk2] 929type=IdeDisk 930children=image 931delay=1000000 932driveID=master 933image=system.disk2.image 934 935[system.disk2.image] 936type=CowDiskImage 937children=child 938child=system.disk2.image.child 939image_file= 940read_only=false 941table_size=65536 942 943[system.disk2.image.child] 944type=RawDiskImage
| 907read_only=true 908 909[system.disk2] 910type=IdeDisk 911children=image 912delay=1000000 913driveID=master 914image=system.disk2.image 915 916[system.disk2.image] 917type=CowDiskImage 918children=child 919child=system.disk2.image.child 920image_file= 921read_only=false 922table_size=65536 923 924[system.disk2.image.child] 925type=RawDiskImage
|
945image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
| 926image_file=/gem5/dist/disks/linux-bigswap2.img
|
946read_only=true 947 948[system.intrctrl] 949type=IntrControl 950sys=system 951 952[system.iobus] 953type=NoncoherentBus 954block_size=64 955clock=1000 956header_cycles=1 957use_default_range=true 958width=8 959default=system.tsunami.pciconfig.pio 960master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 961slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 962 963[system.iocache] 964type=BaseCache
| 927read_only=true 928 929[system.intrctrl] 930type=IntrControl 931sys=system 932 933[system.iobus] 934type=NoncoherentBus 935block_size=64 936clock=1000 937header_cycles=1 938use_default_range=true 939width=8 940default=system.tsunami.pciconfig.pio 941master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 942slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 943 944[system.iocache] 945type=BaseCache
|
965addr_ranges=0:8589934591
| 946addr_ranges=0:134217727
|
966assoc=8 967block_size=64 968clock=1000 969forward_snoops=false
| 947assoc=8 948block_size=64 949clock=1000 950forward_snoops=false
|
970hash_delay=1
| |
971hit_latency=50 972is_top_level=true 973max_miss_count=0 974mshrs=20 975prefetch_on_access=false 976prefetcher=Null
| 951hit_latency=50 952is_top_level=true 953max_miss_count=0 954mshrs=20 955prefetch_on_access=false 956prefetcher=Null
|
977prioritizeRequests=false 978repl=Null
| |
979response_latency=50 980size=1024
| 957response_latency=50 958size=1024
|
981subblock_size=0
| |
982system=system 983tgts_per_mshr=12
| 959system=system 960tgts_per_mshr=12
|
984trace_addr=0
| |
985two_queue=false 986write_buffers=8 987cpu_side=system.iobus.master[29]
| 961two_queue=false 962write_buffers=8 963cpu_side=system.iobus.master[29]
|
988mem_side=system.membus.slave[1]
| 964mem_side=system.membus.slave[2]
|
989 990[system.l2c] 991type=BaseCache 992addr_ranges=0:18446744073709551615 993assoc=8 994block_size=64 995clock=500 996forward_snoops=true
| 965 966[system.l2c] 967type=BaseCache 968addr_ranges=0:18446744073709551615 969assoc=8 970block_size=64 971clock=500 972forward_snoops=true
|
997hash_delay=1
| |
998hit_latency=20 999is_top_level=false 1000max_miss_count=0 1001mshrs=20 1002prefetch_on_access=false 1003prefetcher=Null
| 973hit_latency=20 974is_top_level=false 975max_miss_count=0 976mshrs=20 977prefetch_on_access=false 978prefetcher=Null
|
1004prioritizeRequests=false 1005repl=Null
| |
1006response_latency=20 1007size=4194304
| 979response_latency=20 980size=4194304
|
1008subblock_size=0
| |
1009system=system 1010tgts_per_mshr=12
| 981system=system 982tgts_per_mshr=12
|
1011trace_addr=0
| |
1012two_queue=false 1013write_buffers=8 1014cpu_side=system.toL2Bus.master[0]
| 983two_queue=false 984write_buffers=8 985cpu_side=system.toL2Bus.master[0]
|
1015mem_side=system.membus.slave[2]
| 986mem_side=system.membus.slave[1]
|
1016 1017[system.membus] 1018type=CoherentBus 1019children=badaddr_responder 1020block_size=64 1021clock=1000 1022header_cycles=1 1023use_default_range=false 1024width=8 1025default=system.membus.badaddr_responder.pio 1026master=system.bridge.slave system.physmem.port
| 987 988[system.membus] 989type=CoherentBus 990children=badaddr_responder 991block_size=64 992clock=1000 993header_cycles=1 994use_default_range=false 995width=8 996default=system.membus.badaddr_responder.pio 997master=system.bridge.slave system.physmem.port
|
1027slave=system.system_port system.iocache.mem_side system.l2c.mem_side
| 998slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
1028 1029[system.membus.badaddr_responder] 1030type=IsaFake 1031clock=1000 1032fake_mem=false 1033pio_addr=0 1034pio_latency=100000 1035pio_size=8 1036ret_bad_addr=true 1037ret_data16=65535 1038ret_data32=4294967295 1039ret_data64=18446744073709551615 1040ret_data8=255 1041system=system 1042update_data=false 1043warn_access= 1044pio=system.membus.default 1045 1046[system.physmem] 1047type=SimpleDRAM 1048addr_mapping=openmap 1049banks_per_rank=8 1050clock=1000 1051conf_table_reported=false 1052in_addr_map=true 1053lines_per_rowbuffer=64 1054mem_sched_policy=fcfs 1055null=false 1056page_policy=open 1057range=0:134217727 1058ranks_per_channel=2 1059read_buffer_size=32 1060tBURST=4000 1061tCL=14000 1062tRCD=14000 1063tREFI=7800000 1064tRFC=300000 1065tRP=14000 1066tWTR=1000 1067write_buffer_size=32 1068write_thresh_perc=70 1069zero=false 1070port=system.membus.master[1] 1071 1072[system.simple_disk] 1073type=SimpleDisk 1074children=disk 1075disk=system.simple_disk.disk 1076system=system 1077 1078[system.simple_disk.disk] 1079type=RawDiskImage
| 999 1000[system.membus.badaddr_responder] 1001type=IsaFake 1002clock=1000 1003fake_mem=false 1004pio_addr=0 1005pio_latency=100000 1006pio_size=8 1007ret_bad_addr=true 1008ret_data16=65535 1009ret_data32=4294967295 1010ret_data64=18446744073709551615 1011ret_data8=255 1012system=system 1013update_data=false 1014warn_access= 1015pio=system.membus.default 1016 1017[system.physmem] 1018type=SimpleDRAM 1019addr_mapping=openmap 1020banks_per_rank=8 1021clock=1000 1022conf_table_reported=false 1023in_addr_map=true 1024lines_per_rowbuffer=64 1025mem_sched_policy=fcfs 1026null=false 1027page_policy=open 1028range=0:134217727 1029ranks_per_channel=2 1030read_buffer_size=32 1031tBURST=4000 1032tCL=14000 1033tRCD=14000 1034tREFI=7800000 1035tRFC=300000 1036tRP=14000 1037tWTR=1000 1038write_buffer_size=32 1039write_thresh_perc=70 1040zero=false 1041port=system.membus.master[1] 1042 1043[system.simple_disk] 1044type=SimpleDisk 1045children=disk 1046disk=system.simple_disk.disk 1047system=system 1048 1049[system.simple_disk.disk] 1050type=RawDiskImage
|
1080image_file=/projects/pd/randd/dist/disks/linux-latest.img
| 1051image_file=/gem5/dist/disks/linux-latest.img
|
1081read_only=true 1082 1083[system.terminal] 1084type=Terminal 1085intr_control=system.intrctrl 1086number=0 1087output=true 1088port=3456 1089 1090[system.toL2Bus] 1091type=CoherentBus 1092block_size=64 1093clock=500 1094header_cycles=1 1095use_default_range=false 1096width=8 1097master=system.l2c.cpu_side 1098slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1099 1100[system.tsunami] 1101type=Tsunami 1102children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1103intrctrl=system.intrctrl 1104system=system 1105 1106[system.tsunami.backdoor] 1107type=AlphaBackdoor 1108clock=1000 1109cpu=system.cpu0 1110disk=system.simple_disk 1111pio_addr=8804682956800 1112pio_latency=100000 1113platform=system.tsunami 1114system=system 1115terminal=system.terminal 1116pio=system.iobus.master[24] 1117 1118[system.tsunami.cchip] 1119type=TsunamiCChip 1120clock=1000 1121pio_addr=8803072344064 1122pio_latency=100000 1123system=system 1124tsunami=system.tsunami 1125pio=system.iobus.master[0] 1126 1127[system.tsunami.ethernet] 1128type=NSGigE 1129BAR0=1 1130BAR0LegacyIO=false 1131BAR0Size=256 1132BAR1=0 1133BAR1LegacyIO=false 1134BAR1Size=4096 1135BAR2=0 1136BAR2LegacyIO=false 1137BAR2Size=0 1138BAR3=0 1139BAR3LegacyIO=false 1140BAR3Size=0 1141BAR4=0 1142BAR4LegacyIO=false 1143BAR4Size=0 1144BAR5=0 1145BAR5LegacyIO=false 1146BAR5Size=0 1147BIST=0 1148CacheLineSize=0 1149CardbusCIS=0 1150ClassCode=2 1151Command=0 1152DeviceID=34 1153ExpansionROM=0 1154HeaderType=0 1155InterruptLine=30 1156InterruptPin=1 1157LatencyTimer=0 1158MaximumLatency=52 1159MinimumGrant=176 1160ProgIF=0 1161Revision=0 1162Status=656 1163SubClassCode=0 1164SubsystemID=0 1165SubsystemVendorID=0 1166VendorID=4107
| 1052read_only=true 1053 1054[system.terminal] 1055type=Terminal 1056intr_control=system.intrctrl 1057number=0 1058output=true 1059port=3456 1060 1061[system.toL2Bus] 1062type=CoherentBus 1063block_size=64 1064clock=500 1065header_cycles=1 1066use_default_range=false 1067width=8 1068master=system.l2c.cpu_side 1069slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1070 1071[system.tsunami] 1072type=Tsunami 1073children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1074intrctrl=system.intrctrl 1075system=system 1076 1077[system.tsunami.backdoor] 1078type=AlphaBackdoor 1079clock=1000 1080cpu=system.cpu0 1081disk=system.simple_disk 1082pio_addr=8804682956800 1083pio_latency=100000 1084platform=system.tsunami 1085system=system 1086terminal=system.terminal 1087pio=system.iobus.master[24] 1088 1089[system.tsunami.cchip] 1090type=TsunamiCChip 1091clock=1000 1092pio_addr=8803072344064 1093pio_latency=100000 1094system=system 1095tsunami=system.tsunami 1096pio=system.iobus.master[0] 1097 1098[system.tsunami.ethernet] 1099type=NSGigE 1100BAR0=1 1101BAR0LegacyIO=false 1102BAR0Size=256 1103BAR1=0 1104BAR1LegacyIO=false 1105BAR1Size=4096 1106BAR2=0 1107BAR2LegacyIO=false 1108BAR2Size=0 1109BAR3=0 1110BAR3LegacyIO=false 1111BAR3Size=0 1112BAR4=0 1113BAR4LegacyIO=false 1114BAR4Size=0 1115BAR5=0 1116BAR5LegacyIO=false 1117BAR5Size=0 1118BIST=0 1119CacheLineSize=0 1120CardbusCIS=0 1121ClassCode=2 1122Command=0 1123DeviceID=34 1124ExpansionROM=0 1125HeaderType=0 1126InterruptLine=30 1127InterruptPin=1 1128LatencyTimer=0 1129MaximumLatency=52 1130MinimumGrant=176 1131ProgIF=0 1132Revision=0 1133Status=656 1134SubClassCode=0 1135SubsystemID=0 1136SubsystemVendorID=0 1137VendorID=4107
|
1167clock=0
| 1138clock=2000
|
1168config_latency=20000 1169dma_data_free=false 1170dma_desc_free=false 1171dma_no_allocate=true 1172dma_read_delay=0 1173dma_read_factor=0 1174dma_write_delay=0 1175dma_write_factor=0 1176hardware_address=00:90:00:00:00:01 1177intr_delay=10000000 1178pci_bus=0 1179pci_dev=1 1180pci_func=0 1181pio_latency=30000 1182platform=system.tsunami 1183rss=false 1184rx_delay=1000000 1185rx_fifo_size=524288 1186rx_filter=true 1187rx_thread=false 1188system=system 1189tx_delay=1000000 1190tx_fifo_size=524288 1191tx_thread=false 1192config=system.iobus.master[28] 1193dma=system.iobus.slave[2] 1194pio=system.iobus.master[27] 1195 1196[system.tsunami.fake_OROM] 1197type=IsaFake 1198clock=1000 1199fake_mem=false 1200pio_addr=8796093677568 1201pio_latency=100000 1202pio_size=393216 1203ret_bad_addr=false 1204ret_data16=65535 1205ret_data32=4294967295 1206ret_data64=18446744073709551615 1207ret_data8=255 1208system=system 1209update_data=false 1210warn_access= 1211pio=system.iobus.master[8] 1212 1213[system.tsunami.fake_ata0] 1214type=IsaFake 1215clock=1000 1216fake_mem=false 1217pio_addr=8804615848432 1218pio_latency=100000 1219pio_size=8 1220ret_bad_addr=false 1221ret_data16=65535 1222ret_data32=4294967295 1223ret_data64=18446744073709551615 1224ret_data8=255 1225system=system 1226update_data=false 1227warn_access= 1228pio=system.iobus.master[19] 1229 1230[system.tsunami.fake_ata1] 1231type=IsaFake 1232clock=1000 1233fake_mem=false 1234pio_addr=8804615848304 1235pio_latency=100000 1236pio_size=8 1237ret_bad_addr=false 1238ret_data16=65535 1239ret_data32=4294967295 1240ret_data64=18446744073709551615 1241ret_data8=255 1242system=system 1243update_data=false 1244warn_access= 1245pio=system.iobus.master[20] 1246 1247[system.tsunami.fake_pnp_addr] 1248type=IsaFake 1249clock=1000 1250fake_mem=false 1251pio_addr=8804615848569 1252pio_latency=100000 1253pio_size=8 1254ret_bad_addr=false 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.iobus.master[9] 1263 1264[system.tsunami.fake_pnp_read0] 1265type=IsaFake 1266clock=1000 1267fake_mem=false 1268pio_addr=8804615848451 1269pio_latency=100000 1270pio_size=8 1271ret_bad_addr=false 1272ret_data16=65535 1273ret_data32=4294967295 1274ret_data64=18446744073709551615 1275ret_data8=255 1276system=system 1277update_data=false 1278warn_access= 1279pio=system.iobus.master[11] 1280 1281[system.tsunami.fake_pnp_read1] 1282type=IsaFake 1283clock=1000 1284fake_mem=false 1285pio_addr=8804615848515 1286pio_latency=100000 1287pio_size=8 1288ret_bad_addr=false 1289ret_data16=65535 1290ret_data32=4294967295 1291ret_data64=18446744073709551615 1292ret_data8=255 1293system=system 1294update_data=false 1295warn_access= 1296pio=system.iobus.master[12] 1297 1298[system.tsunami.fake_pnp_read2] 1299type=IsaFake 1300clock=1000 1301fake_mem=false 1302pio_addr=8804615848579 1303pio_latency=100000 1304pio_size=8 1305ret_bad_addr=false 1306ret_data16=65535 1307ret_data32=4294967295 1308ret_data64=18446744073709551615 1309ret_data8=255 1310system=system 1311update_data=false 1312warn_access= 1313pio=system.iobus.master[13] 1314 1315[system.tsunami.fake_pnp_read3] 1316type=IsaFake 1317clock=1000 1318fake_mem=false 1319pio_addr=8804615848643 1320pio_latency=100000 1321pio_size=8 1322ret_bad_addr=false 1323ret_data16=65535 1324ret_data32=4294967295 1325ret_data64=18446744073709551615 1326ret_data8=255 1327system=system 1328update_data=false 1329warn_access= 1330pio=system.iobus.master[14] 1331 1332[system.tsunami.fake_pnp_read4] 1333type=IsaFake 1334clock=1000 1335fake_mem=false 1336pio_addr=8804615848707 1337pio_latency=100000 1338pio_size=8 1339ret_bad_addr=false 1340ret_data16=65535 1341ret_data32=4294967295 1342ret_data64=18446744073709551615 1343ret_data8=255 1344system=system 1345update_data=false 1346warn_access= 1347pio=system.iobus.master[15] 1348 1349[system.tsunami.fake_pnp_read5] 1350type=IsaFake 1351clock=1000 1352fake_mem=false 1353pio_addr=8804615848771 1354pio_latency=100000 1355pio_size=8 1356ret_bad_addr=false 1357ret_data16=65535 1358ret_data32=4294967295 1359ret_data64=18446744073709551615 1360ret_data8=255 1361system=system 1362update_data=false 1363warn_access= 1364pio=system.iobus.master[16] 1365 1366[system.tsunami.fake_pnp_read6] 1367type=IsaFake 1368clock=1000 1369fake_mem=false 1370pio_addr=8804615848835 1371pio_latency=100000 1372pio_size=8 1373ret_bad_addr=false 1374ret_data16=65535 1375ret_data32=4294967295 1376ret_data64=18446744073709551615 1377ret_data8=255 1378system=system 1379update_data=false 1380warn_access= 1381pio=system.iobus.master[17] 1382 1383[system.tsunami.fake_pnp_read7] 1384type=IsaFake 1385clock=1000 1386fake_mem=false 1387pio_addr=8804615848899 1388pio_latency=100000 1389pio_size=8 1390ret_bad_addr=false 1391ret_data16=65535 1392ret_data32=4294967295 1393ret_data64=18446744073709551615 1394ret_data8=255 1395system=system 1396update_data=false 1397warn_access= 1398pio=system.iobus.master[18] 1399 1400[system.tsunami.fake_pnp_write] 1401type=IsaFake 1402clock=1000 1403fake_mem=false 1404pio_addr=8804615850617 1405pio_latency=100000 1406pio_size=8 1407ret_bad_addr=false 1408ret_data16=65535 1409ret_data32=4294967295 1410ret_data64=18446744073709551615 1411ret_data8=255 1412system=system 1413update_data=false 1414warn_access= 1415pio=system.iobus.master[10] 1416 1417[system.tsunami.fake_ppc] 1418type=IsaFake 1419clock=1000 1420fake_mem=false 1421pio_addr=8804615848891 1422pio_latency=100000 1423pio_size=8 1424ret_bad_addr=false 1425ret_data16=65535 1426ret_data32=4294967295 1427ret_data64=18446744073709551615 1428ret_data8=255 1429system=system 1430update_data=false 1431warn_access= 1432pio=system.iobus.master[7] 1433 1434[system.tsunami.fake_sm_chip] 1435type=IsaFake 1436clock=1000 1437fake_mem=false 1438pio_addr=8804615848816 1439pio_latency=100000 1440pio_size=8 1441ret_bad_addr=false 1442ret_data16=65535 1443ret_data32=4294967295 1444ret_data64=18446744073709551615 1445ret_data8=255 1446system=system 1447update_data=false 1448warn_access= 1449pio=system.iobus.master[2] 1450 1451[system.tsunami.fake_uart1] 1452type=IsaFake 1453clock=1000 1454fake_mem=false 1455pio_addr=8804615848696 1456pio_latency=100000 1457pio_size=8 1458ret_bad_addr=false 1459ret_data16=65535 1460ret_data32=4294967295 1461ret_data64=18446744073709551615 1462ret_data8=255 1463system=system 1464update_data=false 1465warn_access= 1466pio=system.iobus.master[3] 1467 1468[system.tsunami.fake_uart2] 1469type=IsaFake 1470clock=1000 1471fake_mem=false 1472pio_addr=8804615848936 1473pio_latency=100000 1474pio_size=8 1475ret_bad_addr=false 1476ret_data16=65535 1477ret_data32=4294967295 1478ret_data64=18446744073709551615 1479ret_data8=255 1480system=system 1481update_data=false 1482warn_access= 1483pio=system.iobus.master[4] 1484 1485[system.tsunami.fake_uart3] 1486type=IsaFake 1487clock=1000 1488fake_mem=false 1489pio_addr=8804615848680 1490pio_latency=100000 1491pio_size=8 1492ret_bad_addr=false 1493ret_data16=65535 1494ret_data32=4294967295 1495ret_data64=18446744073709551615 1496ret_data8=255 1497system=system 1498update_data=false 1499warn_access= 1500pio=system.iobus.master[5] 1501 1502[system.tsunami.fake_uart4] 1503type=IsaFake 1504clock=1000 1505fake_mem=false 1506pio_addr=8804615848944 1507pio_latency=100000 1508pio_size=8 1509ret_bad_addr=false 1510ret_data16=65535 1511ret_data32=4294967295 1512ret_data64=18446744073709551615 1513ret_data8=255 1514system=system 1515update_data=false 1516warn_access= 1517pio=system.iobus.master[6] 1518 1519[system.tsunami.fb] 1520type=BadDevice 1521clock=1000 1522devicename=FrameBuffer 1523pio_addr=8804615848912 1524pio_latency=100000 1525system=system 1526pio=system.iobus.master[21] 1527 1528[system.tsunami.ide] 1529type=IdeController 1530BAR0=1 1531BAR0LegacyIO=false 1532BAR0Size=8 1533BAR1=1 1534BAR1LegacyIO=false 1535BAR1Size=4 1536BAR2=1 1537BAR2LegacyIO=false 1538BAR2Size=8 1539BAR3=1 1540BAR3LegacyIO=false 1541BAR3Size=4 1542BAR4=1 1543BAR4LegacyIO=false 1544BAR4Size=16 1545BAR5=1 1546BAR5LegacyIO=false 1547BAR5Size=0 1548BIST=0 1549CacheLineSize=0 1550CardbusCIS=0 1551ClassCode=1 1552Command=0 1553DeviceID=28945 1554ExpansionROM=0 1555HeaderType=0 1556InterruptLine=31 1557InterruptPin=1 1558LatencyTimer=0 1559MaximumLatency=0 1560MinimumGrant=0 1561ProgIF=133 1562Revision=0 1563Status=640 1564SubClassCode=1 1565SubsystemID=0 1566SubsystemVendorID=0 1567VendorID=32902 1568clock=1000 1569config_latency=20000 1570ctrl_offset=0 1571disks=system.disk0 system.disk2 1572io_shift=0 1573pci_bus=0 1574pci_dev=0 1575pci_func=0 1576pio_latency=30000 1577platform=system.tsunami 1578system=system 1579config=system.iobus.master[26] 1580dma=system.iobus.slave[1] 1581pio=system.iobus.master[25] 1582 1583[system.tsunami.io] 1584type=TsunamiIO 1585clock=1000 1586frequency=976562500 1587pio_addr=8804615847936 1588pio_latency=100000 1589system=system 1590time=Thu Jan 1 00:00:00 2009 1591tsunami=system.tsunami 1592year_is_bcd=false 1593pio=system.iobus.master[22] 1594 1595[system.tsunami.pchip] 1596type=TsunamiPChip 1597clock=1000 1598pio_addr=8802535473152 1599pio_latency=100000 1600system=system 1601tsunami=system.tsunami 1602pio=system.iobus.master[1] 1603 1604[system.tsunami.pciconfig] 1605type=PciConfigAll 1606bus=0 1607clock=1000 1608pio_latency=30000 1609platform=system.tsunami 1610size=16777216 1611system=system 1612pio=system.iobus.default 1613 1614[system.tsunami.uart] 1615type=Uart8250 1616clock=1000 1617pio_addr=8804615848952 1618pio_latency=100000 1619platform=system.tsunami 1620system=system 1621terminal=system.terminal 1622pio=system.iobus.master[23] 1623
| 1139config_latency=20000 1140dma_data_free=false 1141dma_desc_free=false 1142dma_no_allocate=true 1143dma_read_delay=0 1144dma_read_factor=0 1145dma_write_delay=0 1146dma_write_factor=0 1147hardware_address=00:90:00:00:00:01 1148intr_delay=10000000 1149pci_bus=0 1150pci_dev=1 1151pci_func=0 1152pio_latency=30000 1153platform=system.tsunami 1154rss=false 1155rx_delay=1000000 1156rx_fifo_size=524288 1157rx_filter=true 1158rx_thread=false 1159system=system 1160tx_delay=1000000 1161tx_fifo_size=524288 1162tx_thread=false 1163config=system.iobus.master[28] 1164dma=system.iobus.slave[2] 1165pio=system.iobus.master[27] 1166 1167[system.tsunami.fake_OROM] 1168type=IsaFake 1169clock=1000 1170fake_mem=false 1171pio_addr=8796093677568 1172pio_latency=100000 1173pio_size=393216 1174ret_bad_addr=false 1175ret_data16=65535 1176ret_data32=4294967295 1177ret_data64=18446744073709551615 1178ret_data8=255 1179system=system 1180update_data=false 1181warn_access= 1182pio=system.iobus.master[8] 1183 1184[system.tsunami.fake_ata0] 1185type=IsaFake 1186clock=1000 1187fake_mem=false 1188pio_addr=8804615848432 1189pio_latency=100000 1190pio_size=8 1191ret_bad_addr=false 1192ret_data16=65535 1193ret_data32=4294967295 1194ret_data64=18446744073709551615 1195ret_data8=255 1196system=system 1197update_data=false 1198warn_access= 1199pio=system.iobus.master[19] 1200 1201[system.tsunami.fake_ata1] 1202type=IsaFake 1203clock=1000 1204fake_mem=false 1205pio_addr=8804615848304 1206pio_latency=100000 1207pio_size=8 1208ret_bad_addr=false 1209ret_data16=65535 1210ret_data32=4294967295 1211ret_data64=18446744073709551615 1212ret_data8=255 1213system=system 1214update_data=false 1215warn_access= 1216pio=system.iobus.master[20] 1217 1218[system.tsunami.fake_pnp_addr] 1219type=IsaFake 1220clock=1000 1221fake_mem=false 1222pio_addr=8804615848569 1223pio_latency=100000 1224pio_size=8 1225ret_bad_addr=false 1226ret_data16=65535 1227ret_data32=4294967295 1228ret_data64=18446744073709551615 1229ret_data8=255 1230system=system 1231update_data=false 1232warn_access= 1233pio=system.iobus.master[9] 1234 1235[system.tsunami.fake_pnp_read0] 1236type=IsaFake 1237clock=1000 1238fake_mem=false 1239pio_addr=8804615848451 1240pio_latency=100000 1241pio_size=8 1242ret_bad_addr=false 1243ret_data16=65535 1244ret_data32=4294967295 1245ret_data64=18446744073709551615 1246ret_data8=255 1247system=system 1248update_data=false 1249warn_access= 1250pio=system.iobus.master[11] 1251 1252[system.tsunami.fake_pnp_read1] 1253type=IsaFake 1254clock=1000 1255fake_mem=false 1256pio_addr=8804615848515 1257pio_latency=100000 1258pio_size=8 1259ret_bad_addr=false 1260ret_data16=65535 1261ret_data32=4294967295 1262ret_data64=18446744073709551615 1263ret_data8=255 1264system=system 1265update_data=false 1266warn_access= 1267pio=system.iobus.master[12] 1268 1269[system.tsunami.fake_pnp_read2] 1270type=IsaFake 1271clock=1000 1272fake_mem=false 1273pio_addr=8804615848579 1274pio_latency=100000 1275pio_size=8 1276ret_bad_addr=false 1277ret_data16=65535 1278ret_data32=4294967295 1279ret_data64=18446744073709551615 1280ret_data8=255 1281system=system 1282update_data=false 1283warn_access= 1284pio=system.iobus.master[13] 1285 1286[system.tsunami.fake_pnp_read3] 1287type=IsaFake 1288clock=1000 1289fake_mem=false 1290pio_addr=8804615848643 1291pio_latency=100000 1292pio_size=8 1293ret_bad_addr=false 1294ret_data16=65535 1295ret_data32=4294967295 1296ret_data64=18446744073709551615 1297ret_data8=255 1298system=system 1299update_data=false 1300warn_access= 1301pio=system.iobus.master[14] 1302 1303[system.tsunami.fake_pnp_read4] 1304type=IsaFake 1305clock=1000 1306fake_mem=false 1307pio_addr=8804615848707 1308pio_latency=100000 1309pio_size=8 1310ret_bad_addr=false 1311ret_data16=65535 1312ret_data32=4294967295 1313ret_data64=18446744073709551615 1314ret_data8=255 1315system=system 1316update_data=false 1317warn_access= 1318pio=system.iobus.master[15] 1319 1320[system.tsunami.fake_pnp_read5] 1321type=IsaFake 1322clock=1000 1323fake_mem=false 1324pio_addr=8804615848771 1325pio_latency=100000 1326pio_size=8 1327ret_bad_addr=false 1328ret_data16=65535 1329ret_data32=4294967295 1330ret_data64=18446744073709551615 1331ret_data8=255 1332system=system 1333update_data=false 1334warn_access= 1335pio=system.iobus.master[16] 1336 1337[system.tsunami.fake_pnp_read6] 1338type=IsaFake 1339clock=1000 1340fake_mem=false 1341pio_addr=8804615848835 1342pio_latency=100000 1343pio_size=8 1344ret_bad_addr=false 1345ret_data16=65535 1346ret_data32=4294967295 1347ret_data64=18446744073709551615 1348ret_data8=255 1349system=system 1350update_data=false 1351warn_access= 1352pio=system.iobus.master[17] 1353 1354[system.tsunami.fake_pnp_read7] 1355type=IsaFake 1356clock=1000 1357fake_mem=false 1358pio_addr=8804615848899 1359pio_latency=100000 1360pio_size=8 1361ret_bad_addr=false 1362ret_data16=65535 1363ret_data32=4294967295 1364ret_data64=18446744073709551615 1365ret_data8=255 1366system=system 1367update_data=false 1368warn_access= 1369pio=system.iobus.master[18] 1370 1371[system.tsunami.fake_pnp_write] 1372type=IsaFake 1373clock=1000 1374fake_mem=false 1375pio_addr=8804615850617 1376pio_latency=100000 1377pio_size=8 1378ret_bad_addr=false 1379ret_data16=65535 1380ret_data32=4294967295 1381ret_data64=18446744073709551615 1382ret_data8=255 1383system=system 1384update_data=false 1385warn_access= 1386pio=system.iobus.master[10] 1387 1388[system.tsunami.fake_ppc] 1389type=IsaFake 1390clock=1000 1391fake_mem=false 1392pio_addr=8804615848891 1393pio_latency=100000 1394pio_size=8 1395ret_bad_addr=false 1396ret_data16=65535 1397ret_data32=4294967295 1398ret_data64=18446744073709551615 1399ret_data8=255 1400system=system 1401update_data=false 1402warn_access= 1403pio=system.iobus.master[7] 1404 1405[system.tsunami.fake_sm_chip] 1406type=IsaFake 1407clock=1000 1408fake_mem=false 1409pio_addr=8804615848816 1410pio_latency=100000 1411pio_size=8 1412ret_bad_addr=false 1413ret_data16=65535 1414ret_data32=4294967295 1415ret_data64=18446744073709551615 1416ret_data8=255 1417system=system 1418update_data=false 1419warn_access= 1420pio=system.iobus.master[2] 1421 1422[system.tsunami.fake_uart1] 1423type=IsaFake 1424clock=1000 1425fake_mem=false 1426pio_addr=8804615848696 1427pio_latency=100000 1428pio_size=8 1429ret_bad_addr=false 1430ret_data16=65535 1431ret_data32=4294967295 1432ret_data64=18446744073709551615 1433ret_data8=255 1434system=system 1435update_data=false 1436warn_access= 1437pio=system.iobus.master[3] 1438 1439[system.tsunami.fake_uart2] 1440type=IsaFake 1441clock=1000 1442fake_mem=false 1443pio_addr=8804615848936 1444pio_latency=100000 1445pio_size=8 1446ret_bad_addr=false 1447ret_data16=65535 1448ret_data32=4294967295 1449ret_data64=18446744073709551615 1450ret_data8=255 1451system=system 1452update_data=false 1453warn_access= 1454pio=system.iobus.master[4] 1455 1456[system.tsunami.fake_uart3] 1457type=IsaFake 1458clock=1000 1459fake_mem=false 1460pio_addr=8804615848680 1461pio_latency=100000 1462pio_size=8 1463ret_bad_addr=false 1464ret_data16=65535 1465ret_data32=4294967295 1466ret_data64=18446744073709551615 1467ret_data8=255 1468system=system 1469update_data=false 1470warn_access= 1471pio=system.iobus.master[5] 1472 1473[system.tsunami.fake_uart4] 1474type=IsaFake 1475clock=1000 1476fake_mem=false 1477pio_addr=8804615848944 1478pio_latency=100000 1479pio_size=8 1480ret_bad_addr=false 1481ret_data16=65535 1482ret_data32=4294967295 1483ret_data64=18446744073709551615 1484ret_data8=255 1485system=system 1486update_data=false 1487warn_access= 1488pio=system.iobus.master[6] 1489 1490[system.tsunami.fb] 1491type=BadDevice 1492clock=1000 1493devicename=FrameBuffer 1494pio_addr=8804615848912 1495pio_latency=100000 1496system=system 1497pio=system.iobus.master[21] 1498 1499[system.tsunami.ide] 1500type=IdeController 1501BAR0=1 1502BAR0LegacyIO=false 1503BAR0Size=8 1504BAR1=1 1505BAR1LegacyIO=false 1506BAR1Size=4 1507BAR2=1 1508BAR2LegacyIO=false 1509BAR2Size=8 1510BAR3=1 1511BAR3LegacyIO=false 1512BAR3Size=4 1513BAR4=1 1514BAR4LegacyIO=false 1515BAR4Size=16 1516BAR5=1 1517BAR5LegacyIO=false 1518BAR5Size=0 1519BIST=0 1520CacheLineSize=0 1521CardbusCIS=0 1522ClassCode=1 1523Command=0 1524DeviceID=28945 1525ExpansionROM=0 1526HeaderType=0 1527InterruptLine=31 1528InterruptPin=1 1529LatencyTimer=0 1530MaximumLatency=0 1531MinimumGrant=0 1532ProgIF=133 1533Revision=0 1534Status=640 1535SubClassCode=1 1536SubsystemID=0 1537SubsystemVendorID=0 1538VendorID=32902 1539clock=1000 1540config_latency=20000 1541ctrl_offset=0 1542disks=system.disk0 system.disk2 1543io_shift=0 1544pci_bus=0 1545pci_dev=0 1546pci_func=0 1547pio_latency=30000 1548platform=system.tsunami 1549system=system 1550config=system.iobus.master[26] 1551dma=system.iobus.slave[1] 1552pio=system.iobus.master[25] 1553 1554[system.tsunami.io] 1555type=TsunamiIO 1556clock=1000 1557frequency=976562500 1558pio_addr=8804615847936 1559pio_latency=100000 1560system=system 1561time=Thu Jan 1 00:00:00 2009 1562tsunami=system.tsunami 1563year_is_bcd=false 1564pio=system.iobus.master[22] 1565 1566[system.tsunami.pchip] 1567type=TsunamiPChip 1568clock=1000 1569pio_addr=8802535473152 1570pio_latency=100000 1571system=system 1572tsunami=system.tsunami 1573pio=system.iobus.master[1] 1574 1575[system.tsunami.pciconfig] 1576type=PciConfigAll 1577bus=0 1578clock=1000 1579pio_latency=30000 1580platform=system.tsunami 1581size=16777216 1582system=system 1583pio=system.iobus.default 1584 1585[system.tsunami.uart] 1586type=Uart8250 1587clock=1000 1588pio_addr=8804615848952 1589pio_latency=100000 1590platform=system.tsunami 1591system=system 1592terminal=system.terminal 1593pio=system.iobus.master[23] 1594
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