1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0
|
14console=/dist/m5/system/binaries/console
| 14clock=1000 15console=/projects/pd/randd/dist/binaries/console
|
15init_param=0
| 16init_param=0
|
16kernel=/dist/m5/system/binaries/vmlinux
| 17kernel=/projects/pd/randd/dist/binaries/vmlinux
|
17load_addr_mask=1099511627775 18mem_mode=timing 19memories=system.physmem 20num_work_ids=16
| 18load_addr_mask=1099511627775 19mem_mode=timing 20memories=system.physmem 21num_work_ids=16
|
21pal=/dist/m5/system/binaries/ts_osfpal
| 22pal=/projects/pd/randd/dist/binaries/ts_osfpal
|
22readfile=tests/halt.sh 23symbolfile= 24system_rev=1024 25system_type=34 26work_begin_ckpt_count=0 27work_begin_cpu_id_exit=-1 28work_begin_exit_count=0 29work_cpus_ckpt_count=0 30work_end_ckpt_count=0 31work_end_exit_count=0 32work_item_id=-1 33system_port=system.membus.slave[0] 34 35[system.bridge] 36type=Bridge
| 23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.bridge] 37type=Bridge
|
| 38clock=1000
|
37delay=50000
| 39delay=50000
|
38nack_delay=4000
| |
39ranges=8796093022208:18446744073709551615 40req_size=16 41resp_size=16
| 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16
|
42write_ack=false
| |
43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu0] 47type=DerivO3CPU
| 43master=system.iobus.slave[0] 44slave=system.membus.master[0] 45 46[system.cpu0] 47type=DerivO3CPU
|
48children=dcache dtb fuPool icache interrupts itb tracer
| 48children=dcache dtb fuPool icache interrupts isa itb tracer
|
49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu0.interrupts
| 49BTBEntries=4096 50BTBTagSize=16 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55RASSize=16 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60cachePorts=200 61checker=Null 62choiceCtrBits=2 63choicePredictorSize=8192 64clock=500 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74defer_registration=false 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu0.dtb 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu0.fuPool 85function_trace=false 86function_trace_start=0 87globalCtrBits=2 88globalHistoryBits=13 89globalPredictorSize=8192 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94instShiftAmt=2 95interrupts=system.cpu0.interrupts
|
| 96isa=system.cpu0.isa
|
96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu0.itb 99localCtrBits=2 100localHistoryBits=11 101localHistoryTableSize=2048 102localPredictorSize=2048 103max_insts_all_threads=0 104max_insts_any_thread=0 105max_loads_all_threads=0 106max_loads_any_thread=0 107needsTSO=false 108numIQEntries=64 109numPhysFloatRegs=256 110numPhysIntRegs=256 111numROBEntries=192 112numRobs=1 113numThreads=1
| 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu0.itb 100localCtrBits=2 101localHistoryBits=11 102localHistoryTableSize=2048 103localPredictorSize=2048 104max_insts_all_threads=0 105max_insts_any_thread=0 106max_loads_all_threads=0 107max_loads_any_thread=0 108needsTSO=false 109numIQEntries=64 110numPhysFloatRegs=256 111numPhysIntRegs=256 112numROBEntries=192 113numRobs=1 114numThreads=1
|
114phase=0
| |
115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu0.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu0.dcache.cpu_side 141icache_port=system.cpu0.icache.cpu_side 142 143[system.cpu0.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64
| 115predType=tournament 116profile=0 117progress_interval=0 118renameToDecodeDelay=1 119renameToFetchDelay=1 120renameToIEWDelay=2 121renameToROBDelay=1 122renameWidth=8 123smtCommitPolicy=RoundRobin 124smtFetchPolicy=SingleThread 125smtIQPolicy=Partitioned 126smtIQThreshold=100 127smtLSQPolicy=Partitioned 128smtLSQThreshold=100 129smtNumFetchingThreads=1 130smtROBPolicy=Partitioned 131smtROBThreshold=100 132squashWidth=8 133store_set_clear_period=250000 134system=system 135tracer=system.cpu0.tracer 136trapLatency=13 137wbDepth=1 138wbWidth=8 139workload= 140dcache_port=system.cpu0.dcache.cpu_side 141icache_port=system.cpu0.icache.cpu_side 142 143[system.cpu0.dcache] 144type=BaseCache 145addr_ranges=0:18446744073709551615 146assoc=4 147block_size=64
|
| 148clock=500
|
148forward_snoops=true 149hash_delay=1
| 149forward_snoops=true 150hash_delay=1
|
| 151hit_latency=2
|
150is_top_level=true
| 152is_top_level=true
|
151latency=1000
| |
152max_miss_count=0 153mshrs=4 154prefetch_on_access=false 155prefetcher=Null 156prioritizeRequests=false 157repl=Null
| 153max_miss_count=0 154mshrs=4 155prefetch_on_access=false 156prefetcher=Null 157prioritizeRequests=false 158repl=Null
|
| 159response_latency=2
|
158size=32768 159subblock_size=0 160system=system 161tgts_per_mshr=20 162trace_addr=0 163two_queue=false 164write_buffers=8 165cpu_side=system.cpu0.dcache_port 166mem_side=system.toL2Bus.slave[1] 167 168[system.cpu0.dtb] 169type=AlphaTLB 170size=64 171 172[system.cpu0.fuPool] 173type=FUPool 174children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 175FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 176 177[system.cpu0.fuPool.FUList0] 178type=FUDesc 179children=opList 180count=6 181opList=system.cpu0.fuPool.FUList0.opList 182 183[system.cpu0.fuPool.FUList0.opList] 184type=OpDesc 185issueLat=1 186opClass=IntAlu 187opLat=1 188 189[system.cpu0.fuPool.FUList1] 190type=FUDesc 191children=opList0 opList1 192count=2 193opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 194 195[system.cpu0.fuPool.FUList1.opList0] 196type=OpDesc 197issueLat=1 198opClass=IntMult 199opLat=3 200 201[system.cpu0.fuPool.FUList1.opList1] 202type=OpDesc 203issueLat=19 204opClass=IntDiv 205opLat=20 206 207[system.cpu0.fuPool.FUList2] 208type=FUDesc 209children=opList0 opList1 opList2 210count=4 211opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 212 213[system.cpu0.fuPool.FUList2.opList0] 214type=OpDesc 215issueLat=1 216opClass=FloatAdd 217opLat=2 218 219[system.cpu0.fuPool.FUList2.opList1] 220type=OpDesc 221issueLat=1 222opClass=FloatCmp 223opLat=2 224 225[system.cpu0.fuPool.FUList2.opList2] 226type=OpDesc 227issueLat=1 228opClass=FloatCvt 229opLat=2 230 231[system.cpu0.fuPool.FUList3] 232type=FUDesc 233children=opList0 opList1 opList2 234count=2 235opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 236 237[system.cpu0.fuPool.FUList3.opList0] 238type=OpDesc 239issueLat=1 240opClass=FloatMult 241opLat=4 242 243[system.cpu0.fuPool.FUList3.opList1] 244type=OpDesc 245issueLat=12 246opClass=FloatDiv 247opLat=12 248 249[system.cpu0.fuPool.FUList3.opList2] 250type=OpDesc 251issueLat=24 252opClass=FloatSqrt 253opLat=24 254 255[system.cpu0.fuPool.FUList4] 256type=FUDesc 257children=opList 258count=0 259opList=system.cpu0.fuPool.FUList4.opList 260 261[system.cpu0.fuPool.FUList4.opList] 262type=OpDesc 263issueLat=1 264opClass=MemRead 265opLat=1 266 267[system.cpu0.fuPool.FUList5] 268type=FUDesc 269children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 270count=4 271opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 272 273[system.cpu0.fuPool.FUList5.opList00] 274type=OpDesc 275issueLat=1 276opClass=SimdAdd 277opLat=1 278 279[system.cpu0.fuPool.FUList5.opList01] 280type=OpDesc 281issueLat=1 282opClass=SimdAddAcc 283opLat=1 284 285[system.cpu0.fuPool.FUList5.opList02] 286type=OpDesc 287issueLat=1 288opClass=SimdAlu 289opLat=1 290 291[system.cpu0.fuPool.FUList5.opList03] 292type=OpDesc 293issueLat=1 294opClass=SimdCmp 295opLat=1 296 297[system.cpu0.fuPool.FUList5.opList04] 298type=OpDesc 299issueLat=1 300opClass=SimdCvt 301opLat=1 302 303[system.cpu0.fuPool.FUList5.opList05] 304type=OpDesc 305issueLat=1 306opClass=SimdMisc 307opLat=1 308 309[system.cpu0.fuPool.FUList5.opList06] 310type=OpDesc 311issueLat=1 312opClass=SimdMult 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList07] 316type=OpDesc 317issueLat=1 318opClass=SimdMultAcc 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList08] 322type=OpDesc 323issueLat=1 324opClass=SimdShift 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList09] 328type=OpDesc 329issueLat=1 330opClass=SimdShiftAcc 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList10] 334type=OpDesc 335issueLat=1 336opClass=SimdSqrt 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList11] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAdd 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList12] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatAlu 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList13] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCmp 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList14] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatCvt 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList15] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatDiv 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList16] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMisc 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList17] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMult 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList18] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatMultAcc 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList19] 388type=OpDesc 389issueLat=1 390opClass=SimdFloatSqrt 391opLat=1 392 393[system.cpu0.fuPool.FUList6] 394type=FUDesc 395children=opList 396count=0 397opList=system.cpu0.fuPool.FUList6.opList 398 399[system.cpu0.fuPool.FUList6.opList] 400type=OpDesc 401issueLat=1 402opClass=MemWrite 403opLat=1 404 405[system.cpu0.fuPool.FUList7] 406type=FUDesc 407children=opList0 opList1 408count=4 409opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 410 411[system.cpu0.fuPool.FUList7.opList0] 412type=OpDesc 413issueLat=1 414opClass=MemRead 415opLat=1 416 417[system.cpu0.fuPool.FUList7.opList1] 418type=OpDesc 419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu0.fuPool.FUList8] 424type=FUDesc 425children=opList 426count=1 427opList=system.cpu0.fuPool.FUList8.opList 428 429[system.cpu0.fuPool.FUList8.opList] 430type=OpDesc 431issueLat=3 432opClass=IprAccess 433opLat=3 434 435[system.cpu0.icache] 436type=BaseCache 437addr_ranges=0:18446744073709551615 438assoc=1 439block_size=64
| 160size=32768 161subblock_size=0 162system=system 163tgts_per_mshr=20 164trace_addr=0 165two_queue=false 166write_buffers=8 167cpu_side=system.cpu0.dcache_port 168mem_side=system.toL2Bus.slave[1] 169 170[system.cpu0.dtb] 171type=AlphaTLB 172size=64 173 174[system.cpu0.fuPool] 175type=FUPool 176children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 177FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 178 179[system.cpu0.fuPool.FUList0] 180type=FUDesc 181children=opList 182count=6 183opList=system.cpu0.fuPool.FUList0.opList 184 185[system.cpu0.fuPool.FUList0.opList] 186type=OpDesc 187issueLat=1 188opClass=IntAlu 189opLat=1 190 191[system.cpu0.fuPool.FUList1] 192type=FUDesc 193children=opList0 opList1 194count=2 195opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 196 197[system.cpu0.fuPool.FUList1.opList0] 198type=OpDesc 199issueLat=1 200opClass=IntMult 201opLat=3 202 203[system.cpu0.fuPool.FUList1.opList1] 204type=OpDesc 205issueLat=19 206opClass=IntDiv 207opLat=20 208 209[system.cpu0.fuPool.FUList2] 210type=FUDesc 211children=opList0 opList1 opList2 212count=4 213opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 214 215[system.cpu0.fuPool.FUList2.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatAdd 219opLat=2 220 221[system.cpu0.fuPool.FUList2.opList1] 222type=OpDesc 223issueLat=1 224opClass=FloatCmp 225opLat=2 226 227[system.cpu0.fuPool.FUList2.opList2] 228type=OpDesc 229issueLat=1 230opClass=FloatCvt 231opLat=2 232 233[system.cpu0.fuPool.FUList3] 234type=FUDesc 235children=opList0 opList1 opList2 236count=2 237opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 238 239[system.cpu0.fuPool.FUList3.opList0] 240type=OpDesc 241issueLat=1 242opClass=FloatMult 243opLat=4 244 245[system.cpu0.fuPool.FUList3.opList1] 246type=OpDesc 247issueLat=12 248opClass=FloatDiv 249opLat=12 250 251[system.cpu0.fuPool.FUList3.opList2] 252type=OpDesc 253issueLat=24 254opClass=FloatSqrt 255opLat=24 256 257[system.cpu0.fuPool.FUList4] 258type=FUDesc 259children=opList 260count=0 261opList=system.cpu0.fuPool.FUList4.opList 262 263[system.cpu0.fuPool.FUList4.opList] 264type=OpDesc 265issueLat=1 266opClass=MemRead 267opLat=1 268 269[system.cpu0.fuPool.FUList5] 270type=FUDesc 271children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 272count=4 273opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 274 275[system.cpu0.fuPool.FUList5.opList00] 276type=OpDesc 277issueLat=1 278opClass=SimdAdd 279opLat=1 280 281[system.cpu0.fuPool.FUList5.opList01] 282type=OpDesc 283issueLat=1 284opClass=SimdAddAcc 285opLat=1 286 287[system.cpu0.fuPool.FUList5.opList02] 288type=OpDesc 289issueLat=1 290opClass=SimdAlu 291opLat=1 292 293[system.cpu0.fuPool.FUList5.opList03] 294type=OpDesc 295issueLat=1 296opClass=SimdCmp 297opLat=1 298 299[system.cpu0.fuPool.FUList5.opList04] 300type=OpDesc 301issueLat=1 302opClass=SimdCvt 303opLat=1 304 305[system.cpu0.fuPool.FUList5.opList05] 306type=OpDesc 307issueLat=1 308opClass=SimdMisc 309opLat=1 310 311[system.cpu0.fuPool.FUList5.opList06] 312type=OpDesc 313issueLat=1 314opClass=SimdMult 315opLat=1 316 317[system.cpu0.fuPool.FUList5.opList07] 318type=OpDesc 319issueLat=1 320opClass=SimdMultAcc 321opLat=1 322 323[system.cpu0.fuPool.FUList5.opList08] 324type=OpDesc 325issueLat=1 326opClass=SimdShift 327opLat=1 328 329[system.cpu0.fuPool.FUList5.opList09] 330type=OpDesc 331issueLat=1 332opClass=SimdShiftAcc 333opLat=1 334 335[system.cpu0.fuPool.FUList5.opList10] 336type=OpDesc 337issueLat=1 338opClass=SimdSqrt 339opLat=1 340 341[system.cpu0.fuPool.FUList5.opList11] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatAdd 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList12] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatAlu 351opLat=1 352 353[system.cpu0.fuPool.FUList5.opList13] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatCmp 357opLat=1 358 359[system.cpu0.fuPool.FUList5.opList14] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatCvt 363opLat=1 364 365[system.cpu0.fuPool.FUList5.opList15] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatDiv 369opLat=1 370 371[system.cpu0.fuPool.FUList5.opList16] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatMisc 375opLat=1 376 377[system.cpu0.fuPool.FUList5.opList17] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatMult 381opLat=1 382 383[system.cpu0.fuPool.FUList5.opList18] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatMultAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList19] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatSqrt 393opLat=1 394 395[system.cpu0.fuPool.FUList6] 396type=FUDesc 397children=opList 398count=0 399opList=system.cpu0.fuPool.FUList6.opList 400 401[system.cpu0.fuPool.FUList6.opList] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu0.fuPool.FUList7] 408type=FUDesc 409children=opList0 opList1 410count=4 411opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 412 413[system.cpu0.fuPool.FUList7.opList0] 414type=OpDesc 415issueLat=1 416opClass=MemRead 417opLat=1 418 419[system.cpu0.fuPool.FUList7.opList1] 420type=OpDesc 421issueLat=1 422opClass=MemWrite 423opLat=1 424 425[system.cpu0.fuPool.FUList8] 426type=FUDesc 427children=opList 428count=1 429opList=system.cpu0.fuPool.FUList8.opList 430 431[system.cpu0.fuPool.FUList8.opList] 432type=OpDesc 433issueLat=3 434opClass=IprAccess 435opLat=3 436 437[system.cpu0.icache] 438type=BaseCache 439addr_ranges=0:18446744073709551615 440assoc=1 441block_size=64
|
| 442clock=500
|
440forward_snoops=true 441hash_delay=1
| 443forward_snoops=true 444hash_delay=1
|
| 445hit_latency=2
|
442is_top_level=true
| 446is_top_level=true
|
443latency=1000
| |
444max_miss_count=0 445mshrs=4 446prefetch_on_access=false 447prefetcher=Null 448prioritizeRequests=false 449repl=Null
| 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451prioritizeRequests=false 452repl=Null
|
| 453response_latency=2
|
450size=32768 451subblock_size=0 452system=system 453tgts_per_mshr=20 454trace_addr=0 455two_queue=false 456write_buffers=8 457cpu_side=system.cpu0.icache_port 458mem_side=system.toL2Bus.slave[0] 459 460[system.cpu0.interrupts] 461type=AlphaInterrupts 462
| 454size=32768 455subblock_size=0 456system=system 457tgts_per_mshr=20 458trace_addr=0 459two_queue=false 460write_buffers=8 461cpu_side=system.cpu0.icache_port 462mem_side=system.toL2Bus.slave[0] 463 464[system.cpu0.interrupts] 465type=AlphaInterrupts 466
|
| 467[system.cpu0.isa] 468type=AlphaISA 469
|
463[system.cpu0.itb] 464type=AlphaTLB 465size=48 466 467[system.cpu0.tracer] 468type=ExeTracer 469 470[system.cpu1] 471type=DerivO3CPU
| 470[system.cpu0.itb] 471type=AlphaTLB 472size=48 473 474[system.cpu0.tracer] 475type=ExeTracer 476 477[system.cpu1] 478type=DerivO3CPU
|
472children=dcache dtb fuPool icache interrupts itb tracer
| 479children=dcache dtb fuPool icache interrupts isa itb tracer
|
473BTBEntries=4096 474BTBTagSize=16 475LFSTSize=1024 476LQEntries=32 477LSQCheckLoads=true 478LSQDepCheckShift=4 479RASSize=16 480SQEntries=32 481SSITSize=1024 482activity=0 483backComSize=5 484cachePorts=200 485checker=Null 486choiceCtrBits=2 487choicePredictorSize=8192 488clock=500 489commitToDecodeDelay=1 490commitToFetchDelay=1 491commitToIEWDelay=1 492commitToRenameDelay=1 493commitWidth=8 494cpu_id=1 495decodeToFetchDelay=1 496decodeToRenameDelay=1 497decodeWidth=8 498defer_registration=false 499dispatchWidth=8 500do_checkpoint_insts=true 501do_quiesce=true 502do_statistics_insts=true 503dtb=system.cpu1.dtb 504fetchToDecodeDelay=1 505fetchTrapLatency=1 506fetchWidth=8 507forwardComSize=5 508fuPool=system.cpu1.fuPool 509function_trace=false 510function_trace_start=0 511globalCtrBits=2 512globalHistoryBits=13 513globalPredictorSize=8192 514iewToCommitDelay=1 515iewToDecodeDelay=1 516iewToFetchDelay=1 517iewToRenameDelay=1 518instShiftAmt=2 519interrupts=system.cpu1.interrupts
| 480BTBEntries=4096 481BTBTagSize=16 482LFSTSize=1024 483LQEntries=32 484LSQCheckLoads=true 485LSQDepCheckShift=4 486RASSize=16 487SQEntries=32 488SSITSize=1024 489activity=0 490backComSize=5 491cachePorts=200 492checker=Null 493choiceCtrBits=2 494choicePredictorSize=8192 495clock=500 496commitToDecodeDelay=1 497commitToFetchDelay=1 498commitToIEWDelay=1 499commitToRenameDelay=1 500commitWidth=8 501cpu_id=1 502decodeToFetchDelay=1 503decodeToRenameDelay=1 504decodeWidth=8 505defer_registration=false 506dispatchWidth=8 507do_checkpoint_insts=true 508do_quiesce=true 509do_statistics_insts=true 510dtb=system.cpu1.dtb 511fetchToDecodeDelay=1 512fetchTrapLatency=1 513fetchWidth=8 514forwardComSize=5 515fuPool=system.cpu1.fuPool 516function_trace=false 517function_trace_start=0 518globalCtrBits=2 519globalHistoryBits=13 520globalPredictorSize=8192 521iewToCommitDelay=1 522iewToDecodeDelay=1 523iewToFetchDelay=1 524iewToRenameDelay=1 525instShiftAmt=2 526interrupts=system.cpu1.interrupts
|
| 527isa=system.cpu1.isa
|
520issueToExecuteDelay=1 521issueWidth=8 522itb=system.cpu1.itb 523localCtrBits=2 524localHistoryBits=11 525localHistoryTableSize=2048 526localPredictorSize=2048 527max_insts_all_threads=0 528max_insts_any_thread=0 529max_loads_all_threads=0 530max_loads_any_thread=0 531needsTSO=false 532numIQEntries=64 533numPhysFloatRegs=256 534numPhysIntRegs=256 535numROBEntries=192 536numRobs=1 537numThreads=1
| 528issueToExecuteDelay=1 529issueWidth=8 530itb=system.cpu1.itb 531localCtrBits=2 532localHistoryBits=11 533localHistoryTableSize=2048 534localPredictorSize=2048 535max_insts_all_threads=0 536max_insts_any_thread=0 537max_loads_all_threads=0 538max_loads_any_thread=0 539needsTSO=false 540numIQEntries=64 541numPhysFloatRegs=256 542numPhysIntRegs=256 543numROBEntries=192 544numRobs=1 545numThreads=1
|
538phase=0
| |
539predType=tournament 540profile=0 541progress_interval=0 542renameToDecodeDelay=1 543renameToFetchDelay=1 544renameToIEWDelay=2 545renameToROBDelay=1 546renameWidth=8 547smtCommitPolicy=RoundRobin 548smtFetchPolicy=SingleThread 549smtIQPolicy=Partitioned 550smtIQThreshold=100 551smtLSQPolicy=Partitioned 552smtLSQThreshold=100 553smtNumFetchingThreads=1 554smtROBPolicy=Partitioned 555smtROBThreshold=100 556squashWidth=8 557store_set_clear_period=250000 558system=system 559tracer=system.cpu1.tracer 560trapLatency=13 561wbDepth=1 562wbWidth=8 563workload= 564dcache_port=system.cpu1.dcache.cpu_side 565icache_port=system.cpu1.icache.cpu_side 566 567[system.cpu1.dcache] 568type=BaseCache 569addr_ranges=0:18446744073709551615 570assoc=4 571block_size=64
| 546predType=tournament 547profile=0 548progress_interval=0 549renameToDecodeDelay=1 550renameToFetchDelay=1 551renameToIEWDelay=2 552renameToROBDelay=1 553renameWidth=8 554smtCommitPolicy=RoundRobin 555smtFetchPolicy=SingleThread 556smtIQPolicy=Partitioned 557smtIQThreshold=100 558smtLSQPolicy=Partitioned 559smtLSQThreshold=100 560smtNumFetchingThreads=1 561smtROBPolicy=Partitioned 562smtROBThreshold=100 563squashWidth=8 564store_set_clear_period=250000 565system=system 566tracer=system.cpu1.tracer 567trapLatency=13 568wbDepth=1 569wbWidth=8 570workload= 571dcache_port=system.cpu1.dcache.cpu_side 572icache_port=system.cpu1.icache.cpu_side 573 574[system.cpu1.dcache] 575type=BaseCache 576addr_ranges=0:18446744073709551615 577assoc=4 578block_size=64
|
| 579clock=500
|
572forward_snoops=true 573hash_delay=1
| 580forward_snoops=true 581hash_delay=1
|
| 582hit_latency=2
|
574is_top_level=true
| 583is_top_level=true
|
575latency=1000
| |
576max_miss_count=0 577mshrs=4 578prefetch_on_access=false 579prefetcher=Null 580prioritizeRequests=false 581repl=Null
| 584max_miss_count=0 585mshrs=4 586prefetch_on_access=false 587prefetcher=Null 588prioritizeRequests=false 589repl=Null
|
| 590response_latency=2
|
582size=32768 583subblock_size=0 584system=system 585tgts_per_mshr=20 586trace_addr=0 587two_queue=false 588write_buffers=8 589cpu_side=system.cpu1.dcache_port 590mem_side=system.toL2Bus.slave[3] 591 592[system.cpu1.dtb] 593type=AlphaTLB 594size=64 595 596[system.cpu1.fuPool] 597type=FUPool 598children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 599FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 600 601[system.cpu1.fuPool.FUList0] 602type=FUDesc 603children=opList 604count=6 605opList=system.cpu1.fuPool.FUList0.opList 606 607[system.cpu1.fuPool.FUList0.opList] 608type=OpDesc 609issueLat=1 610opClass=IntAlu 611opLat=1 612 613[system.cpu1.fuPool.FUList1] 614type=FUDesc 615children=opList0 opList1 616count=2 617opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 618 619[system.cpu1.fuPool.FUList1.opList0] 620type=OpDesc 621issueLat=1 622opClass=IntMult 623opLat=3 624 625[system.cpu1.fuPool.FUList1.opList1] 626type=OpDesc 627issueLat=19 628opClass=IntDiv 629opLat=20 630 631[system.cpu1.fuPool.FUList2] 632type=FUDesc 633children=opList0 opList1 opList2 634count=4 635opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 636 637[system.cpu1.fuPool.FUList2.opList0] 638type=OpDesc 639issueLat=1 640opClass=FloatAdd 641opLat=2 642 643[system.cpu1.fuPool.FUList2.opList1] 644type=OpDesc 645issueLat=1 646opClass=FloatCmp 647opLat=2 648 649[system.cpu1.fuPool.FUList2.opList2] 650type=OpDesc 651issueLat=1 652opClass=FloatCvt 653opLat=2 654 655[system.cpu1.fuPool.FUList3] 656type=FUDesc 657children=opList0 opList1 opList2 658count=2 659opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 660 661[system.cpu1.fuPool.FUList3.opList0] 662type=OpDesc 663issueLat=1 664opClass=FloatMult 665opLat=4 666 667[system.cpu1.fuPool.FUList3.opList1] 668type=OpDesc 669issueLat=12 670opClass=FloatDiv 671opLat=12 672 673[system.cpu1.fuPool.FUList3.opList2] 674type=OpDesc 675issueLat=24 676opClass=FloatSqrt 677opLat=24 678 679[system.cpu1.fuPool.FUList4] 680type=FUDesc 681children=opList 682count=0 683opList=system.cpu1.fuPool.FUList4.opList 684 685[system.cpu1.fuPool.FUList4.opList] 686type=OpDesc 687issueLat=1 688opClass=MemRead 689opLat=1 690 691[system.cpu1.fuPool.FUList5] 692type=FUDesc 693children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 694count=4 695opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 696 697[system.cpu1.fuPool.FUList5.opList00] 698type=OpDesc 699issueLat=1 700opClass=SimdAdd 701opLat=1 702 703[system.cpu1.fuPool.FUList5.opList01] 704type=OpDesc 705issueLat=1 706opClass=SimdAddAcc 707opLat=1 708 709[system.cpu1.fuPool.FUList5.opList02] 710type=OpDesc 711issueLat=1 712opClass=SimdAlu 713opLat=1 714 715[system.cpu1.fuPool.FUList5.opList03] 716type=OpDesc 717issueLat=1 718opClass=SimdCmp 719opLat=1 720 721[system.cpu1.fuPool.FUList5.opList04] 722type=OpDesc 723issueLat=1 724opClass=SimdCvt 725opLat=1 726 727[system.cpu1.fuPool.FUList5.opList05] 728type=OpDesc 729issueLat=1 730opClass=SimdMisc 731opLat=1 732 733[system.cpu1.fuPool.FUList5.opList06] 734type=OpDesc 735issueLat=1 736opClass=SimdMult 737opLat=1 738 739[system.cpu1.fuPool.FUList5.opList07] 740type=OpDesc 741issueLat=1 742opClass=SimdMultAcc 743opLat=1 744 745[system.cpu1.fuPool.FUList5.opList08] 746type=OpDesc 747issueLat=1 748opClass=SimdShift 749opLat=1 750 751[system.cpu1.fuPool.FUList5.opList09] 752type=OpDesc 753issueLat=1 754opClass=SimdShiftAcc 755opLat=1 756 757[system.cpu1.fuPool.FUList5.opList10] 758type=OpDesc 759issueLat=1 760opClass=SimdSqrt 761opLat=1 762 763[system.cpu1.fuPool.FUList5.opList11] 764type=OpDesc 765issueLat=1 766opClass=SimdFloatAdd 767opLat=1 768 769[system.cpu1.fuPool.FUList5.opList12] 770type=OpDesc 771issueLat=1 772opClass=SimdFloatAlu 773opLat=1 774 775[system.cpu1.fuPool.FUList5.opList13] 776type=OpDesc 777issueLat=1 778opClass=SimdFloatCmp 779opLat=1 780 781[system.cpu1.fuPool.FUList5.opList14] 782type=OpDesc 783issueLat=1 784opClass=SimdFloatCvt 785opLat=1 786 787[system.cpu1.fuPool.FUList5.opList15] 788type=OpDesc 789issueLat=1 790opClass=SimdFloatDiv 791opLat=1 792 793[system.cpu1.fuPool.FUList5.opList16] 794type=OpDesc 795issueLat=1 796opClass=SimdFloatMisc 797opLat=1 798 799[system.cpu1.fuPool.FUList5.opList17] 800type=OpDesc 801issueLat=1 802opClass=SimdFloatMult 803opLat=1 804 805[system.cpu1.fuPool.FUList5.opList18] 806type=OpDesc 807issueLat=1 808opClass=SimdFloatMultAcc 809opLat=1 810 811[system.cpu1.fuPool.FUList5.opList19] 812type=OpDesc 813issueLat=1 814opClass=SimdFloatSqrt 815opLat=1 816 817[system.cpu1.fuPool.FUList6] 818type=FUDesc 819children=opList 820count=0 821opList=system.cpu1.fuPool.FUList6.opList 822 823[system.cpu1.fuPool.FUList6.opList] 824type=OpDesc 825issueLat=1 826opClass=MemWrite 827opLat=1 828 829[system.cpu1.fuPool.FUList7] 830type=FUDesc 831children=opList0 opList1 832count=4 833opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 834 835[system.cpu1.fuPool.FUList7.opList0] 836type=OpDesc 837issueLat=1 838opClass=MemRead 839opLat=1 840 841[system.cpu1.fuPool.FUList7.opList1] 842type=OpDesc 843issueLat=1 844opClass=MemWrite 845opLat=1 846 847[system.cpu1.fuPool.FUList8] 848type=FUDesc 849children=opList 850count=1 851opList=system.cpu1.fuPool.FUList8.opList 852 853[system.cpu1.fuPool.FUList8.opList] 854type=OpDesc 855issueLat=3 856opClass=IprAccess 857opLat=3 858 859[system.cpu1.icache] 860type=BaseCache 861addr_ranges=0:18446744073709551615 862assoc=1 863block_size=64
| 591size=32768 592subblock_size=0 593system=system 594tgts_per_mshr=20 595trace_addr=0 596two_queue=false 597write_buffers=8 598cpu_side=system.cpu1.dcache_port 599mem_side=system.toL2Bus.slave[3] 600 601[system.cpu1.dtb] 602type=AlphaTLB 603size=64 604 605[system.cpu1.fuPool] 606type=FUPool 607children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 608FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 609 610[system.cpu1.fuPool.FUList0] 611type=FUDesc 612children=opList 613count=6 614opList=system.cpu1.fuPool.FUList0.opList 615 616[system.cpu1.fuPool.FUList0.opList] 617type=OpDesc 618issueLat=1 619opClass=IntAlu 620opLat=1 621 622[system.cpu1.fuPool.FUList1] 623type=FUDesc 624children=opList0 opList1 625count=2 626opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 627 628[system.cpu1.fuPool.FUList1.opList0] 629type=OpDesc 630issueLat=1 631opClass=IntMult 632opLat=3 633 634[system.cpu1.fuPool.FUList1.opList1] 635type=OpDesc 636issueLat=19 637opClass=IntDiv 638opLat=20 639 640[system.cpu1.fuPool.FUList2] 641type=FUDesc 642children=opList0 opList1 opList2 643count=4 644opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 645 646[system.cpu1.fuPool.FUList2.opList0] 647type=OpDesc 648issueLat=1 649opClass=FloatAdd 650opLat=2 651 652[system.cpu1.fuPool.FUList2.opList1] 653type=OpDesc 654issueLat=1 655opClass=FloatCmp 656opLat=2 657 658[system.cpu1.fuPool.FUList2.opList2] 659type=OpDesc 660issueLat=1 661opClass=FloatCvt 662opLat=2 663 664[system.cpu1.fuPool.FUList3] 665type=FUDesc 666children=opList0 opList1 opList2 667count=2 668opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 669 670[system.cpu1.fuPool.FUList3.opList0] 671type=OpDesc 672issueLat=1 673opClass=FloatMult 674opLat=4 675 676[system.cpu1.fuPool.FUList3.opList1] 677type=OpDesc 678issueLat=12 679opClass=FloatDiv 680opLat=12 681 682[system.cpu1.fuPool.FUList3.opList2] 683type=OpDesc 684issueLat=24 685opClass=FloatSqrt 686opLat=24 687 688[system.cpu1.fuPool.FUList4] 689type=FUDesc 690children=opList 691count=0 692opList=system.cpu1.fuPool.FUList4.opList 693 694[system.cpu1.fuPool.FUList4.opList] 695type=OpDesc 696issueLat=1 697opClass=MemRead 698opLat=1 699 700[system.cpu1.fuPool.FUList5] 701type=FUDesc 702children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 703count=4 704opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 705 706[system.cpu1.fuPool.FUList5.opList00] 707type=OpDesc 708issueLat=1 709opClass=SimdAdd 710opLat=1 711 712[system.cpu1.fuPool.FUList5.opList01] 713type=OpDesc 714issueLat=1 715opClass=SimdAddAcc 716opLat=1 717 718[system.cpu1.fuPool.FUList5.opList02] 719type=OpDesc 720issueLat=1 721opClass=SimdAlu 722opLat=1 723 724[system.cpu1.fuPool.FUList5.opList03] 725type=OpDesc 726issueLat=1 727opClass=SimdCmp 728opLat=1 729 730[system.cpu1.fuPool.FUList5.opList04] 731type=OpDesc 732issueLat=1 733opClass=SimdCvt 734opLat=1 735 736[system.cpu1.fuPool.FUList5.opList05] 737type=OpDesc 738issueLat=1 739opClass=SimdMisc 740opLat=1 741 742[system.cpu1.fuPool.FUList5.opList06] 743type=OpDesc 744issueLat=1 745opClass=SimdMult 746opLat=1 747 748[system.cpu1.fuPool.FUList5.opList07] 749type=OpDesc 750issueLat=1 751opClass=SimdMultAcc 752opLat=1 753 754[system.cpu1.fuPool.FUList5.opList08] 755type=OpDesc 756issueLat=1 757opClass=SimdShift 758opLat=1 759 760[system.cpu1.fuPool.FUList5.opList09] 761type=OpDesc 762issueLat=1 763opClass=SimdShiftAcc 764opLat=1 765 766[system.cpu1.fuPool.FUList5.opList10] 767type=OpDesc 768issueLat=1 769opClass=SimdSqrt 770opLat=1 771 772[system.cpu1.fuPool.FUList5.opList11] 773type=OpDesc 774issueLat=1 775opClass=SimdFloatAdd 776opLat=1 777 778[system.cpu1.fuPool.FUList5.opList12] 779type=OpDesc 780issueLat=1 781opClass=SimdFloatAlu 782opLat=1 783 784[system.cpu1.fuPool.FUList5.opList13] 785type=OpDesc 786issueLat=1 787opClass=SimdFloatCmp 788opLat=1 789 790[system.cpu1.fuPool.FUList5.opList14] 791type=OpDesc 792issueLat=1 793opClass=SimdFloatCvt 794opLat=1 795 796[system.cpu1.fuPool.FUList5.opList15] 797type=OpDesc 798issueLat=1 799opClass=SimdFloatDiv 800opLat=1 801 802[system.cpu1.fuPool.FUList5.opList16] 803type=OpDesc 804issueLat=1 805opClass=SimdFloatMisc 806opLat=1 807 808[system.cpu1.fuPool.FUList5.opList17] 809type=OpDesc 810issueLat=1 811opClass=SimdFloatMult 812opLat=1 813 814[system.cpu1.fuPool.FUList5.opList18] 815type=OpDesc 816issueLat=1 817opClass=SimdFloatMultAcc 818opLat=1 819 820[system.cpu1.fuPool.FUList5.opList19] 821type=OpDesc 822issueLat=1 823opClass=SimdFloatSqrt 824opLat=1 825 826[system.cpu1.fuPool.FUList6] 827type=FUDesc 828children=opList 829count=0 830opList=system.cpu1.fuPool.FUList6.opList 831 832[system.cpu1.fuPool.FUList6.opList] 833type=OpDesc 834issueLat=1 835opClass=MemWrite 836opLat=1 837 838[system.cpu1.fuPool.FUList7] 839type=FUDesc 840children=opList0 opList1 841count=4 842opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 843 844[system.cpu1.fuPool.FUList7.opList0] 845type=OpDesc 846issueLat=1 847opClass=MemRead 848opLat=1 849 850[system.cpu1.fuPool.FUList7.opList1] 851type=OpDesc 852issueLat=1 853opClass=MemWrite 854opLat=1 855 856[system.cpu1.fuPool.FUList8] 857type=FUDesc 858children=opList 859count=1 860opList=system.cpu1.fuPool.FUList8.opList 861 862[system.cpu1.fuPool.FUList8.opList] 863type=OpDesc 864issueLat=3 865opClass=IprAccess 866opLat=3 867 868[system.cpu1.icache] 869type=BaseCache 870addr_ranges=0:18446744073709551615 871assoc=1 872block_size=64
|
| 873clock=500
|
864forward_snoops=true 865hash_delay=1
| 874forward_snoops=true 875hash_delay=1
|
| 876hit_latency=2
|
866is_top_level=true
| 877is_top_level=true
|
867latency=1000
| |
868max_miss_count=0 869mshrs=4 870prefetch_on_access=false 871prefetcher=Null 872prioritizeRequests=false 873repl=Null
| 878max_miss_count=0 879mshrs=4 880prefetch_on_access=false 881prefetcher=Null 882prioritizeRequests=false 883repl=Null
|
| 884response_latency=2
|
874size=32768 875subblock_size=0 876system=system 877tgts_per_mshr=20 878trace_addr=0 879two_queue=false 880write_buffers=8 881cpu_side=system.cpu1.icache_port 882mem_side=system.toL2Bus.slave[2] 883 884[system.cpu1.interrupts] 885type=AlphaInterrupts 886
| 885size=32768 886subblock_size=0 887system=system 888tgts_per_mshr=20 889trace_addr=0 890two_queue=false 891write_buffers=8 892cpu_side=system.cpu1.icache_port 893mem_side=system.toL2Bus.slave[2] 894 895[system.cpu1.interrupts] 896type=AlphaInterrupts 897
|
| 898[system.cpu1.isa] 899type=AlphaISA 900
|
887[system.cpu1.itb] 888type=AlphaTLB 889size=48 890 891[system.cpu1.tracer] 892type=ExeTracer 893 894[system.disk0] 895type=IdeDisk 896children=image 897delay=1000000 898driveID=master 899image=system.disk0.image 900 901[system.disk0.image] 902type=CowDiskImage 903children=child 904child=system.disk0.image.child 905image_file= 906read_only=false 907table_size=65536 908 909[system.disk0.image.child] 910type=RawDiskImage
| 901[system.cpu1.itb] 902type=AlphaTLB 903size=48 904 905[system.cpu1.tracer] 906type=ExeTracer 907 908[system.disk0] 909type=IdeDisk 910children=image 911delay=1000000 912driveID=master 913image=system.disk0.image 914 915[system.disk0.image] 916type=CowDiskImage 917children=child 918child=system.disk0.image.child 919image_file= 920read_only=false 921table_size=65536 922 923[system.disk0.image.child] 924type=RawDiskImage
|
911image_file=/dist/m5/system/disks/linux-latest.img
| 925image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
912read_only=true 913 914[system.disk2] 915type=IdeDisk 916children=image 917delay=1000000 918driveID=master 919image=system.disk2.image 920 921[system.disk2.image] 922type=CowDiskImage 923children=child 924child=system.disk2.image.child 925image_file= 926read_only=false 927table_size=65536 928 929[system.disk2.image.child] 930type=RawDiskImage
| 926read_only=true 927 928[system.disk2] 929type=IdeDisk 930children=image 931delay=1000000 932driveID=master 933image=system.disk2.image 934 935[system.disk2.image] 936type=CowDiskImage 937children=child 938child=system.disk2.image.child 939image_file= 940read_only=false 941table_size=65536 942 943[system.disk2.image.child] 944type=RawDiskImage
|
931image_file=/dist/m5/system/disks/linux-bigswap2.img
| 945image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
932read_only=true 933 934[system.intrctrl] 935type=IntrControl 936sys=system 937 938[system.iobus] 939type=NoncoherentBus 940block_size=64 941clock=1000 942header_cycles=1 943use_default_range=true 944width=8 945default=system.tsunami.pciconfig.pio 946master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 947slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 948 949[system.iocache] 950type=BaseCache 951addr_ranges=0:8589934591 952assoc=8 953block_size=64
| 946read_only=true 947 948[system.intrctrl] 949type=IntrControl 950sys=system 951 952[system.iobus] 953type=NoncoherentBus 954block_size=64 955clock=1000 956header_cycles=1 957use_default_range=true 958width=8 959default=system.tsunami.pciconfig.pio 960master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 961slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 962 963[system.iocache] 964type=BaseCache 965addr_ranges=0:8589934591 966assoc=8 967block_size=64
|
| 968clock=1000
|
954forward_snoops=false 955hash_delay=1
| 969forward_snoops=false 970hash_delay=1
|
| 971hit_latency=50
|
956is_top_level=true
| 972is_top_level=true
|
957latency=50000
| |
958max_miss_count=0 959mshrs=20 960prefetch_on_access=false 961prefetcher=Null 962prioritizeRequests=false 963repl=Null
| 973max_miss_count=0 974mshrs=20 975prefetch_on_access=false 976prefetcher=Null 977prioritizeRequests=false 978repl=Null
|
| 979response_latency=50
|
964size=1024 965subblock_size=0 966system=system 967tgts_per_mshr=12 968trace_addr=0 969two_queue=false 970write_buffers=8 971cpu_side=system.iobus.master[29] 972mem_side=system.membus.slave[1] 973 974[system.l2c] 975type=BaseCache 976addr_ranges=0:18446744073709551615 977assoc=8 978block_size=64
| 980size=1024 981subblock_size=0 982system=system 983tgts_per_mshr=12 984trace_addr=0 985two_queue=false 986write_buffers=8 987cpu_side=system.iobus.master[29] 988mem_side=system.membus.slave[1] 989 990[system.l2c] 991type=BaseCache 992addr_ranges=0:18446744073709551615 993assoc=8 994block_size=64
|
| 995clock=500
|
979forward_snoops=true 980hash_delay=1
| 996forward_snoops=true 997hash_delay=1
|
| 998hit_latency=20
|
981is_top_level=false
| 999is_top_level=false
|
982latency=10000
| |
983max_miss_count=0
| 1000max_miss_count=0
|
984mshrs=92
| 1001mshrs=20
|
985prefetch_on_access=false 986prefetcher=Null 987prioritizeRequests=false 988repl=Null
| 1002prefetch_on_access=false 1003prefetcher=Null 1004prioritizeRequests=false 1005repl=Null
|
| 1006response_latency=20
|
989size=4194304 990subblock_size=0 991system=system
| 1007size=4194304 1008subblock_size=0 1009system=system
|
992tgts_per_mshr=16
| 1010tgts_per_mshr=12
|
993trace_addr=0 994two_queue=false 995write_buffers=8 996cpu_side=system.toL2Bus.master[0] 997mem_side=system.membus.slave[2] 998 999[system.membus] 1000type=CoherentBus 1001children=badaddr_responder 1002block_size=64 1003clock=1000 1004header_cycles=1 1005use_default_range=false 1006width=8 1007default=system.membus.badaddr_responder.pio 1008master=system.bridge.slave system.physmem.port 1009slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1010 1011[system.membus.badaddr_responder] 1012type=IsaFake
| 1011trace_addr=0 1012two_queue=false 1013write_buffers=8 1014cpu_side=system.toL2Bus.master[0] 1015mem_side=system.membus.slave[2] 1016 1017[system.membus] 1018type=CoherentBus 1019children=badaddr_responder 1020block_size=64 1021clock=1000 1022header_cycles=1 1023use_default_range=false 1024width=8 1025default=system.membus.badaddr_responder.pio 1026master=system.bridge.slave system.physmem.port 1027slave=system.system_port system.iocache.mem_side system.l2c.mem_side 1028 1029[system.membus.badaddr_responder] 1030type=IsaFake
|
| 1031clock=1000
|
1013fake_mem=false 1014pio_addr=0
| 1032fake_mem=false 1033pio_addr=0
|
1015pio_latency=1000
| 1034pio_latency=100000
|
1016pio_size=8 1017ret_bad_addr=true 1018ret_data16=65535 1019ret_data32=4294967295 1020ret_data64=18446744073709551615 1021ret_data8=255 1022system=system 1023update_data=false 1024warn_access= 1025pio=system.membus.default 1026 1027[system.physmem]
| 1035pio_size=8 1036ret_bad_addr=true 1037ret_data16=65535 1038ret_data32=4294967295 1039ret_data64=18446744073709551615 1040ret_data8=255 1041system=system 1042update_data=false 1043warn_access= 1044pio=system.membus.default 1045 1046[system.physmem]
|
1028type=SimpleMemory
| 1047type=SimpleDRAM 1048addr_mapping=openmap 1049banks_per_rank=8 1050clock=1000
|
1029conf_table_reported=false
| 1051conf_table_reported=false
|
1030file=
| |
1031in_addr_map=true
| 1052in_addr_map=true
|
1032latency=30000 1033latency_var=0
| 1053lines_per_rowbuffer=64 1054mem_sched_policy=fcfs
|
1034null=false
| 1055null=false
|
| 1056page_policy=open
|
1035range=0:134217727
| 1057range=0:134217727
|
| 1058ranks_per_channel=2 1059read_buffer_size=32 1060tBURST=4000 1061tCL=14000 1062tRCD=14000 1063tREFI=7800000 1064tRFC=300000 1065tRP=14000 1066tWTR=1000 1067write_buffer_size=32 1068write_thresh_perc=70
|
1036zero=false 1037port=system.membus.master[1] 1038 1039[system.simple_disk] 1040type=SimpleDisk 1041children=disk 1042disk=system.simple_disk.disk 1043system=system 1044 1045[system.simple_disk.disk] 1046type=RawDiskImage
| 1069zero=false 1070port=system.membus.master[1] 1071 1072[system.simple_disk] 1073type=SimpleDisk 1074children=disk 1075disk=system.simple_disk.disk 1076system=system 1077 1078[system.simple_disk.disk] 1079type=RawDiskImage
|
1047image_file=/dist/m5/system/disks/linux-latest.img
| 1080image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
1048read_only=true 1049 1050[system.terminal] 1051type=Terminal 1052intr_control=system.intrctrl 1053number=0 1054output=true 1055port=3456 1056 1057[system.toL2Bus] 1058type=CoherentBus 1059block_size=64
| 1081read_only=true 1082 1083[system.terminal] 1084type=Terminal 1085intr_control=system.intrctrl 1086number=0 1087output=true 1088port=3456 1089 1090[system.toL2Bus] 1091type=CoherentBus 1092block_size=64
|
1060clock=1000
| 1093clock=500
|
1061header_cycles=1 1062use_default_range=false 1063width=8 1064master=system.l2c.cpu_side 1065slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1066 1067[system.tsunami] 1068type=Tsunami 1069children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1070intrctrl=system.intrctrl 1071system=system 1072 1073[system.tsunami.backdoor] 1074type=AlphaBackdoor
| 1094header_cycles=1 1095use_default_range=false 1096width=8 1097master=system.l2c.cpu_side 1098slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1099 1100[system.tsunami] 1101type=Tsunami 1102children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 1103intrctrl=system.intrctrl 1104system=system 1105 1106[system.tsunami.backdoor] 1107type=AlphaBackdoor
|
| 1108clock=1000
|
1075cpu=system.cpu0 1076disk=system.simple_disk 1077pio_addr=8804682956800
| 1109cpu=system.cpu0 1110disk=system.simple_disk 1111pio_addr=8804682956800
|
1078pio_latency=1000
| 1112pio_latency=100000
|
1079platform=system.tsunami 1080system=system 1081terminal=system.terminal 1082pio=system.iobus.master[24] 1083 1084[system.tsunami.cchip] 1085type=TsunamiCChip
| 1113platform=system.tsunami 1114system=system 1115terminal=system.terminal 1116pio=system.iobus.master[24] 1117 1118[system.tsunami.cchip] 1119type=TsunamiCChip
|
| 1120clock=1000
|
1086pio_addr=8803072344064
| 1121pio_addr=8803072344064
|
1087pio_latency=1000
| 1122pio_latency=100000
|
1088system=system 1089tsunami=system.tsunami 1090pio=system.iobus.master[0] 1091 1092[system.tsunami.ethernet] 1093type=NSGigE 1094BAR0=1 1095BAR0LegacyIO=false 1096BAR0Size=256 1097BAR1=0 1098BAR1LegacyIO=false 1099BAR1Size=4096 1100BAR2=0 1101BAR2LegacyIO=false 1102BAR2Size=0 1103BAR3=0 1104BAR3LegacyIO=false 1105BAR3Size=0 1106BAR4=0 1107BAR4LegacyIO=false 1108BAR4Size=0 1109BAR5=0 1110BAR5LegacyIO=false 1111BAR5Size=0 1112BIST=0 1113CacheLineSize=0 1114CardbusCIS=0 1115ClassCode=2 1116Command=0 1117DeviceID=34 1118ExpansionROM=0 1119HeaderType=0 1120InterruptLine=30 1121InterruptPin=1 1122LatencyTimer=0 1123MaximumLatency=52 1124MinimumGrant=176 1125ProgIF=0 1126Revision=0 1127Status=656 1128SubClassCode=0 1129SubsystemID=0 1130SubsystemVendorID=0 1131VendorID=4107 1132clock=0 1133config_latency=20000 1134dma_data_free=false 1135dma_desc_free=false 1136dma_no_allocate=true 1137dma_read_delay=0 1138dma_read_factor=0 1139dma_write_delay=0 1140dma_write_factor=0 1141hardware_address=00:90:00:00:00:01 1142intr_delay=10000000
| 1123system=system 1124tsunami=system.tsunami 1125pio=system.iobus.master[0] 1126 1127[system.tsunami.ethernet] 1128type=NSGigE 1129BAR0=1 1130BAR0LegacyIO=false 1131BAR0Size=256 1132BAR1=0 1133BAR1LegacyIO=false 1134BAR1Size=4096 1135BAR2=0 1136BAR2LegacyIO=false 1137BAR2Size=0 1138BAR3=0 1139BAR3LegacyIO=false 1140BAR3Size=0 1141BAR4=0 1142BAR4LegacyIO=false 1143BAR4Size=0 1144BAR5=0 1145BAR5LegacyIO=false 1146BAR5Size=0 1147BIST=0 1148CacheLineSize=0 1149CardbusCIS=0 1150ClassCode=2 1151Command=0 1152DeviceID=34 1153ExpansionROM=0 1154HeaderType=0 1155InterruptLine=30 1156InterruptPin=1 1157LatencyTimer=0 1158MaximumLatency=52 1159MinimumGrant=176 1160ProgIF=0 1161Revision=0 1162Status=656 1163SubClassCode=0 1164SubsystemID=0 1165SubsystemVendorID=0 1166VendorID=4107 1167clock=0 1168config_latency=20000 1169dma_data_free=false 1170dma_desc_free=false 1171dma_no_allocate=true 1172dma_read_delay=0 1173dma_read_factor=0 1174dma_write_delay=0 1175dma_write_factor=0 1176hardware_address=00:90:00:00:00:01 1177intr_delay=10000000
|
1143max_backoff_delay=10000000 1144min_backoff_delay=4000
| |
1145pci_bus=0 1146pci_dev=1 1147pci_func=0
| 1178pci_bus=0 1179pci_dev=1 1180pci_func=0
|
1148pio_latency=1000
| 1181pio_latency=30000
|
1149platform=system.tsunami 1150rss=false 1151rx_delay=1000000 1152rx_fifo_size=524288 1153rx_filter=true 1154rx_thread=false 1155system=system 1156tx_delay=1000000 1157tx_fifo_size=524288 1158tx_thread=false 1159config=system.iobus.master[28] 1160dma=system.iobus.slave[2] 1161pio=system.iobus.master[27] 1162 1163[system.tsunami.fake_OROM] 1164type=IsaFake
| 1182platform=system.tsunami 1183rss=false 1184rx_delay=1000000 1185rx_fifo_size=524288 1186rx_filter=true 1187rx_thread=false 1188system=system 1189tx_delay=1000000 1190tx_fifo_size=524288 1191tx_thread=false 1192config=system.iobus.master[28] 1193dma=system.iobus.slave[2] 1194pio=system.iobus.master[27] 1195 1196[system.tsunami.fake_OROM] 1197type=IsaFake
|
| 1198clock=1000
|
1165fake_mem=false 1166pio_addr=8796093677568
| 1199fake_mem=false 1200pio_addr=8796093677568
|
1167pio_latency=1000
| 1201pio_latency=100000
|
1168pio_size=393216 1169ret_bad_addr=false 1170ret_data16=65535 1171ret_data32=4294967295 1172ret_data64=18446744073709551615 1173ret_data8=255 1174system=system 1175update_data=false 1176warn_access= 1177pio=system.iobus.master[8] 1178 1179[system.tsunami.fake_ata0] 1180type=IsaFake
| 1202pio_size=393216 1203ret_bad_addr=false 1204ret_data16=65535 1205ret_data32=4294967295 1206ret_data64=18446744073709551615 1207ret_data8=255 1208system=system 1209update_data=false 1210warn_access= 1211pio=system.iobus.master[8] 1212 1213[system.tsunami.fake_ata0] 1214type=IsaFake
|
| 1215clock=1000
|
1181fake_mem=false 1182pio_addr=8804615848432
| 1216fake_mem=false 1217pio_addr=8804615848432
|
1183pio_latency=1000
| 1218pio_latency=100000
|
1184pio_size=8 1185ret_bad_addr=false 1186ret_data16=65535 1187ret_data32=4294967295 1188ret_data64=18446744073709551615 1189ret_data8=255 1190system=system 1191update_data=false 1192warn_access= 1193pio=system.iobus.master[19] 1194 1195[system.tsunami.fake_ata1] 1196type=IsaFake
| 1219pio_size=8 1220ret_bad_addr=false 1221ret_data16=65535 1222ret_data32=4294967295 1223ret_data64=18446744073709551615 1224ret_data8=255 1225system=system 1226update_data=false 1227warn_access= 1228pio=system.iobus.master[19] 1229 1230[system.tsunami.fake_ata1] 1231type=IsaFake
|
| 1232clock=1000
|
1197fake_mem=false 1198pio_addr=8804615848304
| 1233fake_mem=false 1234pio_addr=8804615848304
|
1199pio_latency=1000
| 1235pio_latency=100000
|
1200pio_size=8 1201ret_bad_addr=false 1202ret_data16=65535 1203ret_data32=4294967295 1204ret_data64=18446744073709551615 1205ret_data8=255 1206system=system 1207update_data=false 1208warn_access= 1209pio=system.iobus.master[20] 1210 1211[system.tsunami.fake_pnp_addr] 1212type=IsaFake
| 1236pio_size=8 1237ret_bad_addr=false 1238ret_data16=65535 1239ret_data32=4294967295 1240ret_data64=18446744073709551615 1241ret_data8=255 1242system=system 1243update_data=false 1244warn_access= 1245pio=system.iobus.master[20] 1246 1247[system.tsunami.fake_pnp_addr] 1248type=IsaFake
|
| 1249clock=1000
|
1213fake_mem=false 1214pio_addr=8804615848569
| 1250fake_mem=false 1251pio_addr=8804615848569
|
1215pio_latency=1000
| 1252pio_latency=100000
|
1216pio_size=8 1217ret_bad_addr=false 1218ret_data16=65535 1219ret_data32=4294967295 1220ret_data64=18446744073709551615 1221ret_data8=255 1222system=system 1223update_data=false 1224warn_access= 1225pio=system.iobus.master[9] 1226 1227[system.tsunami.fake_pnp_read0] 1228type=IsaFake
| 1253pio_size=8 1254ret_bad_addr=false 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.iobus.master[9] 1263 1264[system.tsunami.fake_pnp_read0] 1265type=IsaFake
|
| 1266clock=1000
|
1229fake_mem=false 1230pio_addr=8804615848451
| 1267fake_mem=false 1268pio_addr=8804615848451
|
1231pio_latency=1000
| 1269pio_latency=100000
|
1232pio_size=8 1233ret_bad_addr=false 1234ret_data16=65535 1235ret_data32=4294967295 1236ret_data64=18446744073709551615 1237ret_data8=255 1238system=system 1239update_data=false 1240warn_access= 1241pio=system.iobus.master[11] 1242 1243[system.tsunami.fake_pnp_read1] 1244type=IsaFake
| 1270pio_size=8 1271ret_bad_addr=false 1272ret_data16=65535 1273ret_data32=4294967295 1274ret_data64=18446744073709551615 1275ret_data8=255 1276system=system 1277update_data=false 1278warn_access= 1279pio=system.iobus.master[11] 1280 1281[system.tsunami.fake_pnp_read1] 1282type=IsaFake
|
| 1283clock=1000
|
1245fake_mem=false 1246pio_addr=8804615848515
| 1284fake_mem=false 1285pio_addr=8804615848515
|
1247pio_latency=1000
| 1286pio_latency=100000
|
1248pio_size=8 1249ret_bad_addr=false 1250ret_data16=65535 1251ret_data32=4294967295 1252ret_data64=18446744073709551615 1253ret_data8=255 1254system=system 1255update_data=false 1256warn_access= 1257pio=system.iobus.master[12] 1258 1259[system.tsunami.fake_pnp_read2] 1260type=IsaFake
| 1287pio_size=8 1288ret_bad_addr=false 1289ret_data16=65535 1290ret_data32=4294967295 1291ret_data64=18446744073709551615 1292ret_data8=255 1293system=system 1294update_data=false 1295warn_access= 1296pio=system.iobus.master[12] 1297 1298[system.tsunami.fake_pnp_read2] 1299type=IsaFake
|
| 1300clock=1000
|
1261fake_mem=false 1262pio_addr=8804615848579
| 1301fake_mem=false 1302pio_addr=8804615848579
|
1263pio_latency=1000
| 1303pio_latency=100000
|
1264pio_size=8 1265ret_bad_addr=false 1266ret_data16=65535 1267ret_data32=4294967295 1268ret_data64=18446744073709551615 1269ret_data8=255 1270system=system 1271update_data=false 1272warn_access= 1273pio=system.iobus.master[13] 1274 1275[system.tsunami.fake_pnp_read3] 1276type=IsaFake
| 1304pio_size=8 1305ret_bad_addr=false 1306ret_data16=65535 1307ret_data32=4294967295 1308ret_data64=18446744073709551615 1309ret_data8=255 1310system=system 1311update_data=false 1312warn_access= 1313pio=system.iobus.master[13] 1314 1315[system.tsunami.fake_pnp_read3] 1316type=IsaFake
|
| 1317clock=1000
|
1277fake_mem=false 1278pio_addr=8804615848643
| 1318fake_mem=false 1319pio_addr=8804615848643
|
1279pio_latency=1000
| 1320pio_latency=100000
|
1280pio_size=8 1281ret_bad_addr=false 1282ret_data16=65535 1283ret_data32=4294967295 1284ret_data64=18446744073709551615 1285ret_data8=255 1286system=system 1287update_data=false 1288warn_access= 1289pio=system.iobus.master[14] 1290 1291[system.tsunami.fake_pnp_read4] 1292type=IsaFake
| 1321pio_size=8 1322ret_bad_addr=false 1323ret_data16=65535 1324ret_data32=4294967295 1325ret_data64=18446744073709551615 1326ret_data8=255 1327system=system 1328update_data=false 1329warn_access= 1330pio=system.iobus.master[14] 1331 1332[system.tsunami.fake_pnp_read4] 1333type=IsaFake
|
| 1334clock=1000
|
1293fake_mem=false 1294pio_addr=8804615848707
| 1335fake_mem=false 1336pio_addr=8804615848707
|
1295pio_latency=1000
| 1337pio_latency=100000
|
1296pio_size=8 1297ret_bad_addr=false 1298ret_data16=65535 1299ret_data32=4294967295 1300ret_data64=18446744073709551615 1301ret_data8=255 1302system=system 1303update_data=false 1304warn_access= 1305pio=system.iobus.master[15] 1306 1307[system.tsunami.fake_pnp_read5] 1308type=IsaFake
| 1338pio_size=8 1339ret_bad_addr=false 1340ret_data16=65535 1341ret_data32=4294967295 1342ret_data64=18446744073709551615 1343ret_data8=255 1344system=system 1345update_data=false 1346warn_access= 1347pio=system.iobus.master[15] 1348 1349[system.tsunami.fake_pnp_read5] 1350type=IsaFake
|
| 1351clock=1000
|
1309fake_mem=false 1310pio_addr=8804615848771
| 1352fake_mem=false 1353pio_addr=8804615848771
|
1311pio_latency=1000
| 1354pio_latency=100000
|
1312pio_size=8 1313ret_bad_addr=false 1314ret_data16=65535 1315ret_data32=4294967295 1316ret_data64=18446744073709551615 1317ret_data8=255 1318system=system 1319update_data=false 1320warn_access= 1321pio=system.iobus.master[16] 1322 1323[system.tsunami.fake_pnp_read6] 1324type=IsaFake
| 1355pio_size=8 1356ret_bad_addr=false 1357ret_data16=65535 1358ret_data32=4294967295 1359ret_data64=18446744073709551615 1360ret_data8=255 1361system=system 1362update_data=false 1363warn_access= 1364pio=system.iobus.master[16] 1365 1366[system.tsunami.fake_pnp_read6] 1367type=IsaFake
|
| 1368clock=1000
|
1325fake_mem=false 1326pio_addr=8804615848835
| 1369fake_mem=false 1370pio_addr=8804615848835
|
1327pio_latency=1000
| 1371pio_latency=100000
|
1328pio_size=8 1329ret_bad_addr=false 1330ret_data16=65535 1331ret_data32=4294967295 1332ret_data64=18446744073709551615 1333ret_data8=255 1334system=system 1335update_data=false 1336warn_access= 1337pio=system.iobus.master[17] 1338 1339[system.tsunami.fake_pnp_read7] 1340type=IsaFake
| 1372pio_size=8 1373ret_bad_addr=false 1374ret_data16=65535 1375ret_data32=4294967295 1376ret_data64=18446744073709551615 1377ret_data8=255 1378system=system 1379update_data=false 1380warn_access= 1381pio=system.iobus.master[17] 1382 1383[system.tsunami.fake_pnp_read7] 1384type=IsaFake
|
| 1385clock=1000
|
1341fake_mem=false 1342pio_addr=8804615848899
| 1386fake_mem=false 1387pio_addr=8804615848899
|
1343pio_latency=1000
| 1388pio_latency=100000
|
1344pio_size=8 1345ret_bad_addr=false 1346ret_data16=65535 1347ret_data32=4294967295 1348ret_data64=18446744073709551615 1349ret_data8=255 1350system=system 1351update_data=false 1352warn_access= 1353pio=system.iobus.master[18] 1354 1355[system.tsunami.fake_pnp_write] 1356type=IsaFake
| 1389pio_size=8 1390ret_bad_addr=false 1391ret_data16=65535 1392ret_data32=4294967295 1393ret_data64=18446744073709551615 1394ret_data8=255 1395system=system 1396update_data=false 1397warn_access= 1398pio=system.iobus.master[18] 1399 1400[system.tsunami.fake_pnp_write] 1401type=IsaFake
|
| 1402clock=1000
|
1357fake_mem=false 1358pio_addr=8804615850617
| 1403fake_mem=false 1404pio_addr=8804615850617
|
1359pio_latency=1000
| 1405pio_latency=100000
|
1360pio_size=8 1361ret_bad_addr=false 1362ret_data16=65535 1363ret_data32=4294967295 1364ret_data64=18446744073709551615 1365ret_data8=255 1366system=system 1367update_data=false 1368warn_access= 1369pio=system.iobus.master[10] 1370 1371[system.tsunami.fake_ppc] 1372type=IsaFake
| 1406pio_size=8 1407ret_bad_addr=false 1408ret_data16=65535 1409ret_data32=4294967295 1410ret_data64=18446744073709551615 1411ret_data8=255 1412system=system 1413update_data=false 1414warn_access= 1415pio=system.iobus.master[10] 1416 1417[system.tsunami.fake_ppc] 1418type=IsaFake
|
| 1419clock=1000
|
1373fake_mem=false 1374pio_addr=8804615848891
| 1420fake_mem=false 1421pio_addr=8804615848891
|
1375pio_latency=1000
| 1422pio_latency=100000
|
1376pio_size=8 1377ret_bad_addr=false 1378ret_data16=65535 1379ret_data32=4294967295 1380ret_data64=18446744073709551615 1381ret_data8=255 1382system=system 1383update_data=false 1384warn_access= 1385pio=system.iobus.master[7] 1386 1387[system.tsunami.fake_sm_chip] 1388type=IsaFake
| 1423pio_size=8 1424ret_bad_addr=false 1425ret_data16=65535 1426ret_data32=4294967295 1427ret_data64=18446744073709551615 1428ret_data8=255 1429system=system 1430update_data=false 1431warn_access= 1432pio=system.iobus.master[7] 1433 1434[system.tsunami.fake_sm_chip] 1435type=IsaFake
|
| 1436clock=1000
|
1389fake_mem=false 1390pio_addr=8804615848816
| 1437fake_mem=false 1438pio_addr=8804615848816
|
1391pio_latency=1000
| 1439pio_latency=100000
|
1392pio_size=8 1393ret_bad_addr=false 1394ret_data16=65535 1395ret_data32=4294967295 1396ret_data64=18446744073709551615 1397ret_data8=255 1398system=system 1399update_data=false 1400warn_access= 1401pio=system.iobus.master[2] 1402 1403[system.tsunami.fake_uart1] 1404type=IsaFake
| 1440pio_size=8 1441ret_bad_addr=false 1442ret_data16=65535 1443ret_data32=4294967295 1444ret_data64=18446744073709551615 1445ret_data8=255 1446system=system 1447update_data=false 1448warn_access= 1449pio=system.iobus.master[2] 1450 1451[system.tsunami.fake_uart1] 1452type=IsaFake
|
| 1453clock=1000
|
1405fake_mem=false 1406pio_addr=8804615848696
| 1454fake_mem=false 1455pio_addr=8804615848696
|
1407pio_latency=1000
| 1456pio_latency=100000
|
1408pio_size=8 1409ret_bad_addr=false 1410ret_data16=65535 1411ret_data32=4294967295 1412ret_data64=18446744073709551615 1413ret_data8=255 1414system=system 1415update_data=false 1416warn_access= 1417pio=system.iobus.master[3] 1418 1419[system.tsunami.fake_uart2] 1420type=IsaFake
| 1457pio_size=8 1458ret_bad_addr=false 1459ret_data16=65535 1460ret_data32=4294967295 1461ret_data64=18446744073709551615 1462ret_data8=255 1463system=system 1464update_data=false 1465warn_access= 1466pio=system.iobus.master[3] 1467 1468[system.tsunami.fake_uart2] 1469type=IsaFake
|
| 1470clock=1000
|
1421fake_mem=false 1422pio_addr=8804615848936
| 1471fake_mem=false 1472pio_addr=8804615848936
|
1423pio_latency=1000
| 1473pio_latency=100000
|
1424pio_size=8 1425ret_bad_addr=false 1426ret_data16=65535 1427ret_data32=4294967295 1428ret_data64=18446744073709551615 1429ret_data8=255 1430system=system 1431update_data=false 1432warn_access= 1433pio=system.iobus.master[4] 1434 1435[system.tsunami.fake_uart3] 1436type=IsaFake
| 1474pio_size=8 1475ret_bad_addr=false 1476ret_data16=65535 1477ret_data32=4294967295 1478ret_data64=18446744073709551615 1479ret_data8=255 1480system=system 1481update_data=false 1482warn_access= 1483pio=system.iobus.master[4] 1484 1485[system.tsunami.fake_uart3] 1486type=IsaFake
|
| 1487clock=1000
|
1437fake_mem=false 1438pio_addr=8804615848680
| 1488fake_mem=false 1489pio_addr=8804615848680
|
1439pio_latency=1000
| 1490pio_latency=100000
|
1440pio_size=8 1441ret_bad_addr=false 1442ret_data16=65535 1443ret_data32=4294967295 1444ret_data64=18446744073709551615 1445ret_data8=255 1446system=system 1447update_data=false 1448warn_access= 1449pio=system.iobus.master[5] 1450 1451[system.tsunami.fake_uart4] 1452type=IsaFake
| 1491pio_size=8 1492ret_bad_addr=false 1493ret_data16=65535 1494ret_data32=4294967295 1495ret_data64=18446744073709551615 1496ret_data8=255 1497system=system 1498update_data=false 1499warn_access= 1500pio=system.iobus.master[5] 1501 1502[system.tsunami.fake_uart4] 1503type=IsaFake
|
| 1504clock=1000
|
1453fake_mem=false 1454pio_addr=8804615848944
| 1505fake_mem=false 1506pio_addr=8804615848944
|
1455pio_latency=1000
| 1507pio_latency=100000
|
1456pio_size=8 1457ret_bad_addr=false 1458ret_data16=65535 1459ret_data32=4294967295 1460ret_data64=18446744073709551615 1461ret_data8=255 1462system=system 1463update_data=false 1464warn_access= 1465pio=system.iobus.master[6] 1466 1467[system.tsunami.fb] 1468type=BadDevice
| 1508pio_size=8 1509ret_bad_addr=false 1510ret_data16=65535 1511ret_data32=4294967295 1512ret_data64=18446744073709551615 1513ret_data8=255 1514system=system 1515update_data=false 1516warn_access= 1517pio=system.iobus.master[6] 1518 1519[system.tsunami.fb] 1520type=BadDevice
|
| 1521clock=1000
|
1469devicename=FrameBuffer 1470pio_addr=8804615848912
| 1522devicename=FrameBuffer 1523pio_addr=8804615848912
|
1471pio_latency=1000
| 1524pio_latency=100000
|
1472system=system 1473pio=system.iobus.master[21] 1474 1475[system.tsunami.ide] 1476type=IdeController 1477BAR0=1 1478BAR0LegacyIO=false 1479BAR0Size=8 1480BAR1=1 1481BAR1LegacyIO=false 1482BAR1Size=4 1483BAR2=1 1484BAR2LegacyIO=false 1485BAR2Size=8 1486BAR3=1 1487BAR3LegacyIO=false 1488BAR3Size=4 1489BAR4=1 1490BAR4LegacyIO=false 1491BAR4Size=16 1492BAR5=1 1493BAR5LegacyIO=false 1494BAR5Size=0 1495BIST=0 1496CacheLineSize=0 1497CardbusCIS=0 1498ClassCode=1 1499Command=0 1500DeviceID=28945 1501ExpansionROM=0 1502HeaderType=0 1503InterruptLine=31 1504InterruptPin=1 1505LatencyTimer=0 1506MaximumLatency=0 1507MinimumGrant=0 1508ProgIF=133 1509Revision=0 1510Status=640 1511SubClassCode=1 1512SubsystemID=0 1513SubsystemVendorID=0 1514VendorID=32902
| 1525system=system 1526pio=system.iobus.master[21] 1527 1528[system.tsunami.ide] 1529type=IdeController 1530BAR0=1 1531BAR0LegacyIO=false 1532BAR0Size=8 1533BAR1=1 1534BAR1LegacyIO=false 1535BAR1Size=4 1536BAR2=1 1537BAR2LegacyIO=false 1538BAR2Size=8 1539BAR3=1 1540BAR3LegacyIO=false 1541BAR3Size=4 1542BAR4=1 1543BAR4LegacyIO=false 1544BAR4Size=16 1545BAR5=1 1546BAR5LegacyIO=false 1547BAR5Size=0 1548BIST=0 1549CacheLineSize=0 1550CardbusCIS=0 1551ClassCode=1 1552Command=0 1553DeviceID=28945 1554ExpansionROM=0 1555HeaderType=0 1556InterruptLine=31 1557InterruptPin=1 1558LatencyTimer=0 1559MaximumLatency=0 1560MinimumGrant=0 1561ProgIF=133 1562Revision=0 1563Status=640 1564SubClassCode=1 1565SubsystemID=0 1566SubsystemVendorID=0 1567VendorID=32902
|
| 1568clock=1000
|
1515config_latency=20000 1516ctrl_offset=0 1517disks=system.disk0 system.disk2 1518io_shift=0
| 1569config_latency=20000 1570ctrl_offset=0 1571disks=system.disk0 system.disk2 1572io_shift=0
|
1519max_backoff_delay=10000000 1520min_backoff_delay=4000
| |
1521pci_bus=0 1522pci_dev=0 1523pci_func=0
| 1573pci_bus=0 1574pci_dev=0 1575pci_func=0
|
1524pio_latency=1000
| 1576pio_latency=30000
|
1525platform=system.tsunami 1526system=system 1527config=system.iobus.master[26] 1528dma=system.iobus.slave[1] 1529pio=system.iobus.master[25] 1530 1531[system.tsunami.io] 1532type=TsunamiIO
| 1577platform=system.tsunami 1578system=system 1579config=system.iobus.master[26] 1580dma=system.iobus.slave[1] 1581pio=system.iobus.master[25] 1582 1583[system.tsunami.io] 1584type=TsunamiIO
|
| 1585clock=1000
|
1533frequency=976562500 1534pio_addr=8804615847936
| 1586frequency=976562500 1587pio_addr=8804615847936
|
1535pio_latency=1000
| 1588pio_latency=100000
|
1536system=system 1537time=Thu Jan 1 00:00:00 2009 1538tsunami=system.tsunami 1539year_is_bcd=false 1540pio=system.iobus.master[22] 1541 1542[system.tsunami.pchip] 1543type=TsunamiPChip
| 1589system=system 1590time=Thu Jan 1 00:00:00 2009 1591tsunami=system.tsunami 1592year_is_bcd=false 1593pio=system.iobus.master[22] 1594 1595[system.tsunami.pchip] 1596type=TsunamiPChip
|
| 1597clock=1000
|
1544pio_addr=8802535473152
| 1598pio_addr=8802535473152
|
1545pio_latency=1000
| 1599pio_latency=100000
|
1546system=system 1547tsunami=system.tsunami 1548pio=system.iobus.master[1] 1549 1550[system.tsunami.pciconfig] 1551type=PciConfigAll 1552bus=0
| 1600system=system 1601tsunami=system.tsunami 1602pio=system.iobus.master[1] 1603 1604[system.tsunami.pciconfig] 1605type=PciConfigAll 1606bus=0
|
1553pio_latency=1
| 1607clock=1000 1608pio_latency=30000
|
1554platform=system.tsunami 1555size=16777216 1556system=system 1557pio=system.iobus.default 1558 1559[system.tsunami.uart] 1560type=Uart8250
| 1609platform=system.tsunami 1610size=16777216 1611system=system 1612pio=system.iobus.default 1613 1614[system.tsunami.uart] 1615type=Uart8250
|
| 1616clock=1000
|
1561pio_addr=8804615848952
| 1617pio_addr=8804615848952
|
1562pio_latency=1000
| 1618pio_latency=100000
|
1563platform=system.tsunami 1564system=system 1565terminal=system.terminal 1566pio=system.iobus.master[23] 1567
| 1619platform=system.tsunami 1620system=system 1621terminal=system.terminal 1622pio=system.iobus.master[23] 1623
|