1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxAlphaSystem
11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
12boot_cpu_frequency=500
13boot_osflags=root=/dev/hda1 console=ttyS0
14console=/dist/m5/system/binaries/console
15init_param=0
16kernel=/dist/m5/system/binaries/vmlinux
17load_addr_mask=1099511627775
18mem_mode=timing
19memories=system.physmem
20num_work_ids=16
21pal=/dist/m5/system/binaries/ts_osfpal
| 1[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxAlphaSystem
11children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
12boot_cpu_frequency=500
13boot_osflags=root=/dev/hda1 console=ttyS0
14console=/dist/m5/system/binaries/console
15init_param=0
16kernel=/dist/m5/system/binaries/vmlinux
17load_addr_mask=1099511627775
18mem_mode=timing
19memories=system.physmem
20num_work_ids=16
21pal=/dist/m5/system/binaries/ts_osfpal
|
22physmem=system.physmem
| |
23readfile=tests/halt.sh
24symbolfile=
25system_rev=1024
26system_type=34
27work_begin_ckpt_count=0
28work_begin_cpu_id_exit=-1
29work_begin_exit_count=0
30work_cpus_ckpt_count=0
31work_end_ckpt_count=0
32work_end_exit_count=0
33work_item_id=-1
| 22readfile=tests/halt.sh
23symbolfile=
24system_rev=1024
25system_type=34
26work_begin_ckpt_count=0
27work_begin_cpu_id_exit=-1
28work_begin_exit_count=0
29work_cpus_ckpt_count=0
30work_end_ckpt_count=0
31work_end_exit_count=0
32work_item_id=-1
|
34system_port=system.membus.port[2]
| 33system_port=system.membus.slave[0]
|
35
36[system.bridge]
37type=Bridge
38delay=50000
39nack_delay=4000
40ranges=8796093022208:18446744073709551615
41req_size=16
42resp_size=16
43write_ack=false
| 34
35[system.bridge]
36type=Bridge
37delay=50000
38nack_delay=4000
39ranges=8796093022208:18446744073709551615
40req_size=16
41resp_size=16
42write_ack=false
|
44master=system.iobus.port[0]
45slave=system.membus.port[0]
| 43master=system.iobus.slave[0]
44slave=system.membus.master[0]
|
46
47[system.cpu0]
48type=DerivO3CPU
49children=dcache dtb fuPool icache interrupts itb tracer
50BTBEntries=4096
51BTBTagSize=16
52LFSTSize=1024
53LQEntries=32
54LSQCheckLoads=true
55LSQDepCheckShift=4
56RASSize=16
57SQEntries=32
58SSITSize=1024
59activity=0
60backComSize=5
61cachePorts=200
62checker=Null
63choiceCtrBits=2
64choicePredictorSize=8192
65clock=500
66commitToDecodeDelay=1
67commitToFetchDelay=1
68commitToIEWDelay=1
69commitToRenameDelay=1
70commitWidth=8
71cpu_id=0
72decodeToFetchDelay=1
73decodeToRenameDelay=1
74decodeWidth=8
75defer_registration=false
76dispatchWidth=8
77do_checkpoint_insts=true
78do_quiesce=true
79do_statistics_insts=true
80dtb=system.cpu0.dtb
81fetchToDecodeDelay=1
82fetchTrapLatency=1
83fetchWidth=8
84forwardComSize=5
85fuPool=system.cpu0.fuPool
86function_trace=false
87function_trace_start=0
88globalCtrBits=2
89globalHistoryBits=13
90globalPredictorSize=8192
91iewToCommitDelay=1
92iewToDecodeDelay=1
93iewToFetchDelay=1
94iewToRenameDelay=1
95instShiftAmt=2
96interrupts=system.cpu0.interrupts
97issueToExecuteDelay=1
98issueWidth=8
99itb=system.cpu0.itb
100localCtrBits=2
101localHistoryBits=11
102localHistoryTableSize=2048
103localPredictorSize=2048
104max_insts_all_threads=0
105max_insts_any_thread=0
106max_loads_all_threads=0
107max_loads_any_thread=0
108needsTSO=false
109numIQEntries=64
110numPhysFloatRegs=256
111numPhysIntRegs=256
112numROBEntries=192
113numRobs=1
114numThreads=1
115phase=0
116predType=tournament
117profile=0
118progress_interval=0
119renameToDecodeDelay=1
120renameToFetchDelay=1
121renameToIEWDelay=2
122renameToROBDelay=1
123renameWidth=8
124smtCommitPolicy=RoundRobin
125smtFetchPolicy=SingleThread
126smtIQPolicy=Partitioned
127smtIQThreshold=100
128smtLSQPolicy=Partitioned
129smtLSQThreshold=100
130smtNumFetchingThreads=1
131smtROBPolicy=Partitioned
132smtROBThreshold=100
133squashWidth=8
134store_set_clear_period=250000
135system=system
136tracer=system.cpu0.tracer
137trapLatency=13
138wbDepth=1
139wbWidth=8
140workload=
141dcache_port=system.cpu0.dcache.cpu_side
142icache_port=system.cpu0.icache.cpu_side
143
144[system.cpu0.dcache]
145type=BaseCache
| 45
46[system.cpu0]
47type=DerivO3CPU
48children=dcache dtb fuPool icache interrupts itb tracer
49BTBEntries=4096
50BTBTagSize=16
51LFSTSize=1024
52LQEntries=32
53LSQCheckLoads=true
54LSQDepCheckShift=4
55RASSize=16
56SQEntries=32
57SSITSize=1024
58activity=0
59backComSize=5
60cachePorts=200
61checker=Null
62choiceCtrBits=2
63choicePredictorSize=8192
64clock=500
65commitToDecodeDelay=1
66commitToFetchDelay=1
67commitToIEWDelay=1
68commitToRenameDelay=1
69commitWidth=8
70cpu_id=0
71decodeToFetchDelay=1
72decodeToRenameDelay=1
73decodeWidth=8
74defer_registration=false
75dispatchWidth=8
76do_checkpoint_insts=true
77do_quiesce=true
78do_statistics_insts=true
79dtb=system.cpu0.dtb
80fetchToDecodeDelay=1
81fetchTrapLatency=1
82fetchWidth=8
83forwardComSize=5
84fuPool=system.cpu0.fuPool
85function_trace=false
86function_trace_start=0
87globalCtrBits=2
88globalHistoryBits=13
89globalPredictorSize=8192
90iewToCommitDelay=1
91iewToDecodeDelay=1
92iewToFetchDelay=1
93iewToRenameDelay=1
94instShiftAmt=2
95interrupts=system.cpu0.interrupts
96issueToExecuteDelay=1
97issueWidth=8
98itb=system.cpu0.itb
99localCtrBits=2
100localHistoryBits=11
101localHistoryTableSize=2048
102localPredictorSize=2048
103max_insts_all_threads=0
104max_insts_any_thread=0
105max_loads_all_threads=0
106max_loads_any_thread=0
107needsTSO=false
108numIQEntries=64
109numPhysFloatRegs=256
110numPhysIntRegs=256
111numROBEntries=192
112numRobs=1
113numThreads=1
114phase=0
115predType=tournament
116profile=0
117progress_interval=0
118renameToDecodeDelay=1
119renameToFetchDelay=1
120renameToIEWDelay=2
121renameToROBDelay=1
122renameWidth=8
123smtCommitPolicy=RoundRobin
124smtFetchPolicy=SingleThread
125smtIQPolicy=Partitioned
126smtIQThreshold=100
127smtLSQPolicy=Partitioned
128smtLSQThreshold=100
129smtNumFetchingThreads=1
130smtROBPolicy=Partitioned
131smtROBThreshold=100
132squashWidth=8
133store_set_clear_period=250000
134system=system
135tracer=system.cpu0.tracer
136trapLatency=13
137wbDepth=1
138wbWidth=8
139workload=
140dcache_port=system.cpu0.dcache.cpu_side
141icache_port=system.cpu0.icache.cpu_side
142
143[system.cpu0.dcache]
144type=BaseCache
|
146addr_range=0:18446744073709551615
| 145addr_ranges=0:18446744073709551615
|
147assoc=4
148block_size=64
149forward_snoops=true
150hash_delay=1
151is_top_level=true
152latency=1000
153max_miss_count=0
154mshrs=4
155prefetch_on_access=false
156prefetcher=Null
157prioritizeRequests=false
158repl=Null
159size=32768
160subblock_size=0
161system=system
162tgts_per_mshr=20
163trace_addr=0
164two_queue=false
165write_buffers=8
166cpu_side=system.cpu0.dcache_port
| 146assoc=4
147block_size=64
148forward_snoops=true
149hash_delay=1
150is_top_level=true
151latency=1000
152max_miss_count=0
153mshrs=4
154prefetch_on_access=false
155prefetcher=Null
156prioritizeRequests=false
157repl=Null
158size=32768
159subblock_size=0
160system=system
161tgts_per_mshr=20
162trace_addr=0
163two_queue=false
164write_buffers=8
165cpu_side=system.cpu0.dcache_port
|
167mem_side=system.toL2Bus.port[2]
| 166mem_side=system.toL2Bus.slave[1]
|
168
169[system.cpu0.dtb]
170type=AlphaTLB
171size=64
172
173[system.cpu0.fuPool]
174type=FUPool
175children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
176FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
177
178[system.cpu0.fuPool.FUList0]
179type=FUDesc
180children=opList
181count=6
182opList=system.cpu0.fuPool.FUList0.opList
183
184[system.cpu0.fuPool.FUList0.opList]
185type=OpDesc
186issueLat=1
187opClass=IntAlu
188opLat=1
189
190[system.cpu0.fuPool.FUList1]
191type=FUDesc
192children=opList0 opList1
193count=2
194opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
195
196[system.cpu0.fuPool.FUList1.opList0]
197type=OpDesc
198issueLat=1
199opClass=IntMult
200opLat=3
201
202[system.cpu0.fuPool.FUList1.opList1]
203type=OpDesc
204issueLat=19
205opClass=IntDiv
206opLat=20
207
208[system.cpu0.fuPool.FUList2]
209type=FUDesc
210children=opList0 opList1 opList2
211count=4
212opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
213
214[system.cpu0.fuPool.FUList2.opList0]
215type=OpDesc
216issueLat=1
217opClass=FloatAdd
218opLat=2
219
220[system.cpu0.fuPool.FUList2.opList1]
221type=OpDesc
222issueLat=1
223opClass=FloatCmp
224opLat=2
225
226[system.cpu0.fuPool.FUList2.opList2]
227type=OpDesc
228issueLat=1
229opClass=FloatCvt
230opLat=2
231
232[system.cpu0.fuPool.FUList3]
233type=FUDesc
234children=opList0 opList1 opList2
235count=2
236opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
237
238[system.cpu0.fuPool.FUList3.opList0]
239type=OpDesc
240issueLat=1
241opClass=FloatMult
242opLat=4
243
244[system.cpu0.fuPool.FUList3.opList1]
245type=OpDesc
246issueLat=12
247opClass=FloatDiv
248opLat=12
249
250[system.cpu0.fuPool.FUList3.opList2]
251type=OpDesc
252issueLat=24
253opClass=FloatSqrt
254opLat=24
255
256[system.cpu0.fuPool.FUList4]
257type=FUDesc
258children=opList
259count=0
260opList=system.cpu0.fuPool.FUList4.opList
261
262[system.cpu0.fuPool.FUList4.opList]
263type=OpDesc
264issueLat=1
265opClass=MemRead
266opLat=1
267
268[system.cpu0.fuPool.FUList5]
269type=FUDesc
270children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
271count=4
272opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
273
274[system.cpu0.fuPool.FUList5.opList00]
275type=OpDesc
276issueLat=1
277opClass=SimdAdd
278opLat=1
279
280[system.cpu0.fuPool.FUList5.opList01]
281type=OpDesc
282issueLat=1
283opClass=SimdAddAcc
284opLat=1
285
286[system.cpu0.fuPool.FUList5.opList02]
287type=OpDesc
288issueLat=1
289opClass=SimdAlu
290opLat=1
291
292[system.cpu0.fuPool.FUList5.opList03]
293type=OpDesc
294issueLat=1
295opClass=SimdCmp
296opLat=1
297
298[system.cpu0.fuPool.FUList5.opList04]
299type=OpDesc
300issueLat=1
301opClass=SimdCvt
302opLat=1
303
304[system.cpu0.fuPool.FUList5.opList05]
305type=OpDesc
306issueLat=1
307opClass=SimdMisc
308opLat=1
309
310[system.cpu0.fuPool.FUList5.opList06]
311type=OpDesc
312issueLat=1
313opClass=SimdMult
314opLat=1
315
316[system.cpu0.fuPool.FUList5.opList07]
317type=OpDesc
318issueLat=1
319opClass=SimdMultAcc
320opLat=1
321
322[system.cpu0.fuPool.FUList5.opList08]
323type=OpDesc
324issueLat=1
325opClass=SimdShift
326opLat=1
327
328[system.cpu0.fuPool.FUList5.opList09]
329type=OpDesc
330issueLat=1
331opClass=SimdShiftAcc
332opLat=1
333
334[system.cpu0.fuPool.FUList5.opList10]
335type=OpDesc
336issueLat=1
337opClass=SimdSqrt
338opLat=1
339
340[system.cpu0.fuPool.FUList5.opList11]
341type=OpDesc
342issueLat=1
343opClass=SimdFloatAdd
344opLat=1
345
346[system.cpu0.fuPool.FUList5.opList12]
347type=OpDesc
348issueLat=1
349opClass=SimdFloatAlu
350opLat=1
351
352[system.cpu0.fuPool.FUList5.opList13]
353type=OpDesc
354issueLat=1
355opClass=SimdFloatCmp
356opLat=1
357
358[system.cpu0.fuPool.FUList5.opList14]
359type=OpDesc
360issueLat=1
361opClass=SimdFloatCvt
362opLat=1
363
364[system.cpu0.fuPool.FUList5.opList15]
365type=OpDesc
366issueLat=1
367opClass=SimdFloatDiv
368opLat=1
369
370[system.cpu0.fuPool.FUList5.opList16]
371type=OpDesc
372issueLat=1
373opClass=SimdFloatMisc
374opLat=1
375
376[system.cpu0.fuPool.FUList5.opList17]
377type=OpDesc
378issueLat=1
379opClass=SimdFloatMult
380opLat=1
381
382[system.cpu0.fuPool.FUList5.opList18]
383type=OpDesc
384issueLat=1
385opClass=SimdFloatMultAcc
386opLat=1
387
388[system.cpu0.fuPool.FUList5.opList19]
389type=OpDesc
390issueLat=1
391opClass=SimdFloatSqrt
392opLat=1
393
394[system.cpu0.fuPool.FUList6]
395type=FUDesc
396children=opList
397count=0
398opList=system.cpu0.fuPool.FUList6.opList
399
400[system.cpu0.fuPool.FUList6.opList]
401type=OpDesc
402issueLat=1
403opClass=MemWrite
404opLat=1
405
406[system.cpu0.fuPool.FUList7]
407type=FUDesc
408children=opList0 opList1
409count=4
410opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
411
412[system.cpu0.fuPool.FUList7.opList0]
413type=OpDesc
414issueLat=1
415opClass=MemRead
416opLat=1
417
418[system.cpu0.fuPool.FUList7.opList1]
419type=OpDesc
420issueLat=1
421opClass=MemWrite
422opLat=1
423
424[system.cpu0.fuPool.FUList8]
425type=FUDesc
426children=opList
427count=1
428opList=system.cpu0.fuPool.FUList8.opList
429
430[system.cpu0.fuPool.FUList8.opList]
431type=OpDesc
432issueLat=3
433opClass=IprAccess
434opLat=3
435
436[system.cpu0.icache]
437type=BaseCache
| 167
168[system.cpu0.dtb]
169type=AlphaTLB
170size=64
171
172[system.cpu0.fuPool]
173type=FUPool
174children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
175FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
176
177[system.cpu0.fuPool.FUList0]
178type=FUDesc
179children=opList
180count=6
181opList=system.cpu0.fuPool.FUList0.opList
182
183[system.cpu0.fuPool.FUList0.opList]
184type=OpDesc
185issueLat=1
186opClass=IntAlu
187opLat=1
188
189[system.cpu0.fuPool.FUList1]
190type=FUDesc
191children=opList0 opList1
192count=2
193opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
194
195[system.cpu0.fuPool.FUList1.opList0]
196type=OpDesc
197issueLat=1
198opClass=IntMult
199opLat=3
200
201[system.cpu0.fuPool.FUList1.opList1]
202type=OpDesc
203issueLat=19
204opClass=IntDiv
205opLat=20
206
207[system.cpu0.fuPool.FUList2]
208type=FUDesc
209children=opList0 opList1 opList2
210count=4
211opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
212
213[system.cpu0.fuPool.FUList2.opList0]
214type=OpDesc
215issueLat=1
216opClass=FloatAdd
217opLat=2
218
219[system.cpu0.fuPool.FUList2.opList1]
220type=OpDesc
221issueLat=1
222opClass=FloatCmp
223opLat=2
224
225[system.cpu0.fuPool.FUList2.opList2]
226type=OpDesc
227issueLat=1
228opClass=FloatCvt
229opLat=2
230
231[system.cpu0.fuPool.FUList3]
232type=FUDesc
233children=opList0 opList1 opList2
234count=2
235opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
236
237[system.cpu0.fuPool.FUList3.opList0]
238type=OpDesc
239issueLat=1
240opClass=FloatMult
241opLat=4
242
243[system.cpu0.fuPool.FUList3.opList1]
244type=OpDesc
245issueLat=12
246opClass=FloatDiv
247opLat=12
248
249[system.cpu0.fuPool.FUList3.opList2]
250type=OpDesc
251issueLat=24
252opClass=FloatSqrt
253opLat=24
254
255[system.cpu0.fuPool.FUList4]
256type=FUDesc
257children=opList
258count=0
259opList=system.cpu0.fuPool.FUList4.opList
260
261[system.cpu0.fuPool.FUList4.opList]
262type=OpDesc
263issueLat=1
264opClass=MemRead
265opLat=1
266
267[system.cpu0.fuPool.FUList5]
268type=FUDesc
269children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
270count=4
271opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
272
273[system.cpu0.fuPool.FUList5.opList00]
274type=OpDesc
275issueLat=1
276opClass=SimdAdd
277opLat=1
278
279[system.cpu0.fuPool.FUList5.opList01]
280type=OpDesc
281issueLat=1
282opClass=SimdAddAcc
283opLat=1
284
285[system.cpu0.fuPool.FUList5.opList02]
286type=OpDesc
287issueLat=1
288opClass=SimdAlu
289opLat=1
290
291[system.cpu0.fuPool.FUList5.opList03]
292type=OpDesc
293issueLat=1
294opClass=SimdCmp
295opLat=1
296
297[system.cpu0.fuPool.FUList5.opList04]
298type=OpDesc
299issueLat=1
300opClass=SimdCvt
301opLat=1
302
303[system.cpu0.fuPool.FUList5.opList05]
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309[system.cpu0.fuPool.FUList5.opList06]
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315[system.cpu0.fuPool.FUList5.opList07]
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321[system.cpu0.fuPool.FUList5.opList08]
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327[system.cpu0.fuPool.FUList5.opList09]
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333[system.cpu0.fuPool.FUList5.opList10]
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339[system.cpu0.fuPool.FUList5.opList11]
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345[system.cpu0.fuPool.FUList5.opList12]
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351[system.cpu0.fuPool.FUList5.opList13]
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357[system.cpu0.fuPool.FUList5.opList14]
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363[system.cpu0.fuPool.FUList5.opList15]
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369[system.cpu0.fuPool.FUList5.opList16]
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381[system.cpu0.fuPool.FUList5.opList18]
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387[system.cpu0.fuPool.FUList5.opList19]
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393[system.cpu0.fuPool.FUList6]
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399[system.cpu0.fuPool.FUList6.opList]
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405[system.cpu0.fuPool.FUList7]
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417[system.cpu0.fuPool.FUList7.opList1]
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429[system.cpu0.fuPool.FUList8.opList]
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|
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|
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|
459mem_side=system.toL2Bus.port[1]
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|
460
461[system.cpu0.interrupts]
462type=AlphaInterrupts
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464[system.cpu0.itb]
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468[system.cpu0.tracer]
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471[system.cpu1]
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568[system.cpu1.dcache]
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| 459
460[system.cpu0.interrupts]
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462
463[system.cpu0.itb]
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466
467[system.cpu0.tracer]
468type=ExeTracer
469
470[system.cpu1]
471type=DerivO3CPU
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|
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|
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|
591mem_side=system.toL2Bus.port[4]
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|
592
593[system.cpu1.dtb]
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597[system.cpu1.fuPool]
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602[system.cpu1.fuPool.FUList0]
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608[system.cpu1.fuPool.FUList0.opList]
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620[system.cpu1.fuPool.FUList1.opList0]
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626[system.cpu1.fuPool.FUList1.opList1]
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638[system.cpu1.fuPool.FUList2.opList0]
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662[system.cpu1.fuPool.FUList3.opList0]
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698[system.cpu1.fuPool.FUList5.opList00]
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740[system.cpu1.fuPool.FUList5.opList07]
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752[system.cpu1.fuPool.FUList5.opList09]
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758[system.cpu1.fuPool.FUList5.opList10]
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770[system.cpu1.fuPool.FUList5.opList12]
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776[system.cpu1.fuPool.FUList5.opList13]
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800[system.cpu1.fuPool.FUList5.opList17]
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806[system.cpu1.fuPool.FUList5.opList18]
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812[system.cpu1.fuPool.FUList5.opList19]
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818[system.cpu1.fuPool.FUList6]
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824[system.cpu1.fuPool.FUList6.opList]
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830[system.cpu1.fuPool.FUList7]
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836[system.cpu1.fuPool.FUList7.opList0]
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842[system.cpu1.fuPool.FUList7.opList1]
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854[system.cpu1.fuPool.FUList8.opList]
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857opClass=IprAccess
858opLat=3
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860[system.cpu1.icache]
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| 591
592[system.cpu1.dtb]
593type=AlphaTLB
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595
596[system.cpu1.fuPool]
597type=FUPool
598children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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600
601[system.cpu1.fuPool.FUList0]
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607[system.cpu1.fuPool.FUList0.opList]
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613[system.cpu1.fuPool.FUList1]
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619[system.cpu1.fuPool.FUList1.opList0]
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625[system.cpu1.fuPool.FUList1.opList1]
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631[system.cpu1.fuPool.FUList2]
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635opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
636
637[system.cpu1.fuPool.FUList2.opList0]
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642
643[system.cpu1.fuPool.FUList2.opList1]
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649[system.cpu1.fuPool.FUList2.opList2]
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654
655[system.cpu1.fuPool.FUList3]
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660
661[system.cpu1.fuPool.FUList3.opList0]
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665opLat=4
666
667[system.cpu1.fuPool.FUList3.opList1]
668type=OpDesc
669issueLat=12
670opClass=FloatDiv
671opLat=12
672
673[system.cpu1.fuPool.FUList3.opList2]
674type=OpDesc
675issueLat=24
676opClass=FloatSqrt
677opLat=24
678
679[system.cpu1.fuPool.FUList4]
680type=FUDesc
681children=opList
682count=0
683opList=system.cpu1.fuPool.FUList4.opList
684
685[system.cpu1.fuPool.FUList4.opList]
686type=OpDesc
687issueLat=1
688opClass=MemRead
689opLat=1
690
691[system.cpu1.fuPool.FUList5]
692type=FUDesc
693children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
694count=4
695opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
696
697[system.cpu1.fuPool.FUList5.opList00]
698type=OpDesc
699issueLat=1
700opClass=SimdAdd
701opLat=1
702
703[system.cpu1.fuPool.FUList5.opList01]
704type=OpDesc
705issueLat=1
706opClass=SimdAddAcc
707opLat=1
708
709[system.cpu1.fuPool.FUList5.opList02]
710type=OpDesc
711issueLat=1
712opClass=SimdAlu
713opLat=1
714
715[system.cpu1.fuPool.FUList5.opList03]
716type=OpDesc
717issueLat=1
718opClass=SimdCmp
719opLat=1
720
721[system.cpu1.fuPool.FUList5.opList04]
722type=OpDesc
723issueLat=1
724opClass=SimdCvt
725opLat=1
726
727[system.cpu1.fuPool.FUList5.opList05]
728type=OpDesc
729issueLat=1
730opClass=SimdMisc
731opLat=1
732
733[system.cpu1.fuPool.FUList5.opList06]
734type=OpDesc
735issueLat=1
736opClass=SimdMult
737opLat=1
738
739[system.cpu1.fuPool.FUList5.opList07]
740type=OpDesc
741issueLat=1
742opClass=SimdMultAcc
743opLat=1
744
745[system.cpu1.fuPool.FUList5.opList08]
746type=OpDesc
747issueLat=1
748opClass=SimdShift
749opLat=1
750
751[system.cpu1.fuPool.FUList5.opList09]
752type=OpDesc
753issueLat=1
754opClass=SimdShiftAcc
755opLat=1
756
757[system.cpu1.fuPool.FUList5.opList10]
758type=OpDesc
759issueLat=1
760opClass=SimdSqrt
761opLat=1
762
763[system.cpu1.fuPool.FUList5.opList11]
764type=OpDesc
765issueLat=1
766opClass=SimdFloatAdd
767opLat=1
768
769[system.cpu1.fuPool.FUList5.opList12]
770type=OpDesc
771issueLat=1
772opClass=SimdFloatAlu
773opLat=1
774
775[system.cpu1.fuPool.FUList5.opList13]
776type=OpDesc
777issueLat=1
778opClass=SimdFloatCmp
779opLat=1
780
781[system.cpu1.fuPool.FUList5.opList14]
782type=OpDesc
783issueLat=1
784opClass=SimdFloatCvt
785opLat=1
786
787[system.cpu1.fuPool.FUList5.opList15]
788type=OpDesc
789issueLat=1
790opClass=SimdFloatDiv
791opLat=1
792
793[system.cpu1.fuPool.FUList5.opList16]
794type=OpDesc
795issueLat=1
796opClass=SimdFloatMisc
797opLat=1
798
799[system.cpu1.fuPool.FUList5.opList17]
800type=OpDesc
801issueLat=1
802opClass=SimdFloatMult
803opLat=1
804
805[system.cpu1.fuPool.FUList5.opList18]
806type=OpDesc
807issueLat=1
808opClass=SimdFloatMultAcc
809opLat=1
810
811[system.cpu1.fuPool.FUList5.opList19]
812type=OpDesc
813issueLat=1
814opClass=SimdFloatSqrt
815opLat=1
816
817[system.cpu1.fuPool.FUList6]
818type=FUDesc
819children=opList
820count=0
821opList=system.cpu1.fuPool.FUList6.opList
822
823[system.cpu1.fuPool.FUList6.opList]
824type=OpDesc
825issueLat=1
826opClass=MemWrite
827opLat=1
828
829[system.cpu1.fuPool.FUList7]
830type=FUDesc
831children=opList0 opList1
832count=4
833opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
834
835[system.cpu1.fuPool.FUList7.opList0]
836type=OpDesc
837issueLat=1
838opClass=MemRead
839opLat=1
840
841[system.cpu1.fuPool.FUList7.opList1]
842type=OpDesc
843issueLat=1
844opClass=MemWrite
845opLat=1
846
847[system.cpu1.fuPool.FUList8]
848type=FUDesc
849children=opList
850count=1
851opList=system.cpu1.fuPool.FUList8.opList
852
853[system.cpu1.fuPool.FUList8.opList]
854type=OpDesc
855issueLat=3
856opClass=IprAccess
857opLat=3
858
859[system.cpu1.icache]
860type=BaseCache
|
862addr_range=0:18446744073709551615
| 861addr_ranges=0:18446744073709551615
|
863assoc=1
864block_size=64
865forward_snoops=true
866hash_delay=1
867is_top_level=true
868latency=1000
869max_miss_count=0
870mshrs=4
871prefetch_on_access=false
872prefetcher=Null
873prioritizeRequests=false
874repl=Null
875size=32768
876subblock_size=0
877system=system
878tgts_per_mshr=20
879trace_addr=0
880two_queue=false
881write_buffers=8
882cpu_side=system.cpu1.icache_port
| 862assoc=1
863block_size=64
864forward_snoops=true
865hash_delay=1
866is_top_level=true
867latency=1000
868max_miss_count=0
869mshrs=4
870prefetch_on_access=false
871prefetcher=Null
872prioritizeRequests=false
873repl=Null
874size=32768
875subblock_size=0
876system=system
877tgts_per_mshr=20
878trace_addr=0
879two_queue=false
880write_buffers=8
881cpu_side=system.cpu1.icache_port
|
883mem_side=system.toL2Bus.port[3]
| 882mem_side=system.toL2Bus.slave[2]
|
884
885[system.cpu1.interrupts]
886type=AlphaInterrupts
887
888[system.cpu1.itb]
889type=AlphaTLB
890size=48
891
892[system.cpu1.tracer]
893type=ExeTracer
894
895[system.disk0]
896type=IdeDisk
897children=image
898delay=1000000
899driveID=master
900image=system.disk0.image
901
902[system.disk0.image]
903type=CowDiskImage
904children=child
905child=system.disk0.image.child
906image_file=
907read_only=false
908table_size=65536
909
910[system.disk0.image.child]
911type=RawDiskImage
912image_file=/dist/m5/system/disks/linux-latest.img
913read_only=true
914
915[system.disk2]
916type=IdeDisk
917children=image
918delay=1000000
919driveID=master
920image=system.disk2.image
921
922[system.disk2.image]
923type=CowDiskImage
924children=child
925child=system.disk2.image.child
926image_file=
927read_only=false
928table_size=65536
929
930[system.disk2.image.child]
931type=RawDiskImage
932image_file=/dist/m5/system/disks/linux-bigswap2.img
933read_only=true
934
935[system.intrctrl]
936type=IntrControl
937sys=system
938
939[system.iobus]
940type=Bus
941block_size=64
942bus_id=0
943clock=1000
944header_cycles=1
945use_default_range=true
946width=64
947default=system.tsunami.pciconfig.pio
| 883
884[system.cpu1.interrupts]
885type=AlphaInterrupts
886
887[system.cpu1.itb]
888type=AlphaTLB
889size=48
890
891[system.cpu1.tracer]
892type=ExeTracer
893
894[system.disk0]
895type=IdeDisk
896children=image
897delay=1000000
898driveID=master
899image=system.disk0.image
900
901[system.disk0.image]
902type=CowDiskImage
903children=child
904child=system.disk0.image.child
905image_file=
906read_only=false
907table_size=65536
908
909[system.disk0.image.child]
910type=RawDiskImage
911image_file=/dist/m5/system/disks/linux-latest.img
912read_only=true
913
914[system.disk2]
915type=IdeDisk
916children=image
917delay=1000000
918driveID=master
919image=system.disk2.image
920
921[system.disk2.image]
922type=CowDiskImage
923children=child
924child=system.disk2.image.child
925image_file=
926read_only=false
927table_size=65536
928
929[system.disk2.image.child]
930type=RawDiskImage
931image_file=/dist/m5/system/disks/linux-bigswap2.img
932read_only=true
933
934[system.intrctrl]
935type=IntrControl
936sys=system
937
938[system.iobus]
939type=Bus
940block_size=64
941bus_id=0
942clock=1000
943header_cycles=1
944use_default_range=true
945width=64
946default=system.tsunami.pciconfig.pio
|
948port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
| 947master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
948slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
949
950[system.iocache]
951type=BaseCache
| 949
950[system.iocache]
951type=BaseCache
|
952addr_range=0:8589934591
| 952addr_ranges=0:8589934591
|
953assoc=8
954block_size=64
955forward_snoops=false
956hash_delay=1
957is_top_level=true
958latency=50000
959max_miss_count=0
960mshrs=20
961prefetch_on_access=false
962prefetcher=Null
963prioritizeRequests=false
964repl=Null
965size=1024
966subblock_size=0
967system=system
968tgts_per_mshr=12
969trace_addr=0
970two_queue=false
971write_buffers=8
| 953assoc=8
954block_size=64
955forward_snoops=false
956hash_delay=1
957is_top_level=true
958latency=50000
959max_miss_count=0
960mshrs=20
961prefetch_on_access=false
962prefetcher=Null
963prioritizeRequests=false
964repl=Null
965size=1024
966subblock_size=0
967system=system
968tgts_per_mshr=12
969trace_addr=0
970two_queue=false
971write_buffers=8
|
972cpu_side=system.iobus.port[32]
973mem_side=system.membus.port[3]
| 972cpu_side=system.iobus.master[29]
973mem_side=system.membus.slave[1]
|
974
975[system.l2c]
976type=BaseCache
| 974
975[system.l2c]
976type=BaseCache
|
977addr_range=0:18446744073709551615
| 977addr_ranges=0:18446744073709551615
|
978assoc=8
979block_size=64
980forward_snoops=true
981hash_delay=1
982is_top_level=false
983latency=10000
984max_miss_count=0
985mshrs=92
986prefetch_on_access=false
987prefetcher=Null
988prioritizeRequests=false
989repl=Null
990size=4194304
991subblock_size=0
992system=system
993tgts_per_mshr=16
994trace_addr=0
995two_queue=false
996write_buffers=8
| 978assoc=8
979block_size=64
980forward_snoops=true
981hash_delay=1
982is_top_level=false
983latency=10000
984max_miss_count=0
985mshrs=92
986prefetch_on_access=false
987prefetcher=Null
988prioritizeRequests=false
989repl=Null
990size=4194304
991subblock_size=0
992system=system
993tgts_per_mshr=16
994trace_addr=0
995two_queue=false
996write_buffers=8
|
997cpu_side=system.toL2Bus.port[0]
998mem_side=system.membus.port[4]
| 997cpu_side=system.toL2Bus.master[0]
998mem_side=system.membus.slave[2]
|
999
1000[system.membus]
1001type=Bus
1002children=badaddr_responder
1003block_size=64
1004bus_id=1
1005clock=1000
1006header_cycles=1
1007use_default_range=false
1008width=64
1009default=system.membus.badaddr_responder.pio
| 999
1000[system.membus]
1001type=Bus
1002children=badaddr_responder
1003block_size=64
1004bus_id=1
1005clock=1000
1006header_cycles=1
1007use_default_range=false
1008width=64
1009default=system.membus.badaddr_responder.pio
|
1010port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
| 1010master=system.bridge.slave system.physmem.port[0]
1011slave=system.system_port system.iocache.mem_side system.l2c.mem_side
|
1011
1012[system.membus.badaddr_responder]
1013type=IsaFake
1014fake_mem=false
1015pio_addr=0
1016pio_latency=1000
1017pio_size=8
1018ret_bad_addr=true
1019ret_data16=65535
1020ret_data32=4294967295
1021ret_data64=18446744073709551615
1022ret_data8=255
1023system=system
1024update_data=false
1025warn_access=
1026pio=system.membus.default
1027
1028[system.physmem]
| 1012
1013[system.membus.badaddr_responder]
1014type=IsaFake
1015fake_mem=false
1016pio_addr=0
1017pio_latency=1000
1018pio_size=8
1019ret_bad_addr=true
1020ret_data16=65535
1021ret_data32=4294967295
1022ret_data64=18446744073709551615
1023ret_data8=255
1024system=system
1025update_data=false
1026warn_access=
1027pio=system.membus.default
1028
1029[system.physmem]
|
1029type=PhysicalMemory
| 1030type=SimpleMemory
1031conf_table_reported=false
|
1030file=
| 1032file=
|
| 1033in_addr_map=true
|
1031latency=30000
1032latency_var=0
1033null=false
1034range=0:134217727
1035zero=false
| 1034latency=30000
1035latency_var=0
1036null=false
1037range=0:134217727
1038zero=false
|
1036port=system.membus.port[1]
| 1039port=system.membus.master[1]
|
1037
1038[system.simple_disk]
1039type=SimpleDisk
1040children=disk
1041disk=system.simple_disk.disk
1042system=system
1043
1044[system.simple_disk.disk]
1045type=RawDiskImage
1046image_file=/dist/m5/system/disks/linux-latest.img
1047read_only=true
1048
1049[system.terminal]
1050type=Terminal
1051intr_control=system.intrctrl
1052number=0
1053output=true
1054port=3456
1055
1056[system.toL2Bus]
1057type=Bus
1058block_size=64
1059bus_id=0
1060clock=1000
1061header_cycles=1
1062use_default_range=false
1063width=64
| 1040
1041[system.simple_disk]
1042type=SimpleDisk
1043children=disk
1044disk=system.simple_disk.disk
1045system=system
1046
1047[system.simple_disk.disk]
1048type=RawDiskImage
1049image_file=/dist/m5/system/disks/linux-latest.img
1050read_only=true
1051
1052[system.terminal]
1053type=Terminal
1054intr_control=system.intrctrl
1055number=0
1056output=true
1057port=3456
1058
1059[system.toL2Bus]
1060type=Bus
1061block_size=64
1062bus_id=0
1063clock=1000
1064header_cycles=1
1065use_default_range=false
1066width=64
|
1064port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
| 1067master=system.l2c.cpu_side
1068slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
1065
1066[system.tsunami]
1067type=Tsunami
1068children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1069intrctrl=system.intrctrl
1070system=system
1071
1072[system.tsunami.backdoor]
1073type=AlphaBackdoor
1074cpu=system.cpu0
1075disk=system.simple_disk
1076pio_addr=8804682956800
1077pio_latency=1000
1078platform=system.tsunami
1079system=system
1080terminal=system.terminal
| 1069
1070[system.tsunami]
1071type=Tsunami
1072children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
1073intrctrl=system.intrctrl
1074system=system
1075
1076[system.tsunami.backdoor]
1077type=AlphaBackdoor
1078cpu=system.cpu0
1079disk=system.simple_disk
1080pio_addr=8804682956800
1081pio_latency=1000
1082platform=system.tsunami
1083system=system
1084terminal=system.terminal
|
1081pio=system.iobus.port[25]
| 1085pio=system.iobus.master[24]
|
1082
1083[system.tsunami.cchip]
1084type=TsunamiCChip
1085pio_addr=8803072344064
1086pio_latency=1000
1087system=system
1088tsunami=system.tsunami
| 1086
1087[system.tsunami.cchip]
1088type=TsunamiCChip
1089pio_addr=8803072344064
1090pio_latency=1000
1091system=system
1092tsunami=system.tsunami
|
1089pio=system.iobus.port[1]
| 1093pio=system.iobus.master[0]
|
1090
1091[system.tsunami.ethernet]
1092type=NSGigE
1093BAR0=1
1094BAR0LegacyIO=false
1095BAR0Size=256
1096BAR1=0
1097BAR1LegacyIO=false
1098BAR1Size=4096
1099BAR2=0
1100BAR2LegacyIO=false
1101BAR2Size=0
1102BAR3=0
1103BAR3LegacyIO=false
1104BAR3Size=0
1105BAR4=0
1106BAR4LegacyIO=false
1107BAR4Size=0
1108BAR5=0
1109BAR5LegacyIO=false
1110BAR5Size=0
1111BIST=0
1112CacheLineSize=0
1113CardbusCIS=0
1114ClassCode=2
1115Command=0
1116DeviceID=34
1117ExpansionROM=0
1118HeaderType=0
1119InterruptLine=30
1120InterruptPin=1
1121LatencyTimer=0
1122MaximumLatency=52
1123MinimumGrant=176
1124ProgIF=0
1125Revision=0
1126Status=656
1127SubClassCode=0
1128SubsystemID=0
1129SubsystemVendorID=0
1130VendorID=4107
1131clock=0
1132config_latency=20000
1133dma_data_free=false
1134dma_desc_free=false
1135dma_no_allocate=true
1136dma_read_delay=0
1137dma_read_factor=0
1138dma_write_delay=0
1139dma_write_factor=0
1140hardware_address=00:90:00:00:00:01
1141intr_delay=10000000
1142max_backoff_delay=10000000
1143min_backoff_delay=4000
1144pci_bus=0
1145pci_dev=1
1146pci_func=0
1147pio_latency=1000
1148platform=system.tsunami
1149rss=false
1150rx_delay=1000000
1151rx_fifo_size=524288
1152rx_filter=true
1153rx_thread=false
1154system=system
1155tx_delay=1000000
1156tx_fifo_size=524288
1157tx_thread=false
| 1094
1095[system.tsunami.ethernet]
1096type=NSGigE
1097BAR0=1
1098BAR0LegacyIO=false
1099BAR0Size=256
1100BAR1=0
1101BAR1LegacyIO=false
1102BAR1Size=4096
1103BAR2=0
1104BAR2LegacyIO=false
1105BAR2Size=0
1106BAR3=0
1107BAR3LegacyIO=false
1108BAR3Size=0
1109BAR4=0
1110BAR4LegacyIO=false
1111BAR4Size=0
1112BAR5=0
1113BAR5LegacyIO=false
1114BAR5Size=0
1115BIST=0
1116CacheLineSize=0
1117CardbusCIS=0
1118ClassCode=2
1119Command=0
1120DeviceID=34
1121ExpansionROM=0
1122HeaderType=0
1123InterruptLine=30
1124InterruptPin=1
1125LatencyTimer=0
1126MaximumLatency=52
1127MinimumGrant=176
1128ProgIF=0
1129Revision=0
1130Status=656
1131SubClassCode=0
1132SubsystemID=0
1133SubsystemVendorID=0
1134VendorID=4107
1135clock=0
1136config_latency=20000
1137dma_data_free=false
1138dma_desc_free=false
1139dma_no_allocate=true
1140dma_read_delay=0
1141dma_read_factor=0
1142dma_write_delay=0
1143dma_write_factor=0
1144hardware_address=00:90:00:00:00:01
1145intr_delay=10000000
1146max_backoff_delay=10000000
1147min_backoff_delay=4000
1148pci_bus=0
1149pci_dev=1
1150pci_func=0
1151pio_latency=1000
1152platform=system.tsunami
1153rss=false
1154rx_delay=1000000
1155rx_fifo_size=524288
1156rx_filter=true
1157rx_thread=false
1158system=system
1159tx_delay=1000000
1160tx_fifo_size=524288
1161tx_thread=false
|
1158config=system.iobus.port[30]
1159dma=system.iobus.port[31]
1160pio=system.iobus.port[29]
| 1162config=system.iobus.master[28]
1163dma=system.iobus.slave[2]
1164pio=system.iobus.master[27]
|
1161
1162[system.tsunami.fake_OROM]
1163type=IsaFake
1164fake_mem=false
1165pio_addr=8796093677568
1166pio_latency=1000
1167pio_size=393216
1168ret_bad_addr=false
1169ret_data16=65535
1170ret_data32=4294967295
1171ret_data64=18446744073709551615
1172ret_data8=255
1173system=system
1174update_data=false
1175warn_access=
| 1165
1166[system.tsunami.fake_OROM]
1167type=IsaFake
1168fake_mem=false
1169pio_addr=8796093677568
1170pio_latency=1000
1171pio_size=393216
1172ret_bad_addr=false
1173ret_data16=65535
1174ret_data32=4294967295
1175ret_data64=18446744073709551615
1176ret_data8=255
1177system=system
1178update_data=false
1179warn_access=
|
1176pio=system.iobus.port[9]
| 1180pio=system.iobus.master[8]
|
1177
1178[system.tsunami.fake_ata0]
1179type=IsaFake
1180fake_mem=false
1181pio_addr=8804615848432
1182pio_latency=1000
1183pio_size=8
1184ret_bad_addr=false
1185ret_data16=65535
1186ret_data32=4294967295
1187ret_data64=18446744073709551615
1188ret_data8=255
1189system=system
1190update_data=false
1191warn_access=
| 1181
1182[system.tsunami.fake_ata0]
1183type=IsaFake
1184fake_mem=false
1185pio_addr=8804615848432
1186pio_latency=1000
1187pio_size=8
1188ret_bad_addr=false
1189ret_data16=65535
1190ret_data32=4294967295
1191ret_data64=18446744073709551615
1192ret_data8=255
1193system=system
1194update_data=false
1195warn_access=
|
1192pio=system.iobus.port[20]
| 1196pio=system.iobus.master[19]
|
1193
1194[system.tsunami.fake_ata1]
1195type=IsaFake
1196fake_mem=false
1197pio_addr=8804615848304
1198pio_latency=1000
1199pio_size=8
1200ret_bad_addr=false
1201ret_data16=65535
1202ret_data32=4294967295
1203ret_data64=18446744073709551615
1204ret_data8=255
1205system=system
1206update_data=false
1207warn_access=
| 1197
1198[system.tsunami.fake_ata1]
1199type=IsaFake
1200fake_mem=false
1201pio_addr=8804615848304
1202pio_latency=1000
1203pio_size=8
1204ret_bad_addr=false
1205ret_data16=65535
1206ret_data32=4294967295
1207ret_data64=18446744073709551615
1208ret_data8=255
1209system=system
1210update_data=false
1211warn_access=
|
1208pio=system.iobus.port[21]
| 1212pio=system.iobus.master[20]
|
1209
1210[system.tsunami.fake_pnp_addr]
1211type=IsaFake
1212fake_mem=false
1213pio_addr=8804615848569
1214pio_latency=1000
1215pio_size=8
1216ret_bad_addr=false
1217ret_data16=65535
1218ret_data32=4294967295
1219ret_data64=18446744073709551615
1220ret_data8=255
1221system=system
1222update_data=false
1223warn_access=
| 1213
1214[system.tsunami.fake_pnp_addr]
1215type=IsaFake
1216fake_mem=false
1217pio_addr=8804615848569
1218pio_latency=1000
1219pio_size=8
1220ret_bad_addr=false
1221ret_data16=65535
1222ret_data32=4294967295
1223ret_data64=18446744073709551615
1224ret_data8=255
1225system=system
1226update_data=false
1227warn_access=
|
1224pio=system.iobus.port[10]
| 1228pio=system.iobus.master[9]
|
1225
1226[system.tsunami.fake_pnp_read0]
1227type=IsaFake
1228fake_mem=false
1229pio_addr=8804615848451
1230pio_latency=1000
1231pio_size=8
1232ret_bad_addr=false
1233ret_data16=65535
1234ret_data32=4294967295
1235ret_data64=18446744073709551615
1236ret_data8=255
1237system=system
1238update_data=false
1239warn_access=
| 1229
1230[system.tsunami.fake_pnp_read0]
1231type=IsaFake
1232fake_mem=false
1233pio_addr=8804615848451
1234pio_latency=1000
1235pio_size=8
1236ret_bad_addr=false
1237ret_data16=65535
1238ret_data32=4294967295
1239ret_data64=18446744073709551615
1240ret_data8=255
1241system=system
1242update_data=false
1243warn_access=
|
1240pio=system.iobus.port[12]
| 1244pio=system.iobus.master[11]
|
1241
1242[system.tsunami.fake_pnp_read1]
1243type=IsaFake
1244fake_mem=false
1245pio_addr=8804615848515
1246pio_latency=1000
1247pio_size=8
1248ret_bad_addr=false
1249ret_data16=65535
1250ret_data32=4294967295
1251ret_data64=18446744073709551615
1252ret_data8=255
1253system=system
1254update_data=false
1255warn_access=
| 1245
1246[system.tsunami.fake_pnp_read1]
1247type=IsaFake
1248fake_mem=false
1249pio_addr=8804615848515
1250pio_latency=1000
1251pio_size=8
1252ret_bad_addr=false
1253ret_data16=65535
1254ret_data32=4294967295
1255ret_data64=18446744073709551615
1256ret_data8=255
1257system=system
1258update_data=false
1259warn_access=
|
1256pio=system.iobus.port[13]
| 1260pio=system.iobus.master[12]
|
1257
1258[system.tsunami.fake_pnp_read2]
1259type=IsaFake
1260fake_mem=false
1261pio_addr=8804615848579
1262pio_latency=1000
1263pio_size=8
1264ret_bad_addr=false
1265ret_data16=65535
1266ret_data32=4294967295
1267ret_data64=18446744073709551615
1268ret_data8=255
1269system=system
1270update_data=false
1271warn_access=
| 1261
1262[system.tsunami.fake_pnp_read2]
1263type=IsaFake
1264fake_mem=false
1265pio_addr=8804615848579
1266pio_latency=1000
1267pio_size=8
1268ret_bad_addr=false
1269ret_data16=65535
1270ret_data32=4294967295
1271ret_data64=18446744073709551615
1272ret_data8=255
1273system=system
1274update_data=false
1275warn_access=
|
1272pio=system.iobus.port[14]
| 1276pio=system.iobus.master[13]
|
1273
1274[system.tsunami.fake_pnp_read3]
1275type=IsaFake
1276fake_mem=false
1277pio_addr=8804615848643
1278pio_latency=1000
1279pio_size=8
1280ret_bad_addr=false
1281ret_data16=65535
1282ret_data32=4294967295
1283ret_data64=18446744073709551615
1284ret_data8=255
1285system=system
1286update_data=false
1287warn_access=
| 1277
1278[system.tsunami.fake_pnp_read3]
1279type=IsaFake
1280fake_mem=false
1281pio_addr=8804615848643
1282pio_latency=1000
1283pio_size=8
1284ret_bad_addr=false
1285ret_data16=65535
1286ret_data32=4294967295
1287ret_data64=18446744073709551615
1288ret_data8=255
1289system=system
1290update_data=false
1291warn_access=
|
1288pio=system.iobus.port[15]
| 1292pio=system.iobus.master[14]
|
1289
1290[system.tsunami.fake_pnp_read4]
1291type=IsaFake
1292fake_mem=false
1293pio_addr=8804615848707
1294pio_latency=1000
1295pio_size=8
1296ret_bad_addr=false
1297ret_data16=65535
1298ret_data32=4294967295
1299ret_data64=18446744073709551615
1300ret_data8=255
1301system=system
1302update_data=false
1303warn_access=
| 1293
1294[system.tsunami.fake_pnp_read4]
1295type=IsaFake
1296fake_mem=false
1297pio_addr=8804615848707
1298pio_latency=1000
1299pio_size=8
1300ret_bad_addr=false
1301ret_data16=65535
1302ret_data32=4294967295
1303ret_data64=18446744073709551615
1304ret_data8=255
1305system=system
1306update_data=false
1307warn_access=
|
1304pio=system.iobus.port[16]
| 1308pio=system.iobus.master[15]
|
1305
1306[system.tsunami.fake_pnp_read5]
1307type=IsaFake
1308fake_mem=false
1309pio_addr=8804615848771
1310pio_latency=1000
1311pio_size=8
1312ret_bad_addr=false
1313ret_data16=65535
1314ret_data32=4294967295
1315ret_data64=18446744073709551615
1316ret_data8=255
1317system=system
1318update_data=false
1319warn_access=
| 1309
1310[system.tsunami.fake_pnp_read5]
1311type=IsaFake
1312fake_mem=false
1313pio_addr=8804615848771
1314pio_latency=1000
1315pio_size=8
1316ret_bad_addr=false
1317ret_data16=65535
1318ret_data32=4294967295
1319ret_data64=18446744073709551615
1320ret_data8=255
1321system=system
1322update_data=false
1323warn_access=
|
1320pio=system.iobus.port[17]
| 1324pio=system.iobus.master[16]
|
1321
1322[system.tsunami.fake_pnp_read6]
1323type=IsaFake
1324fake_mem=false
1325pio_addr=8804615848835
1326pio_latency=1000
1327pio_size=8
1328ret_bad_addr=false
1329ret_data16=65535
1330ret_data32=4294967295
1331ret_data64=18446744073709551615
1332ret_data8=255
1333system=system
1334update_data=false
1335warn_access=
| 1325
1326[system.tsunami.fake_pnp_read6]
1327type=IsaFake
1328fake_mem=false
1329pio_addr=8804615848835
1330pio_latency=1000
1331pio_size=8
1332ret_bad_addr=false
1333ret_data16=65535
1334ret_data32=4294967295
1335ret_data64=18446744073709551615
1336ret_data8=255
1337system=system
1338update_data=false
1339warn_access=
|
1336pio=system.iobus.port[18]
| 1340pio=system.iobus.master[17]
|
1337
1338[system.tsunami.fake_pnp_read7]
1339type=IsaFake
1340fake_mem=false
1341pio_addr=8804615848899
1342pio_latency=1000
1343pio_size=8
1344ret_bad_addr=false
1345ret_data16=65535
1346ret_data32=4294967295
1347ret_data64=18446744073709551615
1348ret_data8=255
1349system=system
1350update_data=false
1351warn_access=
| 1341
1342[system.tsunami.fake_pnp_read7]
1343type=IsaFake
1344fake_mem=false
1345pio_addr=8804615848899
1346pio_latency=1000
1347pio_size=8
1348ret_bad_addr=false
1349ret_data16=65535
1350ret_data32=4294967295
1351ret_data64=18446744073709551615
1352ret_data8=255
1353system=system
1354update_data=false
1355warn_access=
|
1352pio=system.iobus.port[19]
| 1356pio=system.iobus.master[18]
|
1353
1354[system.tsunami.fake_pnp_write]
1355type=IsaFake
1356fake_mem=false
1357pio_addr=8804615850617
1358pio_latency=1000
1359pio_size=8
1360ret_bad_addr=false
1361ret_data16=65535
1362ret_data32=4294967295
1363ret_data64=18446744073709551615
1364ret_data8=255
1365system=system
1366update_data=false
1367warn_access=
| 1357
1358[system.tsunami.fake_pnp_write]
1359type=IsaFake
1360fake_mem=false
1361pio_addr=8804615850617
1362pio_latency=1000
1363pio_size=8
1364ret_bad_addr=false
1365ret_data16=65535
1366ret_data32=4294967295
1367ret_data64=18446744073709551615
1368ret_data8=255
1369system=system
1370update_data=false
1371warn_access=
|
1368pio=system.iobus.port[11]
| 1372pio=system.iobus.master[10]
|
1369
1370[system.tsunami.fake_ppc]
1371type=IsaFake
1372fake_mem=false
1373pio_addr=8804615848891
1374pio_latency=1000
1375pio_size=8
1376ret_bad_addr=false
1377ret_data16=65535
1378ret_data32=4294967295
1379ret_data64=18446744073709551615
1380ret_data8=255
1381system=system
1382update_data=false
1383warn_access=
| 1373
1374[system.tsunami.fake_ppc]
1375type=IsaFake
1376fake_mem=false
1377pio_addr=8804615848891
1378pio_latency=1000
1379pio_size=8
1380ret_bad_addr=false
1381ret_data16=65535
1382ret_data32=4294967295
1383ret_data64=18446744073709551615
1384ret_data8=255
1385system=system
1386update_data=false
1387warn_access=
|
1384pio=system.iobus.port[8]
| 1388pio=system.iobus.master[7]
|
1385
1386[system.tsunami.fake_sm_chip]
1387type=IsaFake
1388fake_mem=false
1389pio_addr=8804615848816
1390pio_latency=1000
1391pio_size=8
1392ret_bad_addr=false
1393ret_data16=65535
1394ret_data32=4294967295
1395ret_data64=18446744073709551615
1396ret_data8=255
1397system=system
1398update_data=false
1399warn_access=
| 1389
1390[system.tsunami.fake_sm_chip]
1391type=IsaFake
1392fake_mem=false
1393pio_addr=8804615848816
1394pio_latency=1000
1395pio_size=8
1396ret_bad_addr=false
1397ret_data16=65535
1398ret_data32=4294967295
1399ret_data64=18446744073709551615
1400ret_data8=255
1401system=system
1402update_data=false
1403warn_access=
|
1400pio=system.iobus.port[3]
| 1404pio=system.iobus.master[2]
|
1401
1402[system.tsunami.fake_uart1]
1403type=IsaFake
1404fake_mem=false
1405pio_addr=8804615848696
1406pio_latency=1000
1407pio_size=8
1408ret_bad_addr=false
1409ret_data16=65535
1410ret_data32=4294967295
1411ret_data64=18446744073709551615
1412ret_data8=255
1413system=system
1414update_data=false
1415warn_access=
| 1405
1406[system.tsunami.fake_uart1]
1407type=IsaFake
1408fake_mem=false
1409pio_addr=8804615848696
1410pio_latency=1000
1411pio_size=8
1412ret_bad_addr=false
1413ret_data16=65535
1414ret_data32=4294967295
1415ret_data64=18446744073709551615
1416ret_data8=255
1417system=system
1418update_data=false
1419warn_access=
|
1416pio=system.iobus.port[4]
| 1420pio=system.iobus.master[3]
|
1417
1418[system.tsunami.fake_uart2]
1419type=IsaFake
1420fake_mem=false
1421pio_addr=8804615848936
1422pio_latency=1000
1423pio_size=8
1424ret_bad_addr=false
1425ret_data16=65535
1426ret_data32=4294967295
1427ret_data64=18446744073709551615
1428ret_data8=255
1429system=system
1430update_data=false
1431warn_access=
| 1421
1422[system.tsunami.fake_uart2]
1423type=IsaFake
1424fake_mem=false
1425pio_addr=8804615848936
1426pio_latency=1000
1427pio_size=8
1428ret_bad_addr=false
1429ret_data16=65535
1430ret_data32=4294967295
1431ret_data64=18446744073709551615
1432ret_data8=255
1433system=system
1434update_data=false
1435warn_access=
|
1432pio=system.iobus.port[5]
| 1436pio=system.iobus.master[4]
|
1433
1434[system.tsunami.fake_uart3]
1435type=IsaFake
1436fake_mem=false
1437pio_addr=8804615848680
1438pio_latency=1000
1439pio_size=8
1440ret_bad_addr=false
1441ret_data16=65535
1442ret_data32=4294967295
1443ret_data64=18446744073709551615
1444ret_data8=255
1445system=system
1446update_data=false
1447warn_access=
| 1437
1438[system.tsunami.fake_uart3]
1439type=IsaFake
1440fake_mem=false
1441pio_addr=8804615848680
1442pio_latency=1000
1443pio_size=8
1444ret_bad_addr=false
1445ret_data16=65535
1446ret_data32=4294967295
1447ret_data64=18446744073709551615
1448ret_data8=255
1449system=system
1450update_data=false
1451warn_access=
|
1448pio=system.iobus.port[6]
| 1452pio=system.iobus.master[5]
|
1449
1450[system.tsunami.fake_uart4]
1451type=IsaFake
1452fake_mem=false
1453pio_addr=8804615848944
1454pio_latency=1000
1455pio_size=8
1456ret_bad_addr=false
1457ret_data16=65535
1458ret_data32=4294967295
1459ret_data64=18446744073709551615
1460ret_data8=255
1461system=system
1462update_data=false
1463warn_access=
| 1453
1454[system.tsunami.fake_uart4]
1455type=IsaFake
1456fake_mem=false
1457pio_addr=8804615848944
1458pio_latency=1000
1459pio_size=8
1460ret_bad_addr=false
1461ret_data16=65535
1462ret_data32=4294967295
1463ret_data64=18446744073709551615
1464ret_data8=255
1465system=system
1466update_data=false
1467warn_access=
|
1464pio=system.iobus.port[7]
| 1468pio=system.iobus.master[6]
|
1465
1466[system.tsunami.fb]
1467type=BadDevice
1468devicename=FrameBuffer
1469pio_addr=8804615848912
1470pio_latency=1000
1471system=system
| 1469
1470[system.tsunami.fb]
1471type=BadDevice
1472devicename=FrameBuffer
1473pio_addr=8804615848912
1474pio_latency=1000
1475system=system
|
1472pio=system.iobus.port[22]
| 1476pio=system.iobus.master[21]
|
1473
1474[system.tsunami.ide]
1475type=IdeController
1476BAR0=1
1477BAR0LegacyIO=false
1478BAR0Size=8
1479BAR1=1
1480BAR1LegacyIO=false
1481BAR1Size=4
1482BAR2=1
1483BAR2LegacyIO=false
1484BAR2Size=8
1485BAR3=1
1486BAR3LegacyIO=false
1487BAR3Size=4
1488BAR4=1
1489BAR4LegacyIO=false
1490BAR4Size=16
1491BAR5=1
1492BAR5LegacyIO=false
1493BAR5Size=0
1494BIST=0
1495CacheLineSize=0
1496CardbusCIS=0
1497ClassCode=1
1498Command=0
1499DeviceID=28945
1500ExpansionROM=0
1501HeaderType=0
1502InterruptLine=31
1503InterruptPin=1
1504LatencyTimer=0
1505MaximumLatency=0
1506MinimumGrant=0
1507ProgIF=133
1508Revision=0
1509Status=640
1510SubClassCode=1
1511SubsystemID=0
1512SubsystemVendorID=0
1513VendorID=32902
1514config_latency=20000
1515ctrl_offset=0
1516disks=system.disk0 system.disk2
1517io_shift=0
1518max_backoff_delay=10000000
1519min_backoff_delay=4000
1520pci_bus=0
1521pci_dev=0
1522pci_func=0
1523pio_latency=1000
1524platform=system.tsunami
1525system=system
| 1477
1478[system.tsunami.ide]
1479type=IdeController
1480BAR0=1
1481BAR0LegacyIO=false
1482BAR0Size=8
1483BAR1=1
1484BAR1LegacyIO=false
1485BAR1Size=4
1486BAR2=1
1487BAR2LegacyIO=false
1488BAR2Size=8
1489BAR3=1
1490BAR3LegacyIO=false
1491BAR3Size=4
1492BAR4=1
1493BAR4LegacyIO=false
1494BAR4Size=16
1495BAR5=1
1496BAR5LegacyIO=false
1497BAR5Size=0
1498BIST=0
1499CacheLineSize=0
1500CardbusCIS=0
1501ClassCode=1
1502Command=0
1503DeviceID=28945
1504ExpansionROM=0
1505HeaderType=0
1506InterruptLine=31
1507InterruptPin=1
1508LatencyTimer=0
1509MaximumLatency=0
1510MinimumGrant=0
1511ProgIF=133
1512Revision=0
1513Status=640
1514SubClassCode=1
1515SubsystemID=0
1516SubsystemVendorID=0
1517VendorID=32902
1518config_latency=20000
1519ctrl_offset=0
1520disks=system.disk0 system.disk2
1521io_shift=0
1522max_backoff_delay=10000000
1523min_backoff_delay=4000
1524pci_bus=0
1525pci_dev=0
1526pci_func=0
1527pio_latency=1000
1528platform=system.tsunami
1529system=system
|
1526config=system.iobus.port[27]
1527dma=system.iobus.port[28]
1528pio=system.iobus.port[26]
| 1530config=system.iobus.master[26]
1531dma=system.iobus.slave[1]
1532pio=system.iobus.master[25]
|
1529
1530[system.tsunami.io]
1531type=TsunamiIO
1532frequency=976562500
1533pio_addr=8804615847936
1534pio_latency=1000
1535system=system
1536time=Thu Jan 1 00:00:00 2009
1537tsunami=system.tsunami
1538year_is_bcd=false
| 1533
1534[system.tsunami.io]
1535type=TsunamiIO
1536frequency=976562500
1537pio_addr=8804615847936
1538pio_latency=1000
1539system=system
1540time=Thu Jan 1 00:00:00 2009
1541tsunami=system.tsunami
1542year_is_bcd=false
|
1539pio=system.iobus.port[23]
| 1543pio=system.iobus.master[22]
|
1540
1541[system.tsunami.pchip]
1542type=TsunamiPChip
1543pio_addr=8802535473152
1544pio_latency=1000
1545system=system
1546tsunami=system.tsunami
| 1544
1545[system.tsunami.pchip]
1546type=TsunamiPChip
1547pio_addr=8802535473152
1548pio_latency=1000
1549system=system
1550tsunami=system.tsunami
|
1547pio=system.iobus.port[2]
| 1551pio=system.iobus.master[1]
|
1548
1549[system.tsunami.pciconfig]
1550type=PciConfigAll
1551bus=0
1552pio_latency=1
1553platform=system.tsunami
1554size=16777216
1555system=system
1556pio=system.iobus.default
1557
1558[system.tsunami.uart]
1559type=Uart8250
1560pio_addr=8804615848952
1561pio_latency=1000
1562platform=system.tsunami
1563system=system
1564terminal=system.terminal
| 1552
1553[system.tsunami.pciconfig]
1554type=PciConfigAll
1555bus=0
1556pio_latency=1
1557platform=system.tsunami
1558size=16777216
1559system=system
1560pio=system.iobus.default
1561
1562[system.tsunami.uart]
1563type=Uart8250
1564pio_addr=8804615848952
1565pio_latency=1000
1566platform=system.tsunami
1567system=system
1568terminal=system.terminal
|
1565pio=system.iobus.port[24]
| 1569pio=system.iobus.master[23]
|
1566
| 1570
|