Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

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config.ini (11103:38f6188421e0)	config.ini (11245:1c5102c0a7a9)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain
18console=/scratch/nilay/GEM5/system/binaries/console	18console=/work/gem5/dist/binaries/console
19eventq_index=0 20init_param=0	19eventq_index=0 20init_param=0
21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux	21kernel=/work/gem5/dist/binaries/vmlinux
22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem 28mmap_using_noreserve=false	22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem 28mmap_using_noreserve=false
	29multi_thread=false
29num_work_ids=16	30num_work_ids=16
30pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 31readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh	31pal=/work/gem5/dist/binaries/ts_osfpal 32readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
32symbolfile= 33system_rev=1024 34system_type=34 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 37work_begin_exit_count=0 38work_cpus_ckpt_count=0 39work_end_ckpt_count=0 40work_end_exit_count=0 41work_item_id=-1 42system_port=system.membus.slave[0] 43 44[system.bridge] 45type=Bridge 46clk_domain=system.clk_domain 47delay=50000 48eventq_index=0 49ranges=8796093022208:18446744073709551615 50req_size=16 51resp_size=16 52master=system.iobus.slave[0] 53slave=system.membus.master[0] 54 55[system.clk_domain] 56type=SrcClockDomain 57clock=1000 58domain_id=-1 59eventq_index=0 60init_perf_level=0 61voltage_domain=system.voltage_domain 62 63[system.cpu0] 64type=DerivO3CPU 65children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 66LFSTSize=1024 67LQEntries=32 68LSQCheckLoads=true 69LSQDepCheckShift=4 70SQEntries=32 71SSITSize=1024 72activity=0 73backComSize=5 74branchPred=system.cpu0.branchPred 75cachePorts=200 76checker=Null 77clk_domain=system.cpu_clk_domain 78commitToDecodeDelay=1 79commitToFetchDelay=1 80commitToIEWDelay=1 81commitToRenameDelay=1 82commitWidth=8 83cpu_id=0 84decodeToFetchDelay=1 85decodeToRenameDelay=1 86decodeWidth=8 87dispatchWidth=8 88do_checkpoint_insts=true 89do_quiesce=true 90do_statistics_insts=true 91dtb=system.cpu0.dtb 92eventq_index=0 93fetchBufferSize=64 94fetchQueueSize=32 95fetchToDecodeDelay=1 96fetchTrapLatency=1 97fetchWidth=8 98forwardComSize=5 99fuPool=system.cpu0.fuPool 100function_trace=false 101function_trace_start=0 102iewToCommitDelay=1 103iewToDecodeDelay=1 104iewToFetchDelay=1 105iewToRenameDelay=1 106interrupts=system.cpu0.interrupts 107isa=system.cpu0.isa 108issueToExecuteDelay=1 109issueWidth=8 110itb=system.cpu0.itb 111max_insts_all_threads=0 112max_insts_any_thread=0 113max_loads_all_threads=0 114max_loads_any_thread=0 115needsTSO=false 116numIQEntries=64 117numPhysCCRegs=0 118numPhysFloatRegs=256 119numPhysIntRegs=256 120numROBEntries=192 121numRobs=1 122numThreads=1 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=2 128renameToROBDelay=1 129renameWidth=8 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144system=system 145tracer=system.cpu0.tracer 146trapLatency=13 147wbWidth=8 148workload= 149dcache_port=system.cpu0.dcache.cpu_side 150icache_port=system.cpu0.icache.cpu_side 151 152[system.cpu0.branchPred] 153type=TournamentBP 154BTBEntries=4096 155BTBTagSize=16 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162instShiftAmt=2 163localCtrBits=2 164localHistoryTableSize=2048 165localPredictorSize=2048 166numThreads=1 167 168[system.cpu0.dcache] 169type=Cache 170children=tags 171addr_ranges=0:18446744073709551615 172assoc=4 173clk_domain=system.cpu_clk_domain	33symbolfile= 34system_rev=1024 35system_type=34 36work_begin_ckpt_count=0 37work_begin_cpu_id_exit=-1 38work_begin_exit_count=0 39work_cpus_ckpt_count=0 40work_end_ckpt_count=0 41work_end_exit_count=0 42work_item_id=-1 43system_port=system.membus.slave[0] 44 45[system.bridge] 46type=Bridge 47clk_domain=system.clk_domain 48delay=50000 49eventq_index=0 50ranges=8796093022208:18446744073709551615 51req_size=16 52resp_size=16 53master=system.iobus.slave[0] 54slave=system.membus.master[0] 55 56[system.clk_domain] 57type=SrcClockDomain 58clock=1000 59domain_id=-1 60eventq_index=0 61init_perf_level=0 62voltage_domain=system.voltage_domain 63 64[system.cpu0] 65type=DerivO3CPU 66children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 67LFSTSize=1024 68LQEntries=32 69LSQCheckLoads=true 70LSQDepCheckShift=4 71SQEntries=32 72SSITSize=1024 73activity=0 74backComSize=5 75branchPred=system.cpu0.branchPred 76cachePorts=200 77checker=Null 78clk_domain=system.cpu_clk_domain 79commitToDecodeDelay=1 80commitToFetchDelay=1 81commitToIEWDelay=1 82commitToRenameDelay=1 83commitWidth=8 84cpu_id=0 85decodeToFetchDelay=1 86decodeToRenameDelay=1 87decodeWidth=8 88dispatchWidth=8 89do_checkpoint_insts=true 90do_quiesce=true 91do_statistics_insts=true 92dtb=system.cpu0.dtb 93eventq_index=0 94fetchBufferSize=64 95fetchQueueSize=32 96fetchToDecodeDelay=1 97fetchTrapLatency=1 98fetchWidth=8 99forwardComSize=5 100fuPool=system.cpu0.fuPool 101function_trace=false 102function_trace_start=0 103iewToCommitDelay=1 104iewToDecodeDelay=1 105iewToFetchDelay=1 106iewToRenameDelay=1 107interrupts=system.cpu0.interrupts 108isa=system.cpu0.isa 109issueToExecuteDelay=1 110issueWidth=8 111itb=system.cpu0.itb 112max_insts_all_threads=0 113max_insts_any_thread=0 114max_loads_all_threads=0 115max_loads_any_thread=0 116needsTSO=false 117numIQEntries=64 118numPhysCCRegs=0 119numPhysFloatRegs=256 120numPhysIntRegs=256 121numROBEntries=192 122numRobs=1 123numThreads=1 124profile=0 125progress_interval=0 126renameToDecodeDelay=1 127renameToFetchDelay=1 128renameToIEWDelay=2 129renameToROBDelay=1 130renameWidth=8 131simpoint_start_insts= 132smtCommitPolicy=RoundRobin 133smtFetchPolicy=SingleThread 134smtIQPolicy=Partitioned 135smtIQThreshold=100 136smtLSQPolicy=Partitioned 137smtLSQThreshold=100 138smtNumFetchingThreads=1 139smtROBPolicy=Partitioned 140smtROBThreshold=100 141socket_id=0 142squashWidth=8 143store_set_clear_period=250000 144switched_out=false 145system=system 146tracer=system.cpu0.tracer 147trapLatency=13 148wbWidth=8 149workload= 150dcache_port=system.cpu0.dcache.cpu_side 151icache_port=system.cpu0.icache.cpu_side 152 153[system.cpu0.branchPred] 154type=TournamentBP 155BTBEntries=4096 156BTBTagSize=16 157RASSize=16 158choiceCtrBits=2 159choicePredictorSize=8192 160eventq_index=0 161globalCtrBits=2 162globalPredictorSize=8192 163instShiftAmt=2 164localCtrBits=2 165localHistoryTableSize=2048 166localPredictorSize=2048 167numThreads=1 168 169[system.cpu0.dcache] 170type=Cache 171children=tags 172addr_ranges=0:18446744073709551615 173assoc=4 174clk_domain=system.cpu_clk_domain
	175clusivity=mostly_incl
174demand_mshr_reserve=1 175eventq_index=0 176forward_snoops=true 177hit_latency=2 178is_read_only=false 179max_miss_count=0 180mshrs=4 181prefetch_on_access=false 182prefetcher=Null 183response_latency=2 184sequential_access=false 185size=32768 186system=system 187tags=system.cpu0.dcache.tags 188tgts_per_mshr=20 189write_buffers=8	176demand_mshr_reserve=1 177eventq_index=0 178forward_snoops=true 179hit_latency=2 180is_read_only=false 181max_miss_count=0 182mshrs=4 183prefetch_on_access=false 184prefetcher=Null 185response_latency=2 186sequential_access=false 187size=32768 188system=system 189tags=system.cpu0.dcache.tags 190tgts_per_mshr=20 191write_buffers=8
	192writeback_clean=false
190cpu_side=system.cpu0.dcache_port 191mem_side=system.toL2Bus.slave[1] 192 193[system.cpu0.dcache.tags] 194type=LRU 195assoc=4 196block_size=64 197clk_domain=system.cpu_clk_domain 198eventq_index=0 199hit_latency=2 200sequential_access=false 201size=32768 202 203[system.cpu0.dtb] 204type=AlphaTLB 205eventq_index=0 206size=64 207 208[system.cpu0.fuPool] 209type=FUPool 210children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 211FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 212eventq_index=0 213 214[system.cpu0.fuPool.FUList0] 215type=FUDesc 216children=opList 217count=6 218eventq_index=0 219opList=system.cpu0.fuPool.FUList0.opList 220 221[system.cpu0.fuPool.FUList0.opList] 222type=OpDesc 223eventq_index=0 224opClass=IntAlu 225opLat=1 226pipelined=true 227 228[system.cpu0.fuPool.FUList1] 229type=FUDesc 230children=opList0 opList1 231count=2 232eventq_index=0 233opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 234 235[system.cpu0.fuPool.FUList1.opList0] 236type=OpDesc 237eventq_index=0 238opClass=IntMult 239opLat=3 240pipelined=true 241 242[system.cpu0.fuPool.FUList1.opList1] 243type=OpDesc 244eventq_index=0 245opClass=IntDiv 246opLat=20 247pipelined=false 248 249[system.cpu0.fuPool.FUList2] 250type=FUDesc 251children=opList0 opList1 opList2 252count=4 253eventq_index=0 254opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 255 256[system.cpu0.fuPool.FUList2.opList0] 257type=OpDesc 258eventq_index=0 259opClass=FloatAdd 260opLat=2 261pipelined=true 262 263[system.cpu0.fuPool.FUList2.opList1] 264type=OpDesc 265eventq_index=0 266opClass=FloatCmp 267opLat=2 268pipelined=true 269 270[system.cpu0.fuPool.FUList2.opList2] 271type=OpDesc 272eventq_index=0 273opClass=FloatCvt 274opLat=2 275pipelined=true 276 277[system.cpu0.fuPool.FUList3] 278type=FUDesc 279children=opList0 opList1 opList2 280count=2 281eventq_index=0 282opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 283 284[system.cpu0.fuPool.FUList3.opList0] 285type=OpDesc 286eventq_index=0 287opClass=FloatMult 288opLat=4 289pipelined=true 290 291[system.cpu0.fuPool.FUList3.opList1] 292type=OpDesc 293eventq_index=0 294opClass=FloatDiv 295opLat=12 296pipelined=false 297 298[system.cpu0.fuPool.FUList3.opList2] 299type=OpDesc 300eventq_index=0 301opClass=FloatSqrt 302opLat=24 303pipelined=false 304 305[system.cpu0.fuPool.FUList4] 306type=FUDesc 307children=opList 308count=0 309eventq_index=0 310opList=system.cpu0.fuPool.FUList4.opList 311 312[system.cpu0.fuPool.FUList4.opList] 313type=OpDesc 314eventq_index=0 315opClass=MemRead 316opLat=1 317pipelined=true 318 319[system.cpu0.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323eventq_index=0 324opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 325 326[system.cpu0.fuPool.FUList5.opList00] 327type=OpDesc 328eventq_index=0 329opClass=SimdAdd 330opLat=1 331pipelined=true 332 333[system.cpu0.fuPool.FUList5.opList01] 334type=OpDesc 335eventq_index=0 336opClass=SimdAddAcc 337opLat=1 338pipelined=true 339 340[system.cpu0.fuPool.FUList5.opList02] 341type=OpDesc 342eventq_index=0 343opClass=SimdAlu 344opLat=1 345pipelined=true 346 347[system.cpu0.fuPool.FUList5.opList03] 348type=OpDesc 349eventq_index=0 350opClass=SimdCmp 351opLat=1 352pipelined=true 353 354[system.cpu0.fuPool.FUList5.opList04] 355type=OpDesc 356eventq_index=0 357opClass=SimdCvt 358opLat=1 359pipelined=true 360 361[system.cpu0.fuPool.FUList5.opList05] 362type=OpDesc 363eventq_index=0 364opClass=SimdMisc 365opLat=1 366pipelined=true 367 368[system.cpu0.fuPool.FUList5.opList06] 369type=OpDesc 370eventq_index=0 371opClass=SimdMult 372opLat=1 373pipelined=true 374 375[system.cpu0.fuPool.FUList5.opList07] 376type=OpDesc 377eventq_index=0 378opClass=SimdMultAcc 379opLat=1 380pipelined=true 381 382[system.cpu0.fuPool.FUList5.opList08] 383type=OpDesc 384eventq_index=0 385opClass=SimdShift 386opLat=1 387pipelined=true 388 389[system.cpu0.fuPool.FUList5.opList09] 390type=OpDesc 391eventq_index=0 392opClass=SimdShiftAcc 393opLat=1 394pipelined=true 395 396[system.cpu0.fuPool.FUList5.opList10] 397type=OpDesc 398eventq_index=0 399opClass=SimdSqrt 400opLat=1 401pipelined=true 402 403[system.cpu0.fuPool.FUList5.opList11] 404type=OpDesc 405eventq_index=0 406opClass=SimdFloatAdd 407opLat=1 408pipelined=true 409 410[system.cpu0.fuPool.FUList5.opList12] 411type=OpDesc 412eventq_index=0 413opClass=SimdFloatAlu 414opLat=1 415pipelined=true 416 417[system.cpu0.fuPool.FUList5.opList13] 418type=OpDesc 419eventq_index=0 420opClass=SimdFloatCmp 421opLat=1 422pipelined=true 423 424[system.cpu0.fuPool.FUList5.opList14] 425type=OpDesc 426eventq_index=0 427opClass=SimdFloatCvt 428opLat=1 429pipelined=true 430 431[system.cpu0.fuPool.FUList5.opList15] 432type=OpDesc 433eventq_index=0 434opClass=SimdFloatDiv 435opLat=1 436pipelined=true 437 438[system.cpu0.fuPool.FUList5.opList16] 439type=OpDesc 440eventq_index=0 441opClass=SimdFloatMisc 442opLat=1 443pipelined=true 444 445[system.cpu0.fuPool.FUList5.opList17] 446type=OpDesc 447eventq_index=0 448opClass=SimdFloatMult 449opLat=1 450pipelined=true 451 452[system.cpu0.fuPool.FUList5.opList18] 453type=OpDesc 454eventq_index=0 455opClass=SimdFloatMultAcc 456opLat=1 457pipelined=true 458 459[system.cpu0.fuPool.FUList5.opList19] 460type=OpDesc 461eventq_index=0 462opClass=SimdFloatSqrt 463opLat=1 464pipelined=true 465 466[system.cpu0.fuPool.FUList6] 467type=FUDesc 468children=opList 469count=0 470eventq_index=0 471opList=system.cpu0.fuPool.FUList6.opList 472 473[system.cpu0.fuPool.FUList6.opList] 474type=OpDesc 475eventq_index=0 476opClass=MemWrite 477opLat=1 478pipelined=true 479 480[system.cpu0.fuPool.FUList7] 481type=FUDesc 482children=opList0 opList1 483count=4 484eventq_index=0 485opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 486 487[system.cpu0.fuPool.FUList7.opList0] 488type=OpDesc 489eventq_index=0 490opClass=MemRead 491opLat=1 492pipelined=true 493 494[system.cpu0.fuPool.FUList7.opList1] 495type=OpDesc 496eventq_index=0 497opClass=MemWrite 498opLat=1 499pipelined=true 500 501[system.cpu0.fuPool.FUList8] 502type=FUDesc 503children=opList 504count=1 505eventq_index=0 506opList=system.cpu0.fuPool.FUList8.opList 507 508[system.cpu0.fuPool.FUList8.opList] 509type=OpDesc 510eventq_index=0 511opClass=IprAccess 512opLat=3 513pipelined=false 514 515[system.cpu0.icache] 516type=Cache 517children=tags 518addr_ranges=0:18446744073709551615 519assoc=1 520clk_domain=system.cpu_clk_domain	193cpu_side=system.cpu0.dcache_port 194mem_side=system.toL2Bus.slave[1] 195 196[system.cpu0.dcache.tags] 197type=LRU 198assoc=4 199block_size=64 200clk_domain=system.cpu_clk_domain 201eventq_index=0 202hit_latency=2 203sequential_access=false 204size=32768 205 206[system.cpu0.dtb] 207type=AlphaTLB 208eventq_index=0 209size=64 210 211[system.cpu0.fuPool] 212type=FUPool 213children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 214FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 215eventq_index=0 216 217[system.cpu0.fuPool.FUList0] 218type=FUDesc 219children=opList 220count=6 221eventq_index=0 222opList=system.cpu0.fuPool.FUList0.opList 223 224[system.cpu0.fuPool.FUList0.opList] 225type=OpDesc 226eventq_index=0 227opClass=IntAlu 228opLat=1 229pipelined=true 230 231[system.cpu0.fuPool.FUList1] 232type=FUDesc 233children=opList0 opList1 234count=2 235eventq_index=0 236opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 237 238[system.cpu0.fuPool.FUList1.opList0] 239type=OpDesc 240eventq_index=0 241opClass=IntMult 242opLat=3 243pipelined=true 244 245[system.cpu0.fuPool.FUList1.opList1] 246type=OpDesc 247eventq_index=0 248opClass=IntDiv 249opLat=20 250pipelined=false 251 252[system.cpu0.fuPool.FUList2] 253type=FUDesc 254children=opList0 opList1 opList2 255count=4 256eventq_index=0 257opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 258 259[system.cpu0.fuPool.FUList2.opList0] 260type=OpDesc 261eventq_index=0 262opClass=FloatAdd 263opLat=2 264pipelined=true 265 266[system.cpu0.fuPool.FUList2.opList1] 267type=OpDesc 268eventq_index=0 269opClass=FloatCmp 270opLat=2 271pipelined=true 272 273[system.cpu0.fuPool.FUList2.opList2] 274type=OpDesc 275eventq_index=0 276opClass=FloatCvt 277opLat=2 278pipelined=true 279 280[system.cpu0.fuPool.FUList3] 281type=FUDesc 282children=opList0 opList1 opList2 283count=2 284eventq_index=0 285opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 286 287[system.cpu0.fuPool.FUList3.opList0] 288type=OpDesc 289eventq_index=0 290opClass=FloatMult 291opLat=4 292pipelined=true 293 294[system.cpu0.fuPool.FUList3.opList1] 295type=OpDesc 296eventq_index=0 297opClass=FloatDiv 298opLat=12 299pipelined=false 300 301[system.cpu0.fuPool.FUList3.opList2] 302type=OpDesc 303eventq_index=0 304opClass=FloatSqrt 305opLat=24 306pipelined=false 307 308[system.cpu0.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312eventq_index=0 313opList=system.cpu0.fuPool.FUList4.opList 314 315[system.cpu0.fuPool.FUList4.opList] 316type=OpDesc 317eventq_index=0 318opClass=MemRead 319opLat=1 320pipelined=true 321 322[system.cpu0.fuPool.FUList5] 323type=FUDesc 324children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 325count=4 326eventq_index=0 327opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 328 329[system.cpu0.fuPool.FUList5.opList00] 330type=OpDesc 331eventq_index=0 332opClass=SimdAdd 333opLat=1 334pipelined=true 335 336[system.cpu0.fuPool.FUList5.opList01] 337type=OpDesc 338eventq_index=0 339opClass=SimdAddAcc 340opLat=1 341pipelined=true 342 343[system.cpu0.fuPool.FUList5.opList02] 344type=OpDesc 345eventq_index=0 346opClass=SimdAlu 347opLat=1 348pipelined=true 349 350[system.cpu0.fuPool.FUList5.opList03] 351type=OpDesc 352eventq_index=0 353opClass=SimdCmp 354opLat=1 355pipelined=true 356 357[system.cpu0.fuPool.FUList5.opList04] 358type=OpDesc 359eventq_index=0 360opClass=SimdCvt 361opLat=1 362pipelined=true 363 364[system.cpu0.fuPool.FUList5.opList05] 365type=OpDesc 366eventq_index=0 367opClass=SimdMisc 368opLat=1 369pipelined=true 370 371[system.cpu0.fuPool.FUList5.opList06] 372type=OpDesc 373eventq_index=0 374opClass=SimdMult 375opLat=1 376pipelined=true 377 378[system.cpu0.fuPool.FUList5.opList07] 379type=OpDesc 380eventq_index=0 381opClass=SimdMultAcc 382opLat=1 383pipelined=true 384 385[system.cpu0.fuPool.FUList5.opList08] 386type=OpDesc 387eventq_index=0 388opClass=SimdShift 389opLat=1 390pipelined=true 391 392[system.cpu0.fuPool.FUList5.opList09] 393type=OpDesc 394eventq_index=0 395opClass=SimdShiftAcc 396opLat=1 397pipelined=true 398 399[system.cpu0.fuPool.FUList5.opList10] 400type=OpDesc 401eventq_index=0 402opClass=SimdSqrt 403opLat=1 404pipelined=true 405 406[system.cpu0.fuPool.FUList5.opList11] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAdd 410opLat=1 411pipelined=true 412 413[system.cpu0.fuPool.FUList5.opList12] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatAlu 417opLat=1 418pipelined=true 419 420[system.cpu0.fuPool.FUList5.opList13] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCmp 424opLat=1 425pipelined=true 426 427[system.cpu0.fuPool.FUList5.opList14] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatCvt 431opLat=1 432pipelined=true 433 434[system.cpu0.fuPool.FUList5.opList15] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatDiv 438opLat=1 439pipelined=true 440 441[system.cpu0.fuPool.FUList5.opList16] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMisc 445opLat=1 446pipelined=true 447 448[system.cpu0.fuPool.FUList5.opList17] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMult 452opLat=1 453pipelined=true 454 455[system.cpu0.fuPool.FUList5.opList18] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatMultAcc 459opLat=1 460pipelined=true 461 462[system.cpu0.fuPool.FUList5.opList19] 463type=OpDesc 464eventq_index=0 465opClass=SimdFloatSqrt 466opLat=1 467pipelined=true 468 469[system.cpu0.fuPool.FUList6] 470type=FUDesc 471children=opList 472count=0 473eventq_index=0 474opList=system.cpu0.fuPool.FUList6.opList 475 476[system.cpu0.fuPool.FUList6.opList] 477type=OpDesc 478eventq_index=0 479opClass=MemWrite 480opLat=1 481pipelined=true 482 483[system.cpu0.fuPool.FUList7] 484type=FUDesc 485children=opList0 opList1 486count=4 487eventq_index=0 488opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 489 490[system.cpu0.fuPool.FUList7.opList0] 491type=OpDesc 492eventq_index=0 493opClass=MemRead 494opLat=1 495pipelined=true 496 497[system.cpu0.fuPool.FUList7.opList1] 498type=OpDesc 499eventq_index=0 500opClass=MemWrite 501opLat=1 502pipelined=true 503 504[system.cpu0.fuPool.FUList8] 505type=FUDesc 506children=opList 507count=1 508eventq_index=0 509opList=system.cpu0.fuPool.FUList8.opList 510 511[system.cpu0.fuPool.FUList8.opList] 512type=OpDesc 513eventq_index=0 514opClass=IprAccess 515opLat=3 516pipelined=false 517 518[system.cpu0.icache] 519type=Cache 520children=tags 521addr_ranges=0:18446744073709551615 522assoc=1 523clk_domain=system.cpu_clk_domain
	524clusivity=mostly_incl
521demand_mshr_reserve=1 522eventq_index=0 523forward_snoops=true 524hit_latency=2 525is_read_only=true 526max_miss_count=0 527mshrs=4 528prefetch_on_access=false 529prefetcher=Null 530response_latency=2 531sequential_access=false 532size=32768 533system=system 534tags=system.cpu0.icache.tags 535tgts_per_mshr=20 536write_buffers=8	525demand_mshr_reserve=1 526eventq_index=0 527forward_snoops=true 528hit_latency=2 529is_read_only=true 530max_miss_count=0 531mshrs=4 532prefetch_on_access=false 533prefetcher=Null 534response_latency=2 535sequential_access=false 536size=32768 537system=system 538tags=system.cpu0.icache.tags 539tgts_per_mshr=20 540write_buffers=8
	541writeback_clean=true
537cpu_side=system.cpu0.icache_port 538mem_side=system.toL2Bus.slave[0] 539 540[system.cpu0.icache.tags] 541type=LRU 542assoc=1 543block_size=64 544clk_domain=system.cpu_clk_domain 545eventq_index=0 546hit_latency=2 547sequential_access=false 548size=32768 549 550[system.cpu0.interrupts] 551type=AlphaInterrupts 552eventq_index=0 553 554[system.cpu0.isa] 555type=AlphaISA 556eventq_index=0 557system=system 558 559[system.cpu0.itb] 560type=AlphaTLB 561eventq_index=0 562size=48 563 564[system.cpu0.tracer] 565type=ExeTracer 566eventq_index=0 567 568[system.cpu1] 569type=DerivO3CPU 570children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 571LFSTSize=1024 572LQEntries=32 573LSQCheckLoads=true 574LSQDepCheckShift=4 575SQEntries=32 576SSITSize=1024 577activity=0 578backComSize=5 579branchPred=system.cpu1.branchPred 580cachePorts=200 581checker=Null 582clk_domain=system.cpu_clk_domain 583commitToDecodeDelay=1 584commitToFetchDelay=1 585commitToIEWDelay=1 586commitToRenameDelay=1 587commitWidth=8 588cpu_id=1 589decodeToFetchDelay=1 590decodeToRenameDelay=1 591decodeWidth=8 592dispatchWidth=8 593do_checkpoint_insts=true 594do_quiesce=true 595do_statistics_insts=true 596dtb=system.cpu1.dtb 597eventq_index=0 598fetchBufferSize=64 599fetchQueueSize=32 600fetchToDecodeDelay=1 601fetchTrapLatency=1 602fetchWidth=8 603forwardComSize=5 604fuPool=system.cpu1.fuPool 605function_trace=false 606function_trace_start=0 607iewToCommitDelay=1 608iewToDecodeDelay=1 609iewToFetchDelay=1 610iewToRenameDelay=1 611interrupts=system.cpu1.interrupts 612isa=system.cpu1.isa 613issueToExecuteDelay=1 614issueWidth=8 615itb=system.cpu1.itb 616max_insts_all_threads=0 617max_insts_any_thread=0 618max_loads_all_threads=0 619max_loads_any_thread=0 620needsTSO=false 621numIQEntries=64 622numPhysCCRegs=0 623numPhysFloatRegs=256 624numPhysIntRegs=256 625numROBEntries=192 626numRobs=1 627numThreads=1 628profile=0 629progress_interval=0 630renameToDecodeDelay=1 631renameToFetchDelay=1 632renameToIEWDelay=2 633renameToROBDelay=1 634renameWidth=8 635simpoint_start_insts= 636smtCommitPolicy=RoundRobin 637smtFetchPolicy=SingleThread 638smtIQPolicy=Partitioned 639smtIQThreshold=100 640smtLSQPolicy=Partitioned 641smtLSQThreshold=100 642smtNumFetchingThreads=1 643smtROBPolicy=Partitioned 644smtROBThreshold=100 645socket_id=0 646squashWidth=8 647store_set_clear_period=250000 648switched_out=false 649system=system 650tracer=system.cpu1.tracer 651trapLatency=13 652wbWidth=8 653workload= 654dcache_port=system.cpu1.dcache.cpu_side 655icache_port=system.cpu1.icache.cpu_side 656 657[system.cpu1.branchPred] 658type=TournamentBP 659BTBEntries=4096 660BTBTagSize=16 661RASSize=16 662choiceCtrBits=2 663choicePredictorSize=8192 664eventq_index=0 665globalCtrBits=2 666globalPredictorSize=8192 667instShiftAmt=2 668localCtrBits=2 669localHistoryTableSize=2048 670localPredictorSize=2048 671numThreads=1 672 673[system.cpu1.dcache] 674type=Cache 675children=tags 676addr_ranges=0:18446744073709551615 677assoc=4 678clk_domain=system.cpu_clk_domain	542cpu_side=system.cpu0.icache_port 543mem_side=system.toL2Bus.slave[0] 544 545[system.cpu0.icache.tags] 546type=LRU 547assoc=1 548block_size=64 549clk_domain=system.cpu_clk_domain 550eventq_index=0 551hit_latency=2 552sequential_access=false 553size=32768 554 555[system.cpu0.interrupts] 556type=AlphaInterrupts 557eventq_index=0 558 559[system.cpu0.isa] 560type=AlphaISA 561eventq_index=0 562system=system 563 564[system.cpu0.itb] 565type=AlphaTLB 566eventq_index=0 567size=48 568 569[system.cpu0.tracer] 570type=ExeTracer 571eventq_index=0 572 573[system.cpu1] 574type=DerivO3CPU 575children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 576LFSTSize=1024 577LQEntries=32 578LSQCheckLoads=true 579LSQDepCheckShift=4 580SQEntries=32 581SSITSize=1024 582activity=0 583backComSize=5 584branchPred=system.cpu1.branchPred 585cachePorts=200 586checker=Null 587clk_domain=system.cpu_clk_domain 588commitToDecodeDelay=1 589commitToFetchDelay=1 590commitToIEWDelay=1 591commitToRenameDelay=1 592commitWidth=8 593cpu_id=1 594decodeToFetchDelay=1 595decodeToRenameDelay=1 596decodeWidth=8 597dispatchWidth=8 598do_checkpoint_insts=true 599do_quiesce=true 600do_statistics_insts=true 601dtb=system.cpu1.dtb 602eventq_index=0 603fetchBufferSize=64 604fetchQueueSize=32 605fetchToDecodeDelay=1 606fetchTrapLatency=1 607fetchWidth=8 608forwardComSize=5 609fuPool=system.cpu1.fuPool 610function_trace=false 611function_trace_start=0 612iewToCommitDelay=1 613iewToDecodeDelay=1 614iewToFetchDelay=1 615iewToRenameDelay=1 616interrupts=system.cpu1.interrupts 617isa=system.cpu1.isa 618issueToExecuteDelay=1 619issueWidth=8 620itb=system.cpu1.itb 621max_insts_all_threads=0 622max_insts_any_thread=0 623max_loads_all_threads=0 624max_loads_any_thread=0 625needsTSO=false 626numIQEntries=64 627numPhysCCRegs=0 628numPhysFloatRegs=256 629numPhysIntRegs=256 630numROBEntries=192 631numRobs=1 632numThreads=1 633profile=0 634progress_interval=0 635renameToDecodeDelay=1 636renameToFetchDelay=1 637renameToIEWDelay=2 638renameToROBDelay=1 639renameWidth=8 640simpoint_start_insts= 641smtCommitPolicy=RoundRobin 642smtFetchPolicy=SingleThread 643smtIQPolicy=Partitioned 644smtIQThreshold=100 645smtLSQPolicy=Partitioned 646smtLSQThreshold=100 647smtNumFetchingThreads=1 648smtROBPolicy=Partitioned 649smtROBThreshold=100 650socket_id=0 651squashWidth=8 652store_set_clear_period=250000 653switched_out=false 654system=system 655tracer=system.cpu1.tracer 656trapLatency=13 657wbWidth=8 658workload= 659dcache_port=system.cpu1.dcache.cpu_side 660icache_port=system.cpu1.icache.cpu_side 661 662[system.cpu1.branchPred] 663type=TournamentBP 664BTBEntries=4096 665BTBTagSize=16 666RASSize=16 667choiceCtrBits=2 668choicePredictorSize=8192 669eventq_index=0 670globalCtrBits=2 671globalPredictorSize=8192 672instShiftAmt=2 673localCtrBits=2 674localHistoryTableSize=2048 675localPredictorSize=2048 676numThreads=1 677 678[system.cpu1.dcache] 679type=Cache 680children=tags 681addr_ranges=0:18446744073709551615 682assoc=4 683clk_domain=system.cpu_clk_domain
	684clusivity=mostly_incl
679demand_mshr_reserve=1 680eventq_index=0 681forward_snoops=true 682hit_latency=2 683is_read_only=false 684max_miss_count=0 685mshrs=4 686prefetch_on_access=false 687prefetcher=Null 688response_latency=2 689sequential_access=false 690size=32768 691system=system 692tags=system.cpu1.dcache.tags 693tgts_per_mshr=20 694write_buffers=8	685demand_mshr_reserve=1 686eventq_index=0 687forward_snoops=true 688hit_latency=2 689is_read_only=false 690max_miss_count=0 691mshrs=4 692prefetch_on_access=false 693prefetcher=Null 694response_latency=2 695sequential_access=false 696size=32768 697system=system 698tags=system.cpu1.dcache.tags 699tgts_per_mshr=20 700write_buffers=8
	701writeback_clean=false
695cpu_side=system.cpu1.dcache_port 696mem_side=system.toL2Bus.slave[3] 697 698[system.cpu1.dcache.tags] 699type=LRU 700assoc=4 701block_size=64 702clk_domain=system.cpu_clk_domain 703eventq_index=0 704hit_latency=2 705sequential_access=false 706size=32768 707 708[system.cpu1.dtb] 709type=AlphaTLB 710eventq_index=0 711size=64 712 713[system.cpu1.fuPool] 714type=FUPool 715children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 716FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 717eventq_index=0 718 719[system.cpu1.fuPool.FUList0] 720type=FUDesc 721children=opList 722count=6 723eventq_index=0 724opList=system.cpu1.fuPool.FUList0.opList 725 726[system.cpu1.fuPool.FUList0.opList] 727type=OpDesc 728eventq_index=0 729opClass=IntAlu 730opLat=1 731pipelined=true 732 733[system.cpu1.fuPool.FUList1] 734type=FUDesc 735children=opList0 opList1 736count=2 737eventq_index=0 738opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 739 740[system.cpu1.fuPool.FUList1.opList0] 741type=OpDesc 742eventq_index=0 743opClass=IntMult 744opLat=3 745pipelined=true 746 747[system.cpu1.fuPool.FUList1.opList1] 748type=OpDesc 749eventq_index=0 750opClass=IntDiv 751opLat=20 752pipelined=false 753 754[system.cpu1.fuPool.FUList2] 755type=FUDesc 756children=opList0 opList1 opList2 757count=4 758eventq_index=0 759opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 760 761[system.cpu1.fuPool.FUList2.opList0] 762type=OpDesc 763eventq_index=0 764opClass=FloatAdd 765opLat=2 766pipelined=true 767 768[system.cpu1.fuPool.FUList2.opList1] 769type=OpDesc 770eventq_index=0 771opClass=FloatCmp 772opLat=2 773pipelined=true 774 775[system.cpu1.fuPool.FUList2.opList2] 776type=OpDesc 777eventq_index=0 778opClass=FloatCvt 779opLat=2 780pipelined=true 781 782[system.cpu1.fuPool.FUList3] 783type=FUDesc 784children=opList0 opList1 opList2 785count=2 786eventq_index=0 787opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 788 789[system.cpu1.fuPool.FUList3.opList0] 790type=OpDesc 791eventq_index=0 792opClass=FloatMult 793opLat=4 794pipelined=true 795 796[system.cpu1.fuPool.FUList3.opList1] 797type=OpDesc 798eventq_index=0 799opClass=FloatDiv 800opLat=12 801pipelined=false 802 803[system.cpu1.fuPool.FUList3.opList2] 804type=OpDesc 805eventq_index=0 806opClass=FloatSqrt 807opLat=24 808pipelined=false 809 810[system.cpu1.fuPool.FUList4] 811type=FUDesc 812children=opList 813count=0 814eventq_index=0 815opList=system.cpu1.fuPool.FUList4.opList 816 817[system.cpu1.fuPool.FUList4.opList] 818type=OpDesc 819eventq_index=0 820opClass=MemRead 821opLat=1 822pipelined=true 823 824[system.cpu1.fuPool.FUList5] 825type=FUDesc 826children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 827count=4 828eventq_index=0 829opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 830 831[system.cpu1.fuPool.FUList5.opList00] 832type=OpDesc 833eventq_index=0 834opClass=SimdAdd 835opLat=1 836pipelined=true 837 838[system.cpu1.fuPool.FUList5.opList01] 839type=OpDesc 840eventq_index=0 841opClass=SimdAddAcc 842opLat=1 843pipelined=true 844 845[system.cpu1.fuPool.FUList5.opList02] 846type=OpDesc 847eventq_index=0 848opClass=SimdAlu 849opLat=1 850pipelined=true 851 852[system.cpu1.fuPool.FUList5.opList03] 853type=OpDesc 854eventq_index=0 855opClass=SimdCmp 856opLat=1 857pipelined=true 858 859[system.cpu1.fuPool.FUList5.opList04] 860type=OpDesc 861eventq_index=0 862opClass=SimdCvt 863opLat=1 864pipelined=true 865 866[system.cpu1.fuPool.FUList5.opList05] 867type=OpDesc 868eventq_index=0 869opClass=SimdMisc 870opLat=1 871pipelined=true 872 873[system.cpu1.fuPool.FUList5.opList06] 874type=OpDesc 875eventq_index=0 876opClass=SimdMult 877opLat=1 878pipelined=true 879 880[system.cpu1.fuPool.FUList5.opList07] 881type=OpDesc 882eventq_index=0 883opClass=SimdMultAcc 884opLat=1 885pipelined=true 886 887[system.cpu1.fuPool.FUList5.opList08] 888type=OpDesc 889eventq_index=0 890opClass=SimdShift 891opLat=1 892pipelined=true 893 894[system.cpu1.fuPool.FUList5.opList09] 895type=OpDesc 896eventq_index=0 897opClass=SimdShiftAcc 898opLat=1 899pipelined=true 900 901[system.cpu1.fuPool.FUList5.opList10] 902type=OpDesc 903eventq_index=0 904opClass=SimdSqrt 905opLat=1 906pipelined=true 907 908[system.cpu1.fuPool.FUList5.opList11] 909type=OpDesc 910eventq_index=0 911opClass=SimdFloatAdd 912opLat=1 913pipelined=true 914 915[system.cpu1.fuPool.FUList5.opList12] 916type=OpDesc 917eventq_index=0 918opClass=SimdFloatAlu 919opLat=1 920pipelined=true 921 922[system.cpu1.fuPool.FUList5.opList13] 923type=OpDesc 924eventq_index=0 925opClass=SimdFloatCmp 926opLat=1 927pipelined=true 928 929[system.cpu1.fuPool.FUList5.opList14] 930type=OpDesc 931eventq_index=0 932opClass=SimdFloatCvt 933opLat=1 934pipelined=true 935 936[system.cpu1.fuPool.FUList5.opList15] 937type=OpDesc 938eventq_index=0 939opClass=SimdFloatDiv 940opLat=1 941pipelined=true 942 943[system.cpu1.fuPool.FUList5.opList16] 944type=OpDesc 945eventq_index=0 946opClass=SimdFloatMisc 947opLat=1 948pipelined=true 949 950[system.cpu1.fuPool.FUList5.opList17] 951type=OpDesc 952eventq_index=0 953opClass=SimdFloatMult 954opLat=1 955pipelined=true 956 957[system.cpu1.fuPool.FUList5.opList18] 958type=OpDesc 959eventq_index=0 960opClass=SimdFloatMultAcc 961opLat=1 962pipelined=true 963 964[system.cpu1.fuPool.FUList5.opList19] 965type=OpDesc 966eventq_index=0 967opClass=SimdFloatSqrt 968opLat=1 969pipelined=true 970 971[system.cpu1.fuPool.FUList6] 972type=FUDesc 973children=opList 974count=0 975eventq_index=0 976opList=system.cpu1.fuPool.FUList6.opList 977 978[system.cpu1.fuPool.FUList6.opList] 979type=OpDesc 980eventq_index=0 981opClass=MemWrite 982opLat=1 983pipelined=true 984 985[system.cpu1.fuPool.FUList7] 986type=FUDesc 987children=opList0 opList1 988count=4 989eventq_index=0 990opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 991 992[system.cpu1.fuPool.FUList7.opList0] 993type=OpDesc 994eventq_index=0 995opClass=MemRead 996opLat=1 997pipelined=true 998 999[system.cpu1.fuPool.FUList7.opList1] 1000type=OpDesc 1001eventq_index=0 1002opClass=MemWrite 1003opLat=1 1004pipelined=true 1005 1006[system.cpu1.fuPool.FUList8] 1007type=FUDesc 1008children=opList 1009count=1 1010eventq_index=0 1011opList=system.cpu1.fuPool.FUList8.opList 1012 1013[system.cpu1.fuPool.FUList8.opList] 1014type=OpDesc 1015eventq_index=0 1016opClass=IprAccess 1017opLat=3 1018pipelined=false 1019 1020[system.cpu1.icache] 1021type=Cache 1022children=tags 1023addr_ranges=0:18446744073709551615 1024assoc=1 1025clk_domain=system.cpu_clk_domain	702cpu_side=system.cpu1.dcache_port 703mem_side=system.toL2Bus.slave[3] 704 705[system.cpu1.dcache.tags] 706type=LRU 707assoc=4 708block_size=64 709clk_domain=system.cpu_clk_domain 710eventq_index=0 711hit_latency=2 712sequential_access=false 713size=32768 714 715[system.cpu1.dtb] 716type=AlphaTLB 717eventq_index=0 718size=64 719 720[system.cpu1.fuPool] 721type=FUPool 722children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 723FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 724eventq_index=0 725 726[system.cpu1.fuPool.FUList0] 727type=FUDesc 728children=opList 729count=6 730eventq_index=0 731opList=system.cpu1.fuPool.FUList0.opList 732 733[system.cpu1.fuPool.FUList0.opList] 734type=OpDesc 735eventq_index=0 736opClass=IntAlu 737opLat=1 738pipelined=true 739 740[system.cpu1.fuPool.FUList1] 741type=FUDesc 742children=opList0 opList1 743count=2 744eventq_index=0 745opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 746 747[system.cpu1.fuPool.FUList1.opList0] 748type=OpDesc 749eventq_index=0 750opClass=IntMult 751opLat=3 752pipelined=true 753 754[system.cpu1.fuPool.FUList1.opList1] 755type=OpDesc 756eventq_index=0 757opClass=IntDiv 758opLat=20 759pipelined=false 760 761[system.cpu1.fuPool.FUList2] 762type=FUDesc 763children=opList0 opList1 opList2 764count=4 765eventq_index=0 766opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 767 768[system.cpu1.fuPool.FUList2.opList0] 769type=OpDesc 770eventq_index=0 771opClass=FloatAdd 772opLat=2 773pipelined=true 774 775[system.cpu1.fuPool.FUList2.opList1] 776type=OpDesc 777eventq_index=0 778opClass=FloatCmp 779opLat=2 780pipelined=true 781 782[system.cpu1.fuPool.FUList2.opList2] 783type=OpDesc 784eventq_index=0 785opClass=FloatCvt 786opLat=2 787pipelined=true 788 789[system.cpu1.fuPool.FUList3] 790type=FUDesc 791children=opList0 opList1 opList2 792count=2 793eventq_index=0 794opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 795 796[system.cpu1.fuPool.FUList3.opList0] 797type=OpDesc 798eventq_index=0 799opClass=FloatMult 800opLat=4 801pipelined=true 802 803[system.cpu1.fuPool.FUList3.opList1] 804type=OpDesc 805eventq_index=0 806opClass=FloatDiv 807opLat=12 808pipelined=false 809 810[system.cpu1.fuPool.FUList3.opList2] 811type=OpDesc 812eventq_index=0 813opClass=FloatSqrt 814opLat=24 815pipelined=false 816 817[system.cpu1.fuPool.FUList4] 818type=FUDesc 819children=opList 820count=0 821eventq_index=0 822opList=system.cpu1.fuPool.FUList4.opList 823 824[system.cpu1.fuPool.FUList4.opList] 825type=OpDesc 826eventq_index=0 827opClass=MemRead 828opLat=1 829pipelined=true 830 831[system.cpu1.fuPool.FUList5] 832type=FUDesc 833children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 834count=4 835eventq_index=0 836opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 837 838[system.cpu1.fuPool.FUList5.opList00] 839type=OpDesc 840eventq_index=0 841opClass=SimdAdd 842opLat=1 843pipelined=true 844 845[system.cpu1.fuPool.FUList5.opList01] 846type=OpDesc 847eventq_index=0 848opClass=SimdAddAcc 849opLat=1 850pipelined=true 851 852[system.cpu1.fuPool.FUList5.opList02] 853type=OpDesc 854eventq_index=0 855opClass=SimdAlu 856opLat=1 857pipelined=true 858 859[system.cpu1.fuPool.FUList5.opList03] 860type=OpDesc 861eventq_index=0 862opClass=SimdCmp 863opLat=1 864pipelined=true 865 866[system.cpu1.fuPool.FUList5.opList04] 867type=OpDesc 868eventq_index=0 869opClass=SimdCvt 870opLat=1 871pipelined=true 872 873[system.cpu1.fuPool.FUList5.opList05] 874type=OpDesc 875eventq_index=0 876opClass=SimdMisc 877opLat=1 878pipelined=true 879 880[system.cpu1.fuPool.FUList5.opList06] 881type=OpDesc 882eventq_index=0 883opClass=SimdMult 884opLat=1 885pipelined=true 886 887[system.cpu1.fuPool.FUList5.opList07] 888type=OpDesc 889eventq_index=0 890opClass=SimdMultAcc 891opLat=1 892pipelined=true 893 894[system.cpu1.fuPool.FUList5.opList08] 895type=OpDesc 896eventq_index=0 897opClass=SimdShift 898opLat=1 899pipelined=true 900 901[system.cpu1.fuPool.FUList5.opList09] 902type=OpDesc 903eventq_index=0 904opClass=SimdShiftAcc 905opLat=1 906pipelined=true 907 908[system.cpu1.fuPool.FUList5.opList10] 909type=OpDesc 910eventq_index=0 911opClass=SimdSqrt 912opLat=1 913pipelined=true 914 915[system.cpu1.fuPool.FUList5.opList11] 916type=OpDesc 917eventq_index=0 918opClass=SimdFloatAdd 919opLat=1 920pipelined=true 921 922[system.cpu1.fuPool.FUList5.opList12] 923type=OpDesc 924eventq_index=0 925opClass=SimdFloatAlu 926opLat=1 927pipelined=true 928 929[system.cpu1.fuPool.FUList5.opList13] 930type=OpDesc 931eventq_index=0 932opClass=SimdFloatCmp 933opLat=1 934pipelined=true 935 936[system.cpu1.fuPool.FUList5.opList14] 937type=OpDesc 938eventq_index=0 939opClass=SimdFloatCvt 940opLat=1 941pipelined=true 942 943[system.cpu1.fuPool.FUList5.opList15] 944type=OpDesc 945eventq_index=0 946opClass=SimdFloatDiv 947opLat=1 948pipelined=true 949 950[system.cpu1.fuPool.FUList5.opList16] 951type=OpDesc 952eventq_index=0 953opClass=SimdFloatMisc 954opLat=1 955pipelined=true 956 957[system.cpu1.fuPool.FUList5.opList17] 958type=OpDesc 959eventq_index=0 960opClass=SimdFloatMult 961opLat=1 962pipelined=true 963 964[system.cpu1.fuPool.FUList5.opList18] 965type=OpDesc 966eventq_index=0 967opClass=SimdFloatMultAcc 968opLat=1 969pipelined=true 970 971[system.cpu1.fuPool.FUList5.opList19] 972type=OpDesc 973eventq_index=0 974opClass=SimdFloatSqrt 975opLat=1 976pipelined=true 977 978[system.cpu1.fuPool.FUList6] 979type=FUDesc 980children=opList 981count=0 982eventq_index=0 983opList=system.cpu1.fuPool.FUList6.opList 984 985[system.cpu1.fuPool.FUList6.opList] 986type=OpDesc 987eventq_index=0 988opClass=MemWrite 989opLat=1 990pipelined=true 991 992[system.cpu1.fuPool.FUList7] 993type=FUDesc 994children=opList0 opList1 995count=4 996eventq_index=0 997opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 998 999[system.cpu1.fuPool.FUList7.opList0] 1000type=OpDesc 1001eventq_index=0 1002opClass=MemRead 1003opLat=1 1004pipelined=true 1005 1006[system.cpu1.fuPool.FUList7.opList1] 1007type=OpDesc 1008eventq_index=0 1009opClass=MemWrite 1010opLat=1 1011pipelined=true 1012 1013[system.cpu1.fuPool.FUList8] 1014type=FUDesc 1015children=opList 1016count=1 1017eventq_index=0 1018opList=system.cpu1.fuPool.FUList8.opList 1019 1020[system.cpu1.fuPool.FUList8.opList] 1021type=OpDesc 1022eventq_index=0 1023opClass=IprAccess 1024opLat=3 1025pipelined=false 1026 1027[system.cpu1.icache] 1028type=Cache 1029children=tags 1030addr_ranges=0:18446744073709551615 1031assoc=1 1032clk_domain=system.cpu_clk_domain
	1033clusivity=mostly_incl
1026demand_mshr_reserve=1 1027eventq_index=0 1028forward_snoops=true 1029hit_latency=2 1030is_read_only=true 1031max_miss_count=0 1032mshrs=4 1033prefetch_on_access=false 1034prefetcher=Null 1035response_latency=2 1036sequential_access=false 1037size=32768 1038system=system 1039tags=system.cpu1.icache.tags 1040tgts_per_mshr=20 1041write_buffers=8	1034demand_mshr_reserve=1 1035eventq_index=0 1036forward_snoops=true 1037hit_latency=2 1038is_read_only=true 1039max_miss_count=0 1040mshrs=4 1041prefetch_on_access=false 1042prefetcher=Null 1043response_latency=2 1044sequential_access=false 1045size=32768 1046system=system 1047tags=system.cpu1.icache.tags 1048tgts_per_mshr=20 1049write_buffers=8
	1050writeback_clean=true
1042cpu_side=system.cpu1.icache_port 1043mem_side=system.toL2Bus.slave[2] 1044 1045[system.cpu1.icache.tags] 1046type=LRU 1047assoc=1 1048block_size=64 1049clk_domain=system.cpu_clk_domain 1050eventq_index=0 1051hit_latency=2 1052sequential_access=false 1053size=32768 1054 1055[system.cpu1.interrupts] 1056type=AlphaInterrupts 1057eventq_index=0 1058 1059[system.cpu1.isa] 1060type=AlphaISA 1061eventq_index=0 1062system=system 1063 1064[system.cpu1.itb] 1065type=AlphaTLB 1066eventq_index=0 1067size=48 1068 1069[system.cpu1.tracer] 1070type=ExeTracer 1071eventq_index=0 1072 1073[system.cpu_clk_domain] 1074type=SrcClockDomain 1075clock=500 1076domain_id=-1 1077eventq_index=0 1078init_perf_level=0 1079voltage_domain=system.voltage_domain 1080 1081[system.disk0] 1082type=IdeDisk 1083children=image 1084delay=1000000 1085driveID=master 1086eventq_index=0 1087image=system.disk0.image 1088 1089[system.disk0.image] 1090type=CowDiskImage 1091children=child 1092child=system.disk0.image.child 1093eventq_index=0 1094image_file= 1095read_only=false 1096table_size=65536 1097 1098[system.disk0.image.child] 1099type=RawDiskImage 1100eventq_index=0	1051cpu_side=system.cpu1.icache_port 1052mem_side=system.toL2Bus.slave[2] 1053 1054[system.cpu1.icache.tags] 1055type=LRU 1056assoc=1 1057block_size=64 1058clk_domain=system.cpu_clk_domain 1059eventq_index=0 1060hit_latency=2 1061sequential_access=false 1062size=32768 1063 1064[system.cpu1.interrupts] 1065type=AlphaInterrupts 1066eventq_index=0 1067 1068[system.cpu1.isa] 1069type=AlphaISA 1070eventq_index=0 1071system=system 1072 1073[system.cpu1.itb] 1074type=AlphaTLB 1075eventq_index=0 1076size=48 1077 1078[system.cpu1.tracer] 1079type=ExeTracer 1080eventq_index=0 1081 1082[system.cpu_clk_domain] 1083type=SrcClockDomain 1084clock=500 1085domain_id=-1 1086eventq_index=0 1087init_perf_level=0 1088voltage_domain=system.voltage_domain 1089 1090[system.disk0] 1091type=IdeDisk 1092children=image 1093delay=1000000 1094driveID=master 1095eventq_index=0 1096image=system.disk0.image 1097 1098[system.disk0.image] 1099type=CowDiskImage 1100children=child 1101child=system.disk0.image.child 1102eventq_index=0 1103image_file= 1104read_only=false 1105table_size=65536 1106 1107[system.disk0.image.child] 1108type=RawDiskImage 1109eventq_index=0
1101image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img	1110image_file=/work/gem5/dist/disks/linux-latest.img
1102read_only=true 1103 1104[system.disk2] 1105type=IdeDisk 1106children=image 1107delay=1000000 1108driveID=master 1109eventq_index=0 1110image=system.disk2.image 1111 1112[system.disk2.image] 1113type=CowDiskImage 1114children=child 1115child=system.disk2.image.child 1116eventq_index=0 1117image_file= 1118read_only=false 1119table_size=65536 1120 1121[system.disk2.image.child] 1122type=RawDiskImage 1123eventq_index=0	1111read_only=true 1112 1113[system.disk2] 1114type=IdeDisk 1115children=image 1116delay=1000000 1117driveID=master 1118eventq_index=0 1119image=system.disk2.image 1120 1121[system.disk2.image] 1122type=CowDiskImage 1123children=child 1124child=system.disk2.image.child 1125eventq_index=0 1126image_file= 1127read_only=false 1128table_size=65536 1129 1130[system.disk2.image.child] 1131type=RawDiskImage 1132eventq_index=0
1124image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img	1133image_file=/work/gem5/dist/disks/linux-bigswap2.img
1125read_only=true 1126 1127[system.dvfs_handler] 1128type=DVFSHandler 1129domains= 1130enable=false 1131eventq_index=0 1132sys_clk_domain=system.clk_domain 1133transition_latency=100000000 1134 1135[system.intrctrl] 1136type=IntrControl 1137eventq_index=0 1138sys=system 1139 1140[system.iobus] 1141type=NoncoherentXBar 1142clk_domain=system.clk_domain 1143eventq_index=0 1144forward_latency=1 1145frontend_latency=2 1146response_latency=2	1134read_only=true 1135 1136[system.dvfs_handler] 1137type=DVFSHandler 1138domains= 1139enable=false 1140eventq_index=0 1141sys_clk_domain=system.clk_domain 1142transition_latency=100000000 1143 1144[system.intrctrl] 1145type=IntrControl 1146eventq_index=0 1147sys=system 1148 1149[system.iobus] 1150type=NoncoherentXBar 1151clk_domain=system.clk_domain 1152eventq_index=0 1153forward_latency=1 1154frontend_latency=2 1155response_latency=2
1147use_default_range=true	1156use_default_range=false
1148width=16	1157width=16
1149default=system.tsunami.pciconfig.pio 1150master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side	1158master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
1151slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1152 1153[system.iocache] 1154type=Cache 1155children=tags 1156addr_ranges=0:134217727 1157assoc=8 1158clk_domain=system.clk_domain	1159slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1160 1161[system.iocache] 1162type=Cache 1163children=tags 1164addr_ranges=0:134217727 1165assoc=8 1166clk_domain=system.clk_domain
	1167clusivity=mostly_incl
1159demand_mshr_reserve=1 1160eventq_index=0 1161forward_snoops=false 1162hit_latency=50 1163is_read_only=false 1164max_miss_count=0 1165mshrs=20 1166prefetch_on_access=false 1167prefetcher=Null 1168response_latency=50 1169sequential_access=false 1170size=1024 1171system=system 1172tags=system.iocache.tags 1173tgts_per_mshr=12 1174write_buffers=8	1168demand_mshr_reserve=1 1169eventq_index=0 1170forward_snoops=false 1171hit_latency=50 1172is_read_only=false 1173max_miss_count=0 1174mshrs=20 1175prefetch_on_access=false 1176prefetcher=Null 1177response_latency=50 1178sequential_access=false 1179size=1024 1180system=system 1181tags=system.iocache.tags 1182tgts_per_mshr=12 1183write_buffers=8
1175cpu_side=system.iobus.master[29]	1184writeback_clean=false 1185cpu_side=system.iobus.master[27]
1176mem_side=system.membus.slave[2] 1177 1178[system.iocache.tags] 1179type=LRU 1180assoc=8 1181block_size=64 1182clk_domain=system.clk_domain 1183eventq_index=0 1184hit_latency=50 1185sequential_access=false 1186size=1024 1187 1188[system.l2c] 1189type=Cache 1190children=tags 1191addr_ranges=0:18446744073709551615 1192assoc=8 1193clk_domain=system.cpu_clk_domain	1186mem_side=system.membus.slave[2] 1187 1188[system.iocache.tags] 1189type=LRU 1190assoc=8 1191block_size=64 1192clk_domain=system.clk_domain 1193eventq_index=0 1194hit_latency=50 1195sequential_access=false 1196size=1024 1197 1198[system.l2c] 1199type=Cache 1200children=tags 1201addr_ranges=0:18446744073709551615 1202assoc=8 1203clk_domain=system.cpu_clk_domain
	1204clusivity=mostly_incl
1194demand_mshr_reserve=1 1195eventq_index=0 1196forward_snoops=true 1197hit_latency=20 1198is_read_only=false 1199max_miss_count=0 1200mshrs=20 1201prefetch_on_access=false 1202prefetcher=Null 1203response_latency=20 1204sequential_access=false 1205size=4194304 1206system=system 1207tags=system.l2c.tags 1208tgts_per_mshr=12 1209write_buffers=8	1205demand_mshr_reserve=1 1206eventq_index=0 1207forward_snoops=true 1208hit_latency=20 1209is_read_only=false 1210max_miss_count=0 1211mshrs=20 1212prefetch_on_access=false 1213prefetcher=Null 1214response_latency=20 1215sequential_access=false 1216size=4194304 1217system=system 1218tags=system.l2c.tags 1219tgts_per_mshr=12 1220write_buffers=8
	1221writeback_clean=false
1210cpu_side=system.toL2Bus.master[0] 1211mem_side=system.membus.slave[1] 1212 1213[system.l2c.tags] 1214type=LRU 1215assoc=8 1216block_size=64 1217clk_domain=system.cpu_clk_domain 1218eventq_index=0 1219hit_latency=20 1220sequential_access=false 1221size=4194304 1222 1223[system.membus] 1224type=CoherentXBar 1225children=badaddr_responder 1226clk_domain=system.clk_domain 1227eventq_index=0 1228forward_latency=4 1229frontend_latency=3 1230response_latency=2 1231snoop_filter=Null 1232snoop_response_latency=4 1233system=system 1234use_default_range=false 1235width=16 1236default=system.membus.badaddr_responder.pio 1237master=system.bridge.slave system.physmem.port 1238slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1239 1240[system.membus.badaddr_responder] 1241type=IsaFake 1242clk_domain=system.clk_domain 1243eventq_index=0 1244fake_mem=false 1245pio_addr=0 1246pio_latency=100000 1247pio_size=8 1248ret_bad_addr=true 1249ret_data16=65535 1250ret_data32=4294967295 1251ret_data64=18446744073709551615 1252ret_data8=255 1253system=system 1254update_data=false 1255warn_access= 1256pio=system.membus.default 1257 1258[system.physmem] 1259type=DRAMCtrl 1260IDD0=0.075000 1261IDD02=0.000000 1262IDD2N=0.050000 1263IDD2N2=0.000000 1264IDD2P0=0.000000 1265IDD2P02=0.000000 1266IDD2P1=0.000000 1267IDD2P12=0.000000 1268IDD3N=0.057000 1269IDD3N2=0.000000 1270IDD3P0=0.000000 1271IDD3P02=0.000000 1272IDD3P1=0.000000 1273IDD3P12=0.000000 1274IDD4R=0.187000 1275IDD4R2=0.000000 1276IDD4W=0.165000 1277IDD4W2=0.000000 1278IDD5=0.220000 1279IDD52=0.000000 1280IDD6=0.000000 1281IDD62=0.000000 1282VDD=1.500000 1283VDD2=0.000000 1284activation_limit=4 1285addr_mapping=RoRaBaCoCh 1286bank_groups_per_rank=0 1287banks_per_rank=8 1288burst_length=8 1289channels=1 1290clk_domain=system.clk_domain 1291conf_table_reported=true 1292device_bus_width=8 1293device_rowbuffer_size=1024 1294device_size=536870912 1295devices_per_rank=8 1296dll=true 1297eventq_index=0 1298in_addr_map=true 1299max_accesses_per_row=16 1300mem_sched_policy=frfcfs 1301min_writes_per_switch=16 1302null=false 1303page_policy=open_adaptive 1304range=0:134217727 1305ranks_per_channel=2 1306read_buffer_size=32 1307static_backend_latency=10000 1308static_frontend_latency=10000 1309tBURST=5000 1310tCCD_L=0 1311tCK=1250 1312tCL=13750 1313tCS=2500 1314tRAS=35000 1315tRCD=13750 1316tREFI=7800000 1317tRFC=260000 1318tRP=13750 1319tRRD=6000 1320tRRD_L=0 1321tRTP=7500 1322tRTW=2500 1323tWR=15000 1324tWTR=7500 1325tXAW=30000 1326tXP=0 1327tXPDLL=0 1328tXS=0 1329tXSDLL=0 1330write_buffer_size=64 1331write_high_thresh_perc=85 1332write_low_thresh_perc=50 1333port=system.membus.master[1] 1334 1335[system.simple_disk] 1336type=SimpleDisk 1337children=disk 1338disk=system.simple_disk.disk 1339eventq_index=0 1340system=system 1341 1342[system.simple_disk.disk] 1343type=RawDiskImage 1344eventq_index=0	1222cpu_side=system.toL2Bus.master[0] 1223mem_side=system.membus.slave[1] 1224 1225[system.l2c.tags] 1226type=LRU 1227assoc=8 1228block_size=64 1229clk_domain=system.cpu_clk_domain 1230eventq_index=0 1231hit_latency=20 1232sequential_access=false 1233size=4194304 1234 1235[system.membus] 1236type=CoherentXBar 1237children=badaddr_responder 1238clk_domain=system.clk_domain 1239eventq_index=0 1240forward_latency=4 1241frontend_latency=3 1242response_latency=2 1243snoop_filter=Null 1244snoop_response_latency=4 1245system=system 1246use_default_range=false 1247width=16 1248default=system.membus.badaddr_responder.pio 1249master=system.bridge.slave system.physmem.port 1250slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1251 1252[system.membus.badaddr_responder] 1253type=IsaFake 1254clk_domain=system.clk_domain 1255eventq_index=0 1256fake_mem=false 1257pio_addr=0 1258pio_latency=100000 1259pio_size=8 1260ret_bad_addr=true 1261ret_data16=65535 1262ret_data32=4294967295 1263ret_data64=18446744073709551615 1264ret_data8=255 1265system=system 1266update_data=false 1267warn_access= 1268pio=system.membus.default 1269 1270[system.physmem] 1271type=DRAMCtrl 1272IDD0=0.075000 1273IDD02=0.000000 1274IDD2N=0.050000 1275IDD2N2=0.000000 1276IDD2P0=0.000000 1277IDD2P02=0.000000 1278IDD2P1=0.000000 1279IDD2P12=0.000000 1280IDD3N=0.057000 1281IDD3N2=0.000000 1282IDD3P0=0.000000 1283IDD3P02=0.000000 1284IDD3P1=0.000000 1285IDD3P12=0.000000 1286IDD4R=0.187000 1287IDD4R2=0.000000 1288IDD4W=0.165000 1289IDD4W2=0.000000 1290IDD5=0.220000 1291IDD52=0.000000 1292IDD6=0.000000 1293IDD62=0.000000 1294VDD=1.500000 1295VDD2=0.000000 1296activation_limit=4 1297addr_mapping=RoRaBaCoCh 1298bank_groups_per_rank=0 1299banks_per_rank=8 1300burst_length=8 1301channels=1 1302clk_domain=system.clk_domain 1303conf_table_reported=true 1304device_bus_width=8 1305device_rowbuffer_size=1024 1306device_size=536870912 1307devices_per_rank=8 1308dll=true 1309eventq_index=0 1310in_addr_map=true 1311max_accesses_per_row=16 1312mem_sched_policy=frfcfs 1313min_writes_per_switch=16 1314null=false 1315page_policy=open_adaptive 1316range=0:134217727 1317ranks_per_channel=2 1318read_buffer_size=32 1319static_backend_latency=10000 1320static_frontend_latency=10000 1321tBURST=5000 1322tCCD_L=0 1323tCK=1250 1324tCL=13750 1325tCS=2500 1326tRAS=35000 1327tRCD=13750 1328tREFI=7800000 1329tRFC=260000 1330tRP=13750 1331tRRD=6000 1332tRRD_L=0 1333tRTP=7500 1334tRTW=2500 1335tWR=15000 1336tWTR=7500 1337tXAW=30000 1338tXP=0 1339tXPDLL=0 1340tXS=0 1341tXSDLL=0 1342write_buffer_size=64 1343write_high_thresh_perc=85 1344write_low_thresh_perc=50 1345port=system.membus.master[1] 1346 1347[system.simple_disk] 1348type=SimpleDisk 1349children=disk 1350disk=system.simple_disk.disk 1351eventq_index=0 1352system=system 1353 1354[system.simple_disk.disk] 1355type=RawDiskImage 1356eventq_index=0
1345image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img	1357image_file=/work/gem5/dist/disks/linux-latest.img
1346read_only=true 1347 1348[system.terminal] 1349type=Terminal 1350eventq_index=0 1351intr_control=system.intrctrl 1352number=0 1353output=true 1354port=3456 1355 1356[system.toL2Bus] 1357type=CoherentXBar	1358read_only=true 1359 1360[system.terminal] 1361type=Terminal 1362eventq_index=0 1363intr_control=system.intrctrl 1364number=0 1365output=true 1366port=3456 1367 1368[system.toL2Bus] 1369type=CoherentXBar
	1370children=snoop_filter
1358clk_domain=system.cpu_clk_domain 1359eventq_index=0 1360forward_latency=0 1361frontend_latency=1 1362response_latency=1	1371clk_domain=system.cpu_clk_domain 1372eventq_index=0 1373forward_latency=0 1374frontend_latency=1 1375response_latency=1
1363snoop_filter=Null	1376snoop_filter=system.toL2Bus.snoop_filter
1364snoop_response_latency=1 1365system=system 1366use_default_range=false 1367width=32 1368master=system.l2c.cpu_side 1369slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1370	1377snoop_response_latency=1 1378system=system 1379use_default_range=false 1380width=32 1381master=system.l2c.cpu_side 1382slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1383
	1384[system.toL2Bus.snoop_filter] 1385type=SnoopFilter 1386eventq_index=0 1387lookup_latency=0 1388max_capacity=8388608 1389system=system 1390
1371[system.tsunami] 1372type=Tsunami	1391[system.tsunami] 1392type=Tsunami
1373children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart	1393children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
1374eventq_index=0 1375intrctrl=system.intrctrl 1376system=system 1377 1378[system.tsunami.backdoor] 1379type=AlphaBackdoor 1380clk_domain=system.clk_domain 1381cpu=system.cpu0 1382disk=system.simple_disk 1383eventq_index=0 1384pio_addr=8804682956800 1385pio_latency=100000 1386platform=system.tsunami 1387system=system 1388terminal=system.terminal 1389pio=system.iobus.master[24] 1390 1391[system.tsunami.cchip] 1392type=TsunamiCChip 1393clk_domain=system.clk_domain 1394eventq_index=0 1395pio_addr=8803072344064 1396pio_latency=100000 1397system=system 1398tsunami=system.tsunami 1399pio=system.iobus.master[0] 1400 1401[system.tsunami.ethernet] 1402type=NSGigE 1403BAR0=1 1404BAR0LegacyIO=false 1405BAR0Size=256 1406BAR1=0 1407BAR1LegacyIO=false 1408BAR1Size=4096 1409BAR2=0 1410BAR2LegacyIO=false 1411BAR2Size=0 1412BAR3=0 1413BAR3LegacyIO=false 1414BAR3Size=0 1415BAR4=0 1416BAR4LegacyIO=false 1417BAR4Size=0 1418BAR5=0 1419BAR5LegacyIO=false 1420BAR5Size=0 1421BIST=0 1422CacheLineSize=0 1423CapabilityPtr=0 1424CardbusCIS=0 1425ClassCode=2 1426Command=0 1427DeviceID=34 1428ExpansionROM=0 1429HeaderType=0 1430InterruptLine=30 1431InterruptPin=1 1432LatencyTimer=0 1433LegacyIOBase=0 1434MSICAPBaseOffset=0 1435MSICAPCapId=0 1436MSICAPMaskBits=0 1437MSICAPMsgAddr=0 1438MSICAPMsgCtrl=0 1439MSICAPMsgData=0 1440MSICAPMsgUpperAddr=0 1441MSICAPNextCapability=0 1442MSICAPPendingBits=0 1443MSIXCAPBaseOffset=0 1444MSIXCAPCapId=0 1445MSIXCAPNextCapability=0 1446MSIXMsgCtrl=0 1447MSIXPbaOffset=0 1448MSIXTableOffset=0 1449MaximumLatency=52 1450MinimumGrant=176 1451PMCAPBaseOffset=0 1452PMCAPCapId=0 1453PMCAPCapabilities=0 1454PMCAPCtrlStatus=0 1455PMCAPNextCapability=0 1456PXCAPBaseOffset=0 1457PXCAPCapId=0 1458PXCAPCapabilities=0 1459PXCAPDevCap2=0 1460PXCAPDevCapabilities=0 1461PXCAPDevCtrl=0 1462PXCAPDevCtrl2=0 1463PXCAPDevStatus=0 1464PXCAPLinkCap=0 1465PXCAPLinkCtrl=0 1466PXCAPLinkStatus=0 1467PXCAPNextCapability=0 1468ProgIF=0 1469Revision=0 1470Status=656 1471SubClassCode=0 1472SubsystemID=0 1473SubsystemVendorID=0 1474VendorID=4107 1475clk_domain=system.clk_domain 1476config_latency=20000 1477dma_data_free=false 1478dma_desc_free=false 1479dma_no_allocate=true 1480dma_read_delay=0 1481dma_read_factor=0 1482dma_write_delay=0 1483dma_write_factor=0 1484eventq_index=0 1485hardware_address=00:90:00:00:00:01	1394eventq_index=0 1395intrctrl=system.intrctrl 1396system=system 1397 1398[system.tsunami.backdoor] 1399type=AlphaBackdoor 1400clk_domain=system.clk_domain 1401cpu=system.cpu0 1402disk=system.simple_disk 1403eventq_index=0 1404pio_addr=8804682956800 1405pio_latency=100000 1406platform=system.tsunami 1407system=system 1408terminal=system.terminal 1409pio=system.iobus.master[24] 1410 1411[system.tsunami.cchip] 1412type=TsunamiCChip 1413clk_domain=system.clk_domain 1414eventq_index=0 1415pio_addr=8803072344064 1416pio_latency=100000 1417system=system 1418tsunami=system.tsunami 1419pio=system.iobus.master[0] 1420 1421[system.tsunami.ethernet] 1422type=NSGigE 1423BAR0=1 1424BAR0LegacyIO=false 1425BAR0Size=256 1426BAR1=0 1427BAR1LegacyIO=false 1428BAR1Size=4096 1429BAR2=0 1430BAR2LegacyIO=false 1431BAR2Size=0 1432BAR3=0 1433BAR3LegacyIO=false 1434BAR3Size=0 1435BAR4=0 1436BAR4LegacyIO=false 1437BAR4Size=0 1438BAR5=0 1439BAR5LegacyIO=false 1440BAR5Size=0 1441BIST=0 1442CacheLineSize=0 1443CapabilityPtr=0 1444CardbusCIS=0 1445ClassCode=2 1446Command=0 1447DeviceID=34 1448ExpansionROM=0 1449HeaderType=0 1450InterruptLine=30 1451InterruptPin=1 1452LatencyTimer=0 1453LegacyIOBase=0 1454MSICAPBaseOffset=0 1455MSICAPCapId=0 1456MSICAPMaskBits=0 1457MSICAPMsgAddr=0 1458MSICAPMsgCtrl=0 1459MSICAPMsgData=0 1460MSICAPMsgUpperAddr=0 1461MSICAPNextCapability=0 1462MSICAPPendingBits=0 1463MSIXCAPBaseOffset=0 1464MSIXCAPCapId=0 1465MSIXCAPNextCapability=0 1466MSIXMsgCtrl=0 1467MSIXPbaOffset=0 1468MSIXTableOffset=0 1469MaximumLatency=52 1470MinimumGrant=176 1471PMCAPBaseOffset=0 1472PMCAPCapId=0 1473PMCAPCapabilities=0 1474PMCAPCtrlStatus=0 1475PMCAPNextCapability=0 1476PXCAPBaseOffset=0 1477PXCAPCapId=0 1478PXCAPCapabilities=0 1479PXCAPDevCap2=0 1480PXCAPDevCapabilities=0 1481PXCAPDevCtrl=0 1482PXCAPDevCtrl2=0 1483PXCAPDevStatus=0 1484PXCAPLinkCap=0 1485PXCAPLinkCtrl=0 1486PXCAPLinkStatus=0 1487PXCAPNextCapability=0 1488ProgIF=0 1489Revision=0 1490Status=656 1491SubClassCode=0 1492SubsystemID=0 1493SubsystemVendorID=0 1494VendorID=4107 1495clk_domain=system.clk_domain 1496config_latency=20000 1497dma_data_free=false 1498dma_desc_free=false 1499dma_no_allocate=true 1500dma_read_delay=0 1501dma_read_factor=0 1502dma_write_delay=0 1503dma_write_factor=0 1504eventq_index=0 1505hardware_address=00:90:00:00:00:01
	1506host=system.tsunami.pchip
1486intr_delay=10000000 1487pci_bus=0 1488pci_dev=1 1489pci_func=0 1490pio_latency=30000	1507intr_delay=10000000 1508pci_bus=0 1509pci_dev=1 1510pci_func=0 1511pio_latency=30000
1491platform=system.tsunami
1492rss=false 1493rx_delay=1000000 1494rx_fifo_size=524288 1495rx_filter=true 1496rx_thread=false 1497system=system 1498tx_delay=1000000 1499tx_fifo_size=524288 1500tx_thread=false	1512rss=false 1513rx_delay=1000000 1514rx_fifo_size=524288 1515rx_filter=true 1516rx_thread=false 1517system=system 1518tx_delay=1000000 1519tx_fifo_size=524288 1520tx_thread=false
1501config=system.iobus.master[28]
1502dma=system.iobus.slave[2]	1521dma=system.iobus.slave[2]
1503pio=system.iobus.master[27]	1522pio=system.iobus.master[26]
1504 1505[system.tsunami.fake_OROM] 1506type=IsaFake 1507clk_domain=system.clk_domain 1508eventq_index=0 1509fake_mem=false 1510pio_addr=8796093677568 1511pio_latency=100000 1512pio_size=393216 1513ret_bad_addr=false 1514ret_data16=65535 1515ret_data32=4294967295 1516ret_data64=18446744073709551615 1517ret_data8=255 1518system=system 1519update_data=false 1520warn_access= 1521pio=system.iobus.master[8] 1522 1523[system.tsunami.fake_ata0] 1524type=IsaFake 1525clk_domain=system.clk_domain 1526eventq_index=0 1527fake_mem=false 1528pio_addr=8804615848432 1529pio_latency=100000 1530pio_size=8 1531ret_bad_addr=false 1532ret_data16=65535 1533ret_data32=4294967295 1534ret_data64=18446744073709551615 1535ret_data8=255 1536system=system 1537update_data=false 1538warn_access= 1539pio=system.iobus.master[19] 1540 1541[system.tsunami.fake_ata1] 1542type=IsaFake 1543clk_domain=system.clk_domain 1544eventq_index=0 1545fake_mem=false 1546pio_addr=8804615848304 1547pio_latency=100000 1548pio_size=8 1549ret_bad_addr=false 1550ret_data16=65535 1551ret_data32=4294967295 1552ret_data64=18446744073709551615 1553ret_data8=255 1554system=system 1555update_data=false 1556warn_access= 1557pio=system.iobus.master[20] 1558 1559[system.tsunami.fake_pnp_addr] 1560type=IsaFake 1561clk_domain=system.clk_domain 1562eventq_index=0 1563fake_mem=false 1564pio_addr=8804615848569 1565pio_latency=100000 1566pio_size=8 1567ret_bad_addr=false 1568ret_data16=65535 1569ret_data32=4294967295 1570ret_data64=18446744073709551615 1571ret_data8=255 1572system=system 1573update_data=false 1574warn_access= 1575pio=system.iobus.master[9] 1576 1577[system.tsunami.fake_pnp_read0] 1578type=IsaFake 1579clk_domain=system.clk_domain 1580eventq_index=0 1581fake_mem=false 1582pio_addr=8804615848451 1583pio_latency=100000 1584pio_size=8 1585ret_bad_addr=false 1586ret_data16=65535 1587ret_data32=4294967295 1588ret_data64=18446744073709551615 1589ret_data8=255 1590system=system 1591update_data=false 1592warn_access= 1593pio=system.iobus.master[11] 1594 1595[system.tsunami.fake_pnp_read1] 1596type=IsaFake 1597clk_domain=system.clk_domain 1598eventq_index=0 1599fake_mem=false 1600pio_addr=8804615848515 1601pio_latency=100000 1602pio_size=8 1603ret_bad_addr=false 1604ret_data16=65535 1605ret_data32=4294967295 1606ret_data64=18446744073709551615 1607ret_data8=255 1608system=system 1609update_data=false 1610warn_access= 1611pio=system.iobus.master[12] 1612 1613[system.tsunami.fake_pnp_read2] 1614type=IsaFake 1615clk_domain=system.clk_domain 1616eventq_index=0 1617fake_mem=false 1618pio_addr=8804615848579 1619pio_latency=100000 1620pio_size=8 1621ret_bad_addr=false 1622ret_data16=65535 1623ret_data32=4294967295 1624ret_data64=18446744073709551615 1625ret_data8=255 1626system=system 1627update_data=false 1628warn_access= 1629pio=system.iobus.master[13] 1630 1631[system.tsunami.fake_pnp_read3] 1632type=IsaFake 1633clk_domain=system.clk_domain 1634eventq_index=0 1635fake_mem=false 1636pio_addr=8804615848643 1637pio_latency=100000 1638pio_size=8 1639ret_bad_addr=false 1640ret_data16=65535 1641ret_data32=4294967295 1642ret_data64=18446744073709551615 1643ret_data8=255 1644system=system 1645update_data=false 1646warn_access= 1647pio=system.iobus.master[14] 1648 1649[system.tsunami.fake_pnp_read4] 1650type=IsaFake 1651clk_domain=system.clk_domain 1652eventq_index=0 1653fake_mem=false 1654pio_addr=8804615848707 1655pio_latency=100000 1656pio_size=8 1657ret_bad_addr=false 1658ret_data16=65535 1659ret_data32=4294967295 1660ret_data64=18446744073709551615 1661ret_data8=255 1662system=system 1663update_data=false 1664warn_access= 1665pio=system.iobus.master[15] 1666 1667[system.tsunami.fake_pnp_read5] 1668type=IsaFake 1669clk_domain=system.clk_domain 1670eventq_index=0 1671fake_mem=false 1672pio_addr=8804615848771 1673pio_latency=100000 1674pio_size=8 1675ret_bad_addr=false 1676ret_data16=65535 1677ret_data32=4294967295 1678ret_data64=18446744073709551615 1679ret_data8=255 1680system=system 1681update_data=false 1682warn_access= 1683pio=system.iobus.master[16] 1684 1685[system.tsunami.fake_pnp_read6] 1686type=IsaFake 1687clk_domain=system.clk_domain 1688eventq_index=0 1689fake_mem=false 1690pio_addr=8804615848835 1691pio_latency=100000 1692pio_size=8 1693ret_bad_addr=false 1694ret_data16=65535 1695ret_data32=4294967295 1696ret_data64=18446744073709551615 1697ret_data8=255 1698system=system 1699update_data=false 1700warn_access= 1701pio=system.iobus.master[17] 1702 1703[system.tsunami.fake_pnp_read7] 1704type=IsaFake 1705clk_domain=system.clk_domain 1706eventq_index=0 1707fake_mem=false 1708pio_addr=8804615848899 1709pio_latency=100000 1710pio_size=8 1711ret_bad_addr=false 1712ret_data16=65535 1713ret_data32=4294967295 1714ret_data64=18446744073709551615 1715ret_data8=255 1716system=system 1717update_data=false 1718warn_access= 1719pio=system.iobus.master[18] 1720 1721[system.tsunami.fake_pnp_write] 1722type=IsaFake 1723clk_domain=system.clk_domain 1724eventq_index=0 1725fake_mem=false 1726pio_addr=8804615850617 1727pio_latency=100000 1728pio_size=8 1729ret_bad_addr=false 1730ret_data16=65535 1731ret_data32=4294967295 1732ret_data64=18446744073709551615 1733ret_data8=255 1734system=system 1735update_data=false 1736warn_access= 1737pio=system.iobus.master[10] 1738 1739[system.tsunami.fake_ppc] 1740type=IsaFake 1741clk_domain=system.clk_domain 1742eventq_index=0 1743fake_mem=false 1744pio_addr=8804615848891 1745pio_latency=100000 1746pio_size=8 1747ret_bad_addr=false 1748ret_data16=65535 1749ret_data32=4294967295 1750ret_data64=18446744073709551615 1751ret_data8=255 1752system=system 1753update_data=false 1754warn_access= 1755pio=system.iobus.master[7] 1756 1757[system.tsunami.fake_sm_chip] 1758type=IsaFake 1759clk_domain=system.clk_domain 1760eventq_index=0 1761fake_mem=false 1762pio_addr=8804615848816 1763pio_latency=100000 1764pio_size=8 1765ret_bad_addr=false 1766ret_data16=65535 1767ret_data32=4294967295 1768ret_data64=18446744073709551615 1769ret_data8=255 1770system=system 1771update_data=false 1772warn_access= 1773pio=system.iobus.master[2] 1774 1775[system.tsunami.fake_uart1] 1776type=IsaFake 1777clk_domain=system.clk_domain 1778eventq_index=0 1779fake_mem=false 1780pio_addr=8804615848696 1781pio_latency=100000 1782pio_size=8 1783ret_bad_addr=false 1784ret_data16=65535 1785ret_data32=4294967295 1786ret_data64=18446744073709551615 1787ret_data8=255 1788system=system 1789update_data=false 1790warn_access= 1791pio=system.iobus.master[3] 1792 1793[system.tsunami.fake_uart2] 1794type=IsaFake 1795clk_domain=system.clk_domain 1796eventq_index=0 1797fake_mem=false 1798pio_addr=8804615848936 1799pio_latency=100000 1800pio_size=8 1801ret_bad_addr=false 1802ret_data16=65535 1803ret_data32=4294967295 1804ret_data64=18446744073709551615 1805ret_data8=255 1806system=system 1807update_data=false 1808warn_access= 1809pio=system.iobus.master[4] 1810 1811[system.tsunami.fake_uart3] 1812type=IsaFake 1813clk_domain=system.clk_domain 1814eventq_index=0 1815fake_mem=false 1816pio_addr=8804615848680 1817pio_latency=100000 1818pio_size=8 1819ret_bad_addr=false 1820ret_data16=65535 1821ret_data32=4294967295 1822ret_data64=18446744073709551615 1823ret_data8=255 1824system=system 1825update_data=false 1826warn_access= 1827pio=system.iobus.master[5] 1828 1829[system.tsunami.fake_uart4] 1830type=IsaFake 1831clk_domain=system.clk_domain 1832eventq_index=0 1833fake_mem=false 1834pio_addr=8804615848944 1835pio_latency=100000 1836pio_size=8 1837ret_bad_addr=false 1838ret_data16=65535 1839ret_data32=4294967295 1840ret_data64=18446744073709551615 1841ret_data8=255 1842system=system 1843update_data=false 1844warn_access= 1845pio=system.iobus.master[6] 1846 1847[system.tsunami.fb] 1848type=BadDevice 1849clk_domain=system.clk_domain 1850devicename=FrameBuffer 1851eventq_index=0 1852pio_addr=8804615848912 1853pio_latency=100000 1854system=system 1855pio=system.iobus.master[21] 1856 1857[system.tsunami.ide] 1858type=IdeController 1859BAR0=1 1860BAR0LegacyIO=false 1861BAR0Size=8 1862BAR1=1 1863BAR1LegacyIO=false 1864BAR1Size=4 1865BAR2=1 1866BAR2LegacyIO=false 1867BAR2Size=8 1868BAR3=1 1869BAR3LegacyIO=false 1870BAR3Size=4 1871BAR4=1 1872BAR4LegacyIO=false 1873BAR4Size=16 1874BAR5=1 1875BAR5LegacyIO=false 1876BAR5Size=0 1877BIST=0 1878CacheLineSize=0 1879CapabilityPtr=0 1880CardbusCIS=0 1881ClassCode=1 1882Command=0 1883DeviceID=28945 1884ExpansionROM=0 1885HeaderType=0 1886InterruptLine=31 1887InterruptPin=1 1888LatencyTimer=0 1889LegacyIOBase=0 1890MSICAPBaseOffset=0 1891MSICAPCapId=0 1892MSICAPMaskBits=0 1893MSICAPMsgAddr=0 1894MSICAPMsgCtrl=0 1895MSICAPMsgData=0 1896MSICAPMsgUpperAddr=0 1897MSICAPNextCapability=0 1898MSICAPPendingBits=0 1899MSIXCAPBaseOffset=0 1900MSIXCAPCapId=0 1901MSIXCAPNextCapability=0 1902MSIXMsgCtrl=0 1903MSIXPbaOffset=0 1904MSIXTableOffset=0 1905MaximumLatency=0 1906MinimumGrant=0 1907PMCAPBaseOffset=0 1908PMCAPCapId=0 1909PMCAPCapabilities=0 1910PMCAPCtrlStatus=0 1911PMCAPNextCapability=0 1912PXCAPBaseOffset=0 1913PXCAPCapId=0 1914PXCAPCapabilities=0 1915PXCAPDevCap2=0 1916PXCAPDevCapabilities=0 1917PXCAPDevCtrl=0 1918PXCAPDevCtrl2=0 1919PXCAPDevStatus=0 1920PXCAPLinkCap=0 1921PXCAPLinkCtrl=0 1922PXCAPLinkStatus=0 1923PXCAPNextCapability=0 1924ProgIF=133 1925Revision=0 1926Status=640 1927SubClassCode=1 1928SubsystemID=0 1929SubsystemVendorID=0 1930VendorID=32902 1931clk_domain=system.clk_domain 1932config_latency=20000 1933ctrl_offset=0 1934disks=system.disk0 system.disk2 1935eventq_index=0	1523 1524[system.tsunami.fake_OROM] 1525type=IsaFake 1526clk_domain=system.clk_domain 1527eventq_index=0 1528fake_mem=false 1529pio_addr=8796093677568 1530pio_latency=100000 1531pio_size=393216 1532ret_bad_addr=false 1533ret_data16=65535 1534ret_data32=4294967295 1535ret_data64=18446744073709551615 1536ret_data8=255 1537system=system 1538update_data=false 1539warn_access= 1540pio=system.iobus.master[8] 1541 1542[system.tsunami.fake_ata0] 1543type=IsaFake 1544clk_domain=system.clk_domain 1545eventq_index=0 1546fake_mem=false 1547pio_addr=8804615848432 1548pio_latency=100000 1549pio_size=8 1550ret_bad_addr=false 1551ret_data16=65535 1552ret_data32=4294967295 1553ret_data64=18446744073709551615 1554ret_data8=255 1555system=system 1556update_data=false 1557warn_access= 1558pio=system.iobus.master[19] 1559 1560[system.tsunami.fake_ata1] 1561type=IsaFake 1562clk_domain=system.clk_domain 1563eventq_index=0 1564fake_mem=false 1565pio_addr=8804615848304 1566pio_latency=100000 1567pio_size=8 1568ret_bad_addr=false 1569ret_data16=65535 1570ret_data32=4294967295 1571ret_data64=18446744073709551615 1572ret_data8=255 1573system=system 1574update_data=false 1575warn_access= 1576pio=system.iobus.master[20] 1577 1578[system.tsunami.fake_pnp_addr] 1579type=IsaFake 1580clk_domain=system.clk_domain 1581eventq_index=0 1582fake_mem=false 1583pio_addr=8804615848569 1584pio_latency=100000 1585pio_size=8 1586ret_bad_addr=false 1587ret_data16=65535 1588ret_data32=4294967295 1589ret_data64=18446744073709551615 1590ret_data8=255 1591system=system 1592update_data=false 1593warn_access= 1594pio=system.iobus.master[9] 1595 1596[system.tsunami.fake_pnp_read0] 1597type=IsaFake 1598clk_domain=system.clk_domain 1599eventq_index=0 1600fake_mem=false 1601pio_addr=8804615848451 1602pio_latency=100000 1603pio_size=8 1604ret_bad_addr=false 1605ret_data16=65535 1606ret_data32=4294967295 1607ret_data64=18446744073709551615 1608ret_data8=255 1609system=system 1610update_data=false 1611warn_access= 1612pio=system.iobus.master[11] 1613 1614[system.tsunami.fake_pnp_read1] 1615type=IsaFake 1616clk_domain=system.clk_domain 1617eventq_index=0 1618fake_mem=false 1619pio_addr=8804615848515 1620pio_latency=100000 1621pio_size=8 1622ret_bad_addr=false 1623ret_data16=65535 1624ret_data32=4294967295 1625ret_data64=18446744073709551615 1626ret_data8=255 1627system=system 1628update_data=false 1629warn_access= 1630pio=system.iobus.master[12] 1631 1632[system.tsunami.fake_pnp_read2] 1633type=IsaFake 1634clk_domain=system.clk_domain 1635eventq_index=0 1636fake_mem=false 1637pio_addr=8804615848579 1638pio_latency=100000 1639pio_size=8 1640ret_bad_addr=false 1641ret_data16=65535 1642ret_data32=4294967295 1643ret_data64=18446744073709551615 1644ret_data8=255 1645system=system 1646update_data=false 1647warn_access= 1648pio=system.iobus.master[13] 1649 1650[system.tsunami.fake_pnp_read3] 1651type=IsaFake 1652clk_domain=system.clk_domain 1653eventq_index=0 1654fake_mem=false 1655pio_addr=8804615848643 1656pio_latency=100000 1657pio_size=8 1658ret_bad_addr=false 1659ret_data16=65535 1660ret_data32=4294967295 1661ret_data64=18446744073709551615 1662ret_data8=255 1663system=system 1664update_data=false 1665warn_access= 1666pio=system.iobus.master[14] 1667 1668[system.tsunami.fake_pnp_read4] 1669type=IsaFake 1670clk_domain=system.clk_domain 1671eventq_index=0 1672fake_mem=false 1673pio_addr=8804615848707 1674pio_latency=100000 1675pio_size=8 1676ret_bad_addr=false 1677ret_data16=65535 1678ret_data32=4294967295 1679ret_data64=18446744073709551615 1680ret_data8=255 1681system=system 1682update_data=false 1683warn_access= 1684pio=system.iobus.master[15] 1685 1686[system.tsunami.fake_pnp_read5] 1687type=IsaFake 1688clk_domain=system.clk_domain 1689eventq_index=0 1690fake_mem=false 1691pio_addr=8804615848771 1692pio_latency=100000 1693pio_size=8 1694ret_bad_addr=false 1695ret_data16=65535 1696ret_data32=4294967295 1697ret_data64=18446744073709551615 1698ret_data8=255 1699system=system 1700update_data=false 1701warn_access= 1702pio=system.iobus.master[16] 1703 1704[system.tsunami.fake_pnp_read6] 1705type=IsaFake 1706clk_domain=system.clk_domain 1707eventq_index=0 1708fake_mem=false 1709pio_addr=8804615848835 1710pio_latency=100000 1711pio_size=8 1712ret_bad_addr=false 1713ret_data16=65535 1714ret_data32=4294967295 1715ret_data64=18446744073709551615 1716ret_data8=255 1717system=system 1718update_data=false 1719warn_access= 1720pio=system.iobus.master[17] 1721 1722[system.tsunami.fake_pnp_read7] 1723type=IsaFake 1724clk_domain=system.clk_domain 1725eventq_index=0 1726fake_mem=false 1727pio_addr=8804615848899 1728pio_latency=100000 1729pio_size=8 1730ret_bad_addr=false 1731ret_data16=65535 1732ret_data32=4294967295 1733ret_data64=18446744073709551615 1734ret_data8=255 1735system=system 1736update_data=false 1737warn_access= 1738pio=system.iobus.master[18] 1739 1740[system.tsunami.fake_pnp_write] 1741type=IsaFake 1742clk_domain=system.clk_domain 1743eventq_index=0 1744fake_mem=false 1745pio_addr=8804615850617 1746pio_latency=100000 1747pio_size=8 1748ret_bad_addr=false 1749ret_data16=65535 1750ret_data32=4294967295 1751ret_data64=18446744073709551615 1752ret_data8=255 1753system=system 1754update_data=false 1755warn_access= 1756pio=system.iobus.master[10] 1757 1758[system.tsunami.fake_ppc] 1759type=IsaFake 1760clk_domain=system.clk_domain 1761eventq_index=0 1762fake_mem=false 1763pio_addr=8804615848891 1764pio_latency=100000 1765pio_size=8 1766ret_bad_addr=false 1767ret_data16=65535 1768ret_data32=4294967295 1769ret_data64=18446744073709551615 1770ret_data8=255 1771system=system 1772update_data=false 1773warn_access= 1774pio=system.iobus.master[7] 1775 1776[system.tsunami.fake_sm_chip] 1777type=IsaFake 1778clk_domain=system.clk_domain 1779eventq_index=0 1780fake_mem=false 1781pio_addr=8804615848816 1782pio_latency=100000 1783pio_size=8 1784ret_bad_addr=false 1785ret_data16=65535 1786ret_data32=4294967295 1787ret_data64=18446744073709551615 1788ret_data8=255 1789system=system 1790update_data=false 1791warn_access= 1792pio=system.iobus.master[2] 1793 1794[system.tsunami.fake_uart1] 1795type=IsaFake 1796clk_domain=system.clk_domain 1797eventq_index=0 1798fake_mem=false 1799pio_addr=8804615848696 1800pio_latency=100000 1801pio_size=8 1802ret_bad_addr=false 1803ret_data16=65535 1804ret_data32=4294967295 1805ret_data64=18446744073709551615 1806ret_data8=255 1807system=system 1808update_data=false 1809warn_access= 1810pio=system.iobus.master[3] 1811 1812[system.tsunami.fake_uart2] 1813type=IsaFake 1814clk_domain=system.clk_domain 1815eventq_index=0 1816fake_mem=false 1817pio_addr=8804615848936 1818pio_latency=100000 1819pio_size=8 1820ret_bad_addr=false 1821ret_data16=65535 1822ret_data32=4294967295 1823ret_data64=18446744073709551615 1824ret_data8=255 1825system=system 1826update_data=false 1827warn_access= 1828pio=system.iobus.master[4] 1829 1830[system.tsunami.fake_uart3] 1831type=IsaFake 1832clk_domain=system.clk_domain 1833eventq_index=0 1834fake_mem=false 1835pio_addr=8804615848680 1836pio_latency=100000 1837pio_size=8 1838ret_bad_addr=false 1839ret_data16=65535 1840ret_data32=4294967295 1841ret_data64=18446744073709551615 1842ret_data8=255 1843system=system 1844update_data=false 1845warn_access= 1846pio=system.iobus.master[5] 1847 1848[system.tsunami.fake_uart4] 1849type=IsaFake 1850clk_domain=system.clk_domain 1851eventq_index=0 1852fake_mem=false 1853pio_addr=8804615848944 1854pio_latency=100000 1855pio_size=8 1856ret_bad_addr=false 1857ret_data16=65535 1858ret_data32=4294967295 1859ret_data64=18446744073709551615 1860ret_data8=255 1861system=system 1862update_data=false 1863warn_access= 1864pio=system.iobus.master[6] 1865 1866[system.tsunami.fb] 1867type=BadDevice 1868clk_domain=system.clk_domain 1869devicename=FrameBuffer 1870eventq_index=0 1871pio_addr=8804615848912 1872pio_latency=100000 1873system=system 1874pio=system.iobus.master[21] 1875 1876[system.tsunami.ide] 1877type=IdeController 1878BAR0=1 1879BAR0LegacyIO=false 1880BAR0Size=8 1881BAR1=1 1882BAR1LegacyIO=false 1883BAR1Size=4 1884BAR2=1 1885BAR2LegacyIO=false 1886BAR2Size=8 1887BAR3=1 1888BAR3LegacyIO=false 1889BAR3Size=4 1890BAR4=1 1891BAR4LegacyIO=false 1892BAR4Size=16 1893BAR5=1 1894BAR5LegacyIO=false 1895BAR5Size=0 1896BIST=0 1897CacheLineSize=0 1898CapabilityPtr=0 1899CardbusCIS=0 1900ClassCode=1 1901Command=0 1902DeviceID=28945 1903ExpansionROM=0 1904HeaderType=0 1905InterruptLine=31 1906InterruptPin=1 1907LatencyTimer=0 1908LegacyIOBase=0 1909MSICAPBaseOffset=0 1910MSICAPCapId=0 1911MSICAPMaskBits=0 1912MSICAPMsgAddr=0 1913MSICAPMsgCtrl=0 1914MSICAPMsgData=0 1915MSICAPMsgUpperAddr=0 1916MSICAPNextCapability=0 1917MSICAPPendingBits=0 1918MSIXCAPBaseOffset=0 1919MSIXCAPCapId=0 1920MSIXCAPNextCapability=0 1921MSIXMsgCtrl=0 1922MSIXPbaOffset=0 1923MSIXTableOffset=0 1924MaximumLatency=0 1925MinimumGrant=0 1926PMCAPBaseOffset=0 1927PMCAPCapId=0 1928PMCAPCapabilities=0 1929PMCAPCtrlStatus=0 1930PMCAPNextCapability=0 1931PXCAPBaseOffset=0 1932PXCAPCapId=0 1933PXCAPCapabilities=0 1934PXCAPDevCap2=0 1935PXCAPDevCapabilities=0 1936PXCAPDevCtrl=0 1937PXCAPDevCtrl2=0 1938PXCAPDevStatus=0 1939PXCAPLinkCap=0 1940PXCAPLinkCtrl=0 1941PXCAPLinkStatus=0 1942PXCAPNextCapability=0 1943ProgIF=133 1944Revision=0 1945Status=640 1946SubClassCode=1 1947SubsystemID=0 1948SubsystemVendorID=0 1949VendorID=32902 1950clk_domain=system.clk_domain 1951config_latency=20000 1952ctrl_offset=0 1953disks=system.disk0 system.disk2 1954eventq_index=0
	1955host=system.tsunami.pchip
1936io_shift=0 1937pci_bus=0 1938pci_dev=0 1939pci_func=0 1940pio_latency=30000	1956io_shift=0 1957pci_bus=0 1958pci_dev=0 1959pci_func=0 1960pio_latency=30000
1941platform=system.tsunami
1942system=system	1961system=system
1943config=system.iobus.master[26]
1944dma=system.iobus.slave[1] 1945pio=system.iobus.master[25] 1946 1947[system.tsunami.io] 1948type=TsunamiIO 1949clk_domain=system.clk_domain 1950eventq_index=0 1951frequency=976562500 1952pio_addr=8804615847936 1953pio_latency=100000 1954system=system 1955time=Thu Jan 1 00:00:00 2009 1956tsunami=system.tsunami 1957year_is_bcd=false 1958pio=system.iobus.master[22] 1959 1960[system.tsunami.pchip] 1961type=TsunamiPChip 1962clk_domain=system.clk_domain	1962dma=system.iobus.slave[1] 1963pio=system.iobus.master[25] 1964 1965[system.tsunami.io] 1966type=TsunamiIO 1967clk_domain=system.clk_domain 1968eventq_index=0 1969frequency=976562500 1970pio_addr=8804615847936 1971pio_latency=100000 1972system=system 1973time=Thu Jan 1 00:00:00 2009 1974tsunami=system.tsunami 1975year_is_bcd=false 1976pio=system.iobus.master[22] 1977 1978[system.tsunami.pchip] 1979type=TsunamiPChip 1980clk_domain=system.clk_domain
	1981conf_base=8804649402368 1982conf_device_bits=8 1983conf_size=16777216
1963eventq_index=0	1984eventq_index=0
	1985pci_dma_base=0 1986pci_mem_base=8796093022208 1987pci_pio_base=8804615847936
1964pio_addr=8802535473152 1965pio_latency=100000	1988pio_addr=8802535473152 1989pio_latency=100000
	1990platform=system.tsunami
1966system=system 1967tsunami=system.tsunami 1968pio=system.iobus.master[1] 1969	1991system=system 1992tsunami=system.tsunami 1993pio=system.iobus.master[1] 1994
1970[system.tsunami.pciconfig] 1971type=PciConfigAll 1972bus=0 1973clk_domain=system.clk_domain 1974eventq_index=0 1975pio_addr=0 1976pio_latency=30000 1977platform=system.tsunami 1978size=16777216 1979system=system 1980pio=system.iobus.default 1981
1982[system.tsunami.uart] 1983type=Uart8250 1984clk_domain=system.clk_domain 1985eventq_index=0 1986pio_addr=8804615848952 1987pio_latency=100000 1988platform=system.tsunami 1989system=system 1990terminal=system.terminal 1991pio=system.iobus.master[23] 1992 1993[system.voltage_domain] 1994type=VoltageDomain 1995eventq_index=0 1996voltage=1.000000 1997	1995[system.tsunami.uart] 1996type=Uart8250 1997clk_domain=system.clk_domain 1998eventq_index=0 1999pio_addr=8804615848952 2000pio_latency=100000 2001platform=system.tsunami 2002system=system 2003terminal=system.terminal 2004pio=system.iobus.master[23] 2005 2006[system.voltage_domain] 2007type=VoltageDomain 2008eventq_index=0 2009voltage=1.000000 2010