config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
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1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
4eventq_index=0 |
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4full_system=true | 5full_system=true |
6sim_quantum=0 |
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5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxAlphaSystem 11children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 12boot_cpu_frequency=500 13boot_osflags=root=/dev/hda1 console=ttyS0 14cache_line_size=64 15clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
16console=/dist/m5/system/binaries/console | 18console=/scratch/nilay/GEM5/system/binaries/console 19eventq_index=0 |
17init_param=0 | 20init_param=0 |
18kernel=/dist/m5/system/binaries/vmlinux | 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux |
19load_addr_mask=1099511627775 20mem_mode=timing 21mem_ranges=0:134217727 22memories=system.physmem 23num_work_ids=16 | 22load_addr_mask=1099511627775 23mem_mode=timing 24mem_ranges=0:134217727 25memories=system.physmem 26num_work_ids=16 |
24pal=/dist/m5/system/binaries/ts_osfpal | 27pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal |
25readfile=tests/halt.sh 26symbolfile= 27system_rev=1024 28system_type=34 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40clk_domain=system.clk_domain 41delay=50000 | 28readfile=tests/halt.sh 29symbolfile= 30system_rev=1024 31system_type=34 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.bridge] 42type=Bridge 43clk_domain=system.clk_domain 44delay=50000 |
45eventq_index=0 |
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42ranges=8796093022208:18446744073709551615 43req_size=16 44resp_size=16 45master=system.iobus.slave[0] 46slave=system.membus.master[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 | 46ranges=8796093022208:18446744073709551615 47req_size=16 48resp_size=16 49master=system.iobus.slave[0] 50slave=system.membus.master[0] 51 52[system.clk_domain] 53type=SrcClockDomain 54clock=1000 |
55eventq_index=0 |
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51voltage_domain=system.voltage_domain 52 53[system.cpu0] 54type=DerivO3CPU 55children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 56LFSTSize=1024 57LQEntries=32 58LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 74decodeToFetchDelay=1 75decodeToRenameDelay=1 76decodeWidth=8 77dispatchWidth=8 78do_checkpoint_insts=true 79do_quiesce=true 80do_statistics_insts=true 81dtb=system.cpu0.dtb | 56voltage_domain=system.voltage_domain 57 58[system.cpu0] 59type=DerivO3CPU 60children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 61LFSTSize=1024 62LQEntries=32 63LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 79decodeToFetchDelay=1 80decodeToRenameDelay=1 81decodeWidth=8 82dispatchWidth=8 83do_checkpoint_insts=true 84do_quiesce=true 85do_statistics_insts=true 86dtb=system.cpu0.dtb |
87eventq_index=0 88fetchBufferSize=64 |
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82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu0.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 138 139[system.cpu0.branchPred] 140type=BranchPredictor 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 | 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu0.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 145 146[system.cpu0.branchPred] 147type=BranchPredictor 148BTBEntries=4096 149BTBTagSize=16 150RASSize=16 151choiceCtrBits=2 152choicePredictorSize=8192 |
153eventq_index=0 |
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146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=tournament 154 155[system.cpu0.dcache] 156type=BaseCache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=4 160clk_domain=system.cpu_clk_domain | 154globalCtrBits=2 155globalPredictorSize=8192 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=1 161predType=tournament 162 163[system.cpu0.dcache] 164type=BaseCache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=4 168clk_domain=system.cpu_clk_domain |
169eventq_index=0 |
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161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 --- 6 unchanged lines hidden (view full) --- 175cpu_side=system.cpu0.dcache_port 176mem_side=system.toL2Bus.slave[1] 177 178[system.cpu0.dcache.tags] 179type=LRU 180assoc=4 181block_size=64 182clk_domain=system.cpu_clk_domain | 170forward_snoops=true 171hit_latency=2 172is_top_level=true 173max_miss_count=0 174mshrs=4 175prefetch_on_access=false 176prefetcher=Null 177response_latency=2 --- 6 unchanged lines hidden (view full) --- 184cpu_side=system.cpu0.dcache_port 185mem_side=system.toL2Bus.slave[1] 186 187[system.cpu0.dcache.tags] 188type=LRU 189assoc=4 190block_size=64 191clk_domain=system.cpu_clk_domain |
192eventq_index=0 |
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183hit_latency=2 184size=32768 185 186[system.cpu0.dtb] 187type=AlphaTLB | 193hit_latency=2 194size=32768 195 196[system.cpu0.dtb] 197type=AlphaTLB |
198eventq_index=0 |
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188size=64 189 190[system.cpu0.fuPool] 191type=FUPool 192children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 193FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 | 199size=64 200 201[system.cpu0.fuPool] 202type=FUPool 203children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 204FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 |
205eventq_index=0 |
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194 195[system.cpu0.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 | 206 207[system.cpu0.fuPool.FUList0] 208type=FUDesc 209children=opList 210count=6 |
211eventq_index=0 |
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199opList=system.cpu0.fuPool.FUList0.opList 200 201[system.cpu0.fuPool.FUList0.opList] 202type=OpDesc | 212opList=system.cpu0.fuPool.FUList0.opList 213 214[system.cpu0.fuPool.FUList0.opList] 215type=OpDesc |
216eventq_index=0 |
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203issueLat=1 204opClass=IntAlu 205opLat=1 206 207[system.cpu0.fuPool.FUList1] 208type=FUDesc 209children=opList0 opList1 210count=2 | 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu0.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 |
225eventq_index=0 |
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211opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 212 213[system.cpu0.fuPool.FUList1.opList0] 214type=OpDesc | 226opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 227 228[system.cpu0.fuPool.FUList1.opList0] 229type=OpDesc |
230eventq_index=0 |
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215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu0.fuPool.FUList1.opList1] 220type=OpDesc | 231issueLat=1 232opClass=IntMult 233opLat=3 234 235[system.cpu0.fuPool.FUList1.opList1] 236type=OpDesc |
237eventq_index=0 |
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221issueLat=19 222opClass=IntDiv 223opLat=20 224 225[system.cpu0.fuPool.FUList2] 226type=FUDesc 227children=opList0 opList1 opList2 228count=4 | 238issueLat=19 239opClass=IntDiv 240opLat=20 241 242[system.cpu0.fuPool.FUList2] 243type=FUDesc 244children=opList0 opList1 opList2 245count=4 |
246eventq_index=0 |
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229opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 230 231[system.cpu0.fuPool.FUList2.opList0] 232type=OpDesc | 247opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 248 249[system.cpu0.fuPool.FUList2.opList0] 250type=OpDesc |
251eventq_index=0 |
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233issueLat=1 234opClass=FloatAdd 235opLat=2 236 237[system.cpu0.fuPool.FUList2.opList1] 238type=OpDesc | 252issueLat=1 253opClass=FloatAdd 254opLat=2 255 256[system.cpu0.fuPool.FUList2.opList1] 257type=OpDesc |
258eventq_index=0 |
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239issueLat=1 240opClass=FloatCmp 241opLat=2 242 243[system.cpu0.fuPool.FUList2.opList2] 244type=OpDesc | 259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu0.fuPool.FUList2.opList2] 264type=OpDesc |
265eventq_index=0 |
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245issueLat=1 246opClass=FloatCvt 247opLat=2 248 249[system.cpu0.fuPool.FUList3] 250type=FUDesc 251children=opList0 opList1 opList2 252count=2 | 266issueLat=1 267opClass=FloatCvt 268opLat=2 269 270[system.cpu0.fuPool.FUList3] 271type=FUDesc 272children=opList0 opList1 opList2 273count=2 |
274eventq_index=0 |
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253opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 254 255[system.cpu0.fuPool.FUList3.opList0] 256type=OpDesc | 275opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 276 277[system.cpu0.fuPool.FUList3.opList0] 278type=OpDesc |
279eventq_index=0 |
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257issueLat=1 258opClass=FloatMult 259opLat=4 260 261[system.cpu0.fuPool.FUList3.opList1] 262type=OpDesc | 280issueLat=1 281opClass=FloatMult 282opLat=4 283 284[system.cpu0.fuPool.FUList3.opList1] 285type=OpDesc |
286eventq_index=0 |
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263issueLat=12 264opClass=FloatDiv 265opLat=12 266 267[system.cpu0.fuPool.FUList3.opList2] 268type=OpDesc | 287issueLat=12 288opClass=FloatDiv 289opLat=12 290 291[system.cpu0.fuPool.FUList3.opList2] 292type=OpDesc |
293eventq_index=0 |
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269issueLat=24 270opClass=FloatSqrt 271opLat=24 272 273[system.cpu0.fuPool.FUList4] 274type=FUDesc 275children=opList 276count=0 | 294issueLat=24 295opClass=FloatSqrt 296opLat=24 297 298[system.cpu0.fuPool.FUList4] 299type=FUDesc 300children=opList 301count=0 |
302eventq_index=0 |
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277opList=system.cpu0.fuPool.FUList4.opList 278 279[system.cpu0.fuPool.FUList4.opList] 280type=OpDesc | 303opList=system.cpu0.fuPool.FUList4.opList 304 305[system.cpu0.fuPool.FUList4.opList] 306type=OpDesc |
307eventq_index=0 |
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281issueLat=1 282opClass=MemRead 283opLat=1 284 285[system.cpu0.fuPool.FUList5] 286type=FUDesc 287children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 288count=4 | 308issueLat=1 309opClass=MemRead 310opLat=1 311 312[system.cpu0.fuPool.FUList5] 313type=FUDesc 314children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 315count=4 |
316eventq_index=0 |
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289opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 290 291[system.cpu0.fuPool.FUList5.opList00] 292type=OpDesc | 317opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 318 319[system.cpu0.fuPool.FUList5.opList00] 320type=OpDesc |
321eventq_index=0 |
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293issueLat=1 294opClass=SimdAdd 295opLat=1 296 297[system.cpu0.fuPool.FUList5.opList01] 298type=OpDesc | 322issueLat=1 323opClass=SimdAdd 324opLat=1 325 326[system.cpu0.fuPool.FUList5.opList01] 327type=OpDesc |
328eventq_index=0 |
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299issueLat=1 300opClass=SimdAddAcc 301opLat=1 302 303[system.cpu0.fuPool.FUList5.opList02] 304type=OpDesc | 329issueLat=1 330opClass=SimdAddAcc 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList02] 334type=OpDesc |
335eventq_index=0 |
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305issueLat=1 306opClass=SimdAlu 307opLat=1 308 309[system.cpu0.fuPool.FUList5.opList03] 310type=OpDesc | 336issueLat=1 337opClass=SimdAlu 338opLat=1 339 340[system.cpu0.fuPool.FUList5.opList03] 341type=OpDesc |
342eventq_index=0 |
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311issueLat=1 312opClass=SimdCmp 313opLat=1 314 315[system.cpu0.fuPool.FUList5.opList04] 316type=OpDesc | 343issueLat=1 344opClass=SimdCmp 345opLat=1 346 347[system.cpu0.fuPool.FUList5.opList04] 348type=OpDesc |
349eventq_index=0 |
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317issueLat=1 318opClass=SimdCvt 319opLat=1 320 321[system.cpu0.fuPool.FUList5.opList05] 322type=OpDesc | 350issueLat=1 351opClass=SimdCvt 352opLat=1 353 354[system.cpu0.fuPool.FUList5.opList05] 355type=OpDesc |
356eventq_index=0 |
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323issueLat=1 324opClass=SimdMisc 325opLat=1 326 327[system.cpu0.fuPool.FUList5.opList06] 328type=OpDesc | 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu0.fuPool.FUList5.opList06] 362type=OpDesc |
363eventq_index=0 |
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329issueLat=1 330opClass=SimdMult 331opLat=1 332 333[system.cpu0.fuPool.FUList5.opList07] 334type=OpDesc | 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu0.fuPool.FUList5.opList07] 369type=OpDesc |
370eventq_index=0 |
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335issueLat=1 336opClass=SimdMultAcc 337opLat=1 338 339[system.cpu0.fuPool.FUList5.opList08] 340type=OpDesc | 371issueLat=1 372opClass=SimdMultAcc 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList08] 376type=OpDesc |
377eventq_index=0 |
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341issueLat=1 342opClass=SimdShift 343opLat=1 344 345[system.cpu0.fuPool.FUList5.opList09] 346type=OpDesc | 378issueLat=1 379opClass=SimdShift 380opLat=1 381 382[system.cpu0.fuPool.FUList5.opList09] 383type=OpDesc |
384eventq_index=0 |
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347issueLat=1 348opClass=SimdShiftAcc 349opLat=1 350 351[system.cpu0.fuPool.FUList5.opList10] 352type=OpDesc | 385issueLat=1 386opClass=SimdShiftAcc 387opLat=1 388 389[system.cpu0.fuPool.FUList5.opList10] 390type=OpDesc |
391eventq_index=0 |
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353issueLat=1 354opClass=SimdSqrt 355opLat=1 356 357[system.cpu0.fuPool.FUList5.opList11] 358type=OpDesc | 392issueLat=1 393opClass=SimdSqrt 394opLat=1 395 396[system.cpu0.fuPool.FUList5.opList11] 397type=OpDesc |
398eventq_index=0 |
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359issueLat=1 360opClass=SimdFloatAdd 361opLat=1 362 363[system.cpu0.fuPool.FUList5.opList12] 364type=OpDesc | 399issueLat=1 400opClass=SimdFloatAdd 401opLat=1 402 403[system.cpu0.fuPool.FUList5.opList12] 404type=OpDesc |
405eventq_index=0 |
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365issueLat=1 366opClass=SimdFloatAlu 367opLat=1 368 369[system.cpu0.fuPool.FUList5.opList13] 370type=OpDesc | 406issueLat=1 407opClass=SimdFloatAlu 408opLat=1 409 410[system.cpu0.fuPool.FUList5.opList13] 411type=OpDesc |
412eventq_index=0 |
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371issueLat=1 372opClass=SimdFloatCmp 373opLat=1 374 375[system.cpu0.fuPool.FUList5.opList14] 376type=OpDesc | 413issueLat=1 414opClass=SimdFloatCmp 415opLat=1 416 417[system.cpu0.fuPool.FUList5.opList14] 418type=OpDesc |
419eventq_index=0 |
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377issueLat=1 378opClass=SimdFloatCvt 379opLat=1 380 381[system.cpu0.fuPool.FUList5.opList15] 382type=OpDesc | 420issueLat=1 421opClass=SimdFloatCvt 422opLat=1 423 424[system.cpu0.fuPool.FUList5.opList15] 425type=OpDesc |
426eventq_index=0 |
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383issueLat=1 384opClass=SimdFloatDiv 385opLat=1 386 387[system.cpu0.fuPool.FUList5.opList16] 388type=OpDesc | 427issueLat=1 428opClass=SimdFloatDiv 429opLat=1 430 431[system.cpu0.fuPool.FUList5.opList16] 432type=OpDesc |
433eventq_index=0 |
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389issueLat=1 390opClass=SimdFloatMisc 391opLat=1 392 393[system.cpu0.fuPool.FUList5.opList17] 394type=OpDesc | 434issueLat=1 435opClass=SimdFloatMisc 436opLat=1 437 438[system.cpu0.fuPool.FUList5.opList17] 439type=OpDesc |
440eventq_index=0 |
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395issueLat=1 396opClass=SimdFloatMult 397opLat=1 398 399[system.cpu0.fuPool.FUList5.opList18] 400type=OpDesc | 441issueLat=1 442opClass=SimdFloatMult 443opLat=1 444 445[system.cpu0.fuPool.FUList5.opList18] 446type=OpDesc |
447eventq_index=0 |
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401issueLat=1 402opClass=SimdFloatMultAcc 403opLat=1 404 405[system.cpu0.fuPool.FUList5.opList19] 406type=OpDesc | 448issueLat=1 449opClass=SimdFloatMultAcc 450opLat=1 451 452[system.cpu0.fuPool.FUList5.opList19] 453type=OpDesc |
454eventq_index=0 |
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407issueLat=1 408opClass=SimdFloatSqrt 409opLat=1 410 411[system.cpu0.fuPool.FUList6] 412type=FUDesc 413children=opList 414count=0 | 455issueLat=1 456opClass=SimdFloatSqrt 457opLat=1 458 459[system.cpu0.fuPool.FUList6] 460type=FUDesc 461children=opList 462count=0 |
463eventq_index=0 |
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415opList=system.cpu0.fuPool.FUList6.opList 416 417[system.cpu0.fuPool.FUList6.opList] 418type=OpDesc | 464opList=system.cpu0.fuPool.FUList6.opList 465 466[system.cpu0.fuPool.FUList6.opList] 467type=OpDesc |
468eventq_index=0 |
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419issueLat=1 420opClass=MemWrite 421opLat=1 422 423[system.cpu0.fuPool.FUList7] 424type=FUDesc 425children=opList0 opList1 426count=4 | 469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu0.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4 |
477eventq_index=0 |
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427opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 428 429[system.cpu0.fuPool.FUList7.opList0] 430type=OpDesc | 478opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 479 480[system.cpu0.fuPool.FUList7.opList0] 481type=OpDesc |
482eventq_index=0 |
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431issueLat=1 432opClass=MemRead 433opLat=1 434 435[system.cpu0.fuPool.FUList7.opList1] 436type=OpDesc | 483issueLat=1 484opClass=MemRead 485opLat=1 486 487[system.cpu0.fuPool.FUList7.opList1] 488type=OpDesc |
489eventq_index=0 |
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437issueLat=1 438opClass=MemWrite 439opLat=1 440 441[system.cpu0.fuPool.FUList8] 442type=FUDesc 443children=opList 444count=1 | 490issueLat=1 491opClass=MemWrite 492opLat=1 493 494[system.cpu0.fuPool.FUList8] 495type=FUDesc 496children=opList 497count=1 |
498eventq_index=0 |
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445opList=system.cpu0.fuPool.FUList8.opList 446 447[system.cpu0.fuPool.FUList8.opList] 448type=OpDesc | 499opList=system.cpu0.fuPool.FUList8.opList 500 501[system.cpu0.fuPool.FUList8.opList] 502type=OpDesc |
503eventq_index=0 |
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449issueLat=3 450opClass=IprAccess 451opLat=3 452 453[system.cpu0.icache] 454type=BaseCache 455children=tags 456addr_ranges=0:18446744073709551615 457assoc=1 458clk_domain=system.cpu_clk_domain | 504issueLat=3 505opClass=IprAccess 506opLat=3 507 508[system.cpu0.icache] 509type=BaseCache 510children=tags 511addr_ranges=0:18446744073709551615 512assoc=1 513clk_domain=system.cpu_clk_domain |
514eventq_index=0 |
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459forward_snoops=true 460hit_latency=2 461is_top_level=true 462max_miss_count=0 463mshrs=4 464prefetch_on_access=false 465prefetcher=Null 466response_latency=2 --- 6 unchanged lines hidden (view full) --- 473cpu_side=system.cpu0.icache_port 474mem_side=system.toL2Bus.slave[0] 475 476[system.cpu0.icache.tags] 477type=LRU 478assoc=1 479block_size=64 480clk_domain=system.cpu_clk_domain | 515forward_snoops=true 516hit_latency=2 517is_top_level=true 518max_miss_count=0 519mshrs=4 520prefetch_on_access=false 521prefetcher=Null 522response_latency=2 --- 6 unchanged lines hidden (view full) --- 529cpu_side=system.cpu0.icache_port 530mem_side=system.toL2Bus.slave[0] 531 532[system.cpu0.icache.tags] 533type=LRU 534assoc=1 535block_size=64 536clk_domain=system.cpu_clk_domain |
537eventq_index=0 |
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481hit_latency=2 482size=32768 483 484[system.cpu0.interrupts] 485type=AlphaInterrupts | 538hit_latency=2 539size=32768 540 541[system.cpu0.interrupts] 542type=AlphaInterrupts |
543eventq_index=0 |
|
486 487[system.cpu0.isa] 488type=AlphaISA | 544 545[system.cpu0.isa] 546type=AlphaISA |
547eventq_index=0 |
|
489 490[system.cpu0.itb] 491type=AlphaTLB | 548 549[system.cpu0.itb] 550type=AlphaTLB |
551eventq_index=0 |
|
492size=48 493 494[system.cpu0.tracer] 495type=ExeTracer | 552size=48 553 554[system.cpu0.tracer] 555type=ExeTracer |
556eventq_index=0 |
|
496 497[system.cpu1] 498type=DerivO3CPU 499children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 500LFSTSize=1024 501LQEntries=32 502LSQCheckLoads=true 503LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 518decodeToFetchDelay=1 519decodeToRenameDelay=1 520decodeWidth=8 521dispatchWidth=8 522do_checkpoint_insts=true 523do_quiesce=true 524do_statistics_insts=true 525dtb=system.cpu1.dtb | 557 558[system.cpu1] 559type=DerivO3CPU 560children=branchPred dcache dtb fuPool icache interrupts isa itb tracer 561LFSTSize=1024 562LQEntries=32 563LSQCheckLoads=true 564LSQDepCheckShift=4 --- 14 unchanged lines hidden (view full) --- 579decodeToFetchDelay=1 580decodeToRenameDelay=1 581decodeWidth=8 582dispatchWidth=8 583do_checkpoint_insts=true 584do_quiesce=true 585do_statistics_insts=true 586dtb=system.cpu1.dtb |
587eventq_index=0 588fetchBufferSize=64 |
|
526fetchToDecodeDelay=1 527fetchTrapLatency=1 528fetchWidth=8 529forwardComSize=5 530fuPool=system.cpu1.fuPool 531function_trace=false 532function_trace_start=0 533iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 582 583[system.cpu1.branchPred] 584type=BranchPredictor 585BTBEntries=4096 586BTBTagSize=16 587RASSize=16 588choiceCtrBits=2 589choicePredictorSize=8192 | 589fetchToDecodeDelay=1 590fetchTrapLatency=1 591fetchWidth=8 592forwardComSize=5 593fuPool=system.cpu1.fuPool 594function_trace=false 595function_trace_start=0 596iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 645 646[system.cpu1.branchPred] 647type=BranchPredictor 648BTBEntries=4096 649BTBTagSize=16 650RASSize=16 651choiceCtrBits=2 652choicePredictorSize=8192 |
653eventq_index=0 |
|
590globalCtrBits=2 591globalPredictorSize=8192 592instShiftAmt=2 593localCtrBits=2 594localHistoryTableSize=2048 595localPredictorSize=2048 596numThreads=1 597predType=tournament 598 599[system.cpu1.dcache] 600type=BaseCache 601children=tags 602addr_ranges=0:18446744073709551615 603assoc=4 604clk_domain=system.cpu_clk_domain | 654globalCtrBits=2 655globalPredictorSize=8192 656instShiftAmt=2 657localCtrBits=2 658localHistoryTableSize=2048 659localPredictorSize=2048 660numThreads=1 661predType=tournament 662 663[system.cpu1.dcache] 664type=BaseCache 665children=tags 666addr_ranges=0:18446744073709551615 667assoc=4 668clk_domain=system.cpu_clk_domain |
669eventq_index=0 |
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605forward_snoops=true 606hit_latency=2 607is_top_level=true 608max_miss_count=0 609mshrs=4 610prefetch_on_access=false 611prefetcher=Null 612response_latency=2 --- 6 unchanged lines hidden (view full) --- 619cpu_side=system.cpu1.dcache_port 620mem_side=system.toL2Bus.slave[3] 621 622[system.cpu1.dcache.tags] 623type=LRU 624assoc=4 625block_size=64 626clk_domain=system.cpu_clk_domain | 670forward_snoops=true 671hit_latency=2 672is_top_level=true 673max_miss_count=0 674mshrs=4 675prefetch_on_access=false 676prefetcher=Null 677response_latency=2 --- 6 unchanged lines hidden (view full) --- 684cpu_side=system.cpu1.dcache_port 685mem_side=system.toL2Bus.slave[3] 686 687[system.cpu1.dcache.tags] 688type=LRU 689assoc=4 690block_size=64 691clk_domain=system.cpu_clk_domain |
692eventq_index=0 |
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627hit_latency=2 628size=32768 629 630[system.cpu1.dtb] 631type=AlphaTLB | 693hit_latency=2 694size=32768 695 696[system.cpu1.dtb] 697type=AlphaTLB |
698eventq_index=0 |
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632size=64 633 634[system.cpu1.fuPool] 635type=FUPool 636children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 637FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 | 699size=64 700 701[system.cpu1.fuPool] 702type=FUPool 703children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 704FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 |
705eventq_index=0 |
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638 639[system.cpu1.fuPool.FUList0] 640type=FUDesc 641children=opList 642count=6 | 706 707[system.cpu1.fuPool.FUList0] 708type=FUDesc 709children=opList 710count=6 |
711eventq_index=0 |
|
643opList=system.cpu1.fuPool.FUList0.opList 644 645[system.cpu1.fuPool.FUList0.opList] 646type=OpDesc | 712opList=system.cpu1.fuPool.FUList0.opList 713 714[system.cpu1.fuPool.FUList0.opList] 715type=OpDesc |
716eventq_index=0 |
|
647issueLat=1 648opClass=IntAlu 649opLat=1 650 651[system.cpu1.fuPool.FUList1] 652type=FUDesc 653children=opList0 opList1 654count=2 | 717issueLat=1 718opClass=IntAlu 719opLat=1 720 721[system.cpu1.fuPool.FUList1] 722type=FUDesc 723children=opList0 opList1 724count=2 |
725eventq_index=0 |
|
655opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 656 657[system.cpu1.fuPool.FUList1.opList0] 658type=OpDesc | 726opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 727 728[system.cpu1.fuPool.FUList1.opList0] 729type=OpDesc |
730eventq_index=0 |
|
659issueLat=1 660opClass=IntMult 661opLat=3 662 663[system.cpu1.fuPool.FUList1.opList1] 664type=OpDesc | 731issueLat=1 732opClass=IntMult 733opLat=3 734 735[system.cpu1.fuPool.FUList1.opList1] 736type=OpDesc |
737eventq_index=0 |
|
665issueLat=19 666opClass=IntDiv 667opLat=20 668 669[system.cpu1.fuPool.FUList2] 670type=FUDesc 671children=opList0 opList1 opList2 672count=4 | 738issueLat=19 739opClass=IntDiv 740opLat=20 741 742[system.cpu1.fuPool.FUList2] 743type=FUDesc 744children=opList0 opList1 opList2 745count=4 |
746eventq_index=0 |
|
673opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 674 675[system.cpu1.fuPool.FUList2.opList0] 676type=OpDesc | 747opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 748 749[system.cpu1.fuPool.FUList2.opList0] 750type=OpDesc |
751eventq_index=0 |
|
677issueLat=1 678opClass=FloatAdd 679opLat=2 680 681[system.cpu1.fuPool.FUList2.opList1] 682type=OpDesc | 752issueLat=1 753opClass=FloatAdd 754opLat=2 755 756[system.cpu1.fuPool.FUList2.opList1] 757type=OpDesc |
758eventq_index=0 |
|
683issueLat=1 684opClass=FloatCmp 685opLat=2 686 687[system.cpu1.fuPool.FUList2.opList2] 688type=OpDesc | 759issueLat=1 760opClass=FloatCmp 761opLat=2 762 763[system.cpu1.fuPool.FUList2.opList2] 764type=OpDesc |
765eventq_index=0 |
|
689issueLat=1 690opClass=FloatCvt 691opLat=2 692 693[system.cpu1.fuPool.FUList3] 694type=FUDesc 695children=opList0 opList1 opList2 696count=2 | 766issueLat=1 767opClass=FloatCvt 768opLat=2 769 770[system.cpu1.fuPool.FUList3] 771type=FUDesc 772children=opList0 opList1 opList2 773count=2 |
774eventq_index=0 |
|
697opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 698 699[system.cpu1.fuPool.FUList3.opList0] 700type=OpDesc | 775opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 776 777[system.cpu1.fuPool.FUList3.opList0] 778type=OpDesc |
779eventq_index=0 |
|
701issueLat=1 702opClass=FloatMult 703opLat=4 704 705[system.cpu1.fuPool.FUList3.opList1] 706type=OpDesc | 780issueLat=1 781opClass=FloatMult 782opLat=4 783 784[system.cpu1.fuPool.FUList3.opList1] 785type=OpDesc |
786eventq_index=0 |
|
707issueLat=12 708opClass=FloatDiv 709opLat=12 710 711[system.cpu1.fuPool.FUList3.opList2] 712type=OpDesc | 787issueLat=12 788opClass=FloatDiv 789opLat=12 790 791[system.cpu1.fuPool.FUList3.opList2] 792type=OpDesc |
793eventq_index=0 |
|
713issueLat=24 714opClass=FloatSqrt 715opLat=24 716 717[system.cpu1.fuPool.FUList4] 718type=FUDesc 719children=opList 720count=0 | 794issueLat=24 795opClass=FloatSqrt 796opLat=24 797 798[system.cpu1.fuPool.FUList4] 799type=FUDesc 800children=opList 801count=0 |
802eventq_index=0 |
|
721opList=system.cpu1.fuPool.FUList4.opList 722 723[system.cpu1.fuPool.FUList4.opList] 724type=OpDesc | 803opList=system.cpu1.fuPool.FUList4.opList 804 805[system.cpu1.fuPool.FUList4.opList] 806type=OpDesc |
807eventq_index=0 |
|
725issueLat=1 726opClass=MemRead 727opLat=1 728 729[system.cpu1.fuPool.FUList5] 730type=FUDesc 731children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 732count=4 | 808issueLat=1 809opClass=MemRead 810opLat=1 811 812[system.cpu1.fuPool.FUList5] 813type=FUDesc 814children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 815count=4 |
816eventq_index=0 |
|
733opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 734 735[system.cpu1.fuPool.FUList5.opList00] 736type=OpDesc | 817opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 818 819[system.cpu1.fuPool.FUList5.opList00] 820type=OpDesc |
821eventq_index=0 |
|
737issueLat=1 738opClass=SimdAdd 739opLat=1 740 741[system.cpu1.fuPool.FUList5.opList01] 742type=OpDesc | 822issueLat=1 823opClass=SimdAdd 824opLat=1 825 826[system.cpu1.fuPool.FUList5.opList01] 827type=OpDesc |
828eventq_index=0 |
|
743issueLat=1 744opClass=SimdAddAcc 745opLat=1 746 747[system.cpu1.fuPool.FUList5.opList02] 748type=OpDesc | 829issueLat=1 830opClass=SimdAddAcc 831opLat=1 832 833[system.cpu1.fuPool.FUList5.opList02] 834type=OpDesc |
835eventq_index=0 |
|
749issueLat=1 750opClass=SimdAlu 751opLat=1 752 753[system.cpu1.fuPool.FUList5.opList03] 754type=OpDesc | 836issueLat=1 837opClass=SimdAlu 838opLat=1 839 840[system.cpu1.fuPool.FUList5.opList03] 841type=OpDesc |
842eventq_index=0 |
|
755issueLat=1 756opClass=SimdCmp 757opLat=1 758 759[system.cpu1.fuPool.FUList5.opList04] 760type=OpDesc | 843issueLat=1 844opClass=SimdCmp 845opLat=1 846 847[system.cpu1.fuPool.FUList5.opList04] 848type=OpDesc |
849eventq_index=0 |
|
761issueLat=1 762opClass=SimdCvt 763opLat=1 764 765[system.cpu1.fuPool.FUList5.opList05] 766type=OpDesc | 850issueLat=1 851opClass=SimdCvt 852opLat=1 853 854[system.cpu1.fuPool.FUList5.opList05] 855type=OpDesc |
856eventq_index=0 |
|
767issueLat=1 768opClass=SimdMisc 769opLat=1 770 771[system.cpu1.fuPool.FUList5.opList06] 772type=OpDesc | 857issueLat=1 858opClass=SimdMisc 859opLat=1 860 861[system.cpu1.fuPool.FUList5.opList06] 862type=OpDesc |
863eventq_index=0 |
|
773issueLat=1 774opClass=SimdMult 775opLat=1 776 777[system.cpu1.fuPool.FUList5.opList07] 778type=OpDesc | 864issueLat=1 865opClass=SimdMult 866opLat=1 867 868[system.cpu1.fuPool.FUList5.opList07] 869type=OpDesc |
870eventq_index=0 |
|
779issueLat=1 780opClass=SimdMultAcc 781opLat=1 782 783[system.cpu1.fuPool.FUList5.opList08] 784type=OpDesc | 871issueLat=1 872opClass=SimdMultAcc 873opLat=1 874 875[system.cpu1.fuPool.FUList5.opList08] 876type=OpDesc |
877eventq_index=0 |
|
785issueLat=1 786opClass=SimdShift 787opLat=1 788 789[system.cpu1.fuPool.FUList5.opList09] 790type=OpDesc | 878issueLat=1 879opClass=SimdShift 880opLat=1 881 882[system.cpu1.fuPool.FUList5.opList09] 883type=OpDesc |
884eventq_index=0 |
|
791issueLat=1 792opClass=SimdShiftAcc 793opLat=1 794 795[system.cpu1.fuPool.FUList5.opList10] 796type=OpDesc | 885issueLat=1 886opClass=SimdShiftAcc 887opLat=1 888 889[system.cpu1.fuPool.FUList5.opList10] 890type=OpDesc |
891eventq_index=0 |
|
797issueLat=1 798opClass=SimdSqrt 799opLat=1 800 801[system.cpu1.fuPool.FUList5.opList11] 802type=OpDesc | 892issueLat=1 893opClass=SimdSqrt 894opLat=1 895 896[system.cpu1.fuPool.FUList5.opList11] 897type=OpDesc |
898eventq_index=0 |
|
803issueLat=1 804opClass=SimdFloatAdd 805opLat=1 806 807[system.cpu1.fuPool.FUList5.opList12] 808type=OpDesc | 899issueLat=1 900opClass=SimdFloatAdd 901opLat=1 902 903[system.cpu1.fuPool.FUList5.opList12] 904type=OpDesc |
905eventq_index=0 |
|
809issueLat=1 810opClass=SimdFloatAlu 811opLat=1 812 813[system.cpu1.fuPool.FUList5.opList13] 814type=OpDesc | 906issueLat=1 907opClass=SimdFloatAlu 908opLat=1 909 910[system.cpu1.fuPool.FUList5.opList13] 911type=OpDesc |
912eventq_index=0 |
|
815issueLat=1 816opClass=SimdFloatCmp 817opLat=1 818 819[system.cpu1.fuPool.FUList5.opList14] 820type=OpDesc | 913issueLat=1 914opClass=SimdFloatCmp 915opLat=1 916 917[system.cpu1.fuPool.FUList5.opList14] 918type=OpDesc |
919eventq_index=0 |
|
821issueLat=1 822opClass=SimdFloatCvt 823opLat=1 824 825[system.cpu1.fuPool.FUList5.opList15] 826type=OpDesc | 920issueLat=1 921opClass=SimdFloatCvt 922opLat=1 923 924[system.cpu1.fuPool.FUList5.opList15] 925type=OpDesc |
926eventq_index=0 |
|
827issueLat=1 828opClass=SimdFloatDiv 829opLat=1 830 831[system.cpu1.fuPool.FUList5.opList16] 832type=OpDesc | 927issueLat=1 928opClass=SimdFloatDiv 929opLat=1 930 931[system.cpu1.fuPool.FUList5.opList16] 932type=OpDesc |
933eventq_index=0 |
|
833issueLat=1 834opClass=SimdFloatMisc 835opLat=1 836 837[system.cpu1.fuPool.FUList5.opList17] 838type=OpDesc | 934issueLat=1 935opClass=SimdFloatMisc 936opLat=1 937 938[system.cpu1.fuPool.FUList5.opList17] 939type=OpDesc |
940eventq_index=0 |
|
839issueLat=1 840opClass=SimdFloatMult 841opLat=1 842 843[system.cpu1.fuPool.FUList5.opList18] 844type=OpDesc | 941issueLat=1 942opClass=SimdFloatMult 943opLat=1 944 945[system.cpu1.fuPool.FUList5.opList18] 946type=OpDesc |
947eventq_index=0 |
|
845issueLat=1 846opClass=SimdFloatMultAcc 847opLat=1 848 849[system.cpu1.fuPool.FUList5.opList19] 850type=OpDesc | 948issueLat=1 949opClass=SimdFloatMultAcc 950opLat=1 951 952[system.cpu1.fuPool.FUList5.opList19] 953type=OpDesc |
954eventq_index=0 |
|
851issueLat=1 852opClass=SimdFloatSqrt 853opLat=1 854 855[system.cpu1.fuPool.FUList6] 856type=FUDesc 857children=opList 858count=0 | 955issueLat=1 956opClass=SimdFloatSqrt 957opLat=1 958 959[system.cpu1.fuPool.FUList6] 960type=FUDesc 961children=opList 962count=0 |
963eventq_index=0 |
|
859opList=system.cpu1.fuPool.FUList6.opList 860 861[system.cpu1.fuPool.FUList6.opList] 862type=OpDesc | 964opList=system.cpu1.fuPool.FUList6.opList 965 966[system.cpu1.fuPool.FUList6.opList] 967type=OpDesc |
968eventq_index=0 |
|
863issueLat=1 864opClass=MemWrite 865opLat=1 866 867[system.cpu1.fuPool.FUList7] 868type=FUDesc 869children=opList0 opList1 870count=4 | 969issueLat=1 970opClass=MemWrite 971opLat=1 972 973[system.cpu1.fuPool.FUList7] 974type=FUDesc 975children=opList0 opList1 976count=4 |
977eventq_index=0 |
|
871opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 872 873[system.cpu1.fuPool.FUList7.opList0] 874type=OpDesc | 978opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 979 980[system.cpu1.fuPool.FUList7.opList0] 981type=OpDesc |
982eventq_index=0 |
|
875issueLat=1 876opClass=MemRead 877opLat=1 878 879[system.cpu1.fuPool.FUList7.opList1] 880type=OpDesc | 983issueLat=1 984opClass=MemRead 985opLat=1 986 987[system.cpu1.fuPool.FUList7.opList1] 988type=OpDesc |
989eventq_index=0 |
|
881issueLat=1 882opClass=MemWrite 883opLat=1 884 885[system.cpu1.fuPool.FUList8] 886type=FUDesc 887children=opList 888count=1 | 990issueLat=1 991opClass=MemWrite 992opLat=1 993 994[system.cpu1.fuPool.FUList8] 995type=FUDesc 996children=opList 997count=1 |
998eventq_index=0 |
|
889opList=system.cpu1.fuPool.FUList8.opList 890 891[system.cpu1.fuPool.FUList8.opList] 892type=OpDesc | 999opList=system.cpu1.fuPool.FUList8.opList 1000 1001[system.cpu1.fuPool.FUList8.opList] 1002type=OpDesc |
1003eventq_index=0 |
|
893issueLat=3 894opClass=IprAccess 895opLat=3 896 897[system.cpu1.icache] 898type=BaseCache 899children=tags 900addr_ranges=0:18446744073709551615 901assoc=1 902clk_domain=system.cpu_clk_domain | 1004issueLat=3 1005opClass=IprAccess 1006opLat=3 1007 1008[system.cpu1.icache] 1009type=BaseCache 1010children=tags 1011addr_ranges=0:18446744073709551615 1012assoc=1 1013clk_domain=system.cpu_clk_domain |
1014eventq_index=0 |
|
903forward_snoops=true 904hit_latency=2 905is_top_level=true 906max_miss_count=0 907mshrs=4 908prefetch_on_access=false 909prefetcher=Null 910response_latency=2 --- 6 unchanged lines hidden (view full) --- 917cpu_side=system.cpu1.icache_port 918mem_side=system.toL2Bus.slave[2] 919 920[system.cpu1.icache.tags] 921type=LRU 922assoc=1 923block_size=64 924clk_domain=system.cpu_clk_domain | 1015forward_snoops=true 1016hit_latency=2 1017is_top_level=true 1018max_miss_count=0 1019mshrs=4 1020prefetch_on_access=false 1021prefetcher=Null 1022response_latency=2 --- 6 unchanged lines hidden (view full) --- 1029cpu_side=system.cpu1.icache_port 1030mem_side=system.toL2Bus.slave[2] 1031 1032[system.cpu1.icache.tags] 1033type=LRU 1034assoc=1 1035block_size=64 1036clk_domain=system.cpu_clk_domain |
1037eventq_index=0 |
|
925hit_latency=2 926size=32768 927 928[system.cpu1.interrupts] 929type=AlphaInterrupts | 1038hit_latency=2 1039size=32768 1040 1041[system.cpu1.interrupts] 1042type=AlphaInterrupts |
1043eventq_index=0 |
|
930 931[system.cpu1.isa] 932type=AlphaISA | 1044 1045[system.cpu1.isa] 1046type=AlphaISA |
1047eventq_index=0 |
|
933 934[system.cpu1.itb] 935type=AlphaTLB | 1048 1049[system.cpu1.itb] 1050type=AlphaTLB |
1051eventq_index=0 |
|
936size=48 937 938[system.cpu1.tracer] 939type=ExeTracer | 1052size=48 1053 1054[system.cpu1.tracer] 1055type=ExeTracer |
1056eventq_index=0 |
|
940 941[system.cpu_clk_domain] 942type=SrcClockDomain 943clock=500 | 1057 1058[system.cpu_clk_domain] 1059type=SrcClockDomain 1060clock=500 |
1061eventq_index=0 |
|
944voltage_domain=system.voltage_domain 945 946[system.disk0] 947type=IdeDisk 948children=image 949delay=1000000 950driveID=master | 1062voltage_domain=system.voltage_domain 1063 1064[system.disk0] 1065type=IdeDisk 1066children=image 1067delay=1000000 1068driveID=master |
1069eventq_index=0 |
|
951image=system.disk0.image 952 953[system.disk0.image] 954type=CowDiskImage 955children=child 956child=system.disk0.image.child | 1070image=system.disk0.image 1071 1072[system.disk0.image] 1073type=CowDiskImage 1074children=child 1075child=system.disk0.image.child |
1076eventq_index=0 |
|
957image_file= 958read_only=false 959table_size=65536 960 961[system.disk0.image.child] 962type=RawDiskImage | 1077image_file= 1078read_only=false 1079table_size=65536 1080 1081[system.disk0.image.child] 1082type=RawDiskImage |
963image_file=/dist/m5/system/disks/linux-latest.img | 1083eventq_index=0 1084image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
964read_only=true 965 966[system.disk2] 967type=IdeDisk 968children=image 969delay=1000000 970driveID=master | 1085read_only=true 1086 1087[system.disk2] 1088type=IdeDisk 1089children=image 1090delay=1000000 1091driveID=master |
1092eventq_index=0 |
|
971image=system.disk2.image 972 973[system.disk2.image] 974type=CowDiskImage 975children=child 976child=system.disk2.image.child | 1093image=system.disk2.image 1094 1095[system.disk2.image] 1096type=CowDiskImage 1097children=child 1098child=system.disk2.image.child |
1099eventq_index=0 |
|
977image_file= 978read_only=false 979table_size=65536 980 981[system.disk2.image.child] 982type=RawDiskImage | 1100image_file= 1101read_only=false 1102table_size=65536 1103 1104[system.disk2.image.child] 1105type=RawDiskImage |
983image_file=/dist/m5/system/disks/linux-bigswap2.img | 1106eventq_index=0 1107image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img |
984read_only=true 985 986[system.intrctrl] 987type=IntrControl | 1108read_only=true 1109 1110[system.intrctrl] 1111type=IntrControl |
1112eventq_index=0 |
|
988sys=system 989 990[system.iobus] 991type=NoncoherentBus 992clk_domain=system.clk_domain | 1113sys=system 1114 1115[system.iobus] 1116type=NoncoherentBus 1117clk_domain=system.clk_domain |
1118eventq_index=0 |
|
993header_cycles=1 994use_default_range=true 995width=8 996default=system.tsunami.pciconfig.pio 997master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 998slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 999 1000[system.iocache] 1001type=BaseCache 1002children=tags 1003addr_ranges=0:134217727 1004assoc=8 1005clk_domain=system.clk_domain | 1119header_cycles=1 1120use_default_range=true 1121width=8 1122default=system.tsunami.pciconfig.pio 1123master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 1124slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 1125 1126[system.iocache] 1127type=BaseCache 1128children=tags 1129addr_ranges=0:134217727 1130assoc=8 1131clk_domain=system.clk_domain |
1132eventq_index=0 |
|
1006forward_snoops=false 1007hit_latency=50 1008is_top_level=true 1009max_miss_count=0 1010mshrs=20 1011prefetch_on_access=false 1012prefetcher=Null 1013response_latency=50 --- 6 unchanged lines hidden (view full) --- 1020cpu_side=system.iobus.master[29] 1021mem_side=system.membus.slave[2] 1022 1023[system.iocache.tags] 1024type=LRU 1025assoc=8 1026block_size=64 1027clk_domain=system.clk_domain | 1133forward_snoops=false 1134hit_latency=50 1135is_top_level=true 1136max_miss_count=0 1137mshrs=20 1138prefetch_on_access=false 1139prefetcher=Null 1140response_latency=50 --- 6 unchanged lines hidden (view full) --- 1147cpu_side=system.iobus.master[29] 1148mem_side=system.membus.slave[2] 1149 1150[system.iocache.tags] 1151type=LRU 1152assoc=8 1153block_size=64 1154clk_domain=system.clk_domain |
1155eventq_index=0 |
|
1028hit_latency=50 1029size=1024 1030 1031[system.l2c] 1032type=BaseCache 1033children=tags 1034addr_ranges=0:18446744073709551615 1035assoc=8 1036clk_domain=system.cpu_clk_domain | 1156hit_latency=50 1157size=1024 1158 1159[system.l2c] 1160type=BaseCache 1161children=tags 1162addr_ranges=0:18446744073709551615 1163assoc=8 1164clk_domain=system.cpu_clk_domain |
1165eventq_index=0 |
|
1037forward_snoops=true 1038hit_latency=20 1039is_top_level=false 1040max_miss_count=0 1041mshrs=20 1042prefetch_on_access=false 1043prefetcher=Null 1044response_latency=20 --- 6 unchanged lines hidden (view full) --- 1051cpu_side=system.toL2Bus.master[0] 1052mem_side=system.membus.slave[1] 1053 1054[system.l2c.tags] 1055type=LRU 1056assoc=8 1057block_size=64 1058clk_domain=system.cpu_clk_domain | 1166forward_snoops=true 1167hit_latency=20 1168is_top_level=false 1169max_miss_count=0 1170mshrs=20 1171prefetch_on_access=false 1172prefetcher=Null 1173response_latency=20 --- 6 unchanged lines hidden (view full) --- 1180cpu_side=system.toL2Bus.master[0] 1181mem_side=system.membus.slave[1] 1182 1183[system.l2c.tags] 1184type=LRU 1185assoc=8 1186block_size=64 1187clk_domain=system.cpu_clk_domain |
1188eventq_index=0 |
|
1059hit_latency=20 1060size=4194304 1061 1062[system.membus] 1063type=CoherentBus 1064children=badaddr_responder 1065clk_domain=system.clk_domain | 1189hit_latency=20 1190size=4194304 1191 1192[system.membus] 1193type=CoherentBus 1194children=badaddr_responder 1195clk_domain=system.clk_domain |
1196eventq_index=0 |
|
1066header_cycles=1 1067system=system 1068use_default_range=false 1069width=8 1070default=system.membus.badaddr_responder.pio 1071master=system.bridge.slave system.physmem.port 1072slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1073 1074[system.membus.badaddr_responder] 1075type=IsaFake 1076clk_domain=system.clk_domain | 1197header_cycles=1 1198system=system 1199use_default_range=false 1200width=8 1201default=system.membus.badaddr_responder.pio 1202master=system.bridge.slave system.physmem.port 1203slave=system.system_port system.l2c.mem_side system.iocache.mem_side 1204 1205[system.membus.badaddr_responder] 1206type=IsaFake 1207clk_domain=system.clk_domain |
1208eventq_index=0 |
|
1077fake_mem=false 1078pio_addr=0 1079pio_latency=100000 1080pio_size=8 1081ret_bad_addr=true 1082ret_data16=65535 1083ret_data32=4294967295 1084ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 1095banks_per_rank=8 1096burst_length=8 1097channels=1 1098clk_domain=system.clk_domain 1099conf_table_reported=true 1100device_bus_width=8 1101device_rowbuffer_size=1024 1102devices_per_rank=8 | 1209fake_mem=false 1210pio_addr=0 1211pio_latency=100000 1212pio_size=8 1213ret_bad_addr=true 1214ret_data16=65535 1215ret_data32=4294967295 1216ret_data64=18446744073709551615 --- 10 unchanged lines hidden (view full) --- 1227banks_per_rank=8 1228burst_length=8 1229channels=1 1230clk_domain=system.clk_domain 1231conf_table_reported=true 1232device_bus_width=8 1233device_rowbuffer_size=1024 1234devices_per_rank=8 |
1235eventq_index=0 |
|
1103in_addr_map=true 1104mem_sched_policy=frfcfs 1105null=false 1106page_policy=open 1107range=0:134217727 1108ranks_per_channel=2 1109read_buffer_size=32 1110static_backend_latency=10000 1111static_frontend_latency=10000 1112tBURST=5000 1113tCL=13750 | 1236in_addr_map=true 1237mem_sched_policy=frfcfs 1238null=false 1239page_policy=open 1240range=0:134217727 1241ranks_per_channel=2 1242read_buffer_size=32 1243static_backend_latency=10000 1244static_frontend_latency=10000 1245tBURST=5000 1246tCL=13750 |
1247tRAS=35000 |
|
1114tRCD=13750 1115tREFI=7800000 1116tRFC=300000 1117tRP=13750 | 1248tRCD=13750 1249tREFI=7800000 1250tRFC=300000 1251tRP=13750 |
1252tRRD=6250 |
|
1118tWTR=7500 1119tXAW=40000 1120write_buffer_size=32 | 1253tWTR=7500 1254tXAW=40000 1255write_buffer_size=32 |
1121write_thresh_perc=70 | 1256write_high_thresh_perc=70 1257write_low_thresh_perc=0 |
1122port=system.membus.master[1] 1123 1124[system.simple_disk] 1125type=SimpleDisk 1126children=disk 1127disk=system.simple_disk.disk | 1258port=system.membus.master[1] 1259 1260[system.simple_disk] 1261type=SimpleDisk 1262children=disk 1263disk=system.simple_disk.disk |
1264eventq_index=0 |
|
1128system=system 1129 1130[system.simple_disk.disk] 1131type=RawDiskImage | 1265system=system 1266 1267[system.simple_disk.disk] 1268type=RawDiskImage |
1132image_file=/dist/m5/system/disks/linux-latest.img | 1269eventq_index=0 1270image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img |
1133read_only=true 1134 1135[system.terminal] 1136type=Terminal | 1271read_only=true 1272 1273[system.terminal] 1274type=Terminal |
1275eventq_index=0 |
|
1137intr_control=system.intrctrl 1138number=0 1139output=true 1140port=3456 1141 1142[system.toL2Bus] 1143type=CoherentBus 1144clk_domain=system.cpu_clk_domain | 1276intr_control=system.intrctrl 1277number=0 1278output=true 1279port=3456 1280 1281[system.toL2Bus] 1282type=CoherentBus 1283clk_domain=system.cpu_clk_domain |
1284eventq_index=0 |
|
1145header_cycles=1 1146system=system 1147use_default_range=false 1148width=8 1149master=system.l2c.cpu_side 1150slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1151 1152[system.tsunami] 1153type=Tsunami 1154children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart | 1285header_cycles=1 1286system=system 1287use_default_range=false 1288width=8 1289master=system.l2c.cpu_side 1290slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 1291 1292[system.tsunami] 1293type=Tsunami 1294children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart |
1295eventq_index=0 |
|
1155intrctrl=system.intrctrl 1156system=system 1157 1158[system.tsunami.backdoor] 1159type=AlphaBackdoor 1160clk_domain=system.clk_domain 1161cpu=system.cpu0 1162disk=system.simple_disk | 1296intrctrl=system.intrctrl 1297system=system 1298 1299[system.tsunami.backdoor] 1300type=AlphaBackdoor 1301clk_domain=system.clk_domain 1302cpu=system.cpu0 1303disk=system.simple_disk |
1304eventq_index=0 |
|
1163pio_addr=8804682956800 1164pio_latency=100000 1165platform=system.tsunami 1166system=system 1167terminal=system.terminal 1168pio=system.iobus.master[24] 1169 1170[system.tsunami.cchip] 1171type=TsunamiCChip 1172clk_domain=system.clk_domain | 1305pio_addr=8804682956800 1306pio_latency=100000 1307platform=system.tsunami 1308system=system 1309terminal=system.terminal 1310pio=system.iobus.master[24] 1311 1312[system.tsunami.cchip] 1313type=TsunamiCChip 1314clk_domain=system.clk_domain |
1315eventq_index=0 |
|
1173pio_addr=8803072344064 1174pio_latency=100000 1175system=system 1176tsunami=system.tsunami 1177pio=system.iobus.master[0] 1178 1179[system.tsunami.ethernet] 1180type=NSGigE --- 12 unchanged lines hidden (view full) --- 1193BAR4=0 1194BAR4LegacyIO=false 1195BAR4Size=0 1196BAR5=0 1197BAR5LegacyIO=false 1198BAR5Size=0 1199BIST=0 1200CacheLineSize=0 | 1316pio_addr=8803072344064 1317pio_latency=100000 1318system=system 1319tsunami=system.tsunami 1320pio=system.iobus.master[0] 1321 1322[system.tsunami.ethernet] 1323type=NSGigE --- 12 unchanged lines hidden (view full) --- 1336BAR4=0 1337BAR4LegacyIO=false 1338BAR4Size=0 1339BAR5=0 1340BAR5LegacyIO=false 1341BAR5Size=0 1342BIST=0 1343CacheLineSize=0 |
1344CapabilityPtr=0 |
|
1201CardbusCIS=0 1202ClassCode=2 1203Command=0 1204DeviceID=34 1205ExpansionROM=0 1206HeaderType=0 1207InterruptLine=30 1208InterruptPin=1 1209LatencyTimer=0 | 1345CardbusCIS=0 1346ClassCode=2 1347Command=0 1348DeviceID=34 1349ExpansionROM=0 1350HeaderType=0 1351InterruptLine=30 1352InterruptPin=1 1353LatencyTimer=0 |
1354MSICAPBaseOffset=0 1355MSICAPCapId=0 1356MSICAPMaskBits=0 1357MSICAPMsgAddr=0 1358MSICAPMsgCtrl=0 1359MSICAPMsgData=0 1360MSICAPMsgUpperAddr=0 1361MSICAPNextCapability=0 1362MSICAPPendingBits=0 1363MSIXCAPBaseOffset=0 1364MSIXCAPCapId=0 1365MSIXCAPNextCapability=0 1366MSIXMsgCtrl=0 1367MSIXPbaOffset=0 1368MSIXTableOffset=0 |
|
1210MaximumLatency=52 1211MinimumGrant=176 | 1369MaximumLatency=52 1370MinimumGrant=176 |
1371PMCAPBaseOffset=0 1372PMCAPCapId=0 1373PMCAPCapabilities=0 1374PMCAPCtrlStatus=0 1375PMCAPNextCapability=0 1376PXCAPBaseOffset=0 1377PXCAPCapId=0 1378PXCAPCapabilities=0 1379PXCAPDevCap2=0 1380PXCAPDevCapabilities=0 1381PXCAPDevCtrl=0 1382PXCAPDevCtrl2=0 1383PXCAPDevStatus=0 1384PXCAPLinkCap=0 1385PXCAPLinkCtrl=0 1386PXCAPLinkStatus=0 1387PXCAPNextCapability=0 |
|
1212ProgIF=0 1213Revision=0 1214Status=656 1215SubClassCode=0 1216SubsystemID=0 1217SubsystemVendorID=0 1218VendorID=4107 1219clk_domain=system.clk_domain 1220config_latency=20000 1221dma_data_free=false 1222dma_desc_free=false 1223dma_no_allocate=true 1224dma_read_delay=0 1225dma_read_factor=0 1226dma_write_delay=0 1227dma_write_factor=0 | 1388ProgIF=0 1389Revision=0 1390Status=656 1391SubClassCode=0 1392SubsystemID=0 1393SubsystemVendorID=0 1394VendorID=4107 1395clk_domain=system.clk_domain 1396config_latency=20000 1397dma_data_free=false 1398dma_desc_free=false 1399dma_no_allocate=true 1400dma_read_delay=0 1401dma_read_factor=0 1402dma_write_delay=0 1403dma_write_factor=0 |
1404eventq_index=0 |
|
1228hardware_address=00:90:00:00:00:01 1229intr_delay=10000000 1230pci_bus=0 1231pci_dev=1 1232pci_func=0 1233pio_latency=30000 1234platform=system.tsunami 1235rss=false --- 7 unchanged lines hidden (view full) --- 1243tx_thread=false 1244config=system.iobus.master[28] 1245dma=system.iobus.slave[2] 1246pio=system.iobus.master[27] 1247 1248[system.tsunami.fake_OROM] 1249type=IsaFake 1250clk_domain=system.clk_domain | 1405hardware_address=00:90:00:00:00:01 1406intr_delay=10000000 1407pci_bus=0 1408pci_dev=1 1409pci_func=0 1410pio_latency=30000 1411platform=system.tsunami 1412rss=false --- 7 unchanged lines hidden (view full) --- 1420tx_thread=false 1421config=system.iobus.master[28] 1422dma=system.iobus.slave[2] 1423pio=system.iobus.master[27] 1424 1425[system.tsunami.fake_OROM] 1426type=IsaFake 1427clk_domain=system.clk_domain |
1428eventq_index=0 |
|
1251fake_mem=false 1252pio_addr=8796093677568 1253pio_latency=100000 1254pio_size=393216 1255ret_bad_addr=false 1256ret_data16=65535 1257ret_data32=4294967295 1258ret_data64=18446744073709551615 1259ret_data8=255 1260system=system 1261update_data=false 1262warn_access= 1263pio=system.iobus.master[8] 1264 1265[system.tsunami.fake_ata0] 1266type=IsaFake 1267clk_domain=system.clk_domain | 1429fake_mem=false 1430pio_addr=8796093677568 1431pio_latency=100000 1432pio_size=393216 1433ret_bad_addr=false 1434ret_data16=65535 1435ret_data32=4294967295 1436ret_data64=18446744073709551615 1437ret_data8=255 1438system=system 1439update_data=false 1440warn_access= 1441pio=system.iobus.master[8] 1442 1443[system.tsunami.fake_ata0] 1444type=IsaFake 1445clk_domain=system.clk_domain |
1446eventq_index=0 |
|
1268fake_mem=false 1269pio_addr=8804615848432 1270pio_latency=100000 1271pio_size=8 1272ret_bad_addr=false 1273ret_data16=65535 1274ret_data32=4294967295 1275ret_data64=18446744073709551615 1276ret_data8=255 1277system=system 1278update_data=false 1279warn_access= 1280pio=system.iobus.master[19] 1281 1282[system.tsunami.fake_ata1] 1283type=IsaFake 1284clk_domain=system.clk_domain | 1447fake_mem=false 1448pio_addr=8804615848432 1449pio_latency=100000 1450pio_size=8 1451ret_bad_addr=false 1452ret_data16=65535 1453ret_data32=4294967295 1454ret_data64=18446744073709551615 1455ret_data8=255 1456system=system 1457update_data=false 1458warn_access= 1459pio=system.iobus.master[19] 1460 1461[system.tsunami.fake_ata1] 1462type=IsaFake 1463clk_domain=system.clk_domain |
1464eventq_index=0 |
|
1285fake_mem=false 1286pio_addr=8804615848304 1287pio_latency=100000 1288pio_size=8 1289ret_bad_addr=false 1290ret_data16=65535 1291ret_data32=4294967295 1292ret_data64=18446744073709551615 1293ret_data8=255 1294system=system 1295update_data=false 1296warn_access= 1297pio=system.iobus.master[20] 1298 1299[system.tsunami.fake_pnp_addr] 1300type=IsaFake 1301clk_domain=system.clk_domain | 1465fake_mem=false 1466pio_addr=8804615848304 1467pio_latency=100000 1468pio_size=8 1469ret_bad_addr=false 1470ret_data16=65535 1471ret_data32=4294967295 1472ret_data64=18446744073709551615 1473ret_data8=255 1474system=system 1475update_data=false 1476warn_access= 1477pio=system.iobus.master[20] 1478 1479[system.tsunami.fake_pnp_addr] 1480type=IsaFake 1481clk_domain=system.clk_domain |
1482eventq_index=0 |
|
1302fake_mem=false 1303pio_addr=8804615848569 1304pio_latency=100000 1305pio_size=8 1306ret_bad_addr=false 1307ret_data16=65535 1308ret_data32=4294967295 1309ret_data64=18446744073709551615 1310ret_data8=255 1311system=system 1312update_data=false 1313warn_access= 1314pio=system.iobus.master[9] 1315 1316[system.tsunami.fake_pnp_read0] 1317type=IsaFake 1318clk_domain=system.clk_domain | 1483fake_mem=false 1484pio_addr=8804615848569 1485pio_latency=100000 1486pio_size=8 1487ret_bad_addr=false 1488ret_data16=65535 1489ret_data32=4294967295 1490ret_data64=18446744073709551615 1491ret_data8=255 1492system=system 1493update_data=false 1494warn_access= 1495pio=system.iobus.master[9] 1496 1497[system.tsunami.fake_pnp_read0] 1498type=IsaFake 1499clk_domain=system.clk_domain |
1500eventq_index=0 |
|
1319fake_mem=false 1320pio_addr=8804615848451 1321pio_latency=100000 1322pio_size=8 1323ret_bad_addr=false 1324ret_data16=65535 1325ret_data32=4294967295 1326ret_data64=18446744073709551615 1327ret_data8=255 1328system=system 1329update_data=false 1330warn_access= 1331pio=system.iobus.master[11] 1332 1333[system.tsunami.fake_pnp_read1] 1334type=IsaFake 1335clk_domain=system.clk_domain | 1501fake_mem=false 1502pio_addr=8804615848451 1503pio_latency=100000 1504pio_size=8 1505ret_bad_addr=false 1506ret_data16=65535 1507ret_data32=4294967295 1508ret_data64=18446744073709551615 1509ret_data8=255 1510system=system 1511update_data=false 1512warn_access= 1513pio=system.iobus.master[11] 1514 1515[system.tsunami.fake_pnp_read1] 1516type=IsaFake 1517clk_domain=system.clk_domain |
1518eventq_index=0 |
|
1336fake_mem=false 1337pio_addr=8804615848515 1338pio_latency=100000 1339pio_size=8 1340ret_bad_addr=false 1341ret_data16=65535 1342ret_data32=4294967295 1343ret_data64=18446744073709551615 1344ret_data8=255 1345system=system 1346update_data=false 1347warn_access= 1348pio=system.iobus.master[12] 1349 1350[system.tsunami.fake_pnp_read2] 1351type=IsaFake 1352clk_domain=system.clk_domain | 1519fake_mem=false 1520pio_addr=8804615848515 1521pio_latency=100000 1522pio_size=8 1523ret_bad_addr=false 1524ret_data16=65535 1525ret_data32=4294967295 1526ret_data64=18446744073709551615 1527ret_data8=255 1528system=system 1529update_data=false 1530warn_access= 1531pio=system.iobus.master[12] 1532 1533[system.tsunami.fake_pnp_read2] 1534type=IsaFake 1535clk_domain=system.clk_domain |
1536eventq_index=0 |
|
1353fake_mem=false 1354pio_addr=8804615848579 1355pio_latency=100000 1356pio_size=8 1357ret_bad_addr=false 1358ret_data16=65535 1359ret_data32=4294967295 1360ret_data64=18446744073709551615 1361ret_data8=255 1362system=system 1363update_data=false 1364warn_access= 1365pio=system.iobus.master[13] 1366 1367[system.tsunami.fake_pnp_read3] 1368type=IsaFake 1369clk_domain=system.clk_domain | 1537fake_mem=false 1538pio_addr=8804615848579 1539pio_latency=100000 1540pio_size=8 1541ret_bad_addr=false 1542ret_data16=65535 1543ret_data32=4294967295 1544ret_data64=18446744073709551615 1545ret_data8=255 1546system=system 1547update_data=false 1548warn_access= 1549pio=system.iobus.master[13] 1550 1551[system.tsunami.fake_pnp_read3] 1552type=IsaFake 1553clk_domain=system.clk_domain |
1554eventq_index=0 |
|
1370fake_mem=false 1371pio_addr=8804615848643 1372pio_latency=100000 1373pio_size=8 1374ret_bad_addr=false 1375ret_data16=65535 1376ret_data32=4294967295 1377ret_data64=18446744073709551615 1378ret_data8=255 1379system=system 1380update_data=false 1381warn_access= 1382pio=system.iobus.master[14] 1383 1384[system.tsunami.fake_pnp_read4] 1385type=IsaFake 1386clk_domain=system.clk_domain | 1555fake_mem=false 1556pio_addr=8804615848643 1557pio_latency=100000 1558pio_size=8 1559ret_bad_addr=false 1560ret_data16=65535 1561ret_data32=4294967295 1562ret_data64=18446744073709551615 1563ret_data8=255 1564system=system 1565update_data=false 1566warn_access= 1567pio=system.iobus.master[14] 1568 1569[system.tsunami.fake_pnp_read4] 1570type=IsaFake 1571clk_domain=system.clk_domain |
1572eventq_index=0 |
|
1387fake_mem=false 1388pio_addr=8804615848707 1389pio_latency=100000 1390pio_size=8 1391ret_bad_addr=false 1392ret_data16=65535 1393ret_data32=4294967295 1394ret_data64=18446744073709551615 1395ret_data8=255 1396system=system 1397update_data=false 1398warn_access= 1399pio=system.iobus.master[15] 1400 1401[system.tsunami.fake_pnp_read5] 1402type=IsaFake 1403clk_domain=system.clk_domain | 1573fake_mem=false 1574pio_addr=8804615848707 1575pio_latency=100000 1576pio_size=8 1577ret_bad_addr=false 1578ret_data16=65535 1579ret_data32=4294967295 1580ret_data64=18446744073709551615 1581ret_data8=255 1582system=system 1583update_data=false 1584warn_access= 1585pio=system.iobus.master[15] 1586 1587[system.tsunami.fake_pnp_read5] 1588type=IsaFake 1589clk_domain=system.clk_domain |
1590eventq_index=0 |
|
1404fake_mem=false 1405pio_addr=8804615848771 1406pio_latency=100000 1407pio_size=8 1408ret_bad_addr=false 1409ret_data16=65535 1410ret_data32=4294967295 1411ret_data64=18446744073709551615 1412ret_data8=255 1413system=system 1414update_data=false 1415warn_access= 1416pio=system.iobus.master[16] 1417 1418[system.tsunami.fake_pnp_read6] 1419type=IsaFake 1420clk_domain=system.clk_domain | 1591fake_mem=false 1592pio_addr=8804615848771 1593pio_latency=100000 1594pio_size=8 1595ret_bad_addr=false 1596ret_data16=65535 1597ret_data32=4294967295 1598ret_data64=18446744073709551615 1599ret_data8=255 1600system=system 1601update_data=false 1602warn_access= 1603pio=system.iobus.master[16] 1604 1605[system.tsunami.fake_pnp_read6] 1606type=IsaFake 1607clk_domain=system.clk_domain |
1608eventq_index=0 |
|
1421fake_mem=false 1422pio_addr=8804615848835 1423pio_latency=100000 1424pio_size=8 1425ret_bad_addr=false 1426ret_data16=65535 1427ret_data32=4294967295 1428ret_data64=18446744073709551615 1429ret_data8=255 1430system=system 1431update_data=false 1432warn_access= 1433pio=system.iobus.master[17] 1434 1435[system.tsunami.fake_pnp_read7] 1436type=IsaFake 1437clk_domain=system.clk_domain | 1609fake_mem=false 1610pio_addr=8804615848835 1611pio_latency=100000 1612pio_size=8 1613ret_bad_addr=false 1614ret_data16=65535 1615ret_data32=4294967295 1616ret_data64=18446744073709551615 1617ret_data8=255 1618system=system 1619update_data=false 1620warn_access= 1621pio=system.iobus.master[17] 1622 1623[system.tsunami.fake_pnp_read7] 1624type=IsaFake 1625clk_domain=system.clk_domain |
1626eventq_index=0 |
|
1438fake_mem=false 1439pio_addr=8804615848899 1440pio_latency=100000 1441pio_size=8 1442ret_bad_addr=false 1443ret_data16=65535 1444ret_data32=4294967295 1445ret_data64=18446744073709551615 1446ret_data8=255 1447system=system 1448update_data=false 1449warn_access= 1450pio=system.iobus.master[18] 1451 1452[system.tsunami.fake_pnp_write] 1453type=IsaFake 1454clk_domain=system.clk_domain | 1627fake_mem=false 1628pio_addr=8804615848899 1629pio_latency=100000 1630pio_size=8 1631ret_bad_addr=false 1632ret_data16=65535 1633ret_data32=4294967295 1634ret_data64=18446744073709551615 1635ret_data8=255 1636system=system 1637update_data=false 1638warn_access= 1639pio=system.iobus.master[18] 1640 1641[system.tsunami.fake_pnp_write] 1642type=IsaFake 1643clk_domain=system.clk_domain |
1644eventq_index=0 |
|
1455fake_mem=false 1456pio_addr=8804615850617 1457pio_latency=100000 1458pio_size=8 1459ret_bad_addr=false 1460ret_data16=65535 1461ret_data32=4294967295 1462ret_data64=18446744073709551615 1463ret_data8=255 1464system=system 1465update_data=false 1466warn_access= 1467pio=system.iobus.master[10] 1468 1469[system.tsunami.fake_ppc] 1470type=IsaFake 1471clk_domain=system.clk_domain | 1645fake_mem=false 1646pio_addr=8804615850617 1647pio_latency=100000 1648pio_size=8 1649ret_bad_addr=false 1650ret_data16=65535 1651ret_data32=4294967295 1652ret_data64=18446744073709551615 1653ret_data8=255 1654system=system 1655update_data=false 1656warn_access= 1657pio=system.iobus.master[10] 1658 1659[system.tsunami.fake_ppc] 1660type=IsaFake 1661clk_domain=system.clk_domain |
1662eventq_index=0 |
|
1472fake_mem=false 1473pio_addr=8804615848891 1474pio_latency=100000 1475pio_size=8 1476ret_bad_addr=false 1477ret_data16=65535 1478ret_data32=4294967295 1479ret_data64=18446744073709551615 1480ret_data8=255 1481system=system 1482update_data=false 1483warn_access= 1484pio=system.iobus.master[7] 1485 1486[system.tsunami.fake_sm_chip] 1487type=IsaFake 1488clk_domain=system.clk_domain | 1663fake_mem=false 1664pio_addr=8804615848891 1665pio_latency=100000 1666pio_size=8 1667ret_bad_addr=false 1668ret_data16=65535 1669ret_data32=4294967295 1670ret_data64=18446744073709551615 1671ret_data8=255 1672system=system 1673update_data=false 1674warn_access= 1675pio=system.iobus.master[7] 1676 1677[system.tsunami.fake_sm_chip] 1678type=IsaFake 1679clk_domain=system.clk_domain |
1680eventq_index=0 |
|
1489fake_mem=false 1490pio_addr=8804615848816 1491pio_latency=100000 1492pio_size=8 1493ret_bad_addr=false 1494ret_data16=65535 1495ret_data32=4294967295 1496ret_data64=18446744073709551615 1497ret_data8=255 1498system=system 1499update_data=false 1500warn_access= 1501pio=system.iobus.master[2] 1502 1503[system.tsunami.fake_uart1] 1504type=IsaFake 1505clk_domain=system.clk_domain | 1681fake_mem=false 1682pio_addr=8804615848816 1683pio_latency=100000 1684pio_size=8 1685ret_bad_addr=false 1686ret_data16=65535 1687ret_data32=4294967295 1688ret_data64=18446744073709551615 1689ret_data8=255 1690system=system 1691update_data=false 1692warn_access= 1693pio=system.iobus.master[2] 1694 1695[system.tsunami.fake_uart1] 1696type=IsaFake 1697clk_domain=system.clk_domain |
1698eventq_index=0 |
|
1506fake_mem=false 1507pio_addr=8804615848696 1508pio_latency=100000 1509pio_size=8 1510ret_bad_addr=false 1511ret_data16=65535 1512ret_data32=4294967295 1513ret_data64=18446744073709551615 1514ret_data8=255 1515system=system 1516update_data=false 1517warn_access= 1518pio=system.iobus.master[3] 1519 1520[system.tsunami.fake_uart2] 1521type=IsaFake 1522clk_domain=system.clk_domain | 1699fake_mem=false 1700pio_addr=8804615848696 1701pio_latency=100000 1702pio_size=8 1703ret_bad_addr=false 1704ret_data16=65535 1705ret_data32=4294967295 1706ret_data64=18446744073709551615 1707ret_data8=255 1708system=system 1709update_data=false 1710warn_access= 1711pio=system.iobus.master[3] 1712 1713[system.tsunami.fake_uart2] 1714type=IsaFake 1715clk_domain=system.clk_domain |
1716eventq_index=0 |
|
1523fake_mem=false 1524pio_addr=8804615848936 1525pio_latency=100000 1526pio_size=8 1527ret_bad_addr=false 1528ret_data16=65535 1529ret_data32=4294967295 1530ret_data64=18446744073709551615 1531ret_data8=255 1532system=system 1533update_data=false 1534warn_access= 1535pio=system.iobus.master[4] 1536 1537[system.tsunami.fake_uart3] 1538type=IsaFake 1539clk_domain=system.clk_domain | 1717fake_mem=false 1718pio_addr=8804615848936 1719pio_latency=100000 1720pio_size=8 1721ret_bad_addr=false 1722ret_data16=65535 1723ret_data32=4294967295 1724ret_data64=18446744073709551615 1725ret_data8=255 1726system=system 1727update_data=false 1728warn_access= 1729pio=system.iobus.master[4] 1730 1731[system.tsunami.fake_uart3] 1732type=IsaFake 1733clk_domain=system.clk_domain |
1734eventq_index=0 |
|
1540fake_mem=false 1541pio_addr=8804615848680 1542pio_latency=100000 1543pio_size=8 1544ret_bad_addr=false 1545ret_data16=65535 1546ret_data32=4294967295 1547ret_data64=18446744073709551615 1548ret_data8=255 1549system=system 1550update_data=false 1551warn_access= 1552pio=system.iobus.master[5] 1553 1554[system.tsunami.fake_uart4] 1555type=IsaFake 1556clk_domain=system.clk_domain | 1735fake_mem=false 1736pio_addr=8804615848680 1737pio_latency=100000 1738pio_size=8 1739ret_bad_addr=false 1740ret_data16=65535 1741ret_data32=4294967295 1742ret_data64=18446744073709551615 1743ret_data8=255 1744system=system 1745update_data=false 1746warn_access= 1747pio=system.iobus.master[5] 1748 1749[system.tsunami.fake_uart4] 1750type=IsaFake 1751clk_domain=system.clk_domain |
1752eventq_index=0 |
|
1557fake_mem=false 1558pio_addr=8804615848944 1559pio_latency=100000 1560pio_size=8 1561ret_bad_addr=false 1562ret_data16=65535 1563ret_data32=4294967295 1564ret_data64=18446744073709551615 1565ret_data8=255 1566system=system 1567update_data=false 1568warn_access= 1569pio=system.iobus.master[6] 1570 1571[system.tsunami.fb] 1572type=BadDevice 1573clk_domain=system.clk_domain 1574devicename=FrameBuffer | 1753fake_mem=false 1754pio_addr=8804615848944 1755pio_latency=100000 1756pio_size=8 1757ret_bad_addr=false 1758ret_data16=65535 1759ret_data32=4294967295 1760ret_data64=18446744073709551615 1761ret_data8=255 1762system=system 1763update_data=false 1764warn_access= 1765pio=system.iobus.master[6] 1766 1767[system.tsunami.fb] 1768type=BadDevice 1769clk_domain=system.clk_domain 1770devicename=FrameBuffer |
1771eventq_index=0 |
|
1575pio_addr=8804615848912 1576pio_latency=100000 1577system=system 1578pio=system.iobus.master[21] 1579 1580[system.tsunami.ide] 1581type=IdeController 1582BAR0=1 --- 11 unchanged lines hidden (view full) --- 1594BAR4=1 1595BAR4LegacyIO=false 1596BAR4Size=16 1597BAR5=1 1598BAR5LegacyIO=false 1599BAR5Size=0 1600BIST=0 1601CacheLineSize=0 | 1772pio_addr=8804615848912 1773pio_latency=100000 1774system=system 1775pio=system.iobus.master[21] 1776 1777[system.tsunami.ide] 1778type=IdeController 1779BAR0=1 --- 11 unchanged lines hidden (view full) --- 1791BAR4=1 1792BAR4LegacyIO=false 1793BAR4Size=16 1794BAR5=1 1795BAR5LegacyIO=false 1796BAR5Size=0 1797BIST=0 1798CacheLineSize=0 |
1799CapabilityPtr=0 |
|
1602CardbusCIS=0 1603ClassCode=1 1604Command=0 1605DeviceID=28945 1606ExpansionROM=0 1607HeaderType=0 1608InterruptLine=31 1609InterruptPin=1 1610LatencyTimer=0 | 1800CardbusCIS=0 1801ClassCode=1 1802Command=0 1803DeviceID=28945 1804ExpansionROM=0 1805HeaderType=0 1806InterruptLine=31 1807InterruptPin=1 1808LatencyTimer=0 |
1809MSICAPBaseOffset=0 1810MSICAPCapId=0 1811MSICAPMaskBits=0 1812MSICAPMsgAddr=0 1813MSICAPMsgCtrl=0 1814MSICAPMsgData=0 1815MSICAPMsgUpperAddr=0 1816MSICAPNextCapability=0 1817MSICAPPendingBits=0 1818MSIXCAPBaseOffset=0 1819MSIXCAPCapId=0 1820MSIXCAPNextCapability=0 1821MSIXMsgCtrl=0 1822MSIXPbaOffset=0 1823MSIXTableOffset=0 |
|
1611MaximumLatency=0 1612MinimumGrant=0 | 1824MaximumLatency=0 1825MinimumGrant=0 |
1826PMCAPBaseOffset=0 1827PMCAPCapId=0 1828PMCAPCapabilities=0 1829PMCAPCtrlStatus=0 1830PMCAPNextCapability=0 1831PXCAPBaseOffset=0 1832PXCAPCapId=0 1833PXCAPCapabilities=0 1834PXCAPDevCap2=0 1835PXCAPDevCapabilities=0 1836PXCAPDevCtrl=0 1837PXCAPDevCtrl2=0 1838PXCAPDevStatus=0 1839PXCAPLinkCap=0 1840PXCAPLinkCtrl=0 1841PXCAPLinkStatus=0 1842PXCAPNextCapability=0 |
|
1613ProgIF=133 1614Revision=0 1615Status=640 1616SubClassCode=1 1617SubsystemID=0 1618SubsystemVendorID=0 1619VendorID=32902 1620clk_domain=system.clk_domain 1621config_latency=20000 1622ctrl_offset=0 1623disks=system.disk0 system.disk2 | 1843ProgIF=133 1844Revision=0 1845Status=640 1846SubClassCode=1 1847SubsystemID=0 1848SubsystemVendorID=0 1849VendorID=32902 1850clk_domain=system.clk_domain 1851config_latency=20000 1852ctrl_offset=0 1853disks=system.disk0 system.disk2 |
1854eventq_index=0 |
|
1624io_shift=0 1625pci_bus=0 1626pci_dev=0 1627pci_func=0 1628pio_latency=30000 1629platform=system.tsunami 1630system=system 1631config=system.iobus.master[26] 1632dma=system.iobus.slave[1] 1633pio=system.iobus.master[25] 1634 1635[system.tsunami.io] 1636type=TsunamiIO 1637clk_domain=system.clk_domain | 1855io_shift=0 1856pci_bus=0 1857pci_dev=0 1858pci_func=0 1859pio_latency=30000 1860platform=system.tsunami 1861system=system 1862config=system.iobus.master[26] 1863dma=system.iobus.slave[1] 1864pio=system.iobus.master[25] 1865 1866[system.tsunami.io] 1867type=TsunamiIO 1868clk_domain=system.clk_domain |
1869eventq_index=0 |
|
1638frequency=976562500 1639pio_addr=8804615847936 1640pio_latency=100000 1641system=system 1642time=Thu Jan 1 00:00:00 2009 1643tsunami=system.tsunami 1644year_is_bcd=false 1645pio=system.iobus.master[22] 1646 1647[system.tsunami.pchip] 1648type=TsunamiPChip 1649clk_domain=system.clk_domain | 1870frequency=976562500 1871pio_addr=8804615847936 1872pio_latency=100000 1873system=system 1874time=Thu Jan 1 00:00:00 2009 1875tsunami=system.tsunami 1876year_is_bcd=false 1877pio=system.iobus.master[22] 1878 1879[system.tsunami.pchip] 1880type=TsunamiPChip 1881clk_domain=system.clk_domain |
1882eventq_index=0 |
|
1650pio_addr=8802535473152 1651pio_latency=100000 1652system=system 1653tsunami=system.tsunami 1654pio=system.iobus.master[1] 1655 1656[system.tsunami.pciconfig] 1657type=PciConfigAll 1658bus=0 1659clk_domain=system.clk_domain | 1883pio_addr=8802535473152 1884pio_latency=100000 1885system=system 1886tsunami=system.tsunami 1887pio=system.iobus.master[1] 1888 1889[system.tsunami.pciconfig] 1890type=PciConfigAll 1891bus=0 1892clk_domain=system.clk_domain |
1893eventq_index=0 |
|
1660pio_addr=0 1661pio_latency=30000 1662platform=system.tsunami 1663size=16777216 1664system=system 1665pio=system.iobus.default 1666 1667[system.tsunami.uart] 1668type=Uart8250 1669clk_domain=system.clk_domain | 1894pio_addr=0 1895pio_latency=30000 1896platform=system.tsunami 1897size=16777216 1898system=system 1899pio=system.iobus.default 1900 1901[system.tsunami.uart] 1902type=Uart8250 1903clk_domain=system.clk_domain |
1904eventq_index=0 |
|
1670pio_addr=8804615848952 1671pio_latency=100000 1672platform=system.tsunami 1673system=system 1674terminal=system.terminal 1675pio=system.iobus.master[23] 1676 1677[system.voltage_domain] 1678type=VoltageDomain | 1905pio_addr=8804615848952 1906pio_latency=100000 1907platform=system.tsunami 1908system=system 1909terminal=system.terminal 1910pio=system.iobus.master[23] 1911 1912[system.voltage_domain] 1913type=VoltageDomain |
1914eventq_index=0 |
|
1679voltage=1.000000 1680 | 1915voltage=1.000000 1916 |