| stats.txt (11754:c209cb86278a) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.893228 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.893228 # Number of seconds simulated |
| 4sim_ticks 1893227633000 # Number of ticks simulated 5final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1893227678500 # Number of ticks simulated 5final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 25790 # Simulator instruction rate (inst/s) 8host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 869674472 # Simulator tick rate (ticks/s) 10host_mem_usage 393476 # Number of bytes of host memory used 11host_seconds 2176.94 # Real time elapsed on the host 12sim_insts 56143729 # Number of instructions simulated 13sim_ops 56143729 # Number of ops (including micro ops) simulated | 7host_inst_rate 31053 # Simulator instruction rate (inst/s) 8host_op_rate 31053 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1047239405 # Simulator tick rate (ticks/s) 10host_mem_usage 384600 # Number of bytes of host memory used 11host_seconds 1807.83 # Real time elapsed on the host 12sim_insts 56138739 # Number of instructions simulated 13sim_ops 56138739 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) | 34system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) |
| 43system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 404826 # Number of read requests accepted 45system.physmem.writeReqs 118235 # Number of write requests accepted 46system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue | 43system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 404808 # Number of read requests accepted 45system.physmem.writeReqs 118227 # Number of write requests accepted 46system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 25487 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25708 # Per bank write bursts | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 25487 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25708 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::2 25813 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25780 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25224 # Per bank write bursts | 58system.physmem.perBankRdBursts::2 25811 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25775 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25223 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24789 # Per bank write bursts | 61system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24789 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::7 24580 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25111 # Per bank write bursts | 63system.physmem.perBankRdBursts::7 24582 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25110 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::9 25258 # Per bank write bursts | 65system.physmem.perBankRdBursts::9 25258 # Per bank write bursts |
| 66system.physmem.perBankRdBursts::10 25520 # Per bank write bursts | 66system.physmem.perBankRdBursts::10 25516 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::11 24876 # Per bank write bursts | 67system.physmem.perBankRdBursts::11 24876 # Per bank write bursts |
| 68system.physmem.perBankRdBursts::12 24529 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25563 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25801 # Per bank write bursts | 68system.physmem.perBankRdBursts::12 24528 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25560 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25799 # Per bank write bursts |
| 71system.physmem.perBankRdBursts::15 25723 # Per bank write bursts | 71system.physmem.perBankRdBursts::15 25723 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::0 7828 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7672 # Per bank write bursts 74system.physmem.perBankWrBursts::2 8070 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7747 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7316 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6943 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6787 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6421 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7240 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6874 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7389 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6891 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7084 # Per bank write bursts 85system.physmem.perBankWrBursts::13 8012 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7998 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7945 # Per bank write bursts | 72system.physmem.perBankWrBursts::0 7831 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7673 # Per bank write bursts 74system.physmem.perBankWrBursts::2 8069 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7745 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7318 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6942 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6789 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6426 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7239 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6872 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7384 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6889 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7081 # Per bank write bursts 85system.physmem.perBankWrBursts::13 8010 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7995 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7932 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 89system.physmem.numWrRetry 56 # Number of times write queue was full causing retry 90system.physmem.totGap 1893218679000 # Total gap between requests | 89system.physmem.numWrRetry 72 # Number of times write queue was full causing retry 90system.physmem.totGap 1893218795000 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 404826 # Read request sizes (log2) | 97system.physmem.readPktSize::6 404808 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 118235 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 118227 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see |
| 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes | 152system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2380 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5474 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5628 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6323 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7088 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8116 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6716 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7120 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7724 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7371 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6619 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6877 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 6128 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5827 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5756 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads | 222system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads |
| 251system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads | 250system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads |
| 252system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads 255system.physmem.totQLat 5894702000 # Total ticks spent queuing 256system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM 257system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers 258system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst | 251system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads 256system.physmem.totQLat 5912751750 # Total ticks spent queuing 257system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM 258system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers 259system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst |
| 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 260system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst | 261system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst |
| 261system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s | 262system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s 263system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s |
| 263system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s | 264system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s |
| 264system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.14 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 265system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s 266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 267system.physmem.busUtil 0.14 # Data bus utilization in percentage 268system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 269system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 270system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 270system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing 271system.physmem.readRowHits 363769 # Number of row buffer hits during reads 272system.physmem.writeRowHits 95780 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes 275system.physmem.avgGap 3619498.83 # Average gap between requests 276system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) 282system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) 284system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) 285system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) 286system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) 287system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) 288system.physmem_0.averagePower 249.096553 # Core power per rank (mW) 289system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank 290system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states 291system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states 292system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states 296system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) 298system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) 301system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) 303system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) 304system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) 305system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) 306system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) 307system.physmem_1.averagePower 249.231588 # Core power per rank (mW) 308system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank 309system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states 310system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states 311system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states 315system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 316system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 317system.cpu.branchPred.lookups 15259378 # Number of BP lookups 318system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted 319system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect 320system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups 321system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits | 271system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing 272system.physmem.readRowHits 363798 # Number of row buffer hits during reads 273system.physmem.writeRowHits 95706 # Number of row buffer hits during writes 274system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads 275system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes 276system.physmem.avgGap 3619678.98 # Average gap between requests 277system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined 278system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ) 279system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ) 280system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ) 281system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) 282system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ) 283system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ) 284system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ) 285system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ) 286system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ) 287system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ) 288system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ) 289system.physmem_0.averagePower 249.079684 # Core power per rank (mW) 290system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank 291system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states 292system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states 293system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states 297system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ) 304system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ) 305system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ) 306system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ) 307system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ) 308system.physmem_1.averagePower 249.268712 # Core power per rank (mW) 309system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank 310system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states 311system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states 312system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states 313system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states 314system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states 315system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states 316system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 317system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 318system.cpu.branchPred.lookups 15251875 # Number of BP lookups 319system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted 320system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect 321system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups 322system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits |
| 322system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 323system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 323system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage 324system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. 325system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. 326system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. 327system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. 328system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. 329system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. | 324system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage 325system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target. 326system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions. 327system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups. 328system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits. 329system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses. 330system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches. |
| 330system.cpu_clk_domain.clock 500 # Clock period in ticks 331system.cpu.dtb.fetch_hits 0 # ITB hits 332system.cpu.dtb.fetch_misses 0 # ITB misses 333system.cpu.dtb.fetch_acv 0 # ITB acv 334system.cpu.dtb.fetch_accesses 0 # ITB accesses | 331system.cpu_clk_domain.clock 500 # Clock period in ticks 332system.cpu.dtb.fetch_hits 0 # ITB hits 333system.cpu.dtb.fetch_misses 0 # ITB misses 334system.cpu.dtb.fetch_acv 0 # ITB acv 335system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 335system.cpu.dtb.read_hits 9322510 # DTB read hits 336system.cpu.dtb.read_misses 17386 # DTB read misses | 336system.cpu.dtb.read_hits 9319487 # DTB read hits 337system.cpu.dtb.read_misses 17755 # DTB read misses |
| 337system.cpu.dtb.read_acv 211 # DTB read access violations | 338system.cpu.dtb.read_acv 211 # DTB read access violations |
| 338system.cpu.dtb.read_accesses 764595 # DTB read accesses 339system.cpu.dtb.write_hits 6393584 # DTB write hits 340system.cpu.dtb.write_misses 2379 # DTB write misses | 339system.cpu.dtb.read_accesses 764786 # DTB read accesses 340system.cpu.dtb.write_hits 6392965 # DTB write hits 341system.cpu.dtb.write_misses 2560 # DTB write misses |
| 341system.cpu.dtb.write_acv 158 # DTB write access violations | 342system.cpu.dtb.write_acv 158 # DTB write access violations |
| 342system.cpu.dtb.write_accesses 298734 # DTB write accesses 343system.cpu.dtb.data_hits 15716094 # DTB hits 344system.cpu.dtb.data_misses 19765 # DTB misses | 343system.cpu.dtb.write_accesses 298884 # DTB write accesses 344system.cpu.dtb.data_hits 15712452 # DTB hits 345system.cpu.dtb.data_misses 20315 # DTB misses |
| 345system.cpu.dtb.data_acv 369 # DTB access violations | 346system.cpu.dtb.data_acv 369 # DTB access violations |
| 346system.cpu.dtb.data_accesses 1063329 # DTB accesses 347system.cpu.itb.fetch_hits 4018414 # ITB hits 348system.cpu.itb.fetch_misses 6313 # ITB misses 349system.cpu.itb.fetch_acv 710 # ITB acv 350system.cpu.itb.fetch_accesses 4024727 # ITB accesses | 347system.cpu.dtb.data_accesses 1063670 # DTB accesses 348system.cpu.itb.fetch_hits 4023125 # ITB hits 349system.cpu.itb.fetch_misses 6293 # ITB misses 350system.cpu.itb.fetch_acv 687 # ITB acv 351system.cpu.itb.fetch_accesses 4029418 # ITB accesses |
| 351system.cpu.itb.read_hits 0 # DTB read hits 352system.cpu.itb.read_misses 0 # DTB read misses 353system.cpu.itb.read_acv 0 # DTB read access violations 354system.cpu.itb.read_accesses 0 # DTB read accesses 355system.cpu.itb.write_hits 0 # DTB write hits 356system.cpu.itb.write_misses 0 # DTB write misses 357system.cpu.itb.write_acv 0 # DTB write access violations 358system.cpu.itb.write_accesses 0 # DTB write accesses 359system.cpu.itb.data_hits 0 # DTB hits 360system.cpu.itb.data_misses 0 # DTB misses 361system.cpu.itb.data_acv 0 # DTB access violations 362system.cpu.itb.data_accesses 0 # DTB accesses | 352system.cpu.itb.read_hits 0 # DTB read hits 353system.cpu.itb.read_misses 0 # DTB read misses 354system.cpu.itb.read_acv 0 # DTB read access violations 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_hits 0 # DTB write hits 357system.cpu.itb.write_misses 0 # DTB write misses 358system.cpu.itb.write_acv 0 # DTB write access violations 359system.cpu.itb.write_accesses 0 # DTB write accesses 360system.cpu.itb.data_hits 0 # DTB hits 361system.cpu.itb.data_misses 0 # DTB misses 362system.cpu.itb.data_acv 0 # DTB access violations 363system.cpu.itb.data_accesses 0 # DTB accesses |
| 363system.cpu.numPwrStateTransitions 12750 # Number of power state transitions 364system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state 365system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state 366system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state 367system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state 368system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state | 364system.cpu.numPwrStateTransitions 12752 # Number of power state transitions 365system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state 366system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state 367system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state 368system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state 369system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state |
| 369system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state | 370system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| 370system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state 371system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states 372system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states 373system.cpu.numCycles 193068084 # number of cpu cycles simulated | 371system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state 372system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states 373system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states 374system.cpu.numCycles 193159059 # number of cpu cycles simulated |
| 374system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 375system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 376system.cpu.committedInsts 56143729 # Number of instructions committed 377system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed 378system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit 379system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching 380system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 381system.cpu.cpi 3.438818 # CPI: cycles per instruction 382system.cpu.ipc 0.290798 # IPC: instructions per cycle 383system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction 384system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction 385system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction | 377system.cpu.committedInsts 56138739 # Number of instructions committed 378system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed 379system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit 380system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching 381system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 382system.cpu.cpi 3.440745 # CPI: cycles per instruction 383system.cpu.ipc 0.290635 # IPC: instructions per cycle 384system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction 385system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction 386system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction |
| 386system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 387system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction 388system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 389system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 390system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 391system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction | 387system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 388system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction 389system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 390system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 391system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction 392system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction |
| 392system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 393system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction 394system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 395system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 396system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 397system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 398system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 399system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 400system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 401system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 402system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 403system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 404system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 405system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 406system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 407system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 408system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 409system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 410system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 411system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 412system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 413system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 414system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 415system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction 416system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction | 393system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 394system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction 395system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 396system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 397system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 398system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 399system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 400system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 401system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 402system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 403system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 404system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 405system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 406system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 407system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 408system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 409system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 410system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 411system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 412system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 413system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 414system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 415system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 416system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction 417system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction |
| 417system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction 418system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction | 418system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction 419system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction |
| 419system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction | 420system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction |
| 420system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 421system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 421system.cpu.op_class_0::total 56143729 # Class of committed instruction | 422system.cpu.op_class_0::total 56138739 # Class of committed instruction |
| 422system.cpu.kern.inst.arm 0 # number of arm instructions executed | 423system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 423system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 424system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed 425system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl 426system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl | 424system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 425system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed 426system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl 427system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl |
| 427system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl | 428system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl |
| 428system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl 429system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl 430system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 429system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl 430system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl 431system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 431system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 432system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl | 432system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 433system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl |
| 433system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl 434system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl 435system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl 436system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl 437system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl 438system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl 439system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl 440system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl | 434system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl 435system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl 436system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl 437system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl 438system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl 439system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl 440system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl 441system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl |
| 441system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 442system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 442system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 443system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 443system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl 444system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl | 444system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl 445system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl |
| 445system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 446system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 447system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 448system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 449system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed 450system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 451system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 446system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 447system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 448system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 449system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 450system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed 451system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 452system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 452system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed | 453system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed |
| 453system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed 454system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 455system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 456system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 457system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 458system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed 459system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 460system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 454system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed 455system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 456system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 457system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 458system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 459system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed 460system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 461system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 461system.cpu.kern.callpal::total 192387 # number of callpals executed | 462system.cpu.kern.callpal::total 192456 # number of callpals executed |
| 462system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches | 463system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches |
| 463system.cpu.kern.mode_switch::user 1739 # number of protection mode switches | 464system.cpu.kern.mode_switch::user 1736 # number of protection mode switches |
| 464system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches | 465system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches |
| 465system.cpu.kern.mode_good::kernel 1907 466system.cpu.kern.mode_good::user 1739 | 466system.cpu.kern.mode_good::kernel 1904 467system.cpu.kern.mode_good::user 1736 |
| 467system.cpu.kern.mode_good::idle 168 | 468system.cpu.kern.mode_good::idle 168 |
| 468system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches | 469system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches |
| 469system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 470system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches | 470system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 471system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches |
| 471system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches 472system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode 473system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode 474system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode | 472system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches 473system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode 474system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode 475system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode |
| 475system.cpu.kern.swap_context 4174 # number of times the context was actually changed | 476system.cpu.kern.swap_context 4174 # number of times the context was actually changed |
| 476system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked 477system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped 478system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 479system.cpu.dcache.tags.replacements 1394486 # number of replacements 480system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use 481system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. 482system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. 483system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. | 477system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked 478system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped 479system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 480system.cpu.dcache.tags.replacements 1394352 # number of replacements 481system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use 482system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks. 483system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks. 484system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks. |
| 484system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. | 485system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. |
| 485system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor | 486system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor |
| 486system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy 487system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy 488system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 492system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 487system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy 488system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy 489system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 493system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses 494system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses 495system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 496system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits 497system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits 498system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits 499system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits 500system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits 501system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits 502system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits 503system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits 504system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits 505system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits 506system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits 507system.cpu.dcache.overall_hits::total 13563915 # number of overall hits 508system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses 509system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses 510system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses 511system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses 512system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses 513system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses 514system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses 515system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses 516system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses 517system.cpu.dcache.overall_misses::total 1670224 # number of overall misses 518system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles 519system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles 521system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles 522system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles 523system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles 524system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles 525system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles 526system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles 527system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles 528system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) 536system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses 537system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses 538system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses 539system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses 540system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses 541system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses 542system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses 543system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses 544system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses 545system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses 546system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses 547system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses 548system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses 549system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency 551system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency 553system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency 554system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency 555system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency 556system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency 557system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency 559system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency | 494system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses 495system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses 496system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 497system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits 498system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits 499system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits 500system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits 501system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits 502system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits 503system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits 504system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits 505system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits 506system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits 507system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits 508system.cpu.dcache.overall_hits::total 13560926 # number of overall hits 509system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses 510system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses 511system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses 512system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses 513system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses 514system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses 515system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses 516system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses 517system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses 518system.cpu.dcache.overall_misses::total 1670322 # number of overall misses 519system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles 520system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles 521system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles 522system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles 523system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles 524system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles 525system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles 526system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles 527system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles 528system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles 529system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses) 530system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses) 531system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses) 532system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses) 533system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses) 534system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses) 535system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses) 536system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses) 537system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses 538system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses 539system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses 540system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses 541system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses 545system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses 546system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses 547system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses 548system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses 549system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses 550system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses 551system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency 552system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency 553system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency 554system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency 555system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency 556system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency 557system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency 558system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency 559system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency 560system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency |
| 560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 561system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 563system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 564system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 565system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 566system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 566system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks 567system.cpu.dcache.writebacks::total 837775 # number of writebacks 568system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits 569system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits 570system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits 571system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits | 567system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks 568system.cpu.dcache.writebacks::total 837673 # number of writebacks 569system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 570system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 571system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits 572system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits |
| 572system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 573system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 573system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 574system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 574system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits 575system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits 576system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits 577system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits 578system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses 579system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses 580system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses 582system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses 585system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses 586system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses 587system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses | 575system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits 576system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits 577system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits 578system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits 579system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses 580system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses 585system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses 586system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses 587system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses 588system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses |
| 588system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 589system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 590system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 591system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 592system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 593system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses | 589system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 590system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 591system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 592system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 593system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 594system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses |
| 594system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles 596system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles 597system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles 598system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles 599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles 603system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles 604system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles 605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles 606system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles 607system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles 608system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses 609system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses 610system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses 611system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses 612system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses 613system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses 614system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses 615system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses 616system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses 617system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses 618system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency 619system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency 620system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency 621system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency 622system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency 623system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency 624system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency 625system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency 626system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency 627system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency 628system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency 629system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency 630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency 631system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency 632system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 633system.cpu.icache.tags.replacements 1476860 # number of replacements 634system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use 635system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. 636system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. 637system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. 638system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. 639system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor | 595system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles 596system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles 597system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles 598system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles 599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles 600system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles 601system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles 602system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles 603system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles 604system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles 605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles 606system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles 607system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles 608system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles 609system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses 610system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses 611system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses 612system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses 613system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses 614system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses 615system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses 616system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses 617system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses 618system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses 619system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency 620system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency 621system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency 622system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency 623system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency 624system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency 625system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency 626system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency 627system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency 628system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency 629system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency 630system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency 631system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency 632system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency 633system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 634system.cpu.icache.tags.replacements 1477259 # number of replacements 635system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use 636system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks. 637system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks. 638system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks. 639system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit. 640system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor |
| 640system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy 641system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy 642system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 641system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy 642system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy 643system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 643system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 644system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 645system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id | 644system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 645system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 646system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id |
| 646system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 647system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 647system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses 648system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses 649system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 650system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits 651system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits 652system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits 653system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits 654system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits 655system.cpu.icache.overall_hits::total 19221455 # number of overall hits 656system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses 657system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses 658system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses 659system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses 660system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses 661system.cpu.icache.overall_misses::total 1477546 # number of overall misses 662system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles 663system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles 664system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles 665system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles 666system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles 667system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles 668system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses) 669system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses) 670system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses 671system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses 672system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses 673system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses 674system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses 675system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses 676system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses 677system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses 678system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses 679system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses 680system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency 681system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency 682system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency 683system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency 684system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency 685system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency | 648system.cpu.icache.tags.tag_accesses 22196619 # Number of tag accesses 649system.cpu.icache.tags.data_accesses 22196619 # Number of data accesses 650system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 651system.cpu.icache.ReadReq_hits::cpu.inst 19240727 # number of ReadReq hits 652system.cpu.icache.ReadReq_hits::total 19240727 # number of ReadReq hits 653system.cpu.icache.demand_hits::cpu.inst 19240727 # number of demand (read+write) hits 654system.cpu.icache.demand_hits::total 19240727 # number of demand (read+write) hits 655system.cpu.icache.overall_hits::cpu.inst 19240727 # number of overall hits 656system.cpu.icache.overall_hits::total 19240727 # number of overall hits 657system.cpu.icache.ReadReq_misses::cpu.inst 1477946 # number of ReadReq misses 658system.cpu.icache.ReadReq_misses::total 1477946 # number of ReadReq misses 659system.cpu.icache.demand_misses::cpu.inst 1477946 # number of demand (read+write) misses 660system.cpu.icache.demand_misses::total 1477946 # number of demand (read+write) misses 661system.cpu.icache.overall_misses::cpu.inst 1477946 # number of overall misses 662system.cpu.icache.overall_misses::total 1477946 # number of overall misses 663system.cpu.icache.ReadReq_miss_latency::cpu.inst 20694155000 # number of ReadReq miss cycles 664system.cpu.icache.ReadReq_miss_latency::total 20694155000 # number of ReadReq miss cycles 665system.cpu.icache.demand_miss_latency::cpu.inst 20694155000 # number of demand (read+write) miss cycles 666system.cpu.icache.demand_miss_latency::total 20694155000 # number of demand (read+write) miss cycles 667system.cpu.icache.overall_miss_latency::cpu.inst 20694155000 # number of overall miss cycles 668system.cpu.icache.overall_miss_latency::total 20694155000 # number of overall miss cycles 669system.cpu.icache.ReadReq_accesses::cpu.inst 20718673 # number of ReadReq accesses(hits+misses) 670system.cpu.icache.ReadReq_accesses::total 20718673 # number of ReadReq accesses(hits+misses) 671system.cpu.icache.demand_accesses::cpu.inst 20718673 # number of demand (read+write) accesses 672system.cpu.icache.demand_accesses::total 20718673 # number of demand (read+write) accesses 673system.cpu.icache.overall_accesses::cpu.inst 20718673 # number of overall (read+write) accesses 674system.cpu.icache.overall_accesses::total 20718673 # number of overall (read+write) accesses 675system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071334 # miss rate for ReadReq accesses 676system.cpu.icache.ReadReq_miss_rate::total 0.071334 # miss rate for ReadReq accesses 677system.cpu.icache.demand_miss_rate::cpu.inst 0.071334 # miss rate for demand accesses 678system.cpu.icache.demand_miss_rate::total 0.071334 # miss rate for demand accesses 679system.cpu.icache.overall_miss_rate::cpu.inst 0.071334 # miss rate for overall accesses 680system.cpu.icache.overall_miss_rate::total 0.071334 # miss rate for overall accesses 681system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625 # average ReadReq miss latency 682system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625 # average ReadReq miss latency 683system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency 684system.cpu.icache.demand_avg_miss_latency::total 14001.969625 # average overall miss latency 685system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency 686system.cpu.icache.overall_avg_miss_latency::total 14001.969625 # average overall miss latency |
| 686system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 687system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 688system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 689system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 690system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 691system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 687system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 692system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks 693system.cpu.icache.writebacks::total 1476860 # number of writebacks 694system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses 695system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses 696system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses 697system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses 698system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses 699system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses 700system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles 701system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles 702system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles 703system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles 704system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles 705system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles 706system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses 708system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses 709system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses 710system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses 711system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency 713system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency 714system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency 715system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency 716system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency 717system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency 718system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 719system.cpu.l2cache.tags.replacements 339644 # number of replacements 720system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use 721system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks. 722system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks. 723system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks. 724system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit. 725system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor 726system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor 727system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor 728system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy 729system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy 730system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy 731system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy | 693system.cpu.icache.writebacks::writebacks 1477259 # number of writebacks 694system.cpu.icache.writebacks::total 1477259 # number of writebacks 695system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477946 # number of ReadReq MSHR misses 696system.cpu.icache.ReadReq_mshr_misses::total 1477946 # number of ReadReq MSHR misses 697system.cpu.icache.demand_mshr_misses::cpu.inst 1477946 # number of demand (read+write) MSHR misses 698system.cpu.icache.demand_mshr_misses::total 1477946 # number of demand (read+write) MSHR misses 699system.cpu.icache.overall_mshr_misses::cpu.inst 1477946 # number of overall MSHR misses 700system.cpu.icache.overall_mshr_misses::total 1477946 # number of overall MSHR misses 701system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19216209000 # number of ReadReq MSHR miss cycles 702system.cpu.icache.ReadReq_mshr_miss_latency::total 19216209000 # number of ReadReq MSHR miss cycles 703system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19216209000 # number of demand (read+write) MSHR miss cycles 704system.cpu.icache.demand_mshr_miss_latency::total 19216209000 # number of demand (read+write) MSHR miss cycles 705system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19216209000 # number of overall MSHR miss cycles 706system.cpu.icache.overall_mshr_miss_latency::total 19216209000 # number of overall MSHR miss cycles 707system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for ReadReq accesses 708system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071334 # mshr miss rate for ReadReq accesses 709system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for demand accesses 710system.cpu.icache.demand_mshr_miss_rate::total 0.071334 # mshr miss rate for demand accesses 711system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for overall accesses 712system.cpu.icache.overall_mshr_miss_rate::total 0.071334 # mshr miss rate for overall accesses 713system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625 # average ReadReq mshr miss latency 714system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625 # average ReadReq mshr miss latency 715system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency 716system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency 717system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency 718system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency 719system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 720system.cpu.l2cache.tags.replacements 339629 # number of replacements 721system.cpu.l2cache.tags.tagsinuse 65408.640121 # Cycle average of tags in use 722system.cpu.l2cache.tags.total_refs 5336861 # Total number of references to valid blocks. 723system.cpu.l2cache.tags.sampled_refs 405151 # Sample count of references to valid blocks. 724system.cpu.l2cache.tags.avg_refs 13.172523 # Average number of references to valid blocks. 725system.cpu.l2cache.tags.warmup_cycle 6812650000 # Cycle when the warmup percentage was hit. 726system.cpu.l2cache.tags.occ_blocks::writebacks 268.308507 # Average occupied blocks per requestor 727system.cpu.l2cache.tags.occ_blocks::cpu.inst 5784.509565 # Average occupied blocks per requestor 728system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049 # Average occupied blocks per requestor 729system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy 730system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088265 # Average percentage of cache occupancy 731system.cpu.l2cache.tags.occ_percent::cpu.data 0.905698 # Average percentage of cache occupancy 732system.cpu.l2cache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy |
| 732system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 733system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 734system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id | 733system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 734system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 735system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id |
| 735system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id | 736system.cpu.l2cache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id |
| 736system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id | 737system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id |
| 737system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id | 738system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59336 # Occupied blocks per task id |
| 738system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id | 739system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id |
| 739system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses 740system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses 741system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 742system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits 743system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits 744system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits 745system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits 746system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits 747system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits 748system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits 749system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits 750system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits 751system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits 752system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits 753system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits 754system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits 755system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits 756system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits 757system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits 758system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits 759system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits | 740system.cpu.l2cache.tags.tag_accesses 46345268 # Number of tag accesses 741system.cpu.l2cache.tags.data_accesses 46345268 # Number of data accesses 742system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 743system.cpu.l2cache.WritebackDirty_hits::writebacks 837673 # number of WritebackDirty hits 744system.cpu.l2cache.WritebackDirty_hits::total 837673 # number of WritebackDirty hits 745system.cpu.l2cache.WritebackClean_hits::writebacks 1476684 # number of WritebackClean hits 746system.cpu.l2cache.WritebackClean_hits::total 1476684 # number of WritebackClean hits 747system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 748system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 749system.cpu.l2cache.ReadExReq_hits::cpu.data 187384 # number of ReadExReq hits 750system.cpu.l2cache.ReadExReq_hits::total 187384 # number of ReadExReq hits 751system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461541 # number of ReadCleanReq hits 752system.cpu.l2cache.ReadCleanReq_hits::total 1461541 # number of ReadCleanReq hits 753system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818635 # number of ReadSharedReq hits 754system.cpu.l2cache.ReadSharedReq_hits::total 818635 # number of ReadSharedReq hits 755system.cpu.l2cache.demand_hits::cpu.inst 1461541 # number of demand (read+write) hits 756system.cpu.l2cache.demand_hits::cpu.data 1006019 # number of demand (read+write) hits 757system.cpu.l2cache.demand_hits::total 2467560 # number of demand (read+write) hits 758system.cpu.l2cache.overall_hits::cpu.inst 1461541 # number of overall hits 759system.cpu.l2cache.overall_hits::cpu.data 1006019 # number of overall hits 760system.cpu.l2cache.overall_hits::total 2467560 # number of overall hits |
| 760system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 761system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses | 761system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 762system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses |
| 762system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses 763system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses 764system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses 765system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses 766system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses 767system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses 768system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses 769system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses 770system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses 771system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses 772system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses 773system.cpu.l2cache.overall_misses::total 405239 # number of overall misses | 763system.cpu.l2cache.ReadExReq_misses::cpu.data 116650 # number of ReadExReq misses 764system.cpu.l2cache.ReadExReq_misses::total 116650 # number of ReadExReq misses 765system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16351 # number of ReadCleanReq misses 766system.cpu.l2cache.ReadCleanReq_misses::total 16351 # number of ReadCleanReq misses 767system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272221 # number of ReadSharedReq misses 768system.cpu.l2cache.ReadSharedReq_misses::total 272221 # number of ReadSharedReq misses 769system.cpu.l2cache.demand_misses::cpu.inst 16351 # number of demand (read+write) misses 770system.cpu.l2cache.demand_misses::cpu.data 388871 # number of demand (read+write) misses 771system.cpu.l2cache.demand_misses::total 405222 # number of demand (read+write) misses 772system.cpu.l2cache.overall_misses::cpu.inst 16351 # number of overall misses 773system.cpu.l2cache.overall_misses::cpu.data 388871 # number of overall misses 774system.cpu.l2cache.overall_misses::total 405222 # number of overall misses |
| 774system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles 775system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles | 775system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles 776system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles |
| 776system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles 777system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles 778system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles 779system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles 780system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles 781system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles 782system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles 783system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles 784system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles 785system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles 786system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles 787system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles 788system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses) 789system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses) 790system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses) 791system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses) 792system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) 793system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) 794system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses) 795system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses) 796system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses) 797system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses) 798system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses) 799system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses) 800system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses 801system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses 802system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses 803system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses 804system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses 805system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses 806system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses 807system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses 808system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses 809system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses 811system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses 812system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses 813system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses 814system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses 815system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses 816system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses 817system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses 818system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses 819system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses | 777system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10508664000 # number of ReadExReq miss cycles 778system.cpu.l2cache.ReadExReq_miss_latency::total 10508664000 # number of ReadExReq miss cycles 779system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1613902000 # number of ReadCleanReq miss cycles 780system.cpu.l2cache.ReadCleanReq_miss_latency::total 1613902000 # number of ReadCleanReq miss cycles 781system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21967740000 # number of ReadSharedReq miss cycles 782system.cpu.l2cache.ReadSharedReq_miss_latency::total 21967740000 # number of ReadSharedReq miss cycles 783system.cpu.l2cache.demand_miss_latency::cpu.inst 1613902000 # number of demand (read+write) miss cycles 784system.cpu.l2cache.demand_miss_latency::cpu.data 32476404000 # number of demand (read+write) miss cycles 785system.cpu.l2cache.demand_miss_latency::total 34090306000 # number of demand (read+write) miss cycles 786system.cpu.l2cache.overall_miss_latency::cpu.inst 1613902000 # number of overall miss cycles 787system.cpu.l2cache.overall_miss_latency::cpu.data 32476404000 # number of overall miss cycles 788system.cpu.l2cache.overall_miss_latency::total 34090306000 # number of overall miss cycles 789system.cpu.l2cache.WritebackDirty_accesses::writebacks 837673 # number of WritebackDirty accesses(hits+misses) 790system.cpu.l2cache.WritebackDirty_accesses::total 837673 # number of WritebackDirty accesses(hits+misses) 791system.cpu.l2cache.WritebackClean_accesses::writebacks 1476684 # number of WritebackClean accesses(hits+misses) 792system.cpu.l2cache.WritebackClean_accesses::total 1476684 # number of WritebackClean accesses(hits+misses) 793system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) 794system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 795system.cpu.l2cache.ReadExReq_accesses::cpu.data 304034 # number of ReadExReq accesses(hits+misses) 796system.cpu.l2cache.ReadExReq_accesses::total 304034 # number of ReadExReq accesses(hits+misses) 797system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477892 # number of ReadCleanReq accesses(hits+misses) 798system.cpu.l2cache.ReadCleanReq_accesses::total 1477892 # number of ReadCleanReq accesses(hits+misses) 799system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090856 # number of ReadSharedReq accesses(hits+misses) 800system.cpu.l2cache.ReadSharedReq_accesses::total 1090856 # number of ReadSharedReq accesses(hits+misses) 801system.cpu.l2cache.demand_accesses::cpu.inst 1477892 # number of demand (read+write) accesses 802system.cpu.l2cache.demand_accesses::cpu.data 1394890 # number of demand (read+write) accesses 803system.cpu.l2cache.demand_accesses::total 2872782 # number of demand (read+write) accesses 804system.cpu.l2cache.overall_accesses::cpu.inst 1477892 # number of overall (read+write) accesses 805system.cpu.l2cache.overall_accesses::cpu.data 1394890 # number of overall (read+write) accesses 806system.cpu.l2cache.overall_accesses::total 2872782 # number of overall (read+write) accesses 807system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for UpgradeReq accesses 808system.cpu.l2cache.UpgradeReq_miss_rate::total 0.272727 # miss rate for UpgradeReq accesses 809system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383674 # miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadExReq_miss_rate::total 0.383674 # miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011064 # miss rate for ReadCleanReq accesses 812system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011064 # miss rate for ReadCleanReq accesses 813system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249548 # miss rate for ReadSharedReq accesses 814system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249548 # miss rate for ReadSharedReq accesses 815system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011064 # miss rate for demand accesses 816system.cpu.l2cache.demand_miss_rate::cpu.data 0.278783 # miss rate for demand accesses 817system.cpu.l2cache.demand_miss_rate::total 0.141056 # miss rate for demand accesses 818system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011064 # miss rate for overall accesses 819system.cpu.l2cache.overall_miss_rate::cpu.data 0.278783 # miss rate for overall accesses 820system.cpu.l2cache.overall_miss_rate::total 0.141056 # miss rate for overall accesses |
| 820system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency 821system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency | 821system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency 822system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency |
| 822system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency 823system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency 824system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency 825system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency 826system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency 827system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency 828system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency | 823system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447 # average ReadExReq miss latency 824system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447 # average ReadExReq miss latency 825system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531 # average ReadCleanReq miss latency 826system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531 # average ReadCleanReq miss latency 827system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727 # average ReadSharedReq miss latency 828system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727 # average ReadSharedReq miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739 # average overall miss latency |
| 834system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 835system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 840system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks 841system.cpu.l2cache.writebacks::total 76723 # number of writebacks | 841system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks 842system.cpu.l2cache.writebacks::total 76715 # number of writebacks |
| 842system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 843system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses | 843system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 844system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses |
| 844system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses 845system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses 847system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses 848system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses 849system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses 850system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses 854system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses 855system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses | 845system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses 847system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16351 # number of ReadCleanReq MSHR misses 848system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16351 # number of ReadCleanReq MSHR misses 849system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272221 # number of ReadSharedReq MSHR misses 850system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272221 # number of ReadSharedReq MSHR misses 851system.cpu.l2cache.demand_mshr_misses::cpu.inst 16351 # number of demand (read+write) MSHR misses 852system.cpu.l2cache.demand_mshr_misses::cpu.data 388871 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.demand_mshr_misses::total 405222 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.overall_mshr_misses::cpu.inst 16351 # number of overall MSHR misses 855system.cpu.l2cache.overall_mshr_misses::cpu.data 388871 # number of overall MSHR misses 856system.cpu.l2cache.overall_mshr_misses::total 405222 # number of overall MSHR misses |
| 856system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 857system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 858system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 859system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 860system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 861system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses 862system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles 863system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles | 857system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 858system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 859system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable 860system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable 861system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses 862system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses 863system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles 864system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles |
| 864system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles 865system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles 866system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles 867system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles 868system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles 869system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles 870system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles 871system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles 874system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles 875system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles 876system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles 877system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles 878system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles 879system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles 880system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses 881system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses 882system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses 883system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses 885system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses 886system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses 887system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses 888system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses 889system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses 890system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses 891system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses 892system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses 893system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses | 865system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9342164000 # number of ReadExReq MSHR miss cycles 866system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9342164000 # number of ReadExReq MSHR miss cycles 867system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1450392000 # number of ReadCleanReq MSHR miss cycles 868system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1450392000 # number of ReadCleanReq MSHR miss cycles 869system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19248668000 # number of ReadSharedReq MSHR miss cycles 870system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19248668000 # number of ReadSharedReq MSHR miss cycles 871system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1450392000 # number of demand (read+write) MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28590832000 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.demand_mshr_miss_latency::total 30041224000 # number of demand (read+write) MSHR miss cycles 874system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1450392000 # number of overall MSHR miss cycles 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28590832000 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::total 30041224000 # number of overall MSHR miss cycles 877system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles 878system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles 879system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles 880system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles 881system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for UpgradeReq accesses 882system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for UpgradeReq accesses 883system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383674 # mshr miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383674 # mshr miss rate for ReadExReq accesses 885system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for ReadCleanReq accesses 886system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011064 # mshr miss rate for ReadCleanReq accesses 887system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249548 # mshr miss rate for ReadSharedReq accesses 888system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249548 # mshr miss rate for ReadSharedReq accesses 889system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for demand accesses 890system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for demand accesses 891system.cpu.l2cache.demand_mshr_miss_rate::total 0.141056 # mshr miss rate for demand accesses 892system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for overall accesses 893system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for overall accesses 894system.cpu.l2cache.overall_mshr_miss_rate::total 0.141056 # mshr miss rate for overall accesses |
| 894system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency 895system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency | 895system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency 896system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency |
| 896system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency 897system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency 898system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency 899system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency 900system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency 901system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency 904system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency 907system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency 908system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency 909system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency 910system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency 911system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency 912system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. 913system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. 914system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 915system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. 916system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 897system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency 898system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency 899system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency 900system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency 901system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency 902system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency 903system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency 904system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency 905system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency 906system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency 907system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency 908system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency 909system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency 910system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency 911system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency 912system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency 913system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter. 914system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 917system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 918system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 918system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 919system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 919system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 920system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 920system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution | 921system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution |
| 921system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution | 922system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution |
| 923system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution 935system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.snoops 340255 # Total snoops (count) 942system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) 943system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram 945system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram | 924system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution 936system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.snoops 340239 # Total snoops (count) 943system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes) 944system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram 945system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram |
| 946system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 947system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 947system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram | 948system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram |
| 949system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 950system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 953system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram 954system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) | 954system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram 955system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks) |
| 955system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) | 956system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 956system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) | 957system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) |
| 957system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 958system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 958system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) | 959system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks) |
| 959system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 960system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 960system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) | 961system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks) |
| 961system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 962system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 963system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 964system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 965system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 966system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 967system.disk0.dma_write_txs 395 # Number of DMA write transactions. 968system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 969system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 970system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 971system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 972system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 973system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 962system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 963system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 964system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 965system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 966system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 967system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 968system.disk0.dma_write_txs 395 # Number of DMA write transactions. 969system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 970system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 971system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 972system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 973system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 974system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 974system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 975system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 975system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 976system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 977system.iobus.trans_dist::WriteReq 51175 # Transaction distribution 978system.iobus.trans_dist::WriteResp 51175 # Transaction distribution 979system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) 980system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 981system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 997system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 998system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 999system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1001system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) 1002system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1003system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1004system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) | 976system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 977system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 978system.iobus.trans_dist::WriteReq 51175 # Transaction distribution 979system.iobus.trans_dist::WriteResp 51175 # Transaction distribution 980system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) 981system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 983system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 998system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 999system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1001system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1002system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) 1003system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1004system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 1005system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) |
| 1005system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) | 1006system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks) |
| 1006system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1007system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1007system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) | 1008system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks) |
| 1008system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1010system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1011system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1012system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 1009system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1010system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) 1011system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1012system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1013system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 1013system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) | 1014system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) |
| 1014system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1015system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1015system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) | 1016system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks) |
| 1016system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1017system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) 1018system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1017system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1018system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) 1019system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1019system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) | 1020system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks) |
| 1020system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1021system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1022system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1021system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1022system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1023system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1023system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) | 1024system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks) |
| 1024system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1025system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) 1026system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1027system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1028system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1025system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1026system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) 1027system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1028system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1029system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1029system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 1030system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 1030system.iocache.tags.replacements 41685 # number of replacements | 1031system.iocache.tags.replacements 41685 # number of replacements |
| 1031system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use | 1032system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use |
| 1032system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1033system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1034system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1033system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1034system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1035system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1035system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. 1036system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor 1037system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy 1038system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy | 1036system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit. 1037system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor 1038system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy 1039system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy |
| 1039system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1040system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1041system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1042system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1043system.iocache.tags.data_accesses 375525 # Number of data accesses | 1040system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1041system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1042system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1043system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1044system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1044system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 1045system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 1045system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1046system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1047system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1048system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1049system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1050system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1051system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1052system.iocache.overall_misses::total 41725 # number of overall misses 1053system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles 1054system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles | 1046system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1047system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1048system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1049system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1050system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1051system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1052system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1053system.iocache.overall_misses::total 41725 # number of overall misses 1054system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles 1055system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles |
| 1055system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles 1056system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles 1057system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles 1058system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles 1059system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles 1060system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles | 1056system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles 1057system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles 1058system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles 1059system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles 1060system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles 1061system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles |
| 1061system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1062system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1063system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1064system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1065system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1066system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1067system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1068system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1069system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1070system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1071system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1072system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1073system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1074system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1075system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1076system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1077system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency 1078system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency | 1062system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1063system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1064system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1065system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1066system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1067system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1068system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1069system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1070system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1071system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1072system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1073system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1074system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1075system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1076system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1077system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1078system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency 1079system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency |
| 1079system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency 1080system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency 1081system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency 1082system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency 1083system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency 1084system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency 1085system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked | 1080system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency 1081system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency 1082system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency 1083system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency 1084system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency 1085system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency 1086system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked |
| 1086system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1087system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1087system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked | 1088system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked |
| 1088system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1089system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1089system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked | 1090system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked |
| 1090system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1091system.iocache.writebacks::writebacks 41512 # number of writebacks 1092system.iocache.writebacks::total 41512 # number of writebacks 1093system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1094system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1095system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1096system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1097system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1098system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1099system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1100system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1101system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles 1102system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles | 1091system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.iocache.writebacks::writebacks 41512 # number of writebacks 1093system.iocache.writebacks::total 41512 # number of writebacks 1094system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1095system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1096system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1097system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1098system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1099system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1100system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1101system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1102system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles 1103system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles |
| 1103system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles 1104system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles 1105system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles 1106system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles 1107system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles 1108system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles | 1104system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles 1105system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles 1106system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles 1107system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles 1108system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles 1109system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles |
| 1109system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1110system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1111system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1112system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1113system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1114system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1115system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1116system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1117system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency 1118system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency | 1110system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1111system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1112system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1113system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1114system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1115system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1116system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1117system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1118system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency 1119system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency |
| 1119system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency 1120system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency 1121system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency 1122system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency 1123system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency 1124system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency 1125system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. 1126system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1120system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency 1121system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency 1122system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency 1123system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency 1124system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency 1125system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency 1126system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter. 1127system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1127system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1128system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1129system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1130system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1128system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1129system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1130system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1131system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1131system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 1132system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 1132system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1133system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1133system.membus.trans_dist::ReadResp 295677 # Transaction distribution | 1134system.membus.trans_dist::ReadResp 295651 # Transaction distribution |
| 1134system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1135system.membus.trans_dist::WriteResp 9623 # Transaction distribution | 1135system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1136system.membus.trans_dist::WriteResp 9623 # Transaction distribution |
| 1136system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution 1137system.membus.trans_dist::CleanEvict 262254 # Transaction distribution | 1137system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution 1138system.membus.trans_dist::CleanEvict 262247 # Transaction distribution |
| 1138system.membus.trans_dist::UpgradeReq 138 # Transaction distribution 1139system.membus.trans_dist::UpgradeResp 3 # Transaction distribution | 1139system.membus.trans_dist::UpgradeReq 138 # Transaction distribution 1140system.membus.trans_dist::UpgradeResp 3 # Transaction distribution |
| 1140system.membus.trans_dist::ReadExReq 116510 # Transaction distribution 1141system.membus.trans_dist::ReadExResp 116510 # Transaction distribution 1142system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution 1143system.membus.trans_dist::BadAddressError 23 # Transaction distribution | 1141system.membus.trans_dist::ReadExReq 116518 # Transaction distribution 1142system.membus.trans_dist::ReadExResp 116518 # Transaction distribution 1143system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution 1144system.membus.trans_dist::BadAddressError 24 # Transaction distribution |
| 1144system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1145system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1145system.membus.trans_dist::InvalidateResp 127 # Transaction distribution | 1146system.membus.trans_dist::InvalidateResp 124 # Transaction distribution |
| 1146system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) | 1147system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) |
| 1147system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) 1148system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) 1149system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) | 1148system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes) 1149system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) 1150system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes) |
| 1150system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1151system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) | 1151system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1152system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) |
| 1152system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) | 1153system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes) |
| 1153system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) | 1154system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) |
| 1154system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) 1155system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) | 1155system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes) 1156system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes) |
| 1156system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1157system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1157system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1158system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1158system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) 1159system.membus.snoops 561 # Total snoops (count) | 1159system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes) 1160system.membus.snoops 558 # Total snoops (count) |
| 1160system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) | 1161system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) |
| 1161system.membus.snoop_fanout::samples 463523 # Request fanout histogram 1162system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram 1163system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram | 1162system.membus.snoop_fanout::samples 463506 # Request fanout histogram 1163system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram 1164system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram |
| 1164system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1165system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1165system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram 1166system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram | 1166system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram 1167system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram |
| 1167system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1168system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1169system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1170system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1168system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1169system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1170system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1171system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1171system.membus.snoop_fanout::total 463523 # Request fanout histogram 1172system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) | 1172system.membus.snoop_fanout::total 463506 # Request fanout histogram 1173system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks) |
| 1173system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1174system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1174system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) | 1175system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks) |
| 1175system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1176system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1176system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) | 1177system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) |
| 1177system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1178system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1178system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) | 1179system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks) |
| 1179system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1180system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1180system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) | 1181system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks) |
| 1181system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1182system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1182system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1183system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1184system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1185system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1186system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 1183system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1184system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1185system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1186system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1187system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 1187system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1188system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1189system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1190system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1191system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1192system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1193system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1194system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1210system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1211system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1212system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1213system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1214system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1215system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1216system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1217system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1188system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1189system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1190system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1191system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1192system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1193system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1194system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1195system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1211system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1212system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1213system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1214system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1215system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1216system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1217system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1218system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1218system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1219system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1220system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1221system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1222system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1223system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1226system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1227system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1228system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1229system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1230system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1231system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1232system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1237system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1238system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1239system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states 1240system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states | 1219system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1220system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1221system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1222system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1223system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1226system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1227system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1228system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1229system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1230system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1231system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1232system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1237system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1238system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1239system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1240system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states 1241system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states |
| 1241 1242---------- End Simulation Statistics ---------- | 1242 1243---------- End Simulation Statistics ---------- |