| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.909061 # Number of seconds simulated 4sim_ticks 1909061460000 # Number of ticks simulated 5final_tick 1909061460000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.889223 # Number of seconds simulated 4sim_ticks 1889223246000 # Number of ticks simulated 5final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 24403 # Simulator instruction rate (inst/s) 8host_op_rate 24403 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 829686396 # Simulator tick rate (ticks/s) 10host_mem_usage 385840 # Number of bytes of host memory used 11host_seconds 2300.94 # Real time elapsed on the host 12sim_insts 56149847 # Number of instructions simulated 13sim_ops 56149847 # Number of ops (including micro ops) simulated | 7host_inst_rate 22780 # Simulator instruction rate (inst/s) 8host_op_rate 22780 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 766551699 # Simulator tick rate (ticks/s) 10host_mem_usage 396616 # Number of bytes of host memory used 11host_seconds 2464.57 # Real time elapsed on the host 12sim_insts 56141873 # Number of instructions simulated 13sim_ops 56141873 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1046656 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24857664 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 25905280 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1046656 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1046656 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7563328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7563328 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 16354 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388401 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 404770 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 118177 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 118177 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 548257 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13020882 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13569642 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 548257 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 548257 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3961804 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3961804 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3961804 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 548257 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13020882 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17531446 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 404770 # Number of read requests accepted 45system.physmem.writeReqs 118177 # Number of write requests accepted 46system.physmem.readBursts 404770 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 118177 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25897600 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25905280 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7563328 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue | 28system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 404805 # Number of read requests accepted 45system.physmem.writeReqs 118227 # Number of write requests accepted 46system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 25467 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25712 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25810 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25757 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25010 # Per bank write bursts 61system.physmem.perBankRdBursts::5 25117 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24705 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24573 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25203 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25292 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25386 # Per bank write bursts 67system.physmem.perBankRdBursts::11 25018 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24535 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25541 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25794 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25730 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7820 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 25470 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25713 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25812 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25774 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25230 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24950 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24793 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24569 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25113 # Per bank write bursts 65system.physmem.perBankRdBursts::9 25266 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25525 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24857 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24533 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25560 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25804 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25731 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7815 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::1 7678 # Per bank write bursts | 73system.physmem.perBankWrBursts::1 7678 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::2 8070 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7721 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7116 # Per bank write bursts 77system.physmem.perBankWrBursts::5 7111 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6703 # Per bank write bursts | 74system.physmem.perBankWrBursts::2 8068 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7736 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7326 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6953 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6780 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::7 6420 # Per bank write bursts | 79system.physmem.perBankWrBursts::7 6420 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::8 7317 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6903 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7274 # Per bank write bursts 83system.physmem.perBankWrBursts::11 7007 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7092 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7990 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7984 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7946 # Per bank write bursts | 80system.physmem.perBankWrBursts::8 7238 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6883 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7397 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6875 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7088 # Per bank write bursts 85system.physmem.perBankWrBursts::13 8006 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7993 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7949 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 89system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 90system.physmem.totGap 1909052547000 # Total gap between requests | 89system.physmem.numWrRetry 20 # Number of times write queue was full causing retry 90system.physmem.totGap 1889214280000 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 404770 # Read request sizes (log2) | 97system.physmem.readPktSize::6 404805 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 118177 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 402459 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 118227 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see |
| 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see --- 28 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1514 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2905 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 7219 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6802 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6024 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 5843 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 6456 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6884 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6578 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8579 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 8848 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7457 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 7892 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 7078 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 7321 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5605 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 214 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 136 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 184 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 88 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 64573 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 518.162823 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 316.799935 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 407.231768 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14977 23.19% 23.19% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11234 17.40% 40.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4851 7.51% 48.10% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3268 5.06% 53.16% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2473 3.83% 56.99% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 2033 3.15% 60.14% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 4174 6.46% 66.61% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1362 2.11% 68.72% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 20201 31.28% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 64573 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 76.433321 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2890.025475 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5291 99.94% 99.94% # Reads before turning the bus around for writes | 152system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.318096 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 19.102648 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 19.930772 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4682 88.44% 88.44% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 33 0.62% 89.06% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 23 0.43% 89.50% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 33 0.62% 90.12% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 222 4.19% 94.31% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 11 0.21% 94.52% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 11 0.21% 94.73% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 35 0.66% 95.39% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 195 3.68% 99.07% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 5 0.09% 99.17% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 6 0.11% 99.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 4 0.08% 99.36% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::128-135 5 0.09% 99.45% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::136-143 2 0.04% 99.49% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::144-151 1 0.02% 99.51% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::160-167 2 0.04% 99.55% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::168-175 9 0.17% 99.72% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::176-183 4 0.08% 99.79% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::184-191 2 0.04% 99.83% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::208-215 5 0.09% 99.92% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::216-223 1 0.02% 99.94% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::224-231 1 0.02% 99.96% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads 251system.physmem.totQLat 2639973000 # Total ticks spent queuing 252system.physmem.totMemAccLat 10227160500 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 2023250000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 6524.09 # Average queueing delay per DRAM burst | 222system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads 253system.physmem.totQLat 2164522000 # Total ticks spent queuing 254system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst |
| 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 256system.physmem.avgMemAccLat 25274.09 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 13.57 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 13.57 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s | 258system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s 262system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s |
| 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 0.14 # Data bus utilization in percentage 263system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.14 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 266system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing 267system.physmem.readRowHits 362738 # Number of row buffer hits during reads 268system.physmem.writeRowHits 95491 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 89.64 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes 271system.physmem.avgGap 3650566.02 # Average gap between requests 272system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined 273system.physmem_0.actEnergy 238623840 # Energy for activate commands per rank (pJ) 274system.physmem_0.preEnergy 130201500 # Energy for precharge commands per rank (pJ) 275system.physmem_0.readEnergy 1576777800 # Energy for read commands per rank (pJ) 276system.physmem_0.writeEnergy 379980720 # Energy for write commands per rank (pJ) 277system.physmem_0.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) 278system.physmem_0.actBackEnergy 68013230490 # Energy for active background per rank (pJ) 279system.physmem_0.preBackEnergy 1085773099500 # Energy for precharge background per rank (pJ) 280system.physmem_0.totalEnergy 1280802180330 # Total energy per rank (pJ) 281system.physmem_0.averagePower 670.908515 # Core power per rank (mW) 282system.physmem_0.memoryStateTime::IDLE 1806022540250 # Time in different power states 283system.physmem_0.memoryStateTime::REF 63747580000 # Time in different power states | 268system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing 269system.physmem.readRowHits 363251 # Number of row buffer hits during reads 270system.physmem.writeRowHits 95908 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes 273system.physmem.avgGap 3612043.39 # Average gap between requests 274system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined 275system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ) 282system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ) 283system.physmem_0.averagePower 670.494357 # Core power per rank (mW) 284system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states 285system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states |
| 284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 286system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 285system.physmem_0.memoryStateTime::ACT 39286273500 # Time in different power states | 287system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states |
| 286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 288system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 287system.physmem_1.actEnergy 249548040 # Energy for activate commands per rank (pJ) 288system.physmem_1.preEnergy 136162125 # Energy for precharge commands per rank (pJ) 289system.physmem_1.readEnergy 1579492200 # Energy for read commands per rank (pJ) 290system.physmem_1.writeEnergy 385644240 # Energy for write commands per rank (pJ) 291system.physmem_1.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) 292system.physmem_1.actBackEnergy 68685352830 # Energy for active background per rank (pJ) 293system.physmem_1.preBackEnergy 1085183526750 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 1280909992665 # Total energy per rank (pJ) 295system.physmem_1.averagePower 670.964984 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 1805042162250 # Time in different power states 297system.physmem_1.memoryStateTime::REF 63747580000 # Time in different power states | 289system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ) 290system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ) 291system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ) 292system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ) 293system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) 294system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ) 295system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ) 297system.physmem_1.averagePower 670.577899 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states 299system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states |
| 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 299system.physmem_1.memoryStateTime::ACT 40266665250 # Time in different power states | 301system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states |
| 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 301system.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 302system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 303system.cpu.branchPred.lookups 15258422 # Number of BP lookups 304system.cpu.branchPred.condPredicted 13121569 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 520615 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 12105776 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 4568162 # Number of BTB hits | 303system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 304system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 305system.cpu.branchPred.lookups 15253451 # Number of BP lookups 306system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted 307system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect 308system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups 309system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits |
| 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 310system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 309system.cpu.branchPred.BTBHitPct 37.735392 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 863536 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 33630 # Number of incorrect RAS predictions. 312system.cpu.branchPred.indirectLookups 6539212 # Number of indirect predictor lookups. 313system.cpu.branchPred.indirectHits 544524 # Number of indirect target hits. 314system.cpu.branchPred.indirectMisses 5994688 # Number of indirect misses. 315system.cpu.branchPredindirectMispredicted 219095 # Number of mispredicted indirect branches. | 311system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage 312system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target. 313system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions. 314system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups. 315system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits. 316system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses. 317system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches. |
| 316system.cpu_clk_domain.clock 500 # Clock period in ticks 317system.cpu.dtb.fetch_hits 0 # ITB hits 318system.cpu.dtb.fetch_misses 0 # ITB misses 319system.cpu.dtb.fetch_acv 0 # ITB acv 320system.cpu.dtb.fetch_accesses 0 # ITB accesses | 318system.cpu_clk_domain.clock 500 # Clock period in ticks 319system.cpu.dtb.fetch_hits 0 # ITB hits 320system.cpu.dtb.fetch_misses 0 # ITB misses 321system.cpu.dtb.fetch_acv 0 # ITB acv 322system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 321system.cpu.dtb.read_hits 9320175 # DTB read hits 322system.cpu.dtb.read_misses 17427 # DTB read misses | 323system.cpu.dtb.read_hits 9316925 # DTB read hits 324system.cpu.dtb.read_misses 17695 # DTB read misses |
| 323system.cpu.dtb.read_acv 211 # DTB read access violations | 325system.cpu.dtb.read_acv 211 # DTB read access violations |
| 324system.cpu.dtb.read_accesses 764388 # DTB read accesses 325system.cpu.dtb.write_hits 6394455 # DTB write hits 326system.cpu.dtb.write_misses 2545 # DTB write misses 327system.cpu.dtb.write_acv 159 # DTB write access violations 328system.cpu.dtb.write_accesses 298887 # DTB write accesses 329system.cpu.dtb.data_hits 15714630 # DTB hits 330system.cpu.dtb.data_misses 19972 # DTB misses 331system.cpu.dtb.data_acv 370 # DTB access violations 332system.cpu.dtb.data_accesses 1063275 # DTB accesses 333system.cpu.itb.fetch_hits 4019631 # ITB hits 334system.cpu.itb.fetch_misses 6355 # ITB misses 335system.cpu.itb.fetch_acv 661 # ITB acv 336system.cpu.itb.fetch_accesses 4025986 # ITB accesses | 326system.cpu.dtb.read_accesses 764827 # DTB read accesses 327system.cpu.dtb.write_hits 6393212 # DTB write hits 328system.cpu.dtb.write_misses 2442 # DTB write misses 329system.cpu.dtb.write_acv 158 # DTB write access violations 330system.cpu.dtb.write_accesses 298820 # DTB write accesses 331system.cpu.dtb.data_hits 15710137 # DTB hits 332system.cpu.dtb.data_misses 20137 # DTB misses 333system.cpu.dtb.data_acv 369 # DTB access violations 334system.cpu.dtb.data_accesses 1063647 # DTB accesses 335system.cpu.itb.fetch_hits 4018824 # ITB hits 336system.cpu.itb.fetch_misses 6310 # ITB misses 337system.cpu.itb.fetch_acv 701 # ITB acv 338system.cpu.itb.fetch_accesses 4025134 # ITB accesses |
| 337system.cpu.itb.read_hits 0 # DTB read hits 338system.cpu.itb.read_misses 0 # DTB read misses 339system.cpu.itb.read_acv 0 # DTB read access violations 340system.cpu.itb.read_accesses 0 # DTB read accesses 341system.cpu.itb.write_hits 0 # DTB write hits 342system.cpu.itb.write_misses 0 # DTB write misses 343system.cpu.itb.write_acv 0 # DTB write access violations 344system.cpu.itb.write_accesses 0 # DTB write accesses 345system.cpu.itb.data_hits 0 # DTB hits 346system.cpu.itb.data_misses 0 # DTB misses 347system.cpu.itb.data_acv 0 # DTB access violations 348system.cpu.itb.data_accesses 0 # DTB accesses | 339system.cpu.itb.read_hits 0 # DTB read hits 340system.cpu.itb.read_misses 0 # DTB read misses 341system.cpu.itb.read_acv 0 # DTB read access violations 342system.cpu.itb.read_accesses 0 # DTB read accesses 343system.cpu.itb.write_hits 0 # DTB write hits 344system.cpu.itb.write_misses 0 # DTB write misses 345system.cpu.itb.write_acv 0 # DTB write access violations 346system.cpu.itb.write_accesses 0 # DTB write accesses 347system.cpu.itb.data_hits 0 # DTB hits 348system.cpu.itb.data_misses 0 # DTB misses 349system.cpu.itb.data_acv 0 # DTB access violations 350system.cpu.itb.data_accesses 0 # DTB accesses |
| 349system.cpu.numPwrStateTransitions 12756 # Number of power state transitions 350system.cpu.pwrStateClkGateDist::samples 6378 # Distribution of time spent in the clock gated state 351system.cpu.pwrStateClkGateDist::mean 281603673.878959 # Distribution of time spent in the clock gated state 352system.cpu.pwrStateClkGateDist::stdev 439873554.784215 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 354system.cpu.pwrStateClkGateDist::1000-5e+10 6377 99.98% 100.00% # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state | 351system.cpu.numPwrStateTransitions 12752 # Number of power state transitions 352system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state 354system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state |
| 356system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state | 357system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| 357system.cpu.pwrStateClkGateDist::total 6378 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateResidencyTicks::ON 112993228000 # Cumulative time (in ticks) in various power states 359system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000 # Cumulative time (in ticks) in various power states 360system.cpu.numCycles 226008061 # number of cpu cycles simulated | 358system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state 359system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states 360system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states 361system.cpu.numCycles 185630526 # number of cpu cycles simulated |
| 361system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 363system.cpu.committedInsts 56149847 # Number of instructions committed 364system.cpu.committedOps 56149847 # Number of ops (including micro ops) committed 365system.cpu.discardedOps 2969857 # Number of ops (including micro ops) which were discarded before commit 366system.cpu.numFetchSuspends 6378 # Number of times Execute suspended instruction fetching 367system.cpu.quiesceCycles 3592114868 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 368system.cpu.cpi 4.025088 # CPI: cycles per instruction 369system.cpu.ipc 0.248442 # IPC: instructions per cycle 370system.cpu.op_class_0::No_OpClass 3199355 5.70% 5.70% # Class of committed instruction 371system.cpu.op_class_0::IntAlu 36201883 64.47% 70.17% # Class of committed instruction 372system.cpu.op_class_0::IntMult 60840 0.11% 70.28% # Class of committed instruction | 364system.cpu.committedInsts 56141873 # Number of instructions committed 365system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed 366system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit 367system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching 368system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 369system.cpu.cpi 3.306454 # CPI: cycles per instruction 370system.cpu.ipc 0.302439 # IPC: instructions per cycle 371system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction 372system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction 373system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction |
| 373system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 374system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction 375system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 376system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 377system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction | 374system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction 375system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction 376system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction 377system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction 378system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction |
| 378system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction 379system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction 380system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction 381system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction 382system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction 383system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction 384system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction 385system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction 386system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction 387system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction 388system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction 389system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction 390system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction 391system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction 392system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction 393system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction 394system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction 395system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction 396system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction 397system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction 398system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction 399system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction 400system.cpu.op_class_0::MemRead 9320961 16.60% 86.95% # Class of committed instruction 401system.cpu.op_class_0::MemWrite 6373595 11.35% 98.31% # Class of committed instruction 402system.cpu.op_class_0::IprAccess 951498 1.69% 100.00% # Class of committed instruction | 379system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction 380system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction 381system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction 382system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction 383system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction 384system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction 385system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction 386system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction 387system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction 388system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction 389system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction 390system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction 391system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction 392system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction 393system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction 394system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction 395system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction 396system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction 397system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction 398system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction 399system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction 400system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction 401system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction 402system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction 403system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction |
| 403system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 404system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 404system.cpu.op_class_0::total 56149847 # Class of committed instruction | 405system.cpu.op_class_0::total 56141873 # Class of committed instruction |
| 405system.cpu.kern.inst.arm 0 # number of arm instructions executed | 406system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 406system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed 407system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed 408system.cpu.kern.ipl_count::0 74821 40.93% 40.93% # number of times we switched to this ipl 409system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl 410system.cpu.kern.ipl_count::22 1907 1.04% 42.04% # number of times we switched to this ipl 411system.cpu.kern.ipl_count::31 105943 57.96% 100.00% # number of times we switched to this ipl 412system.cpu.kern.ipl_count::total 182802 # number of times we switched to this ipl 413system.cpu.kern.ipl_good::0 73454 49.32% 49.32% # number of times we switched to this ipl from a different ipl | 407system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 408system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed 409system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl 410system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl 411system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl 412system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl 413system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl 414system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl |
| 414system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 415system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 415system.cpu.kern.ipl_good::22 1907 1.28% 50.68% # number of times we switched to this ipl from a different ipl 416system.cpu.kern.ipl_good::31 73454 49.32% 100.00% # number of times we switched to this ipl from a different ipl 417system.cpu.kern.ipl_good::total 148946 # number of times we switched to this ipl from a different ipl 418system.cpu.kern.ipl_ticks::0 1839859866500 96.38% 96.38% # number of cycles we spent at this ipl 419system.cpu.kern.ipl_ticks::21 85941500 0.00% 96.38% # number of cycles we spent at this ipl 420system.cpu.kern.ipl_ticks::22 711439500 0.04% 96.42% # number of cycles we spent at this ipl 421system.cpu.kern.ipl_ticks::31 68403193000 3.58% 100.00% # number of cycles we spent at this ipl 422system.cpu.kern.ipl_ticks::total 1909060440500 # number of cycles we spent at this ipl 423system.cpu.kern.ipl_used::0 0.981730 # fraction of swpipl calls that actually changed the ipl | 416system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl 417system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl 418system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl 419system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl 420system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl 421system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl 422system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl 423system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl 424system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl |
| 424system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 425system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 425system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 426system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 426system.cpu.kern.ipl_used::31 0.693335 # fraction of swpipl calls that actually changed the ipl 427system.cpu.kern.ipl_used::total 0.814794 # fraction of swpipl calls that actually changed the ipl | 427system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl 428system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl |
| 428system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 429system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 430system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 431system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 432system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 433system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 434system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 435system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 458system.cpu.kern.syscall::total 326 # number of syscalls executed 459system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 460system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 461system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 462system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 463system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed 464system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 465system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 429system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 430system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 431system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 432system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 433system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 434system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 435system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 436system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 459system.cpu.kern.syscall::total 326 # number of syscalls executed 460system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 461system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 462system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 463system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 464system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed 465system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 466system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 466system.cpu.kern.callpal::swpipl 175631 91.22% 93.43% # number of callpals executed 467system.cpu.kern.callpal::rdps 6810 3.54% 96.96% # number of callpals executed | 467system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed 468system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed |
| 468system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 469system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 470system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 471system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 469system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 470system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 471system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 472system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 472system.cpu.kern.callpal::rti 5132 2.67% 99.64% # number of callpals executed | 473system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed |
| 473system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 474system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 474system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 475system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 475system.cpu.kern.callpal::total 192526 # number of callpals executed 476system.cpu.kern.mode_switch::kernel 5877 # number of protection mode switches 477system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 478system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 479system.cpu.kern.mode_good::kernel 1906 480system.cpu.kern.mode_good::user 1738 | 476system.cpu.kern.callpal::total 192434 # number of callpals executed 477system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches 478system.cpu.kern.mode_switch::user 1737 # number of protection mode switches 479system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches 480system.cpu.kern.mode_good::kernel 1905 481system.cpu.kern.mode_good::user 1737 |
| 481system.cpu.kern.mode_good::idle 168 | 482system.cpu.kern.mode_good::idle 168 |
| 482system.cpu.kern.mode_switch_good::kernel 0.324315 # fraction of useful protection mode switches | 483system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches |
| 483system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 484system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 484system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches 485system.cpu.kern.mode_switch_good::total 0.392625 # fraction of useful protection mode switches 486system.cpu.kern.mode_ticks::kernel 38921683000 2.04% 2.04% # number of ticks spent at the given mode 487system.cpu.kern.mode_ticks::user 4598347000 0.24% 2.28% # number of ticks spent at the given mode 488system.cpu.kern.mode_ticks::idle 1865540400500 97.72% 100.00% # number of ticks spent at the given mode | 485system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches 486system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches 487system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode 488system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode 489system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode |
| 489system.cpu.kern.swap_context 4174 # number of times the context was actually changed | 490system.cpu.kern.swap_context 4174 # number of times the context was actually changed |
| 490system.cpu.tickCycles 85327235 # Number of cycles that the object actually ticked 491system.cpu.idleCycles 140680826 # Total number of cycles that the object has spent stopped 492system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 493system.cpu.dcache.tags.replacements 1394976 # number of replacements 494system.cpu.dcache.tags.tagsinuse 511.976740 # Cycle average of tags in use 495system.cpu.dcache.tags.total_refs 13944378 # Total number of references to valid blocks. 496system.cpu.dcache.tags.sampled_refs 1395488 # Sample count of references to valid blocks. 497system.cpu.dcache.tags.avg_refs 9.992474 # Average number of references to valid blocks. 498system.cpu.dcache.tags.warmup_cycle 124106500 # Cycle when the warmup percentage was hit. 499system.cpu.dcache.tags.occ_blocks::cpu.data 511.976740 # Average occupied blocks per requestor 500system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy 501system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy | 491system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked 492system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped 493system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 494system.cpu.dcache.tags.replacements 1394263 # number of replacements 495system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use 496system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks. 497system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks. 498system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks. 499system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit. 500system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor 501system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy 502system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy |
| 502system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 503system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 503system.cpu.dcache.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id 504system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id | 504system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 505system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id |
| 505system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 506system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 506system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 507system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 507system.cpu.dcache.tags.tag_accesses 63924438 # Number of tag accesses 508system.cpu.dcache.tags.data_accesses 63924438 # Number of data accesses 509system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 510system.cpu.dcache.ReadReq_hits::cpu.data 7983946 # number of ReadReq hits 511system.cpu.dcache.ReadReq_hits::total 7983946 # number of ReadReq hits 512system.cpu.dcache.WriteReq_hits::cpu.data 5577839 # number of WriteReq hits 513system.cpu.dcache.WriteReq_hits::total 5577839 # number of WriteReq hits 514system.cpu.dcache.LoadLockedReq_hits::cpu.data 183518 # number of LoadLockedReq hits 515system.cpu.dcache.LoadLockedReq_hits::total 183518 # number of LoadLockedReq hits 516system.cpu.dcache.StoreCondReq_hits::cpu.data 199043 # number of StoreCondReq hits 517system.cpu.dcache.StoreCondReq_hits::total 199043 # number of StoreCondReq hits 518system.cpu.dcache.demand_hits::cpu.data 13561785 # number of demand (read+write) hits 519system.cpu.dcache.demand_hits::total 13561785 # number of demand (read+write) hits 520system.cpu.dcache.overall_hits::cpu.data 13561785 # number of overall hits 521system.cpu.dcache.overall_hits::total 13561785 # number of overall hits 522system.cpu.dcache.ReadReq_misses::cpu.data 1096703 # number of ReadReq misses 523system.cpu.dcache.ReadReq_misses::total 1096703 # number of ReadReq misses 524system.cpu.dcache.WriteReq_misses::cpu.data 574639 # number of WriteReq misses 525system.cpu.dcache.WriteReq_misses::total 574639 # number of WriteReq misses 526system.cpu.dcache.LoadLockedReq_misses::cpu.data 16549 # number of LoadLockedReq misses 527system.cpu.dcache.LoadLockedReq_misses::total 16549 # number of LoadLockedReq misses 528system.cpu.dcache.demand_misses::cpu.data 1671342 # number of demand (read+write) misses 529system.cpu.dcache.demand_misses::total 1671342 # number of demand (read+write) misses 530system.cpu.dcache.overall_misses::cpu.data 1671342 # number of overall misses 531system.cpu.dcache.overall_misses::total 1671342 # number of overall misses 532system.cpu.dcache.ReadReq_miss_latency::cpu.data 45383174000 # number of ReadReq miss cycles 533system.cpu.dcache.ReadReq_miss_latency::total 45383174000 # number of ReadReq miss cycles 534system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964439500 # number of WriteReq miss cycles 535system.cpu.dcache.WriteReq_miss_latency::total 33964439500 # number of WriteReq miss cycles 536system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226601500 # number of LoadLockedReq miss cycles 537system.cpu.dcache.LoadLockedReq_miss_latency::total 226601500 # number of LoadLockedReq miss cycles 538system.cpu.dcache.demand_miss_latency::cpu.data 79347613500 # number of demand (read+write) miss cycles 539system.cpu.dcache.demand_miss_latency::total 79347613500 # number of demand (read+write) miss cycles 540system.cpu.dcache.overall_miss_latency::cpu.data 79347613500 # number of overall miss cycles 541system.cpu.dcache.overall_miss_latency::total 79347613500 # number of overall miss cycles 542system.cpu.dcache.ReadReq_accesses::cpu.data 9080649 # number of ReadReq accesses(hits+misses) 543system.cpu.dcache.ReadReq_accesses::total 9080649 # number of ReadReq accesses(hits+misses) 544system.cpu.dcache.WriteReq_accesses::cpu.data 6152478 # number of WriteReq accesses(hits+misses) 545system.cpu.dcache.WriteReq_accesses::total 6152478 # number of WriteReq accesses(hits+misses) 546system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200067 # number of LoadLockedReq accesses(hits+misses) 547system.cpu.dcache.LoadLockedReq_accesses::total 200067 # number of LoadLockedReq accesses(hits+misses) 548system.cpu.dcache.StoreCondReq_accesses::cpu.data 199043 # number of StoreCondReq accesses(hits+misses) 549system.cpu.dcache.StoreCondReq_accesses::total 199043 # number of StoreCondReq accesses(hits+misses) 550system.cpu.dcache.demand_accesses::cpu.data 15233127 # number of demand (read+write) accesses 551system.cpu.dcache.demand_accesses::total 15233127 # number of demand (read+write) accesses 552system.cpu.dcache.overall_accesses::cpu.data 15233127 # number of overall (read+write) accesses 553system.cpu.dcache.overall_accesses::total 15233127 # number of overall (read+write) accesses 554system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120774 # miss rate for ReadReq accesses 555system.cpu.dcache.ReadReq_miss_rate::total 0.120774 # miss rate for ReadReq accesses 556system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093400 # miss rate for WriteReq accesses 557system.cpu.dcache.WriteReq_miss_rate::total 0.093400 # miss rate for WriteReq accesses 558system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082717 # miss rate for LoadLockedReq accesses 559system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082717 # miss rate for LoadLockedReq accesses 560system.cpu.dcache.demand_miss_rate::cpu.data 0.109718 # miss rate for demand accesses 561system.cpu.dcache.demand_miss_rate::total 0.109718 # miss rate for demand accesses 562system.cpu.dcache.overall_miss_rate::cpu.data 0.109718 # miss rate for overall accesses 563system.cpu.dcache.overall_miss_rate::total 0.109718 # miss rate for overall accesses 564system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438 # average ReadReq miss latency 565system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438 # average ReadReq miss latency 566system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534 # average WriteReq miss latency 567system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534 # average WriteReq miss latency 568system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892 # average LoadLockedReq miss latency 569system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892 # average LoadLockedReq miss latency 570system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency 571system.cpu.dcache.demand_avg_miss_latency::total 47475.390136 # average overall miss latency 572system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency 573system.cpu.dcache.overall_avg_miss_latency::total 47475.390136 # average overall miss latency | 508system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses 509system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses 510system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 511system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits 512system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits 513system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits 514system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits 515system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits 516system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits 517system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits 518system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits 519system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits 520system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits 521system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits 522system.cpu.dcache.overall_hits::total 13559548 # number of overall hits 523system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses 524system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses 525system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses 526system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses 527system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses 528system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses 529system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses 530system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses 531system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses 532system.cpu.dcache.overall_misses::total 1669982 # number of overall misses 533system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles 534system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles 535system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles 536system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles 537system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles 538system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles 539system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles 540system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles 541system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles 542system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles 543system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses) 544system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses) 545system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses) 546system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses) 547system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses) 548system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) 549system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses) 550system.cpu.dcache.StoreCondReq_accesses::total 199007 # number of StoreCondReq accesses(hits+misses) 551system.cpu.dcache.demand_accesses::cpu.data 15229530 # number of demand (read+write) accesses 552system.cpu.dcache.demand_accesses::total 15229530 # number of demand (read+write) accesses 553system.cpu.dcache.overall_accesses::cpu.data 15229530 # number of overall (read+write) accesses 554system.cpu.dcache.overall_accesses::total 15229530 # number of overall (read+write) accesses 555system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120767 # miss rate for ReadReq accesses 556system.cpu.dcache.ReadReq_miss_rate::total 0.120767 # miss rate for ReadReq accesses 557system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093256 # miss rate for WriteReq accesses 558system.cpu.dcache.WriteReq_miss_rate::total 0.093256 # miss rate for WriteReq accesses 559system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082893 # miss rate for LoadLockedReq accesses 560system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082893 # miss rate for LoadLockedReq accesses 561system.cpu.dcache.demand_miss_rate::cpu.data 0.109654 # miss rate for demand accesses 562system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses 563system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses 564system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses 565system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency 566system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency 567system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency 568system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency 569system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency 570system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency 571system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency 572system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency 573system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency 574system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency |
| 574system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 575system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 576system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 577system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 578system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 579system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 575system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 576system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 577system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 578system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 579system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 580system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 580system.cpu.dcache.writebacks::writebacks 838068 # number of writebacks 581system.cpu.dcache.writebacks::total 838068 # number of writebacks 582system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21939 # number of ReadReq MSHR hits 583system.cpu.dcache.ReadReq_mshr_hits::total 21939 # number of ReadReq MSHR hits 584system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270415 # number of WriteReq MSHR hits 585system.cpu.dcache.WriteReq_mshr_hits::total 270415 # number of WriteReq MSHR hits | 581system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks 582system.cpu.dcache.writebacks::total 837697 # number of writebacks 583system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits 584system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits 585system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits 586system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits |
| 586system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 587system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 587system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 588system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 588system.cpu.dcache.demand_mshr_hits::cpu.data 292354 # number of demand (read+write) MSHR hits 589system.cpu.dcache.demand_mshr_hits::total 292354 # number of demand (read+write) MSHR hits 590system.cpu.dcache.overall_mshr_hits::cpu.data 292354 # number of overall MSHR hits 591system.cpu.dcache.overall_mshr_hits::total 292354 # number of overall MSHR hits 592system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074764 # number of ReadReq MSHR misses 593system.cpu.dcache.ReadReq_mshr_misses::total 1074764 # number of ReadReq MSHR misses 594system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304224 # number of WriteReq MSHR misses 595system.cpu.dcache.WriteReq_mshr_misses::total 304224 # number of WriteReq MSHR misses 596system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16546 # number of LoadLockedReq MSHR misses 597system.cpu.dcache.LoadLockedReq_mshr_misses::total 16546 # number of LoadLockedReq MSHR misses 598system.cpu.dcache.demand_mshr_misses::cpu.data 1378988 # number of demand (read+write) MSHR misses 599system.cpu.dcache.demand_mshr_misses::total 1378988 # number of demand (read+write) MSHR misses 600system.cpu.dcache.overall_mshr_misses::cpu.data 1378988 # number of overall MSHR misses 601system.cpu.dcache.overall_mshr_misses::total 1378988 # number of overall MSHR misses | 589system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits 590system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits 591system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits 592system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits 593system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses 594system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses 595system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses 596system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses 597system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses 598system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses 599system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses 600system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses 601system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses 602system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses |
| 602system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 603system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 603system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 604system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 604system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable 605system.cpu.dcache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable 606system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses 607system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses 608system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43721360500 # number of ReadReq MSHR miss cycles 609system.cpu.dcache.ReadReq_mshr_miss_latency::total 43721360500 # number of ReadReq MSHR miss cycles 610system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17277660500 # number of WriteReq MSHR miss cycles 611system.cpu.dcache.WriteReq_mshr_miss_latency::total 17277660500 # number of WriteReq MSHR miss cycles 612system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209790000 # number of LoadLockedReq MSHR miss cycles 613system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209790000 # number of LoadLockedReq MSHR miss cycles 614system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60999021000 # number of demand (read+write) MSHR miss cycles 615system.cpu.dcache.demand_mshr_miss_latency::total 60999021000 # number of demand (read+write) MSHR miss cycles 616system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60999021000 # number of overall MSHR miss cycles 617system.cpu.dcache.overall_mshr_miss_latency::total 60999021000 # number of overall MSHR miss cycles 618system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527294000 # number of ReadReq MSHR uncacheable cycles 619system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527294000 # number of ReadReq MSHR uncacheable cycles 620system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1527294000 # number of overall MSHR uncacheable cycles 621system.cpu.dcache.overall_mshr_uncacheable_latency::total 1527294000 # number of overall MSHR uncacheable cycles 622system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118358 # mshr miss rate for ReadReq accesses 623system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118358 # mshr miss rate for ReadReq accesses 624system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049447 # mshr miss rate for WriteReq accesses 625system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049447 # mshr miss rate for WriteReq accesses 626system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082702 # mshr miss rate for LoadLockedReq accesses 627system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082702 # mshr miss rate for LoadLockedReq accesses 628system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for demand accesses 629system.cpu.dcache.demand_mshr_miss_rate::total 0.090526 # mshr miss rate for demand accesses 630system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for overall accesses 631system.cpu.dcache.overall_mshr_miss_rate::total 0.090526 # mshr miss rate for overall accesses 632system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694 # average ReadReq mshr miss latency 633system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694 # average ReadReq mshr miss latency 634system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388 # average WriteReq mshr miss latency 635system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388 # average WriteReq mshr miss latency 636system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389 # average LoadLockedReq mshr miss latency 637system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389 # average LoadLockedReq mshr miss latency 638system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency 639system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency 640system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency 641system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency 642system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589 # average ReadReq mshr uncacheable latency 643system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589 # average ReadReq mshr uncacheable latency 644system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549 # average overall mshr uncacheable latency 645system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549 # average overall mshr uncacheable latency 646system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 647system.cpu.icache.tags.replacements 1477492 # number of replacements 648system.cpu.icache.tags.tagsinuse 508.111413 # Cycle average of tags in use 649system.cpu.icache.tags.total_refs 19219698 # Total number of references to valid blocks. 650system.cpu.icache.tags.sampled_refs 1478003 # Sample count of references to valid blocks. 651system.cpu.icache.tags.avg_refs 13.003829 # Average number of references to valid blocks. 652system.cpu.icache.tags.warmup_cycle 50147606500 # Cycle when the warmup percentage was hit. 653system.cpu.icache.tags.occ_blocks::cpu.inst 508.111413 # Average occupied blocks per requestor 654system.cpu.icache.tags.occ_percent::cpu.inst 0.992405 # Average percentage of cache occupancy 655system.cpu.icache.tags.occ_percent::total 0.992405 # Average percentage of cache occupancy | 605system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable 606system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable 607system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses 608system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses 609system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles 610system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles 611system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles 612system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles 613system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles 614system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles 615system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles 616system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles 617system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles 618system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles 619system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles 620system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles 621system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles 622system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles 623system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses 624system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses 625system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses 626system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses 627system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses 628system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses 629system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses 630system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses 631system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses 632system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses 633system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency 634system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency 635system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency 636system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency 637system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency 638system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency 639system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency 640system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency 641system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency 642system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency 643system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency 644system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency 645system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency 646system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency 647system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 648system.cpu.icache.tags.replacements 1476241 # number of replacements 649system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use 650system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks. 651system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks. 652system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks. 653system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit. 654system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor 655system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy 656system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy |
| 656system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 657system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 657system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 658system.cpu.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id | 658system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 659system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 660system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # Occupied blocks per task id |
| 659system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 661system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 660system.cpu.icache.tags.tag_accesses 22176055 # Number of tag accesses 661system.cpu.icache.tags.data_accesses 22176055 # Number of data accesses 662system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 663system.cpu.icache.ReadReq_hits::cpu.inst 19219701 # number of ReadReq hits 664system.cpu.icache.ReadReq_hits::total 19219701 # number of ReadReq hits 665system.cpu.icache.demand_hits::cpu.inst 19219701 # number of demand (read+write) hits 666system.cpu.icache.demand_hits::total 19219701 # number of demand (read+write) hits 667system.cpu.icache.overall_hits::cpu.inst 19219701 # number of overall hits 668system.cpu.icache.overall_hits::total 19219701 # number of overall hits 669system.cpu.icache.ReadReq_misses::cpu.inst 1478177 # number of ReadReq misses 670system.cpu.icache.ReadReq_misses::total 1478177 # number of ReadReq misses 671system.cpu.icache.demand_misses::cpu.inst 1478177 # number of demand (read+write) misses 672system.cpu.icache.demand_misses::total 1478177 # number of demand (read+write) misses 673system.cpu.icache.overall_misses::cpu.inst 1478177 # number of overall misses 674system.cpu.icache.overall_misses::total 1478177 # number of overall misses 675system.cpu.icache.ReadReq_miss_latency::cpu.inst 21231255000 # number of ReadReq miss cycles 676system.cpu.icache.ReadReq_miss_latency::total 21231255000 # number of ReadReq miss cycles 677system.cpu.icache.demand_miss_latency::cpu.inst 21231255000 # number of demand (read+write) miss cycles 678system.cpu.icache.demand_miss_latency::total 21231255000 # number of demand (read+write) miss cycles 679system.cpu.icache.overall_miss_latency::cpu.inst 21231255000 # number of overall miss cycles 680system.cpu.icache.overall_miss_latency::total 21231255000 # number of overall miss cycles 681system.cpu.icache.ReadReq_accesses::cpu.inst 20697878 # number of ReadReq accesses(hits+misses) 682system.cpu.icache.ReadReq_accesses::total 20697878 # number of ReadReq accesses(hits+misses) 683system.cpu.icache.demand_accesses::cpu.inst 20697878 # number of demand (read+write) accesses 684system.cpu.icache.demand_accesses::total 20697878 # number of demand (read+write) accesses 685system.cpu.icache.overall_accesses::cpu.inst 20697878 # number of overall (read+write) accesses 686system.cpu.icache.overall_accesses::total 20697878 # number of overall (read+write) accesses 687system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071417 # miss rate for ReadReq accesses 688system.cpu.icache.ReadReq_miss_rate::total 0.071417 # miss rate for ReadReq accesses 689system.cpu.icache.demand_miss_rate::cpu.inst 0.071417 # miss rate for demand accesses 690system.cpu.icache.demand_miss_rate::total 0.071417 # miss rate for demand accesses 691system.cpu.icache.overall_miss_rate::cpu.inst 0.071417 # miss rate for overall accesses 692system.cpu.icache.overall_miss_rate::total 0.071417 # miss rate for overall accesses 693system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14363.134455 # average ReadReq miss latency 694system.cpu.icache.ReadReq_avg_miss_latency::total 14363.134455 # average ReadReq miss latency 695system.cpu.icache.demand_avg_miss_latency::cpu.inst 14363.134455 # average overall miss latency 696system.cpu.icache.demand_avg_miss_latency::total 14363.134455 # average overall miss latency 697system.cpu.icache.overall_avg_miss_latency::cpu.inst 14363.134455 # average overall miss latency 698system.cpu.icache.overall_avg_miss_latency::total 14363.134455 # average overall miss latency | 662system.cpu.icache.tags.tag_accesses 22162507 # Number of tag accesses 663system.cpu.icache.tags.data_accesses 22162507 # Number of data accesses 664system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 665system.cpu.icache.ReadReq_hits::cpu.inst 19208655 # number of ReadReq hits 666system.cpu.icache.ReadReq_hits::total 19208655 # number of ReadReq hits 667system.cpu.icache.demand_hits::cpu.inst 19208655 # number of demand (read+write) hits 668system.cpu.icache.demand_hits::total 19208655 # number of demand (read+write) hits 669system.cpu.icache.overall_hits::cpu.inst 19208655 # number of overall hits 670system.cpu.icache.overall_hits::total 19208655 # number of overall hits 671system.cpu.icache.ReadReq_misses::cpu.inst 1476926 # number of ReadReq misses 672system.cpu.icache.ReadReq_misses::total 1476926 # number of ReadReq misses 673system.cpu.icache.demand_misses::cpu.inst 1476926 # number of demand (read+write) misses 674system.cpu.icache.demand_misses::total 1476926 # number of demand (read+write) misses 675system.cpu.icache.overall_misses::cpu.inst 1476926 # number of overall misses 676system.cpu.icache.overall_misses::total 1476926 # number of overall misses 677system.cpu.icache.ReadReq_miss_latency::cpu.inst 20401531500 # number of ReadReq miss cycles 678system.cpu.icache.ReadReq_miss_latency::total 20401531500 # number of ReadReq miss cycles 679system.cpu.icache.demand_miss_latency::cpu.inst 20401531500 # number of demand (read+write) miss cycles 680system.cpu.icache.demand_miss_latency::total 20401531500 # number of demand (read+write) miss cycles 681system.cpu.icache.overall_miss_latency::cpu.inst 20401531500 # number of overall miss cycles 682system.cpu.icache.overall_miss_latency::total 20401531500 # number of overall miss cycles 683system.cpu.icache.ReadReq_accesses::cpu.inst 20685581 # number of ReadReq accesses(hits+misses) 684system.cpu.icache.ReadReq_accesses::total 20685581 # number of ReadReq accesses(hits+misses) 685system.cpu.icache.demand_accesses::cpu.inst 20685581 # number of demand (read+write) accesses 686system.cpu.icache.demand_accesses::total 20685581 # number of demand (read+write) accesses 687system.cpu.icache.overall_accesses::cpu.inst 20685581 # number of overall (read+write) accesses 688system.cpu.icache.overall_accesses::total 20685581 # number of overall (read+write) accesses 689system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071399 # miss rate for ReadReq accesses 690system.cpu.icache.ReadReq_miss_rate::total 0.071399 # miss rate for ReadReq accesses 691system.cpu.icache.demand_miss_rate::cpu.inst 0.071399 # miss rate for demand accesses 692system.cpu.icache.demand_miss_rate::total 0.071399 # miss rate for demand accesses 693system.cpu.icache.overall_miss_rate::cpu.inst 0.071399 # miss rate for overall accesses 694system.cpu.icache.overall_miss_rate::total 0.071399 # miss rate for overall accesses 695system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13813.509614 # average ReadReq miss latency 696system.cpu.icache.ReadReq_avg_miss_latency::total 13813.509614 # average ReadReq miss latency 697system.cpu.icache.demand_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency 698system.cpu.icache.demand_avg_miss_latency::total 13813.509614 # average overall miss latency 699system.cpu.icache.overall_avg_miss_latency::cpu.inst 13813.509614 # average overall miss latency 700system.cpu.icache.overall_avg_miss_latency::total 13813.509614 # average overall miss latency |
| 699system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 700system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 702system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 703system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 704system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 701system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 702system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 703system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 704system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 705system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 706system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 705system.cpu.icache.writebacks::writebacks 1477492 # number of writebacks 706system.cpu.icache.writebacks::total 1477492 # number of writebacks 707system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1478177 # number of ReadReq MSHR misses 708system.cpu.icache.ReadReq_mshr_misses::total 1478177 # number of ReadReq MSHR misses 709system.cpu.icache.demand_mshr_misses::cpu.inst 1478177 # number of demand (read+write) MSHR misses 710system.cpu.icache.demand_mshr_misses::total 1478177 # number of demand (read+write) MSHR misses 711system.cpu.icache.overall_mshr_misses::cpu.inst 1478177 # number of overall MSHR misses 712system.cpu.icache.overall_mshr_misses::total 1478177 # number of overall MSHR misses 713system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19753078000 # number of ReadReq MSHR miss cycles 714system.cpu.icache.ReadReq_mshr_miss_latency::total 19753078000 # number of ReadReq MSHR miss cycles 715system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19753078000 # number of demand (read+write) MSHR miss cycles 716system.cpu.icache.demand_mshr_miss_latency::total 19753078000 # number of demand (read+write) MSHR miss cycles 717system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19753078000 # number of overall MSHR miss cycles 718system.cpu.icache.overall_mshr_miss_latency::total 19753078000 # number of overall MSHR miss cycles 719system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071417 # mshr miss rate for ReadReq accesses 721system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for demand accesses 722system.cpu.icache.demand_mshr_miss_rate::total 0.071417 # mshr miss rate for demand accesses 723system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071417 # mshr miss rate for overall accesses 724system.cpu.icache.overall_mshr_miss_rate::total 0.071417 # mshr miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13363.134455 # average ReadReq mshr miss latency 726system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13363.134455 # average ReadReq mshr miss latency 727system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13363.134455 # average overall mshr miss latency 728system.cpu.icache.demand_avg_mshr_miss_latency::total 13363.134455 # average overall mshr miss latency 729system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13363.134455 # average overall mshr miss latency 730system.cpu.icache.overall_avg_mshr_miss_latency::total 13363.134455 # average overall mshr miss latency 731system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 732system.cpu.l2cache.tags.replacements 339587 # number of replacements 733system.cpu.l2cache.tags.tagsinuse 65260.798092 # Cycle average of tags in use 734system.cpu.l2cache.tags.total_refs 5032980 # Total number of references to valid blocks. 735system.cpu.l2cache.tags.sampled_refs 404749 # Sample count of references to valid blocks. 736system.cpu.l2cache.tags.avg_refs 12.434818 # Average number of references to valid blocks. 737system.cpu.l2cache.tags.warmup_cycle 9689078000 # Cycle when the warmup percentage was hit. 738system.cpu.l2cache.tags.occ_blocks::writebacks 54026.178970 # Average occupied blocks per requestor 739system.cpu.l2cache.tags.occ_blocks::cpu.inst 5735.607676 # Average occupied blocks per requestor 740system.cpu.l2cache.tags.occ_blocks::cpu.data 5499.011446 # Average occupied blocks per requestor 741system.cpu.l2cache.tags.occ_percent::writebacks 0.824374 # Average percentage of cache occupancy 742system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087518 # Average percentage of cache occupancy 743system.cpu.l2cache.tags.occ_percent::cpu.data 0.083908 # Average percentage of cache occupancy 744system.cpu.l2cache.tags.occ_percent::total 0.995801 # Average percentage of cache occupancy 745system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 746system.cpu.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 747system.cpu.l2cache.tags.age_task_id_blocks_1024::1 888 # Occupied blocks per task id 748system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5593 # Occupied blocks per task id 749system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2924 # Occupied blocks per task id 750system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id 751system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 752system.cpu.l2cache.tags.tag_accesses 46662747 # Number of tag accesses 753system.cpu.l2cache.tags.data_accesses 46662747 # Number of data accesses 754system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 755system.cpu.l2cache.WritebackDirty_hits::writebacks 838068 # number of WritebackDirty hits 756system.cpu.l2cache.WritebackDirty_hits::total 838068 # number of WritebackDirty hits 757system.cpu.l2cache.WritebackClean_hits::writebacks 1476917 # number of WritebackClean hits 758system.cpu.l2cache.WritebackClean_hits::total 1476917 # number of WritebackClean hits 759system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 760system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 761system.cpu.l2cache.ReadExReq_hits::cpu.data 187586 # number of ReadExReq hits 762system.cpu.l2cache.ReadExReq_hits::total 187586 # number of ReadExReq hits 763system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461767 # number of ReadCleanReq hits 764system.cpu.l2cache.ReadCleanReq_hits::total 1461767 # number of ReadCleanReq hits 765system.cpu.l2cache.ReadSharedReq_hits::cpu.data 819079 # number of ReadSharedReq hits 766system.cpu.l2cache.ReadSharedReq_hits::total 819079 # number of ReadSharedReq hits 767system.cpu.l2cache.demand_hits::cpu.inst 1461767 # number of demand (read+write) hits 768system.cpu.l2cache.demand_hits::cpu.data 1006665 # number of demand (read+write) hits 769system.cpu.l2cache.demand_hits::total 2468432 # number of demand (read+write) hits 770system.cpu.l2cache.overall_hits::cpu.inst 1461767 # number of overall hits 771system.cpu.l2cache.overall_hits::cpu.data 1006665 # number of overall hits 772system.cpu.l2cache.overall_hits::total 2468432 # number of overall hits 773system.cpu.l2cache.UpgradeReq_misses::cpu.data 15 # number of UpgradeReq misses 774system.cpu.l2cache.UpgradeReq_misses::total 15 # number of UpgradeReq misses 775system.cpu.l2cache.ReadExReq_misses::cpu.data 116651 # number of ReadExReq misses 776system.cpu.l2cache.ReadExReq_misses::total 116651 # number of ReadExReq misses 777system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16355 # number of ReadCleanReq misses 778system.cpu.l2cache.ReadCleanReq_misses::total 16355 # number of ReadCleanReq misses 779system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272198 # number of ReadSharedReq misses 780system.cpu.l2cache.ReadSharedReq_misses::total 272198 # number of ReadSharedReq misses 781system.cpu.l2cache.demand_misses::cpu.inst 16355 # number of demand (read+write) misses | 707system.cpu.icache.writebacks::writebacks 1476241 # number of writebacks 708system.cpu.icache.writebacks::total 1476241 # number of writebacks 709system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1476926 # number of ReadReq MSHR misses 710system.cpu.icache.ReadReq_mshr_misses::total 1476926 # number of ReadReq MSHR misses 711system.cpu.icache.demand_mshr_misses::cpu.inst 1476926 # number of demand (read+write) MSHR misses 712system.cpu.icache.demand_mshr_misses::total 1476926 # number of demand (read+write) MSHR misses 713system.cpu.icache.overall_mshr_misses::cpu.inst 1476926 # number of overall MSHR misses 714system.cpu.icache.overall_mshr_misses::total 1476926 # number of overall MSHR misses 715system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18924605500 # number of ReadReq MSHR miss cycles 716system.cpu.icache.ReadReq_mshr_miss_latency::total 18924605500 # number of ReadReq MSHR miss cycles 717system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18924605500 # number of demand (read+write) MSHR miss cycles 718system.cpu.icache.demand_mshr_miss_latency::total 18924605500 # number of demand (read+write) MSHR miss cycles 719system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18924605500 # number of overall MSHR miss cycles 720system.cpu.icache.overall_mshr_miss_latency::total 18924605500 # number of overall MSHR miss cycles 721system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for ReadReq accesses 722system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071399 # mshr miss rate for ReadReq accesses 723system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for demand accesses 724system.cpu.icache.demand_mshr_miss_rate::total 0.071399 # mshr miss rate for demand accesses 725system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071399 # mshr miss rate for overall accesses 726system.cpu.icache.overall_mshr_miss_rate::total 0.071399 # mshr miss rate for overall accesses 727system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12813.509614 # average ReadReq mshr miss latency 728system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12813.509614 # average ReadReq mshr miss latency 729system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency 730system.cpu.icache.demand_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency 731system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12813.509614 # average overall mshr miss latency 732system.cpu.icache.overall_avg_mshr_miss_latency::total 12813.509614 # average overall mshr miss latency 733system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 734system.cpu.l2cache.tags.replacements 339622 # number of replacements 735system.cpu.l2cache.tags.tagsinuse 65416.328180 # Cycle average of tags in use 736system.cpu.l2cache.tags.total_refs 5334629 # Total number of references to valid blocks. 737system.cpu.l2cache.tags.sampled_refs 405144 # Sample count of references to valid blocks. 738system.cpu.l2cache.tags.avg_refs 13.167242 # Average number of references to valid blocks. 739system.cpu.l2cache.tags.warmup_cycle 6356009000 # Cycle when the warmup percentage was hit. 740system.cpu.l2cache.tags.occ_blocks::writebacks 267.504634 # Average occupied blocks per requestor 741system.cpu.l2cache.tags.occ_blocks::cpu.inst 5791.332200 # Average occupied blocks per requestor 742system.cpu.l2cache.tags.occ_blocks::cpu.data 59357.491346 # Average occupied blocks per requestor 743system.cpu.l2cache.tags.occ_percent::writebacks 0.004082 # Average percentage of cache occupancy 744system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088369 # Average percentage of cache occupancy 745system.cpu.l2cache.tags.occ_percent::cpu.data 0.905723 # Average percentage of cache occupancy 746system.cpu.l2cache.tags.occ_percent::total 0.998174 # Average percentage of cache occupancy 747system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 748system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 749system.cpu.l2cache.tags.age_task_id_blocks_1024::1 631 # Occupied blocks per task id 750system.cpu.l2cache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id 751system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5153 # Occupied blocks per task id 752system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59330 # Occupied blocks per task id 753system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 754system.cpu.l2cache.tags.tag_accesses 46327377 # Number of tag accesses 755system.cpu.l2cache.tags.data_accesses 46327377 # Number of data accesses 756system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 757system.cpu.l2cache.WritebackDirty_hits::writebacks 837697 # number of WritebackDirty hits 758system.cpu.l2cache.WritebackDirty_hits::total 837697 # number of WritebackDirty hits 759system.cpu.l2cache.WritebackClean_hits::writebacks 1475656 # number of WritebackClean hits 760system.cpu.l2cache.WritebackClean_hits::total 1475656 # number of WritebackClean hits 761system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits 762system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits 763system.cpu.l2cache.ReadExReq_hits::cpu.data 187300 # number of ReadExReq hits 764system.cpu.l2cache.ReadExReq_hits::total 187300 # number of ReadExReq hits 765system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1460502 # number of ReadCleanReq hits 766system.cpu.l2cache.ReadCleanReq_hits::total 1460502 # number of ReadCleanReq hits 767system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818651 # number of ReadSharedReq hits 768system.cpu.l2cache.ReadSharedReq_hits::total 818651 # number of ReadSharedReq hits 769system.cpu.l2cache.demand_hits::cpu.inst 1460502 # number of demand (read+write) hits 770system.cpu.l2cache.demand_hits::cpu.data 1005951 # number of demand (read+write) hits 771system.cpu.l2cache.demand_hits::total 2466453 # number of demand (read+write) hits 772system.cpu.l2cache.overall_hits::cpu.inst 1460502 # number of overall hits 773system.cpu.l2cache.overall_hits::cpu.data 1005951 # number of overall hits 774system.cpu.l2cache.overall_hits::total 2466453 # number of overall hits 775system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 776system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 777system.cpu.l2cache.ReadExReq_misses::cpu.data 116630 # number of ReadExReq misses 778system.cpu.l2cache.ReadExReq_misses::total 116630 # number of ReadExReq misses 779system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses 780system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses 781system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272219 # number of ReadSharedReq misses 782system.cpu.l2cache.ReadSharedReq_misses::total 272219 # number of ReadSharedReq misses 783system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses |
| 782system.cpu.l2cache.demand_misses::cpu.data 388849 # number of demand (read+write) misses | 784system.cpu.l2cache.demand_misses::cpu.data 388849 # number of demand (read+write) misses |
| 783system.cpu.l2cache.demand_misses::total 405204 # number of demand (read+write) misses 784system.cpu.l2cache.overall_misses::cpu.inst 16355 # number of overall misses | 785system.cpu.l2cache.demand_misses::total 405218 # number of demand (read+write) misses 786system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses |
| 785system.cpu.l2cache.overall_misses::cpu.data 388849 # number of overall misses | 787system.cpu.l2cache.overall_misses::cpu.data 388849 # number of overall misses |
| 786system.cpu.l2cache.overall_misses::total 405204 # number of overall misses 787system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 396500 # number of UpgradeReq miss cycles 788system.cpu.l2cache.UpgradeReq_miss_latency::total 396500 # number of UpgradeReq miss cycles 789system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14845341000 # number of ReadExReq miss cycles 790system.cpu.l2cache.ReadExReq_miss_latency::total 14845341000 # number of ReadExReq miss cycles 791system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2146863500 # number of ReadCleanReq miss cycles 792system.cpu.l2cache.ReadCleanReq_miss_latency::total 2146863500 # number of ReadCleanReq miss cycles 793system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33671183000 # number of ReadSharedReq miss cycles 794system.cpu.l2cache.ReadSharedReq_miss_latency::total 33671183000 # number of ReadSharedReq miss cycles 795system.cpu.l2cache.demand_miss_latency::cpu.inst 2146863500 # number of demand (read+write) miss cycles 796system.cpu.l2cache.demand_miss_latency::cpu.data 48516524000 # number of demand (read+write) miss cycles 797system.cpu.l2cache.demand_miss_latency::total 50663387500 # number of demand (read+write) miss cycles 798system.cpu.l2cache.overall_miss_latency::cpu.inst 2146863500 # number of overall miss cycles 799system.cpu.l2cache.overall_miss_latency::cpu.data 48516524000 # number of overall miss cycles 800system.cpu.l2cache.overall_miss_latency::total 50663387500 # number of overall miss cycles 801system.cpu.l2cache.WritebackDirty_accesses::writebacks 838068 # number of WritebackDirty accesses(hits+misses) 802system.cpu.l2cache.WritebackDirty_accesses::total 838068 # number of WritebackDirty accesses(hits+misses) 803system.cpu.l2cache.WritebackClean_accesses::writebacks 1476917 # number of WritebackClean accesses(hits+misses) 804system.cpu.l2cache.WritebackClean_accesses::total 1476917 # number of WritebackClean accesses(hits+misses) | 788system.cpu.l2cache.overall_misses::total 405218 # number of overall misses 789system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 249500 # number of UpgradeReq miss cycles 790system.cpu.l2cache.UpgradeReq_miss_latency::total 249500 # number of UpgradeReq miss cycles 791system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9053314500 # number of ReadExReq miss cycles 792system.cpu.l2cache.ReadExReq_miss_latency::total 9053314500 # number of ReadExReq miss cycles 793system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1334237500 # number of ReadCleanReq miss cycles 794system.cpu.l2cache.ReadCleanReq_miss_latency::total 1334237500 # number of ReadCleanReq miss cycles 795system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19962557500 # number of ReadSharedReq miss cycles 796system.cpu.l2cache.ReadSharedReq_miss_latency::total 19962557500 # number of ReadSharedReq miss cycles 797system.cpu.l2cache.demand_miss_latency::cpu.inst 1334237500 # number of demand (read+write) miss cycles 798system.cpu.l2cache.demand_miss_latency::cpu.data 29015872000 # number of demand (read+write) miss cycles 799system.cpu.l2cache.demand_miss_latency::total 30350109500 # number of demand (read+write) miss cycles 800system.cpu.l2cache.overall_miss_latency::cpu.inst 1334237500 # number of overall miss cycles 801system.cpu.l2cache.overall_miss_latency::cpu.data 29015872000 # number of overall miss cycles 802system.cpu.l2cache.overall_miss_latency::total 30350109500 # number of overall miss cycles 803system.cpu.l2cache.WritebackDirty_accesses::writebacks 837697 # number of WritebackDirty accesses(hits+misses) 804system.cpu.l2cache.WritebackDirty_accesses::total 837697 # number of WritebackDirty accesses(hits+misses) 805system.cpu.l2cache.WritebackClean_accesses::writebacks 1475656 # number of WritebackClean accesses(hits+misses) 806system.cpu.l2cache.WritebackClean_accesses::total 1475656 # number of WritebackClean accesses(hits+misses) |
| 805system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) 806system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) | 807system.cpu.l2cache.UpgradeReq_accesses::cpu.data 20 # number of UpgradeReq accesses(hits+misses) 808system.cpu.l2cache.UpgradeReq_accesses::total 20 # number of UpgradeReq accesses(hits+misses) |
| 807system.cpu.l2cache.ReadExReq_accesses::cpu.data 304237 # number of ReadExReq accesses(hits+misses) 808system.cpu.l2cache.ReadExReq_accesses::total 304237 # number of ReadExReq accesses(hits+misses) 809system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1478122 # number of ReadCleanReq accesses(hits+misses) 810system.cpu.l2cache.ReadCleanReq_accesses::total 1478122 # number of ReadCleanReq accesses(hits+misses) 811system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091277 # number of ReadSharedReq accesses(hits+misses) 812system.cpu.l2cache.ReadSharedReq_accesses::total 1091277 # number of ReadSharedReq accesses(hits+misses) 813system.cpu.l2cache.demand_accesses::cpu.inst 1478122 # number of demand (read+write) accesses 814system.cpu.l2cache.demand_accesses::cpu.data 1395514 # number of demand (read+write) accesses 815system.cpu.l2cache.demand_accesses::total 2873636 # number of demand (read+write) accesses 816system.cpu.l2cache.overall_accesses::cpu.inst 1478122 # number of overall (read+write) accesses 817system.cpu.l2cache.overall_accesses::cpu.data 1395514 # number of overall (read+write) accesses 818system.cpu.l2cache.overall_accesses::total 2873636 # number of overall (read+write) accesses 819system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 820system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 821system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383421 # miss rate for ReadExReq accesses 822system.cpu.l2cache.ReadExReq_miss_rate::total 0.383421 # miss rate for ReadExReq accesses 823system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011065 # miss rate for ReadCleanReq accesses 824system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011065 # miss rate for ReadCleanReq accesses 825system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249431 # miss rate for ReadSharedReq accesses 826system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249431 # miss rate for ReadSharedReq accesses 827system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011065 # miss rate for demand accesses 828system.cpu.l2cache.demand_miss_rate::cpu.data 0.278642 # miss rate for demand accesses 829system.cpu.l2cache.demand_miss_rate::total 0.141007 # miss rate for demand accesses 830system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011065 # miss rate for overall accesses 831system.cpu.l2cache.overall_miss_rate::cpu.data 0.278642 # miss rate for overall accesses 832system.cpu.l2cache.overall_miss_rate::total 0.141007 # miss rate for overall accesses 833system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 26433.333333 # average UpgradeReq miss latency 834system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 26433.333333 # average UpgradeReq miss latency 835system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127262.869585 # average ReadExReq miss latency 836system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127262.869585 # average ReadExReq miss latency 837system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131266.493427 # average ReadCleanReq miss latency 838system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131266.493427 # average ReadCleanReq miss latency 839system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123701.066870 # average ReadSharedReq miss latency 840system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123701.066870 # average ReadSharedReq miss latency 841system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131266.493427 # average overall miss latency 842system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124769.573793 # average overall miss latency 843system.cpu.l2cache.demand_avg_miss_latency::total 125031.804967 # average overall miss latency 844system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131266.493427 # average overall miss latency 845system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124769.573793 # average overall miss latency 846system.cpu.l2cache.overall_avg_miss_latency::total 125031.804967 # average overall miss latency | 809system.cpu.l2cache.ReadExReq_accesses::cpu.data 303930 # number of ReadExReq accesses(hits+misses) 810system.cpu.l2cache.ReadExReq_accesses::total 303930 # number of ReadExReq accesses(hits+misses) 811system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1476871 # number of ReadCleanReq accesses(hits+misses) 812system.cpu.l2cache.ReadCleanReq_accesses::total 1476871 # number of ReadCleanReq accesses(hits+misses) 813system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090870 # number of ReadSharedReq accesses(hits+misses) 814system.cpu.l2cache.ReadSharedReq_accesses::total 1090870 # number of ReadSharedReq accesses(hits+misses) 815system.cpu.l2cache.demand_accesses::cpu.inst 1476871 # number of demand (read+write) accesses 816system.cpu.l2cache.demand_accesses::cpu.data 1394800 # number of demand (read+write) accesses 817system.cpu.l2cache.demand_accesses::total 2871671 # number of demand (read+write) accesses 818system.cpu.l2cache.overall_accesses::cpu.inst 1476871 # number of overall (read+write) accesses 819system.cpu.l2cache.overall_accesses::cpu.data 1394800 # number of overall (read+write) accesses 820system.cpu.l2cache.overall_accesses::total 2871671 # number of overall (read+write) accesses 821system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses 822system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses 823system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383740 # miss rate for ReadExReq accesses 824system.cpu.l2cache.ReadExReq_miss_rate::total 0.383740 # miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011084 # miss rate for ReadCleanReq accesses 826system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011084 # miss rate for ReadCleanReq accesses 827system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249543 # miss rate for ReadSharedReq accesses 828system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249543 # miss rate for ReadSharedReq accesses 829system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011084 # miss rate for demand accesses 830system.cpu.l2cache.demand_miss_rate::cpu.data 0.278785 # miss rate for demand accesses 831system.cpu.l2cache.demand_miss_rate::total 0.141109 # miss rate for demand accesses 832system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011084 # miss rate for overall accesses 833system.cpu.l2cache.overall_miss_rate::cpu.data 0.278785 # miss rate for overall accesses 834system.cpu.l2cache.overall_miss_rate::total 0.141109 # miss rate for overall accesses 835system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49900 # average UpgradeReq miss latency 836system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49900 # average UpgradeReq miss latency 837system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77624.234759 # average ReadExReq miss latency 838system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77624.234759 # average ReadExReq miss latency 839system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81510.018938 # average ReadCleanReq miss latency 840system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81510.018938 # average ReadCleanReq miss latency 841system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73332.711897 # average ReadSharedReq miss latency 842system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73332.711897 # average ReadSharedReq miss latency 843system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency 844system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency 845system.cpu.l2cache.demand_avg_miss_latency::total 74898.226387 # average overall miss latency 846system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81510.018938 # average overall miss latency 847system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74619.896155 # average overall miss latency 848system.cpu.l2cache.overall_avg_miss_latency::total 74898.226387 # average overall miss latency |
| 847system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 848system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 849system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 850system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 851system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 852system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 849system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 850system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 851system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 852system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 853system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 854system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 853system.cpu.l2cache.writebacks::writebacks 76665 # number of writebacks 854system.cpu.l2cache.writebacks::total 76665 # number of writebacks 855system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses 856system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses 857system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116651 # number of ReadExReq MSHR misses 858system.cpu.l2cache.ReadExReq_mshr_misses::total 116651 # number of ReadExReq MSHR misses 859system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16355 # number of ReadCleanReq MSHR misses 860system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16355 # number of ReadCleanReq MSHR misses 861system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272198 # number of ReadSharedReq MSHR misses 862system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272198 # number of ReadSharedReq MSHR misses 863system.cpu.l2cache.demand_mshr_misses::cpu.inst 16355 # number of demand (read+write) MSHR misses | 855system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks 856system.cpu.l2cache.writebacks::total 76715 # number of writebacks 857system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 858system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses 859system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116630 # number of ReadExReq MSHR misses 860system.cpu.l2cache.ReadExReq_mshr_misses::total 116630 # number of ReadExReq MSHR misses 861system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses 862system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses 863system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272219 # number of ReadSharedReq MSHR misses 864system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272219 # number of ReadSharedReq MSHR misses 865system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses |
| 864system.cpu.l2cache.demand_mshr_misses::cpu.data 388849 # number of demand (read+write) MSHR misses | 866system.cpu.l2cache.demand_mshr_misses::cpu.data 388849 # number of demand (read+write) MSHR misses |
| 865system.cpu.l2cache.demand_mshr_misses::total 405204 # number of demand (read+write) MSHR misses 866system.cpu.l2cache.overall_mshr_misses::cpu.inst 16355 # number of overall MSHR misses | 867system.cpu.l2cache.demand_mshr_misses::total 405218 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses |
| 867system.cpu.l2cache.overall_mshr_misses::cpu.data 388849 # number of overall MSHR misses | 869system.cpu.l2cache.overall_mshr_misses::cpu.data 388849 # number of overall MSHR misses |
| 868system.cpu.l2cache.overall_mshr_misses::total 405204 # number of overall MSHR misses | 870system.cpu.l2cache.overall_mshr_misses::total 405218 # number of overall MSHR misses |
| 869system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 870system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 871system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 872system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 871system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable 872system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable 873system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses 874system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses 875system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1032500 # number of UpgradeReq MSHR miss cycles 876system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1032500 # number of UpgradeReq MSHR miss cycles 877system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13678831000 # number of ReadExReq MSHR miss cycles 878system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13678831000 # number of ReadExReq MSHR miss cycles 879system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1983313500 # number of ReadCleanReq MSHR miss cycles 880system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1983313500 # number of ReadCleanReq MSHR miss cycles 881system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30952316500 # number of ReadSharedReq MSHR miss cycles 882system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30952316500 # number of ReadSharedReq MSHR miss cycles 883system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1983313500 # number of demand (read+write) MSHR miss cycles 884system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631147500 # number of demand (read+write) MSHR miss cycles 885system.cpu.l2cache.demand_mshr_miss_latency::total 46614461000 # number of demand (read+write) MSHR miss cycles 886system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1983313500 # number of overall MSHR miss cycles 887system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631147500 # number of overall MSHR miss cycles 888system.cpu.l2cache.overall_mshr_miss_latency::total 46614461000 # number of overall MSHR miss cycles 889system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440649500 # number of ReadReq MSHR uncacheable cycles 890system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440649500 # number of ReadReq MSHR uncacheable cycles 891system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440649500 # number of overall MSHR uncacheable cycles 892system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440649500 # number of overall MSHR uncacheable cycles 893system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses 894system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses 895system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383421 # mshr miss rate for ReadExReq accesses 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383421 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for ReadCleanReq accesses 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011065 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249431 # mshr miss rate for ReadSharedReq accesses 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249431 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for demand accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278642 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::total 0.141007 # mshr miss rate for demand accesses 904system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011065 # mshr miss rate for overall accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278642 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::total 0.141007 # mshr miss rate for overall accesses 907system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68833.333333 # average UpgradeReq mshr miss latency 908system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68833.333333 # average UpgradeReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117262.869585 # average ReadExReq mshr miss latency 910system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117262.869585 # average ReadExReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121266.493427 # average ReadCleanReq mshr miss latency 912system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121266.493427 # average ReadCleanReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113712.505235 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113712.505235 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121266.493427 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114777.580758 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115039.488751 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121266.493427 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114777.580758 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115039.488751 # average overall mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207885.930736 # average ReadReq mshr uncacheable latency 922system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207885.930736 # average ReadReq mshr uncacheable latency 923system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87022.017517 # average overall mshr uncacheable latency 924system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87022.017517 # average overall mshr uncacheable latency 925system.cpu.toL2Bus.snoop_filter.tot_requests 5746179 # Total number of requests made to the snoop filter. 926system.cpu.toL2Bus.snoop_filter.hit_single_requests 2872664 # Number of requests hitting in the snoop filter with a single holder of the requested data. 927system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1960 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 928system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. 929system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 873system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable 874system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable 875system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses 876system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses 877system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 199500 # number of UpgradeReq MSHR miss cycles 878system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 199500 # number of UpgradeReq MSHR miss cycles 879system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7887014500 # number of ReadExReq MSHR miss cycles 880system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7887014500 # number of ReadExReq MSHR miss cycles 881system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1170547500 # number of ReadCleanReq MSHR miss cycles 882system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1170547500 # number of ReadCleanReq MSHR miss cycles 883system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17243377000 # number of ReadSharedReq MSHR miss cycles 884system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17243377000 # number of ReadSharedReq MSHR miss cycles 885system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170547500 # number of demand (read+write) MSHR miss cycles 886system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25130391500 # number of demand (read+write) MSHR miss cycles 887system.cpu.l2cache.demand_mshr_miss_latency::total 26300939000 # number of demand (read+write) MSHR miss cycles 888system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170547500 # number of overall MSHR miss cycles 889system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25130391500 # number of overall MSHR miss cycles 890system.cpu.l2cache.overall_mshr_miss_latency::total 26300939000 # number of overall MSHR miss cycles 891system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles 892system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles 893system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles 894system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles 895system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for UpgradeReq accesses 896system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for UpgradeReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383740 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383740 # mshr miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011084 # mshr miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249543 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249543 # mshr miss rate for ReadSharedReq accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.141109 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.141109 # mshr miss rate for overall accesses 909system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39900 # average UpgradeReq mshr miss latency 910system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39900 # average UpgradeReq mshr miss latency 911system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759 # average ReadExReq mshr miss latency 912system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759 # average ReadExReq mshr miss latency 913system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency 914system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency 915system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency 916system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency 919system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency 923system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency 924system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency 925system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency 926system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency 927system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter. 928system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data. 929system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 930system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. 931system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 930system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 932system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 931system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 933system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 932system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 934system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 933system.cpu.toL2Bus.trans_dist::ReadResp 2576516 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::WriteReq 9625 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::WriteResp 9625 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::WritebackDirty 956247 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::WritebackClean 1477492 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::CleanEvict 820003 # Transaction distribution | 935system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution |
| 939system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution | 941system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution |
| 941system.cpu.toL2Bus.trans_dist::ReadExReq 304237 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadExResp 304237 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::ReadCleanReq 1478177 # Transaction distribution 944system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091450 # Transaction distribution 945system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution 946system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 947system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433791 # Packet count per connected master and slave (bytes) 948system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) 949system.cpu.toL2Bus.pkt_count::total 8653101 # Packet count per connected master and slave (bytes) 950system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189159296 # Cumulative packet size per connected master and slave (bytes) 951system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143002060 # Cumulative packet size per connected master and slave (bytes) 952system.cpu.toL2Bus.pkt_size::total 332161356 # Cumulative packet size per connected master and slave (bytes) 953system.cpu.toL2Bus.snoops 423210 # Total snoops (count) 954system.cpu.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) 955system.cpu.toL2Bus.snoop_fanout::samples 3313265 # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::mean 0.001022 # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::stdev 0.031947 # Request fanout histogram | 943system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution 944system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution 945system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution 946system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution 947system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution 949system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes) 950system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes) 951system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes) 952system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes) 953system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes) 954system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes) 955system.cpu.toL2Bus.snoops 340234 # Total snoops (count) 956system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes) 957system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram |
| 958system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 960system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 959system.cpu.toL2Bus.snoop_fanout::0 3309880 99.90% 99.90% # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::1 3385 0.10% 100.00% # Request fanout histogram | 961system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram |
| 961system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 963system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 963system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 965system.cpu.toL2Bus.snoop_fanout::total 3313265 # Request fanout histogram 966system.cpu.toL2Bus.reqLayer0.occupancy 5201739500 # Layer occupancy (ticks) | 967system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram 968system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks) |
| 967system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 968system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 969system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 969system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 970system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) 971system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 970system.cpu.toL2Bus.respLayer0.occupancy 2217424681 # Layer occupancy (ticks) | 972system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks) |
| 971system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 973system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 972system.cpu.toL2Bus.respLayer1.occupancy 2105003991 # Layer occupancy (ticks) | 974system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks) |
| 973system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 974system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 975system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 976system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 977system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 978system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 979system.disk0.dma_write_txs 395 # Number of DMA write transactions. 980system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 981system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 982system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 983system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 984system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 985system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 975system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 976system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 977system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 978system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 979system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 980system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 981system.disk0.dma_write_txs 395 # Number of DMA write transactions. 982system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 983system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 984system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 985system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 986system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 987system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 986system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 988system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 987system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 988system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 989system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 990system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 989system.iobus.trans_dist::WriteReq 51177 # Transaction distribution 990system.iobus.trans_dist::WriteResp 51177 # Transaction distribution 991system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5106 # Packet count per connected master and slave (bytes) | 991system.iobus.trans_dist::WriteReq 51173 # Transaction distribution 992system.iobus.trans_dist::WriteResp 51173 # Transaction distribution 993system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes) |
| 992system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 996system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 997system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 999system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) | 994system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 996system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 997system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 999system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1001system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| 1000system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) | 1002system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes) |
| 1001system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1002system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 1003system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 1003system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20424 # Cumulative packet size per connected master and slave (bytes) | 1005system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes) |
| 1005system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1006system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1007system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1008system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1009system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1010system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1011system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1012system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) | 1007system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1008system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1009system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1010system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1011system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1012system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1013system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1014system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| 1013system.iobus.pkt_size_system.bridge.master::total 44364 # Cumulative packet size per connected master and slave (bytes) | 1015system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes) |
| 1014system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1015system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 1016system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1017system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 1016system.iobus.pkt_size::total 2705972 # Cumulative packet size per connected master and slave (bytes) 1017system.iobus.reqLayer0.occupancy 5417500 # Layer occupancy (ticks) | 1018system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes) 1019system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks) |
| 1018system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1020system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1019system.iobus.reqLayer1.occupancy 799000 # Layer occupancy (ticks) | 1021system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks) |
| 1020system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1022system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1021system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) | 1023system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) |
| 1022system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1023system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1024system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1025system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) 1026system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1024system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1025system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) 1026system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1027system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) 1028system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1027system.iobus.reqLayer23.occupancy 15625500 # Layer occupancy (ticks) | 1029system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks) |
| 1028system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1029system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) 1030system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1030system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1031system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) 1032system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1031system.iobus.reqLayer25.occupancy 6004000 # Layer occupancy (ticks) | 1033system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks) |
| 1032system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1033system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1034system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1034system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1035system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) 1036system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1035system.iobus.reqLayer27.occupancy 215719668 # Layer occupancy (ticks) | 1037system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks) |
| 1036system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) | 1038system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1037system.iobus.respLayer0.occupancy 23485000 # Layer occupancy (ticks) | 1039system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks) |
| 1038system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1039system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1040system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1040system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1041system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1042system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1041system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 1043system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 1042system.iocache.tags.replacements 41685 # number of replacements | 1044system.iocache.tags.replacements 41685 # number of replacements |
| 1043system.iocache.tags.tagsinuse 1.297488 # Cycle average of tags in use | 1045system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use |
| 1044system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1045system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1046system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1046system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1047system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1048system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1047system.iocache.tags.warmup_cycle 1750571994000 # Cycle when the warmup percentage was hit. 1048system.iocache.tags.occ_blocks::tsunami.ide 1.297488 # Average occupied blocks per requestor 1049system.iocache.tags.occ_percent::tsunami.ide 0.081093 # Average percentage of cache occupancy 1050system.iocache.tags.occ_percent::total 0.081093 # Average percentage of cache occupancy | 1049system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit. 1050system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor 1051system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy 1052system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy |
| 1051system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1052system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1053system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1054system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1055system.iocache.tags.data_accesses 375525 # Number of data accesses | 1053system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1054system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1055system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1056system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1057system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1056system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 1058system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 1057system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1058system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1059system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1060system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1061system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1062system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1063system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1064system.iocache.overall_misses::total 41725 # number of overall misses | 1059system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1060system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1061system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1062system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1063system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1064system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1065system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1066system.iocache.overall_misses::total 41725 # number of overall misses |
| 1065system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles 1066system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles 1067system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244162285 # number of WriteLineReq miss cycles 1068system.iocache.WriteLineReq_miss_latency::total 5244162285 # number of WriteLineReq miss cycles 1069system.iocache.demand_miss_latency::tsunami.ide 5266079668 # number of demand (read+write) miss cycles 1070system.iocache.demand_miss_latency::total 5266079668 # number of demand (read+write) miss cycles 1071system.iocache.overall_miss_latency::tsunami.ide 5266079668 # number of overall miss cycles 1072system.iocache.overall_miss_latency::total 5266079668 # number of overall miss cycles | 1067system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles 1068system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles 1069system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles 1070system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles 1071system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles 1072system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles 1073system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles 1074system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles |
| 1073system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1074system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1075system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1076system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1077system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1078system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1079system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1080system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1081system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1082system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1083system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1084system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1085system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1086system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1087system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1088system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1075system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1076system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1077system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1078system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1079system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1080system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1081system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1082system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1083system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1084system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1085system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1086system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1087system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1088system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1089system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1090system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1089system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency 1090system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency 1091system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101 # average WriteLineReq miss latency 1092system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101 # average WriteLineReq miss latency 1093system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency 1094system.iocache.demand_avg_miss_latency::total 126209.219125 # average overall miss latency 1095system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency 1096system.iocache.overall_avg_miss_latency::total 126209.219125 # average overall miss latency 1097system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1091system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency 1092system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency 1093system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency 1094system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency 1095system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency 1096system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency 1097system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency 1098system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency 1099system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked |
| 1098system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1100system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1099system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1101system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 1100system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1102system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1101system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1103system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked |
| 1102system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1103system.iocache.writebacks::writebacks 41512 # number of writebacks 1104system.iocache.writebacks::total 41512 # number of writebacks 1105system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1106system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1107system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1108system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1109system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1110system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1111system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1112system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 1104system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1105system.iocache.writebacks::writebacks 41512 # number of writebacks 1106system.iocache.writebacks::total 41512 # number of writebacks 1107system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1108system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1109system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1110system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1111system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1112system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1113system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1114system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1113system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles 1114system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles 1115system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3164763984 # number of WriteLineReq MSHR miss cycles 1116system.iocache.WriteLineReq_mshr_miss_latency::total 3164763984 # number of WriteLineReq MSHR miss cycles 1117system.iocache.demand_mshr_miss_latency::tsunami.ide 3178031367 # number of demand (read+write) MSHR miss cycles 1118system.iocache.demand_mshr_miss_latency::total 3178031367 # number of demand (read+write) MSHR miss cycles 1119system.iocache.overall_mshr_miss_latency::tsunami.ide 3178031367 # number of overall MSHR miss cycles 1120system.iocache.overall_mshr_miss_latency::total 3178031367 # number of overall MSHR miss cycles | 1115system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles 1116system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles 1117system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles 1118system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles 1119system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles 1120system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles 1121system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles 1122system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles |
| 1121system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1122system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1123system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1124system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1125system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1126system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1127system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1128system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1123system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1124system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1125system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1126system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1127system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1128system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1129system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1130system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1129system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency 1130system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency 1131system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776 # average WriteLineReq mshr miss latency 1132system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776 # average WriteLineReq mshr miss latency 1133system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency 1134system.iocache.demand_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency 1135system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency 1136system.iocache.overall_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency 1137system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 1131system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency 1132system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency 1133system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency 1134system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency 1135system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency 1136system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency 1137system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency 1138system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency 1139system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter. 1140system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1141system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1142system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1143system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1144system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1145system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 1138system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1146system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1139system.membus.trans_dist::ReadResp 295632 # Transaction distribution 1140system.membus.trans_dist::WriteReq 9625 # Transaction distribution 1141system.membus.trans_dist::WriteResp 9625 # Transaction distribution 1142system.membus.trans_dist::WritebackDirty 118177 # Transaction distribution 1143system.membus.trans_dist::CleanEvict 262256 # Transaction distribution 1144system.membus.trans_dist::UpgradeReq 167 # Transaction distribution | 1147system.membus.trans_dist::ReadResp 295668 # Transaction distribution 1148system.membus.trans_dist::WriteReq 9621 # Transaction distribution 1149system.membus.trans_dist::WriteResp 9621 # Transaction distribution 1150system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution 1151system.membus.trans_dist::CleanEvict 262241 # Transaction distribution 1152system.membus.trans_dist::UpgradeReq 137 # Transaction distribution |
| 1145system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1153system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1146system.membus.trans_dist::ReadExReq 116499 # Transaction distribution 1147system.membus.trans_dist::ReadExResp 116499 # Transaction distribution 1148system.membus.trans_dist::ReadSharedReq 288726 # Transaction distribution 1149system.membus.trans_dist::BadAddressError 24 # Transaction distribution | 1154system.membus.trans_dist::ReadExReq 116498 # Transaction distribution 1155system.membus.trans_dist::ReadExResp 116498 # Transaction distribution 1156system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution 1157system.membus.trans_dist::BadAddressError 23 # Transaction distribution |
| 1150system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1158system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1151system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) 1152system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148698 # Packet count per connected master and slave (bytes) 1153system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) 1154system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181856 # Packet count per connected master and slave (bytes) | 1159system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes) 1160system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes) 1161system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) 1162system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes) |
| 1155system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1156system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) | 1163system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1164system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) |
| 1157system.membus.pkt_count::total 1265281 # Packet count per connected master and slave (bytes) 1158system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44364 # Cumulative packet size per connected master and slave (bytes) 1159system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810880 # Cumulative packet size per connected master and slave (bytes) 1160system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855244 # Cumulative packet size per connected master and slave (bytes) | 1165system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes) 1166system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes) 1167system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes) 1168system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes) |
| 1161system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1162system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1169system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1170system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1163system.membus.pkt_size::total 33512972 # Cumulative packet size per connected master and slave (bytes) | 1171system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes) |
| 1164system.membus.snoops 433 # Total snoops (count) 1165system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) | 1172system.membus.snoops 433 # Total snoops (count) 1173system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) |
| 1166system.membus.snoop_fanout::samples 843934 # Request fanout histogram 1167system.membus.snoop_fanout::mean 1 # Request fanout histogram 1168system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1174system.membus.snoop_fanout::samples 463499 # Request fanout histogram 1175system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram 1176system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram |
| 1169system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1177system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1170system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1171system.membus.snoop_fanout::1 843934 100.00% 100.00% # Request fanout histogram | 1178system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram 1179system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram |
| 1172system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1173system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1180system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1181system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1174system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1182system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1175system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1183system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1176system.membus.snoop_fanout::total 843934 # Request fanout histogram 1177system.membus.reqLayer0.occupancy 30445500 # Layer occupancy (ticks) | 1184system.membus.snoop_fanout::total 463499 # Request fanout histogram 1185system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks) |
| 1178system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1186system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1179system.membus.reqLayer1.occupancy 1319244966 # Layer occupancy (ticks) | 1187system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks) |
| 1180system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1188system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1181system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) | 1189system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks) |
| 1182system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1190system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1183system.membus.respLayer1.occupancy 2159924750 # Layer occupancy (ticks) | 1191system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks) |
| 1184system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1185system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) 1186system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1192system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1193system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) 1194system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1187system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1188system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1189system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1190system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1191system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 1195system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1196system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1197system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1198system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1199system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 1192system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1193system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1194system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1195system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1196system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1197system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1198system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1199system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1215system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1216system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1217system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1218system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1219system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1220system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1221system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1222system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1200system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1201system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1202system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1203system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1204system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1205system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1206system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1207system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1223system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1224system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1225system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1226system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1227system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1228system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1229system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1230system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1223system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1226system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1227system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1228system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1229system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1230system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1231system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1232system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1237system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1238system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1239system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1240system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1241system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1242system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1243system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1244system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states 1245system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states | 1231system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1232system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1237system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1238system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1239system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1240system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1241system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1242system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1243system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1244system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1245system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1246system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1247system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1248system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1249system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1250system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1251system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1252system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states 1253system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states |
| 1246 1247---------- End Simulation Statistics ---------- | 1254 1255---------- End Simulation Statistics ---------- |