| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.907083 # Number of seconds simulated 4sim_ticks 1907083088000 # Number of ticks simulated 5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.907083 # Number of seconds simulated 4sim_ticks 1907083088000 # Number of ticks simulated 5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 20329 # Simulator instruction rate (inst/s) 8host_op_rate 20329 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 690572794 # Simulator tick rate (ticks/s) 10host_mem_usage 384580 # Number of bytes of host memory used 11host_seconds 2761.60 # Real time elapsed on the host | 7host_inst_rate 17729 # Simulator instruction rate (inst/s) 8host_op_rate 17729 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 602270723 # Simulator tick rate (ticks/s) 10host_mem_usage 432228 # Number of bytes of host memory used 11host_seconds 3166.49 # Real time elapsed on the host |
| 12sim_insts 56139550 # Number of instructions simulated 13sim_ops 56139550 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 56139550 # Number of instructions simulated 13sim_ops 56139550 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory --- 270 unchanged lines hidden (view full) --- 294system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ) 296system.physmem_1.averagePower 670.962459 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states 298system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 1045632 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 1045632 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7558144 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7558144 # Number of bytes written to this memory --- 270 unchanged lines hidden (view full) --- 295system.physmem_1.preBackEnergy 1084112170500 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 1279578204480 # Total energy per rank (pJ) 297system.physmem_1.averagePower 670.962459 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 1803261638750 # Time in different power states 299system.physmem_1.memoryStateTime::REF 63681540000 # Time in different power states 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 301system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 304system.bridge.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 302system.cpu.branchPred.lookups 15213605 # Number of BP lookups 303system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted 304system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect 305system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups 306system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits 307system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 308system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage 309system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target. --- 30 unchanged lines hidden (view full) --- 340system.cpu.itb.write_hits 0 # DTB write hits 341system.cpu.itb.write_misses 0 # DTB write misses 342system.cpu.itb.write_acv 0 # DTB write access violations 343system.cpu.itb.write_accesses 0 # DTB write accesses 344system.cpu.itb.data_hits 0 # DTB hits 345system.cpu.itb.data_misses 0 # DTB misses 346system.cpu.itb.data_acv 0 # DTB access violations 347system.cpu.itb.data_accesses 0 # DTB accesses | 305system.cpu.branchPred.lookups 15213605 # Number of BP lookups 306system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted 307system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect 308system.cpu.branchPred.BTBLookups 11946485 # Number of BTB lookups 309system.cpu.branchPred.BTBHits 4550663 # Number of BTB hits 310system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 311system.cpu.branchPred.BTBHitPct 38.092066 # BTB Hit Percentage 312system.cpu.branchPred.usedRAS 861069 # Number of times the RAS was used to get a target. --- 30 unchanged lines hidden (view full) --- 343system.cpu.itb.write_hits 0 # DTB write hits 344system.cpu.itb.write_misses 0 # DTB write misses 345system.cpu.itb.write_acv 0 # DTB write access violations 346system.cpu.itb.write_accesses 0 # DTB write accesses 347system.cpu.itb.data_hits 0 # DTB hits 348system.cpu.itb.data_misses 0 # DTB misses 349system.cpu.itb.data_acv 0 # DTB access violations 350system.cpu.itb.data_accesses 0 # DTB accesses |
| 351system.cpu.numPwrStateTransitions 12752 # Number of power state transitions 352system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::mean 281609048.541405 # Distribution of time spent in the clock gated state 354system.cpu.pwrStateClkGateDist::stdev 439540029.573258 # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::min_value 10500 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state 359system.cpu.pwrStateResidencyTicks::ON 111543794500 # Cumulative time (in ticks) in various power states 360system.cpu.pwrStateResidencyTicks::CLK_GATED 1795539293500 # Cumulative time (in ticks) in various power states |
|
| 348system.cpu.numCycles 223105667 # number of cpu cycles simulated 349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 351system.cpu.committedInsts 56139550 # Number of instructions committed 352system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed 353system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit 354system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching 355system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 116 unchanged lines hidden (view full) --- 472system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches 473system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches 474system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode 475system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode 476system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode 477system.cpu.kern.swap_context 4178 # number of times the context was actually changed 478system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked 479system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped | 361system.cpu.numCycles 223105667 # number of cpu cycles simulated 362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 364system.cpu.committedInsts 56139550 # Number of instructions committed 365system.cpu.committedOps 56139550 # Number of ops (including micro ops) committed 366system.cpu.discardedOps 2984225 # Number of ops (including micro ops) which were discarded before commit 367system.cpu.numFetchSuspends 5570 # Number of times Execute suspended instruction fetching 368system.cpu.quiesceCycles 3591060509 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 116 unchanged lines hidden (view full) --- 485system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches 486system.cpu.kern.mode_switch_good::total 0.392750 # fraction of useful protection mode switches 487system.cpu.kern.mode_ticks::kernel 38852804500 2.04% 2.04% # number of ticks spent at the given mode 488system.cpu.kern.mode_ticks::user 4558296500 0.24% 2.28% # number of ticks spent at the given mode 489system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # number of ticks spent at the given mode 490system.cpu.kern.swap_context 4178 # number of times the context was actually changed 491system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked 492system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped |
| 493system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 480system.cpu.dcache.tags.replacements 1394573 # number of replacements 481system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use 482system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks. 483system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks. 484system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks. 485system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. 486system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor 487system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy 488system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy 489system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 494system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses 495system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses | 494system.cpu.dcache.tags.replacements 1394573 # number of replacements 495system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use 496system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks. 497system.cpu.dcache.tags.sampled_refs 1395085 # Sample count of references to valid blocks. 498system.cpu.dcache.tags.avg_refs 9.912639 # Average number of references to valid blocks. 499system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. 500system.cpu.dcache.tags.occ_blocks::cpu.data 511.976747 # Average occupied blocks per requestor 501system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy 502system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy 503system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 504system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 505system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 506system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 507system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 508system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses 509system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses |
| 510system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 496system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits 497system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits 498system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits 499system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits 500system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits 501system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits 502system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits 503system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits --- 120 unchanged lines hidden (view full) --- 624system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 625system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 626system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 627system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 628system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency 629system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency 630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency 631system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency | 511system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits 512system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits 513system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits 514system.cpu.dcache.WriteReq_hits::total 5576818 # number of WriteReq hits 515system.cpu.dcache.LoadLockedReq_hits::cpu.data 183500 # number of LoadLockedReq hits 516system.cpu.dcache.LoadLockedReq_hits::total 183500 # number of LoadLockedReq hits 517system.cpu.dcache.StoreCondReq_hits::cpu.data 199049 # number of StoreCondReq hits 518system.cpu.dcache.StoreCondReq_hits::total 199049 # number of StoreCondReq hits --- 120 unchanged lines hidden (view full) --- 639system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 640system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 641system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 642system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 643system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency 644system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency 645system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency 646system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency |
| 647system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 632system.cpu.icache.tags.replacements 1471396 # number of replacements 633system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use 634system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. 635system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks. 636system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks. 637system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit. 638system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor 639system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy 640system.cpu.icache.tags.occ_percent::total 0.992398 # Average percentage of cache occupancy 641system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 642system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 643system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 644system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id 645system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 646system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses 647system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses | 648system.cpu.icache.tags.replacements 1471396 # number of replacements 649system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use 650system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. 651system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks. 652system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks. 653system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit. 654system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor 655system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy 656system.cpu.icache.tags.occ_percent::total 0.992398 # Average percentage of cache occupancy 657system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 658system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 659system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 660system.cpu.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id 661system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 662system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses 663system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses |
| 664system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 648system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits 649system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits 650system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits 651system.cpu.icache.demand_hits::total 19138985 # number of demand (read+write) hits 652system.cpu.icache.overall_hits::cpu.inst 19138985 # number of overall hits 653system.cpu.icache.overall_hits::total 19138985 # number of overall hits 654system.cpu.icache.ReadReq_misses::cpu.inst 1472080 # number of ReadReq misses 655system.cpu.icache.ReadReq_misses::total 1472080 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 708system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses 709system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency 711system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency 712system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 713system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency 714system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 715system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency | 665system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits 666system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits 667system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits 668system.cpu.icache.demand_hits::total 19138985 # number of demand (read+write) hits 669system.cpu.icache.overall_hits::cpu.inst 19138985 # number of overall hits 670system.cpu.icache.overall_hits::total 19138985 # number of overall hits 671system.cpu.icache.ReadReq_misses::cpu.inst 1472080 # number of ReadReq misses 672system.cpu.icache.ReadReq_misses::total 1472080 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 725system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses 726system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses 727system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency 728system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency 729system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 730system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency 731system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 732system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency |
| 733system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 716system.cpu.l2cache.tags.replacements 339491 # number of replacements 717system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use 718system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. 719system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks. 720system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks. 721system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit. 722system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor 723system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 730system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id 732system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5606 # Occupied blocks per task id 733system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2934 # Occupied blocks per task id 734system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 # Occupied blocks per task id 735system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 736system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses 737system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses | 734system.cpu.l2cache.tags.replacements 339491 # number of replacements 735system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use 736system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. 737system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks. 738system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks. 739system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit. 740system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor 741system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 748system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 749system.cpu.l2cache.tags.age_task_id_blocks_1024::1 883 # Occupied blocks per task id 750system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5606 # Occupied blocks per task id 751system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2934 # Occupied blocks per task id 752system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 # Occupied blocks per task id 753system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 754system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses 755system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses |
| 756system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 738system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits 739system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits 740system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits 741system.cpu.l2cache.WritebackClean_hits::total 1470820 # number of WritebackClean hits 742system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 743system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 744system.cpu.l2cache.ReadExReq_hits::cpu.data 187526 # number of ReadExReq hits 745system.cpu.l2cache.ReadExReq_hits::total 187526 # number of ReadExReq hits --- 160 unchanged lines hidden (view full) --- 906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency 907system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency 908system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. 909system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. 910system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 911system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. 912system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 913system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 757system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits 758system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits 759system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits 760system.cpu.l2cache.WritebackClean_hits::total 1470820 # number of WritebackClean hits 761system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 762system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 763system.cpu.l2cache.ReadExReq_hits::cpu.data 187526 # number of ReadExReq hits 764system.cpu.l2cache.ReadExReq_hits::total 187526 # number of ReadExReq hits --- 160 unchanged lines hidden (view full) --- 925system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency 926system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency 927system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. 928system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. 929system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 930system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. 931system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 932system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 933system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 914system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 915system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution 917system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 959system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 960system.disk0.dma_write_txs 395 # Number of DMA write transactions. 961system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 962system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 963system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 964system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 965system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 966system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 934system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::WritebackDirty 956097 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::WritebackClean 1471396 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::CleanEvict 819662 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 979system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 980system.disk0.dma_write_txs 395 # Number of DMA write transactions. 981system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 982system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 983system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 984system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 985system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 986system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 987system.iobus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 967system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 968system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 969system.iobus.trans_dist::WriteReq 51175 # Transaction distribution 970system.iobus.trans_dist::WriteResp 51175 # Transaction distribution 971system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) 972system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 973system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 974system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1013system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) 1014system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1015system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks) 1016system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1017system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) 1018system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1019system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1020system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 988system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 989system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 990system.iobus.trans_dist::WriteReq 51175 # Transaction distribution 991system.iobus.trans_dist::WriteResp 51175 # Transaction distribution 992system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1034system.iobus.reqLayer26.occupancy 93000 # Layer occupancy (ticks) 1035system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1036system.iobus.reqLayer27.occupancy 215722666 # Layer occupancy (ticks) 1037system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1038system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) 1039system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1040system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1041system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1042system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 1021system.iocache.tags.replacements 41685 # number of replacements 1022system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use 1023system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1024system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1025system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1026system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit. 1027system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor 1028system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy 1029system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy 1030system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1031system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1032system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1033system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1034system.iocache.tags.data_accesses 375525 # Number of data accesses | 1043system.iocache.tags.replacements 41685 # number of replacements 1044system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use 1045system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1046system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1047system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1048system.iocache.tags.warmup_cycle 1748617417000 # Cycle when the warmup percentage was hit. 1049system.iocache.tags.occ_blocks::tsunami.ide 1.298739 # Average occupied blocks per requestor 1050system.iocache.tags.occ_percent::tsunami.ide 0.081171 # Average percentage of cache occupancy 1051system.iocache.tags.occ_percent::total 0.081171 # Average percentage of cache occupancy 1052system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1053system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1054system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1055system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1056system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1057system.iocache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 1035system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1036system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1037system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1038system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1039system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1040system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1041system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1042system.iocache.overall_misses::total 41725 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1107system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency 1108system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency 1109system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency 1110system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency 1111system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1112system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency 1113system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1114system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency | 1058system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1059system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1060system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1061system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1062system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1063system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1064system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1065system.iocache.overall_misses::total 41725 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1130system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency 1131system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency 1132system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency 1133system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency 1134system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1135system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency 1136system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1137system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency |
| 1138system.membus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 1115system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1116system.membus.trans_dist::ReadResp 295608 # Transaction distribution 1117system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1118system.membus.trans_dist::WriteResp 9623 # Transaction distribution 1119system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution 1120system.membus.trans_dist::CleanEvict 262242 # Transaction distribution 1121system.membus.trans_dist::UpgradeReq 167 # Transaction distribution 1122system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 32 unchanged lines hidden (view full) --- 1155system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks) 1156system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1157system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) 1158system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1159system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks) 1160system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1161system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) 1162system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1139system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1140system.membus.trans_dist::ReadResp 295608 # Transaction distribution 1141system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1142system.membus.trans_dist::WriteResp 9623 # Transaction distribution 1143system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution 1144system.membus.trans_dist::CleanEvict 262242 # Transaction distribution 1145system.membus.trans_dist::UpgradeReq 167 # Transaction distribution 1146system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 32 unchanged lines hidden (view full) --- 1179system.membus.reqLayer1.occupancy 1318874217 # Layer occupancy (ticks) 1180system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1181system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) 1182system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1183system.membus.respLayer1.occupancy 2159448000 # Layer occupancy (ticks) 1184system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1185system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) 1186system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1187system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1188system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1189system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1190system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1191system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 1163system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1164system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1165system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1166system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1167system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1168system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1169system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1170system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1186system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1187system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1188system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1189system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1190system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1191system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1192system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1193system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1192system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1193system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1194system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1195system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1196system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1197system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1198system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1199system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1215system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1216system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1217system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1218system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1219system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1220system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1221system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1222system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1223system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1226system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1227system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1228system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1229system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1230system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1231system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1232system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1237system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1238system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1239system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1240system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1241system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1242system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1243system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1244system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states 1245system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states |
|
| 1194 1195---------- End Simulation Statistics ---------- | 1246 1247---------- End Simulation Statistics ---------- |