| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.907083 # Number of seconds simulated 4sim_ticks 1907083088000 # Number of ticks simulated 5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.907083 # Number of seconds simulated 4sim_ticks 1907083088000 # Number of ticks simulated 5final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 20030 # Simulator instruction rate (inst/s) 8host_op_rate 20030 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 680419212 # Simulator tick rate (ticks/s) | 7host_inst_rate 20979 # Simulator instruction rate (inst/s) 8host_op_rate 20979 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 712669715 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 389460 # Number of bytes of host memory used | 10host_mem_usage 389460 # Number of bytes of host memory used |
| 11host_seconds 2802.81 # Real time elapsed on the host | 11host_seconds 2675.97 # Real time elapsed on the host |
| 12sim_insts 56139550 # Number of instructions simulated 13sim_ops 56139550 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory --- 538 unchanged lines hidden (view full) --- 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency 559system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency 560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 56139550 # Number of instructions simulated 13sim_ops 56139550 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25899200 # Number of bytes read from this memory --- 538 unchanged lines hidden (view full) --- 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 45565.166284 # average overall miss latency 559system.cpu.dcache.overall_avg_miss_latency::total 45565.166284 # average overall miss latency 560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 566system.cpu.dcache.fast_writes 0 # number of fast writes performed 567system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 568system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks 569system.cpu.dcache.writebacks::total 837991 # number of writebacks 570system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits 571system.cpu.dcache.ReadReq_mshr_hits::total 126783 # number of ReadReq MSHR hits 572system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270556 # number of WriteReq MSHR hits 573system.cpu.dcache.WriteReq_mshr_hits::total 270556 # number of WriteReq MSHR hits 574system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 575system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits --- 24 unchanged lines hidden (view full) --- 600system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209962500 # number of LoadLockedReq MSHR miss cycles 601system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209962500 # number of LoadLockedReq MSHR miss cycles 602system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles 603system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles 604system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles 605system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles 606system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles 607system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles | 566system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks 567system.cpu.dcache.writebacks::total 837991 # number of writebacks 568system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits 569system.cpu.dcache.ReadReq_mshr_hits::total 126783 # number of ReadReq MSHR hits 570system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270556 # number of WriteReq MSHR hits 571system.cpu.dcache.WriteReq_mshr_hits::total 270556 # number of WriteReq MSHR hits 572system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 573system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits --- 24 unchanged lines hidden (view full) --- 598system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209962500 # number of LoadLockedReq MSHR miss cycles 599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209962500 # number of LoadLockedReq MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61084599500 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.demand_mshr_miss_latency::total 61084599500 # number of demand (read+write) MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 # number of overall MSHR miss cycles 603system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles 604system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles 605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles |
| 608system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles 609system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles 610system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles 611system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles | 606system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles 607system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles |
| 612system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049434 # mshr miss rate for WriteReq accesses 616system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082806 # mshr miss rate for LoadLockedReq accesses 617system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082806 # mshr miss rate for LoadLockedReq accesses 618system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for demand accesses 619system.cpu.dcache.demand_mshr_miss_rate::total 0.090562 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756 # average LoadLockedReq mshr miss latency 627system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756 # average LoadLockedReq mshr miss latency 628system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 629system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 630system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 631system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency 633system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency | 608system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses 609system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses 610system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses 611system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049434 # mshr miss rate for WriteReq accesses 612system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082806 # mshr miss rate for LoadLockedReq accesses 613system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082806 # mshr miss rate for LoadLockedReq accesses 614system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090562 # mshr miss rate for demand accesses 615system.cpu.dcache.demand_mshr_miss_rate::total 0.090562 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 622system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12673.537756 # average LoadLockedReq mshr miss latency 623system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.537756 # average LoadLockedReq mshr miss latency 624system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 625system.cpu.dcache.demand_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 626system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 # average overall mshr miss latency 627system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency 628system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency 629system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency |
| 634system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency 635system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency 636system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency 637system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency 638system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency 631system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency |
| 639system.cpu.icache.tags.replacements 1471396 # number of replacements 640system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use 641system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. 642system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks. 643system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks. 644system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit. 645system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor 646system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 689system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency 690system.cpu.icache.overall_avg_miss_latency::total 14369.070974 # average overall miss latency 691system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 695system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 632system.cpu.icache.tags.replacements 1471396 # number of replacements 633system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use 634system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. 635system.cpu.icache.tags.sampled_refs 1471907 # Sample count of references to valid blocks. 636system.cpu.icache.tags.avg_refs 13.002847 # Average number of references to valid blocks. 637system.cpu.icache.tags.warmup_cycle 50134801500 # Cycle when the warmup percentage was hit. 638system.cpu.icache.tags.occ_blocks::cpu.inst 508.107952 # Average occupied blocks per requestor 639system.cpu.icache.tags.occ_percent::cpu.inst 0.992398 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 682system.cpu.icache.overall_avg_miss_latency::cpu.inst 14369.070974 # average overall miss latency 683system.cpu.icache.overall_avg_miss_latency::total 14369.070974 # average overall miss latency 684system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 685system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 686system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 687system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 688system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 689system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 697system.cpu.icache.fast_writes 0 # number of fast writes performed 698system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 699system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks 700system.cpu.icache.writebacks::total 1471396 # number of writebacks 701system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses 702system.cpu.icache.ReadReq_mshr_misses::total 1472080 # number of ReadReq MSHR misses 703system.cpu.icache.demand_mshr_misses::cpu.inst 1472080 # number of demand (read+write) MSHR misses 704system.cpu.icache.demand_mshr_misses::total 1472080 # number of demand (read+write) MSHR misses 705system.cpu.icache.overall_mshr_misses::cpu.inst 1472080 # number of overall MSHR misses 706system.cpu.icache.overall_mshr_misses::total 1472080 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 717system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses 718system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses 719system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency 720system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency 721system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 722system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency 723system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 724system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency | 690system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks 691system.cpu.icache.writebacks::total 1471396 # number of writebacks 692system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses 693system.cpu.icache.ReadReq_mshr_misses::total 1472080 # number of ReadReq MSHR misses 694system.cpu.icache.demand_mshr_misses::cpu.inst 1472080 # number of demand (read+write) MSHR misses 695system.cpu.icache.demand_mshr_misses::total 1472080 # number of demand (read+write) MSHR misses 696system.cpu.icache.overall_mshr_misses::cpu.inst 1472080 # number of overall MSHR misses 697system.cpu.icache.overall_mshr_misses::total 1472080 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 708system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071422 # mshr miss rate for overall accesses 709system.cpu.icache.overall_mshr_miss_rate::total 0.071422 # mshr miss rate for overall accesses 710system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13369.070974 # average ReadReq mshr miss latency 711system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13369.070974 # average ReadReq mshr miss latency 712system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 713system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency 714system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency 715system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency |
| 725system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 726system.cpu.l2cache.tags.replacements 339491 # number of replacements 727system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use 728system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. 729system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks. 730system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks. 731system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit. 732system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor 733system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 838system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency 840system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 841system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 842system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 845system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 716system.cpu.l2cache.tags.replacements 339491 # number of replacements 717system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use 718system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. 719system.cpu.l2cache.tags.sampled_refs 404654 # Sample count of references to valid blocks. 720system.cpu.l2cache.tags.avg_refs 12.406226 # Average number of references to valid blocks. 721system.cpu.l2cache.tags.warmup_cycle 9688326000 # Cycle when the warmup percentage was hit. 722system.cpu.l2cache.tags.occ_blocks::writebacks 54061.905720 # Average occupied blocks per requestor 723system.cpu.l2cache.tags.occ_blocks::cpu.inst 5741.199661 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 828system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124793.692929 # average overall miss latency 829system.cpu.l2cache.overall_avg_miss_latency::total 125061.315597 # average overall miss latency 830system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 832system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 835system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 846system.cpu.l2cache.fast_writes 0 # number of fast writes performed 847system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 848system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks 849system.cpu.l2cache.writebacks::total 76584 # number of writebacks 850system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses 851system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses 852system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses 853system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses 854system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses 855system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses --- 22 unchanged lines hidden (view full) --- 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles 885system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles | 836system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks 837system.cpu.l2cache.writebacks::total 76584 # number of writebacks 838system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses 839system.cpu.l2cache.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses 840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116580 # number of ReadExReq MSHR misses 841system.cpu.l2cache.ReadExReq_mshr_misses::total 116580 # number of ReadExReq MSHR misses 842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16339 # number of ReadCleanReq MSHR misses 843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16339 # number of ReadCleanReq MSHR misses --- 22 unchanged lines hidden (view full) --- 866system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1984030500 # number of demand (read+write) MSHR miss cycles 867system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631457500 # number of demand (read+write) MSHR miss cycles 868system.cpu.l2cache.demand_mshr_miss_latency::total 46615488000 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1984030500 # number of overall MSHR miss cycles 870system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 # number of overall MSHR miss cycles 871system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles 872system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles 873system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles |
| 886system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles 887system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles 888system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles 889system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles | 874system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles 875system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles |
| 890system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses 891system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses 892system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses 895system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses 896system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses 897system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses --- 14 unchanged lines hidden (view full) --- 912system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency 913system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency 916system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency 918system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency 919system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency | 876system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses 877system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses 878system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses 879system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383353 # mshr miss rate for ReadExReq accesses 880system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011100 # mshr miss rate for ReadCleanReq accesses 881system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011100 # mshr miss rate for ReadCleanReq accesses 882system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249486 # mshr miss rate for ReadSharedReq accesses 883system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249486 # mshr miss rate for ReadSharedReq accesses --- 14 unchanged lines hidden (view full) --- 898system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency 899system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121429.126630 # average overall mshr miss latency 902system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency 904system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency 905system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency |
| 920system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency 921system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency 922system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency 923system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency 924system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency 907system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency |
| 925system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. 926system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. 927system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 928system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. 929system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 930system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 931system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution --- 115 unchanged lines hidden (view full) --- 1048system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1049system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1050system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1051system.iocache.tags.data_accesses 375525 # Number of data accesses 1052system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1053system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1054system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1055system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses | 908system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. 909system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. 910system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 911system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. 912system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 913system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 914system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 915system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution --- 115 unchanged lines hidden (view full) --- 1031system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1032system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1033system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1034system.iocache.tags.data_accesses 375525 # Number of data accesses 1035system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1036system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1037system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1038system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| 1056system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1057system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1058system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1059system.iocache.overall_misses::total 173 # number of overall misses | 1039system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1040system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1041system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1042system.iocache.overall_misses::total 41725 # number of overall misses |
| 1060system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles 1061system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles 1062system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles 1063system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles | 1043system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles 1044system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles 1045system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles 1046system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles |
| 1064system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles 1065system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles 1066system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles 1067system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles | 1047system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles 1048system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles 1049system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles 1050system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles |
| 1068system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1069system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1070system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1071system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) | 1051system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1052system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1053system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1054system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| 1072system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1073system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1074system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1075system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses | 1055system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1056system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1057system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1058system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses |
| 1076system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1077system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1078system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1079system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1080system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1081system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1082system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1083system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1084system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency 1085system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency 1086system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency 1087system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency | 1059system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1060system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1061system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1062system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1063system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1064system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1065system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1066system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1067system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency 1068system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency 1069system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency 1070system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency |
| 1088system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency 1089system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency 1090system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency 1091system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency | 1071system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency 1072system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency 1073system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency 1074system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency |
| 1092system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked 1093system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1094system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked 1095system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1096system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked 1097system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1075system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked 1076system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1077system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked 1078system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1079system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked 1080system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1098system.iocache.fast_writes 0 # number of fast writes performed 1099system.iocache.cache_copies 0 # number of cache copies performed | |
| 1100system.iocache.writebacks::writebacks 41512 # number of writebacks 1101system.iocache.writebacks::total 41512 # number of writebacks 1102system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1103system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1104system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1105system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses | 1081system.iocache.writebacks::writebacks 41512 # number of writebacks 1082system.iocache.writebacks::total 41512 # number of writebacks 1083system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1084system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1085system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1086system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| 1106system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1107system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1108system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1109system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1087system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1088system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1089system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1090system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1110system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles 1111system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles 1112system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles 1113system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles | 1091system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles 1092system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles 1093system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles 1094system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles |
| 1114system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles 1115system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles 1116system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles 1117system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles | 1095system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles 1096system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles 1097system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles 1098system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles |
| 1118system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1119system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1120system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1121system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1122system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1123system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1124system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1125system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1126system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency 1127system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency 1128system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency 1129system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency | 1099system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1100system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1101system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1102system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1103system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1104system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1105system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1106system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1107system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency 1108system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency 1109system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency 1110system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency |
| 1130system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency 1131system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency 1132system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency 1133system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency 1134system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1111system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1112system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency 1113system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency 1114system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency |
| 1135system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1136system.membus.trans_dist::ReadResp 295608 # Transaction distribution 1137system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1138system.membus.trans_dist::WriteResp 9623 # Transaction distribution 1139system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution 1140system.membus.trans_dist::CleanEvict 262242 # Transaction distribution 1141system.membus.trans_dist::UpgradeReq 167 # Transaction distribution 1142system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 73 unchanged lines hidden --- | 1115system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1116system.membus.trans_dist::ReadResp 295608 # Transaction distribution 1117system.membus.trans_dist::WriteReq 9623 # Transaction distribution 1118system.membus.trans_dist::WriteResp 9623 # Transaction distribution 1119system.membus.trans_dist::WritebackDirty 118096 # Transaction distribution 1120system.membus.trans_dist::CleanEvict 262242 # Transaction distribution 1121system.membus.trans_dist::UpgradeReq 167 # Transaction distribution 1122system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 73 unchanged lines hidden --- |